IPB180N04S400ATMA1 [INFINEON]

Power Field-Effect Transistor, 180A I(D), 40V, 0.00098ohm, 1-Element, N-Channel, Silicon, Metal-Oxide Semiconductor FET, TO-263, GREEN, PLASTIC PACKAGE-7/6;
IPB180N04S400ATMA1
型号: IPB180N04S400ATMA1
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, 180A I(D), 40V, 0.00098ohm, 1-Element, N-Channel, Silicon, Metal-Oxide Semiconductor FET, TO-263, GREEN, PLASTIC PACKAGE-7/6

脉冲 晶体管
文件: 总9页 (文件大小:354K)
中文:  中文翻译
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IPB180N04S4-00  
OptiMOS®-T2 Power-Transistor  
Product Summary  
VDS  
RDS(on)  
ID  
40  
V
0.98  
180  
mW  
A
Features  
• N-channel - Enhancement mode  
PG-TO263-7-3  
• AEC qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green product (RoHS compliant)  
• Ultra low Rds(on)  
• 100% Avalanche tested  
Type  
Package  
Marking  
IPB180N04S4-00  
PG-TO263-7-3  
4N0400  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
T C=25°C, V GS=10V1)  
I D  
Continuous drain current  
180  
180  
A
T C=100 °C,  
V GS=10 V2)  
Pulsed drain current2)  
I D,pulse  
E AS  
T C=25 °C  
720  
1250  
Avalanche energy, single pulse2)  
Avalanche current, single pulse  
Gate source voltage  
I D=90 A  
mJ  
A
I AS  
-
180  
V GS  
-
±20  
V
P tot  
T C=25 °C  
Power dissipation  
300  
W
°C  
T j, T stg  
Operating and storage temperature  
-
-55 ... +175  
Rev. 1.1  
page 1  
2015-10-07  
IPB180N04S4-00  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
R thJA  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
-
0.5  
62  
40  
K/W  
minimal footprint  
6 cm2 cooling area3)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS V GS=0 V, I D= 1 mA  
V GS(th) V DS=V GS, I D=230 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
40  
-
-
V
2.0  
3.0  
4.0  
V DS=40 V, V GS=0 V,  
T j=25 °C  
I DSS  
Zero gate voltage drain current  
-
-
0.1  
1
1
µA  
V DS=18 V, V GS=0 V,  
T j=85 °C2)  
20  
I GSS  
V GS=20 V, V DS=0 V  
Gate-source leakage current  
-
-
100 nA  
RDS(on) V GS=10 V, I D=100 A  
Drain-source on-state resistance  
-
0.8  
0.98 mΩ  
Rev. 1.1  
page 2  
2015-10-07  
IPB180N04S4-00  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
17600  
3780  
130  
53  
22880 pF  
4900  
V GS=0 V, V DS=25 V,  
f =1 MHz  
300  
-
-
-
-
ns  
24  
V DD=20 V, V GS=10 V,  
I D=180 A, R G=3.5 W  
t d(off)  
t f  
Turn-off delay time  
Fall time  
67  
58  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
87  
29  
113 nC  
67  
Q gd  
V DD=32 V, I D=180 A,  
V GS=0 to 10 V  
Q g  
220  
5.0  
286  
V plateau  
Gate plateau voltage  
-
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
-
-
-
-
180  
720  
T C=25 °C  
I S,pulse  
V GS=0 V, I F=100 A,  
T j=25 °C  
V SD  
Diode forward voltage  
-
0.9  
1.3  
V
Reverse recovery time2)  
t rr  
-
-
85  
-
-
ns  
V R=20 V, I F=50A,  
di F/dt =100 A/µs  
Reverse recovery charge2)  
Q rr  
132  
nC  
1) Current is limited by bondwire; with an R thJC = 0.5 K/W the chip is able to carry 425A at 25°C.  
2) Defined by design. Not subject to production test.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.1  
page 3  
2015-10-07  
IPB180N04S4-00  
1 Power dissipation  
2 Drain current  
P tot = f(T C); V GS = 10 V  
I D = f(T C); V GS = 10 V  
350  
300  
250  
200  
150  
100  
50  
200  
180  
160  
140  
120  
100  
80  
60  
40  
20  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
TC [°C]  
TC [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
Z thJC = f(t p)  
I D = f(V DS); T C = 25 °C; D = 0  
parameter: t p  
parameter: D =t p/T  
100  
1000  
1 µs  
10 µs  
0.5  
100 µs  
1 ms  
10-1  
100  
10  
1
0.1  
0.05  
0.01  
10-2  
single pulse  
10-3  
0.1  
1
10  
100  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
VDS [V]  
tp [s]  
Rev. 1.1  
page 4  
2015-10-07  
IPB180N04S4-00  
5 Typ. output characteristics  
I D = f(V DS); T j = 25 °C  
parameter: V GS  
6 Typ. drain-source on-state resistance  
R DS(on) = (I D); T j = 25 °C  
parameter: V GS  
6
700  
10 V  
5 V  
5.5 V  
6 V  
7 V  
6.5 V  
600  
5
4
3
2
1
0
6 V  
500  
400  
300  
200  
100  
0
5.5 V  
6.5 V  
7 V  
5 V  
10 V  
0
100  
200  
300  
400  
500  
600  
0
2
4
6
ID [A]  
VDS [V]  
7 Typ. transfer characteristics  
I D = f(V GS); V DS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R DS(on) = f(T j); I D = 100 A; V GS = 10 V  
720  
630  
540  
450  
360  
1.5  
1.25  
1
270  
175 °C  
0.75  
0.5  
180  
25 °C  
90  
-55 °C  
0
-60  
-20  
20  
60  
100  
140  
180  
2
4
6
8
Tj [°C]  
VGS [V]  
Rev. 1.1  
page 5  
2015-10-07  
IPB180N04S4-00  
9 Typ. gate threshold voltage  
V GS(th) = f(T j); V GS = V DS  
parameter: I D  
10 Typ. capacitances  
C = f(V DS); V GS = 0 V; f = 1 MHz  
105  
104  
103  
102  
4
3.5  
3
Ciss  
2300 µA  
Coss  
230 µA  
2.5  
2
1.5  
1
Crss  
0
5
10  
15  
20  
25  
30  
-60  
-20  
20  
60  
100  
140  
180  
Tj [°C]  
VDS [V]  
11 Typical forward diode characteristicis  
12 Typ. avalanche characteristics  
I AS = f(t AV  
IF = f(VSD)  
)
parameter: T j  
parameter: Tj(start)  
103  
1000  
102  
25 °C  
100  
100 °C  
150 °C  
25 °C  
175 °C  
101  
10  
100  
1
1
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
10  
100  
1000  
VSD [V]  
tAV [µs]  
Rev. 1.1  
page 6  
2015-10-07  
IPB180N04S4-00  
13 Typical avalanche energy  
E AS = f(T j)  
14 Drain-source breakdown voltage  
V BR(DSS) = f(T j); I D = 1 mA  
parameter: I D  
44  
3000  
45 A  
2500  
42  
40  
38  
2000  
1500  
90 A  
1000  
180 A  
500  
0
-60  
-20  
20  
60  
100  
140  
180  
25  
75  
125  
175  
Tj [°C]  
Tj [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
V GS = f(Q gate); I D = 180 A pulsed  
parameter: V DD  
12  
10  
8
VGS  
Q g  
8 V  
32 V  
6
4
Qgate  
2
Qgd  
Q gs  
0
0
40  
80  
120  
160  
200  
240  
Qgate [nC]  
Rev. 1.1  
page 7  
2015-10-07  
IPB180N04S4-00  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2015  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.1  
page 8  
2015-10-07  
IPB180N04S4-00  
Revision History  
Version  
Date  
Changes  
Revision 1.0  
Revision 1.1  
2010-04-13 Final Data Sheet  
2015-10-07 Update of labeling of diagram 6  
Rev. 1.1  
page 9  
2015-10-07  

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