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IPDH4N03LA-G [INFINEON]

OPTIMOS 2 POWER - TRANSISTOR; OPTIMOS 2个电源 - 晶体管
IPDH4N03LA-G
型号： IPDH4N03LA-G
厂家： Infineon    Infineon
描述：

OPTIMOS 2 POWER - TRANSISTOR
OPTIMOS 2个电源 - 晶体管

晶体 晶体管
文件： 总9页 (文件大小：305K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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IPDH4N03LA G  
IPSH4N03LA G  
OptiMOS®2 Power-Transistor  
Product Summary  
V DS  
Features  
25  
4.2  
90  
V
• Ideal for high-frequency dc/dc converters  
• Qualified according to JEDEC1) for target applications  
R
DS(on),max (SMD Version)  
mΩ  
A
I D  
• N-channel, logic level  
• Excellent gate charge x R DS(on) product (FOM)  
• Superior thermal resistance  
• 175 °C operating temperature  
• Pb-free lead plating; RoHS compliant  
Type  
IPDH4N03LA G  
IPSH4N03LA G  
Package  
P-TO252-3-11  
Q67042-S4250  
H4N03LA  
P-TO251-3-11  
Q67042-S4254  
H4N03LA  
Ordering Code  
Marking  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol Conditions  
Unit  
T C=25 °C2)  
I D  
Continuous drain current  
90  
77  
A
T C=100 °C  
T C=25 °C3)  
I D,pulse  
Pulsed drain current  
360  
150  
E AS  
I D=90 A, R GS=25 Ω  
Avalanche energy, single pulse  
mJ  
I D=90 A, V DS=20 V,  
di /dt =200 A/µs,  
Reverse diode dv /dt  
dv /dt  
6
kV/µs  
T
j,max=175 °C  
Gate source voltage4)  
V GS  
±20  
94  
V
P tot  
T C=25 °C  
Power dissipation  
W
°C  
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... 175  
55/175/56  
Rev. 0.92 - target data sheet  
page 1  
2004-10-27  
IPDH4N03LA G  
Values  
IPSH4N03LA G  
Parameter  
Symbol Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics  
R thJC  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
1.6  
75  
50  
K/W  
R thJA  
minimal footprint  
6 cm2 cooling area5)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS  
V GS(th)  
V
V
GS=0 V, I D=1 mA  
DS=V GS, I D=40 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
25  
-
-
V
1.2  
1.6  
2
V
DS=25 V, V GS=0 V,  
I DSS  
Zero gate voltage drain current  
-
-
0.1  
10  
1
µA  
T j=25 °C  
V
DS=25 V, V GS=0 V,  
100  
T j=125 °C  
I GSS  
V
V
GS=20 V, V DS=0 V  
GS=4.5 V, I D=50 A  
Gate-source leakage current  
-
-
10  
100 nA  
R DS(on)  
Drain-source on-state resistance  
6.1  
7.6  
7.4  
4.4  
4.2  
-
mΩ  
V
GS=4.5 V, I D=50 A,  
-
-
5.9  
3.7  
3.5  
1.3  
90  
SMD version  
V
GS=10 V, I D=60 A  
V
GS=10 V, I D=60 A,  
-
SMD version  
R G  
g fs  
Gate resistance  
-
Ω
|V DS|>2|I D|R DS(on)max  
I D=60 A  
,
Transconductance  
45  
-
S
1) J-STD20 and JESD22  
1) Current is limited by bondwire; with anR thJC=1.6 K/W the chip is able to carry 109 A.  
3) See figure 3  
4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V  
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
2
Rev. 0.92 - target data sheet  
page 2  
2004-10-27  
IPDH4N03LA G  
Values  
IPSH4N03LA G  
Parameter  
Symbol Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
-
-
-
-
-
-
-
2400  
920  
110  
9
3200 pF  
1200  
V
GS=0 V, V DS=15 V,  
C oss  
Crss  
t d(on)  
t r  
f =1 MHz  
160  
14  
11  
44  
7
ns  
7
V
DD=15 V, V GS=10 V,  
I D=25 A, R G=2.7 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
29  
4.6  
Gate Charge Characteristics6)  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge  
Switching charge  
Q gs  
-
-
-
-
-
-
8
11  
5.1  
8
nC  
Q g(th)  
Q gd  
3.9  
5.6  
10  
V
V
DD=15 V, I D=45 A,  
GS=0 to 5 V  
Q sw  
14  
26  
-
Q g  
Gate charge total  
19  
V plateau  
Gate plateau voltage  
3.4  
V
V
V
DS=0.1 V,  
Q g(sync)  
Q oss  
Gate charge total, sync. FET  
Output charge  
-
-
17  
20  
23  
27  
nC  
GS=0 to 5 V  
V
DD=15 V, V GS=0 V  
Reverse Diode  
I S  
Diode continous forward current  
Diode pulse current  
-
-
-
-
78  
A
T C=25 °C  
I S,pulse  
360  
V
GS=0 V, I F=78 A,  
V SD  
Q rr  
Diode forward voltage  
-
-
0.93  
-
1.2  
15  
V
T j=25 °C  
V R=15 V, I F=I S,  
di F/dt =400 A/µs  
Reverse recovery charge  
nC  
6) See figure 16 for gate charge parameter definition  
Rev. 0.92 - target data sheet  
page 3  
2004-10-27  
Rev. 0.92 - target data sheet  
page 4  
2004-10-27  
IPDH4N03LA G  
2 Drain current  
IPSH4N03LA G  
1 Power dissipation  
P
tot=f(T C)  
120  
100  
80  
I D=f(T C); V GS≥10 V  
100  
80  
60  
40  
20  
0
60  
40  
20  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
I D=f(V DS); T C=25 °C; D =0  
parameter: t p  
4 Max. transient thermal impedance  
thJC=f(t p)  
Z
parameter: D =t p/T  
1000  
10  
limited by on-state  
resistance  
1 µs  
10 µs  
100 µs  
100  
0.5  
0.2  
1
DC  
1 ms  
0.1  
0.05  
10  
0.1  
0.02  
0.01  
10 ms  
single pulse  
1
0.01  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
V
DS [V]  
t
p [s]  
Rev. 0.92 - target data sheet  
page 5  
2004-10-27  
IPDH4N03LA G  
IPSH4N03LA G  
5 Typ. output characteristics  
I D=f(V DS); T j=25 °C  
6 Typ. drain-source on resistance  
R
DS(on)=f(I D); T j=25 °C  
parameter: V GS  
parameter: V GS  
100  
16  
4.5 V  
4 V  
3 V  
3.2 V  
3.4 V  
3.7 V  
4 V  
90  
10 V  
14  
12  
10  
8
80  
70  
60  
50  
40  
30  
20  
10  
0
3.7 V  
3.4 V  
3.2 V  
4.5 V  
10 V  
6
4
3 V  
2
2.8 V  
0
0
1
2
3
0
20  
40  
60  
80  
100  
V
DS [V]  
ID [A]  
7 Typ. transfer characteristics  
I D=f(V GS); |V DS|>2|I D|R DS(on)max  
parameter: T j  
8 Typ. forward transconductance  
g fs=f(I D); T j=25 °C  
100  
140  
120  
100  
80  
80  
60  
60  
40  
40  
20  
175 °C  
20  
25 °C  
0
0
0
1
2
3
4
5
0
20  
40  
60  
80  
100  
V
GS [V]  
ID [A]  
Rev. 0.92 - target data sheet  
page 6  
2004-10-27  
IPDH4N03LA G  
IPSH4N03LA G  
9 Drain-source on-state resistance  
10 Typ. gate threshold voltage  
R
DS(on)=f(T j); I D=60 A; V GS=10 V  
V GS(th)=f(T j); V GS=V DS  
parameter: I D  
8
7
6
2.5  
2
1.5  
1
400 µA  
5
98 %  
40 µA  
4
typ  
3
2
1
0
0.5  
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
T j [°C]  
11 Typ. capacitances  
12 Forward characteristics of reverse diode  
I F=f(V SD  
C =f(V DS); V GS=0 V; f =1 MHz  
)
parameter: T j  
104  
1000  
25 °C, 98%  
Ciss  
Coss  
175 °C, 98%  
103  
100  
10  
25 °C  
175 °C  
Crss  
102  
101  
1
0
10  
20  
30  
0.0  
0.5  
1.0  
1.5  
2.0  
V
DS [V]  
V
SD [V]  
Rev. 0.92 - target data sheet  
page 7  
2004-10-27  
IPDH4N03LA G  
14 Typ. gate charge  
GS=f(Q gate); I D=45 A pulsed  
IPSH4N03LA G  
13 Avalanche characteristics  
AS=f(t AV); R GS=25 Ω  
V
I
parameter: Tj(start)  
parameter: V DD  
100  
12  
25 °C  
150 °C  
100 °C  
15 V  
10  
8
5 V  
20 V  
10  
6
4
2
1
0
0
1
10  
100  
1000  
10  
20  
30  
40  
t
AV [µs]  
Q
gate [nC]  
15 Drain-source breakdown voltage  
16 Gate charge waveforms  
V
BR(DSS)=f(T j); I D=1 mA  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
V GS  
Q g  
V gs(th)  
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
Rev. 0.92 - target data sheet  
page 8  
2004-10-27  
IPDH4N03LA G  
IPSH4N03LA G  
Package Outline  
P-TO252-3-11: Outline  
Footprint:  
Packaging:  
Dimensions in mm  
Rev. 0.92 - target data sheet  
page 9  
2004-10-27  

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