IPDH6N03LA [INFINEON]
OptiMOS Power-Transistor Feature Enhancement mode Logic Level Avalanche rated; 的OptiMOS功率三极管特性增强模式的逻辑电平额定雪崩![IPDH6N03LA](http://pdffile.icpdf.com/pdf1/p00135/img/icpdf/IPDH6_748920_icpdf.jpg)
型号: | IPDH6N03LA |
厂家: | ![]() |
描述: | OptiMOS Power-Transistor Feature Enhancement mode Logic Level Avalanche rated |
文件: | 总12页 (文件大小:538K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
OptiMOS®2 Power-Transistor
Product Summary
V DS
Features
25
6
V
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target application
R
DS(on),max (SMD version)
mΩ
A
I D
50
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
• Superior thermal resistance
• 175 °C operating temperature
• Pb-free lead plating; RoHS compliant
Type
IPDH6N03LA G
IPFH6N03LA G
IPSH6N03LA G
IPUH6N03LA G
Package
Marking
PG-TO252-3-11
H6N03LA
PG-TO252-3-23
H6N03LA
PG-TO251-3-11
H6N03LA
PG-TO251-3-1
H6N03LA
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol Conditions
Unit
T C=25 °C2)
I D
Continuous drain current
50
50
A
T C=100 °C
T C=25 °C3)
I D,pulse
Pulsed drain current
350
150
E AS
I D=50 A, R GS=25 Ω
Avalanche energy, single pulse
mJ
I D=50 A, V DS=20 V,
di /dt =200 A/µs,
Reverse diode dv /dt
dv /dt
6
kV/µs
T
j,max=175 °C
Gate source voltage4)
V GS
±20
71
V
P tot
T C=25 °C
Power dissipation
W
°C
T j, T stg
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-55 ... 175
55/175/56
Rev. 1.5
page 1
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Thermal characteristics
R thJC
Thermal resistance, junction - case
SMD version, device on PCB
-
-
-
-
-
-
2.1
75
50
K/W
R thJA
minimal footprint
6 cm2 cooling area5)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V (BR)DSS
V GS(th)
V
V
GS=0 V, I D=1 mA
DS=V GS, I D=30 µA
Drain-source breakdown voltage
Gate threshold voltage
25
-
-
V
1.2
1.6
2
V
DS=25 V, V GS=0 V,
I DSS
Zero gate voltage drain current
-
-
0.1
10
1
µA
T j=25 °C
V
DS=25 V, V GS=0 V,
100
T j=125 °C
I GSS
V
V
GS=20 V, V DS=0 V
GS=4.5 V, I D=30 A
Gate-source leakage current
-
-
10
100 nA
R DS(on)
Drain-source on-state resistance
8.2
10.2
10
6.2
6
mΩ
V
GS=4.5 V, I D=30 A,
-
-
8
IPD version
V
GS=10 V, I D=50 A
5.2
5
V
GS=10 V, I D=50 A,
-
IPD version
R G
g fs
Gate resistance
-
1.3
69
-
Ω
|V DS|>2|I D|R DS(on)max
I D=50 A
,
Transconductance
35
-
S
1) J-STD20 and JESD22
2) Current is limited by bondwire; with anR thJC=2.1 K/W the chip is able to carry 80 A.
3) See figure 3
4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
2
Rev. 1.5
page 2
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Dynamic characteristics
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C iss
-
-
-
-
-
-
-
1800
690
85
2390 pF
920
V
GS=0 V, V DS=15 V,
C oss
Crss
t d(on)
t r
f =1 MHz
130
6
9
8
ns
5.4
23
V
DD=15 V, V GS=10 V,
I D=25 A, R G=2.7 Ω
t d(off)
t f
Turn-off delay time
Fall time
34
6.3
4.2
Gate Charge Characteristics6)
Gate to source charge
Gate charge at threshold
Gate to drain charge
Switching charge
Q gs
-
-
-
-
-
-
5.9
2.9
4.1
7.1
14
7.8
3.8
6.1
10
19
-
nC
Q g(th)
Q gd
V
V
DD=15 V, I D=25 A,
GS=0 to 5 V
Q sw
Q g
Gate charge total
V plateau
Gate plateau voltage
3.3
V
V
V
DS=0.1 V,
Q g(sync)
Q oss
Gate charge total, sync. FET
Output charge
-
-
13
15
17
20
nC
GS=0 to 5 V
V
DD=15 V, V GS=0 V
Reverse Diode
I S
Diode continous forward current
Diode pulse current
-
-
-
-
50
A
T C=25 °C
I S,pulse
350
V
GS=0 V, I F=50 A,
V SD
Q rr
Diode forward voltage
-
-
0.93
-
1.2
10
V
T j=25 °C
V R=15 V, I F=I S,
di F/dt =400 A/µs
Reverse recovery charge
nC
6) See figure 16 for gate charge parameter definition
Rev. 1.5
page 3
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
1 Power dissipation
2 Drain current
P
tot=f(T C)
I D=f(T C); V GS≥10 V
80
70
60
50
40
30
20
10
60
50
40
30
20
10
0
0
0
50
100
150
200
0
50
100
150
200
T
C [°C]
T
C [°C]
3 Safe operating area
I D=f(V DS); T C=25 °C; D =0
parameter: t p
4 Max. transient thermal impedance
thJC=f(t p)
Z
parameter: D =t p/T
1000
10
1 µs
limited by on-state
resistance
10 µs
0.5
100
1
0.2
100 µs
DC
0.1
1 ms
0.05
10
0.1
10 ms
0.02
0.01
single pulse
1
0
0
0
0
0
0
1
0.01
10-6
10-5
10-4
10-3
p [s]
10-2
10-1
100
0.1
1
10
100
t
V
DS [V]
Rev. 1.5
page 4
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
5 Typ. output characteristics
I D=f(V DS); T j=25 °C
6 Typ. drain-source on resistance
DS(on)=f(I D); T j=25 °C
R
parameter: V GS
parameter: V GS
100
20
4.1 V
4.5 V
10 V
3.8 V
3.5 V
90
80
70
60
50
40
30
20
10
0
18
16
14
12
10
8
3.2 V
4.1 V
3.8 V
4.5 V
10 V
3.5 V
3.2 V
6
4
3 V
2
2.8 V
0
0
1
2
3
0
20
40
60
80
100
V
DS [V]
ID [A]
7 Typ. transfer characteristics
I D=f(V GS); |V DS|>2|I D|R DS(on)max
parameter: T j
8 Typ. forward transconductance
g fs=f(I D); T j=25 °C
100
80
70
60
50
40
30
20
10
0
80
60
40
20
175 °C
25 °C
0
0
1
2
3
4
5
0
10
20
30
40
50
60
I
D [A]
V
GS [V]
Rev. 1.5
page 5
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
GS(th)=f(T j); V GS=V DS
R
DS(on)=f(T j); I D=50 A; V GS=10 V
V
parameter: I D
12
10
2.5
2
1.5
1
300 µA
8
98 %
30 µA
6
typ
4
2
0
0.5
0
-60
-20
20
60
100
140
180
-60
-20
20
60
100
140
180
T j [°C]
T j [°C]
11 Typ. capacitances
12 Forward characteristics of reverse diode
I F=f(V SD
C =f(V DS); V GS=0 V; f =1 MHz
)
parameter: T j
104
1000
25 °C
Ciss
103
102
101
100
10
Coss
175 °C, 98%
175 °C
25 °C, 98%
Crss
1
0
10
20
30
0.0
0.5
1.0
SD [V]
1.5
2.0
V
DS [V]
V
Rev. 1.5
page 6
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
13 Avalanche characteristics
AS=f(t AV); R GS=25 Ω
14 Typ. gate charge
GS=f(Q gate); I D=25 A pulsed
V
I
parameter: Tj(start)
parameter: V DD
100
12
15 V
10
8
5 V
100 °C
25 °C
20 V
150 °C
10
6
4
2
1
1
0
0
10
100
1000
5
10
15
20
25
30
Q
gate [nC]
t
AV [µs]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V
BR(DSS)=f(T j); I D=1 mA
30
28
27
26
24
23
21
20
V GS
Q g
V gs(th)
Q g(th)
Q sw
Q gd
Q gate
Q gs
-60
-20
20
60
100
140
180
T j [°C]
Rev. 1.5
page 7
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
Package Outline
PG-TO252-3-11
Rev. 1.5
page 8
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
Package Outline
PG-TO252-3-23
Rev. 1.5
page 9
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
Package Outline
PG-TO251-3-11
Rev. 1.5
page 10
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
Package Outline
PG-TO251-3-21
Rev. 1.5
page 11
2008-04-14
IPDH6N03LA G IPFH6N03LA G
IPSH6N03LA G IPUH6N03LA G
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of
conditions or characteristics. With respect to any examples or hints given herein, any typical
values stated herein and/or any information regarding the application of the device,
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,
including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please
contact the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information
on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with
the express written approval of Infineon Technologies, if a failure of such components can
reasonably be expected to cause the failure of that life-support device or system or to affect
the safety or effectiveness of that device or system. Life support devices or systems are
intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user
or other persons may be endangered.
Rev. 1.5
page 12
2008-04-14
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