IPG20N04S4-08A [INFINEON]

Power Field-Effect Transistor;
IPG20N04S4-08A
型号: IPG20N04S4-08A
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor

晶体 晶体管 功率场效应晶体管 脉冲 光电二极管
文件: 总9页 (文件大小:158K)
中文:  中文翻译
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IPG20N04S4-08  
OptiMOS-T2 Power-Transistor  
Product Summary  
V DS  
40  
7.6  
20  
V
4)  
mW  
A
R DS(on),max  
I D  
Features  
• Dual N-channel Normal Level - Enhancement mode  
PG-TDSON-8-4  
• AEC Q101 qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green Product (RoHS compliant)  
• 100% Avalanche tested  
Type  
Package  
Marking  
IPG20N04S4-08  
PG-TDSON-8-4 4N0408  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
Continuous drain current  
one channel active  
T C=25 °C, V GS=10 V1)  
I D  
20  
20  
80  
A
T C=100 °C,  
V GS=10 V2)  
Pulsed drain current2)  
one channel active  
I D,pulse  
-
Avalanche energy, single pulse2, 4)  
Avalanche current, single pulse4)  
Gate source voltage  
E AS  
I AS  
I D=10A  
230  
15  
mJ  
A
-
V GS  
-
±20  
V
Power dissipation  
one channel active  
P tot  
T C=25 °C  
65  
W
T j, T stg  
Operating and storage temperature  
-
-55 ... +175  
°C  
Rev. 1.0  
page 1  
2010-10-05  
IPG20N04S4-08  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
R thJA  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
2.3  
K/W  
minimal footprint  
100  
60  
-
-
6 cm2 cooling area3)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS V GS=0 V, I D= 1 mA  
V GS(th) V DS=V GS, I D= 30µA  
Drain-source breakdown voltage  
Gate threshold voltage  
40  
-
-
V
2.0  
3.0  
4.0  
V DS=40 V, V GS=0 V,  
T j=25 °C  
Zero gate voltage drain current4)  
I DSS  
-
-
0.01  
1
1
µA  
V DS=18 V, V GS=0 V,  
T j=85 °C2)  
100  
Gate-source leakage current4)  
I GSS  
V GS=20 V, V DS=0 V  
-
-
-
100 nA  
Drain-source on-state resistance4)  
R DS(on) V GS=10 V, I D=17 A  
7.0  
7.6  
mW  
Rev. 1.0  
page 2  
2010-10-05  
IPG20N04S4-08  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance4)  
Output capacitance4)  
Reverse transfer capacitance4)  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
2260  
555  
17  
2940 pF  
720  
V GS=0 V, V DS=25 V,  
f =1 MHz  
39  
15  
-
-
-
-
ns  
5
V DD=20 V, V GS=10 V,  
I D=20 A, R G=11 W  
t d(off)  
t f  
Turn-off delay time  
Fall time  
20  
13  
Gate Charge Characteristics2, 4)  
Gate to source charge  
Gate to drain charge  
Q gs  
-
-
-
-
12  
4
15  
9
nC  
Q gd  
V DD=32 V, I D=20 A,  
V GS=0 to 10 V  
Q g  
Gate charge total  
28  
5.2  
36  
-
V plateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current2)  
one channel active  
I S  
-
-
-
-
-
-
20  
80  
1.3  
-
T C=25 °C  
Diode pulse current2)  
one channel active  
I S,pulse  
V SD  
t rr  
-
V GS=0 V, I F=17 A,  
T j=25 °C  
Diode forward voltage  
0.9  
36  
34  
V
V R=20 V, I F=I S,  
di F/dt =100 A/µs  
Reverse recovery time2)  
Reverse recovery charge2, 4)  
ns  
nC  
Q rr  
-
1) Current is limited by bondwire; with an R thJC =2.3 K/W the chip is able to carry 71A at 25°C.  
2) Specified by design. Not subject to production test.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
4) Per channel  
Rev. 1.0  
page 3  
2010-10-05  
IPG20N04S4-08  
1 Power dissipation  
2 Drain current  
P tot = f(T C); V GS ≥ 6 V; one channel active  
I D = f(T C); V GS ≥ 6 V; one channel active  
70  
60  
50  
40  
30  
20  
10  
0
25  
20  
15  
10  
5
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T C [°C]  
T C [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
Z thJC = f(t p)  
I D=f(V DS); T C=25°C; D =0; one channel active  
parameter: t p  
parameter: D =t p/T  
101  
100  
1 µs  
10 µs  
100 µs  
0.5  
100  
10  
0.1  
1 ms  
0.05  
10-1  
1
0.01  
single pulse  
10-2  
0.1  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
t p [s]  
V DS [V]  
Rev. 1.0  
page 4  
2010-10-05  
IPG20N04S4-08  
5 Typ. output characteristics4)  
I D = f(V DS); T j = 25 °C  
parameter: V GS  
6 Typ. drain-source on-state resistance4)  
R DS(on) = f(I D); T j = 25 °C  
parameter: V GS  
80  
45  
10 V  
6.5 V  
6.25 V  
5.5 V  
5 V  
6 V  
6 V  
60  
40  
20  
0
35  
25  
15  
5
5.5 V  
5 V  
6.5 V  
10 V  
0
2
4
6
8
0
20  
40  
60  
80  
V DS [V]  
I D [A]  
7 Typ. transfer characteristics4)  
I D = f(V GS); V DS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance4)  
R DS(on) = f(T j); I D = 17 A; V GS = 10 V  
80  
60  
40  
12  
10  
8
20  
6
175 °C  
25 °C  
-55 °C  
0
4
3
4
5
6
7
-60  
-20  
20  
60  
100  
140  
180  
V GS [V]  
T j [°C]  
Rev. 1.0  
page 5  
2010-10-05  
IPG20N04S4-08  
10 Typ. Capacitances4)  
9 Typ. gate threshold voltage  
V GS(th) = f(T j); V GS = V DS  
parameter: I D  
C = f(V DS); V GS = 0 V; f = 1 MHz  
4
3.5  
3
104  
103  
102  
101  
Ciss  
300µA  
Coss  
30µA  
2.5  
2
1.5  
1
Crss  
0
5
10  
15  
20  
25  
30  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
V DS [V]  
11 Typical forward diode characteristicis4)  
IF = f(VSD  
12 Avalanche characteristics4)  
I A S= f(t AV  
)
)
parameter: T j  
parameter: Tj(start)  
102  
100  
25 °C  
100 °C  
101  
10  
150 °C  
25 °C  
175 °C  
100  
0
1
1
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
10  
100  
1000  
V SD [V]  
t AV [µs]  
Rev. 1.0  
page 6  
2010-10-05  
IPG20N04S4-08  
13 Avalanche energy4)  
14 Drain-source breakdown voltage  
E AS = f(T j), I D = 10A  
V BR(DSS) = f(T j); I D = 1 mA  
44  
43  
42  
41  
40  
39  
38  
37  
250  
200  
150  
100  
50  
0
-60  
-20  
20  
60  
100  
140  
180  
25  
50  
75  
100  
125  
150  
175  
T j [°C]  
T j [°C]  
15 Typ. gate charge4)  
16 Gate charge waveforms  
V GS = f(Q gate); I D = 20 A pulsed  
parameter: V DD  
12  
10  
8
V GS  
Q g  
8 V  
32 V  
6
V gs(th)  
4
2
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
0
0
5
10  
15  
20  
25  
30  
Q gate [nC]  
Rev. 1.0  
page 7  
2010-10-05  
IPG20N04S4-08  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2010  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 8  
2010-10-05  
IPG20N04S4-08  
Revision History  
Version  
Date  
Changes  
Revision 1.0  
05.10.2010  
Data Sheet revision 1.0  
Rev. 1.0  
page 9  
2010-10-05  

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