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IQE006NE2LM5CG [INFINEON]

在英飞凌创新的源极底置技术下推出了OptiMOS™ 低压功率MOSFET（IQE006NE2LM5CG）中心门极封装版本。将门极放置在封装的中间位置，从而实现最佳的源极连接。由于中心门极具有更大的漏极至源极爬电距离，因此中心门极封装提供 MOSFET 优化且易于并联的优势。这样，即可在一个 PCB 层上连接多个设备的门极，从而提高电流能力，实现更高的输出电平。此外，源极底置中心门极封装提供高系统效率和高功率密度。;
IQE006NE2LM5CG
型号： IQE006NE2LM5CG
厂家： Infineon    Infineon
描述：

在英飞凌创新的源极底置技术下推出了OptiMOS™ 低压功率MOSFET（IQE006NE2LM5CG）中心门极封装版本。将门极放置在封装的中间位置，从而实现最佳的源极连接。由于中心门极具有更大的漏极至源极爬电距离，因此中心门极封装提供 MOSFET 优化且易于并联的优势。这样，即可在一个 PCB 层上连接多个设备的门极，从而提高电流能力，实现更高的输出电平。此外，源极底置中心门极封装提供高系统效率和高功率密度。

PC
文件： 总13页 (文件大小：1024K)
中文：  中文翻译
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IQE006NE2LM5CG  
MOSFET  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
PG-TTFN-9-1  
1
2
Features  
•ꢀVeryꢀlowꢀon-resistanceꢀRDS(on)  
•ꢀ100%ꢀavalancheꢀtested  
•ꢀSuperiorꢀthermalꢀresistance  
•ꢀN-channel,ꢀlogicꢀlevel  
•ꢀPb-freeꢀleadꢀplating;ꢀRoHSꢀcompliant  
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21  
3
4
9
8
7
6
5
Productꢀvalidation  
FullyꢀqualifiedꢀaccordingꢀtoꢀJEDECꢀforꢀIndustrialꢀApplications  
Drain  
Pin 5-8  
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters  
Parameter  
Value  
Unit  
Gate  
Pin 9  
VDS  
25  
V
Source  
Pin 1-4  
RDS(on),max  
ID  
0.65  
298  
41  
mΩ  
A
Qoss  
nC  
nC  
QG(0V..4.5V)  
29  
Typeꢀ/ꢀOrderingꢀCode  
Package  
Marking  
RelatedꢀLinks  
IQE006NE2LM5CG  
PG-TTFN-9-1  
006E2C5  
-
Final Data Sheet  
1
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
TableꢀofꢀContents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Final Data Sheet  
2
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
1ꢀꢀꢀꢀꢀMaximumꢀratings  
atꢀTA=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
VGS=10ꢀV,ꢀTC=25ꢀ°C  
VGS=10ꢀV,ꢀTC=100ꢀ°C  
-
-
-
-
-
-
298  
188  
41  
Continuous drain current1)  
ID  
A
VGS=4.5ꢀV,ꢀTA=25ꢀ°C,  
RTHJA=60ꢀ°C/W2)  
Pulsed drain current3)  
Avalanche energy, single pulse4)  
ID,pulse  
EAS  
-
-
-
-
1192  
140  
16  
A
TA=25ꢀ°C  
-
mJ  
V
ID=20ꢀA,ꢀRGS=25ꢀΩ  
Gate source voltage  
VGS  
-16  
-
-
-
-
-
89  
2.1  
TC=25ꢀ°C  
Power dissipation  
Ptot  
W
TA=25ꢀ°C,ꢀRTHJA=60ꢀ°C/W2)  
IEC climatic category; DIN IEC 68-1:  
55/150/56  
Operating and storage temperature  
Tj,ꢀTstg  
-55  
-
150  
°C  
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Values  
Typ.  
-
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Thermal resistance, junction - case  
RthJC  
RthJA  
-
1.4  
°C/W -  
°C/W -  
Device on PCB,  
6 cm² cooling area  
-
-
60  
1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature  
at 25°C. For higher case temperature please refer to Diagram 2. De-rating will be required based on the actual  
environmental conditions.  
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
3) See Diagram 3 for more detailed information  
4) See Diagram 13 for more detailed information  
Final Data Sheet  
3
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics  
atꢀTj=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics  
Values  
Typ.  
-
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
25  
Max.  
Drain-source breakdown voltage  
Gate threshold voltage  
V(BR)DSS  
VGS(th)  
-
V
V
VGS=0ꢀV,ꢀID=1ꢀmA  
1.2  
1.6  
2
VDS=VGS,ꢀID=250ꢀµA  
-
-
0.1  
10  
1
100  
VDS=20ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C  
VDS=20ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C  
Zero gate voltage drain current  
Gate-source leakage current  
Drain-source on-state resistance  
IDSS  
µA  
nA  
IGSS  
-
10  
100  
VGS=16ꢀV,ꢀVDS=0ꢀV  
-
-
0.50  
0.65  
0.65  
0.80  
VGS=10ꢀV,ꢀID=20ꢀA  
VGS=4.5ꢀV,ꢀID=20ꢀA  
RDS(on)  
mΩ  
Gate resistance1)  
Transconductance  
RG  
gfs  
-
-
0.7  
1.2  
-
Ω
-
220  
S
|VDS|≥2|ID|RDS(on)max,ꢀID=20ꢀA  
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Input capacitance1)  
Output capacitance1)  
Reverse transfer capacitance1)  
Ciss  
Coss  
Crss  
-
-
-
4100 5453 pF  
1700 2261 pF  
VGS=0ꢀV,ꢀVDS=12ꢀV,ꢀf=1ꢀMHz  
VGS=0ꢀV,ꢀVDS=12ꢀV,ꢀf=1ꢀMHz  
VGS=0ꢀV,ꢀVDS=12ꢀV,ꢀf=1ꢀMHz  
130  
5.3  
195  
-
pF  
ns  
VDD=12ꢀV,ꢀVGS=4.5ꢀV,ꢀID=20ꢀA,  
RG,ext=1.6ꢀΩ  
Turn-on delay time  
Rise time  
td(on)  
tr  
td(off)  
tf  
-
-
-
-
VDD=12ꢀV,ꢀVGS=4.5ꢀV,ꢀID=20ꢀA,  
RG,ext=1.6ꢀΩ  
2.6  
-
-
-
ns  
ns  
ns  
VDD=12ꢀV,ꢀVGS=4.5ꢀV,ꢀID=20ꢀA,  
RG,ext=1.6ꢀΩ  
Turn-off delay time  
Fall time  
27.0  
5.3  
VDD=12ꢀV,ꢀVGS=4.5ꢀV,ꢀID=20ꢀA,  
RG,ext=1.6ꢀΩ  
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ  
Values  
Typ.  
9.2  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge1)  
Switching charge  
Qgs  
-
-
-
-
-
-
-
-
-
-
nC  
nC  
nC  
nC  
nC  
V
VDD=12ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=12ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=12ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=12ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=12ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=12ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ4.5ꢀV  
VDD=12ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDS=0.1ꢀV,ꢀVGS=0ꢀtoꢀ10ꢀV  
Qg(th)  
Qgd  
5.8  
-
5.6  
8.4  
Qsw  
9.0  
-
Gate charge total1)  
Qg  
28.5  
2.2  
37.9  
Gate plateau voltage  
Gate charge total1)  
Vplateau  
Qg  
-
61.7  
60.4  
41.3  
82.1  
nC  
nC  
nC  
Gate charge total, sync. FET  
Output charge  
Qg(sync)  
Qoss  
-
-
VDD=12ꢀV,ꢀVGS=0ꢀV  
1) Defined by design. Not subject to production test.  
2) See ″Gate charge waveforms″ for parameter definition  
Final Data Sheet  
4
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode  
Values  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Typ.  
-
Max.  
83  
Diode continuous forward current  
Diode pulse current  
IS  
-
-
-
-
A
TC=25ꢀ°C  
IS,pulse  
VSD  
Qrr  
-
1192  
1
A
TC=25ꢀ°C  
Diode forward voltage  
0.75  
25  
V
VGS=0ꢀV,ꢀIF=20ꢀA,ꢀTj=25ꢀ°C  
VR=12ꢀV,ꢀIF=20ꢀA,ꢀdiF/dt=100ꢀA/µs  
Reverse recovery charge  
-
nC  
Final Data Sheet  
5
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams  
Diagramꢀ1:ꢀPowerꢀdissipation  
Diagramꢀ2:ꢀDrainꢀcurrent  
100  
350  
300  
250  
200  
150  
100  
50  
80  
60  
40  
20  
0
0
0
20  
40  
60  
80  
100  
120  
140  
160  
0
20  
40  
60  
80  
100  
120  
140  
160  
TCꢀ[°C]  
TCꢀ[°C]  
Ptot=f(TC)  
ID=f(TC);ꢀVGS≥10ꢀV  
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea  
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance  
104  
101  
single pulse  
0.01  
0.02  
0.05  
0.1  
103  
1 µs  
0.2  
0.5  
10 µs  
10 ms  
102  
100  
10-1  
10-2  
100 µs  
101  
100  
1 ms  
DC  
10-1  
10-2  
10-1  
100  
101  
102  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
VDSꢀ[V]  
tpꢀ[s]  
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp  
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T  
Final Data Sheet  
6
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics  
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
1200  
1.50  
3 V  
2.8 V  
4 V  
4.5 V  
3.5 V  
1000  
800  
600  
400  
200  
0
1.25  
5 V  
10 V  
1.00  
0.75  
0.50  
0.25  
0.00  
3.5 V  
4 V  
4.5 V  
3 V  
5 V  
10 V  
2.8 V  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
0
100  
200  
300  
400  
500  
600  
VDSꢀ[V]  
IDꢀ[A]  
ID=f(VDS),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS  
RDS(on)=f(ID),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS  
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics  
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
1200  
1.50  
1000  
800  
600  
400  
200  
1.25  
1.00  
150 °C  
0.75  
0.50  
0.25  
0.00  
25 °C  
150 °C  
25 °C  
0
0
1
2
3
4
5
0
2
4
6
8
10  
VGSꢀ[V]  
VGSꢀ[V]  
ID=f(VGS),ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj  
RDS(on)=f(VGS),ꢀID=20ꢀA;ꢀparameter:ꢀTj  
Final Data Sheet  
7
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance  
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage  
1.6  
2.00  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
1.75  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
0.00  
2500 µA  
250 µA  
-80  
-40  
0
40  
80  
120  
160  
-80  
-40  
0
40  
80  
120  
160  
Tjꢀ[°C]  
Tjꢀ[°C]  
RDS(on)=f(Tj),ꢀID=20ꢀA,ꢀVGS=10ꢀV  
VGS(th=f(Tj),ꢀVGS=VDS;ꢀparameter:ꢀID  
Diagramꢀ11:ꢀTyp.ꢀcapacitances  
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode  
104  
104  
25 °C  
25 °C, max  
150 °C  
150 °C, max  
Ciss  
Coss  
103  
102  
101  
103  
102  
101  
Crss  
0
5
10  
15  
20  
25  
0.00  
0.25  
0.50  
0.75  
1.00  
1.25  
1.50  
VDSꢀ[V]  
VSDꢀ[V]  
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz  
IF=f(VSD);ꢀparameter:ꢀTj  
Final Data Sheet  
8
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
Diagramꢀ13:ꢀAvalancheꢀcharacteristics  
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge  
102  
10  
5 V  
12 V  
20 V  
8
6
4
2
0
25 °C  
101  
100 °C  
125 °C  
100  
100  
101  
102  
103  
0
10  
20  
30  
40  
50  
60  
70  
tAVꢀ[µs]  
Qgateꢀ[nC]  
IAS=f(tAV);ꢀRGS=25ꢀΩ;ꢀparameter:ꢀTj,start  
VGS=f(Qgate),ꢀID=20ꢀAꢀpulsed,ꢀTj=25ꢀ°C;ꢀparameter:ꢀVDD  
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage  
Diagram Gate charge waveforms  
28  
27  
26  
25  
24  
23  
-80  
-40  
0
40  
80  
120  
160  
Tjꢀ[°C]  
VBR(DSS)=f(Tj);ꢀID=1ꢀmA  
Final Data Sheet  
9
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
5ꢀꢀꢀꢀꢀPackageꢀOutlines  
MILLIMETERS  
DIMENSION  
DOCUMENT NO.  
Z8B00192161  
MIN.  
-
MAX.  
1.10  
0.05  
0.40  
0.52  
A
A1  
b
REVISION  
03  
-
0.20  
0.32  
b1  
c
0.20  
3.30  
SCALE 10:1  
D
2mm  
0
1
D1  
D2  
E
2.31  
1.58  
2.51  
1.78  
3.30  
EUROPEAN PROJECTION  
E1  
e
1.50  
1.70  
0.65  
e1  
L
0.395  
0.35  
0.10  
0.40  
1.285  
0.73  
0.55  
0.30  
0.60  
1.485  
0.93  
L1  
L2  
L3  
L4  
ISSUE DATE  
08.11.2019  
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TTFN-9-1,ꢀdimensionsꢀinꢀmm  
Final Data Sheet  
10  
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
3.6  
12  
Figureꢀ2ꢀꢀꢀꢀꢀOutlineꢀTapeꢀ(PG-TTFN-9-1),ꢀdimensionsꢀinꢀmm  
Final Data Sheet  
11  
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
1.629  
1.059  
0.15  
0.35  
8x  
0.595  
1.1  
0.3  
6x  
0.975  
0.3  
4x  
1.06  
2x  
1.6  
0.42  
2x  
0.65  
6x  
0.3  
4x  
0.475  
0.65  
6x  
1.1  
4x  
Pin 1  
0.365  
0.055  
2x  
1.35  
1.15  
0.975  
0.615  
copper  
solder mask  
All dimensions are in units mm  
stencil apertures  
Figureꢀ3ꢀꢀꢀꢀꢀOutlineꢀBoardpadꢀ(PG-TTFN-9-1),ꢀdimensionsꢀinꢀmm  
Final Data Sheet  
12  
Rev.ꢀ2.1,ꢀꢀ2020-03-16  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ25ꢀV  
IQE006NE2LM5CG  
RevisionꢀHistory  
IQE006NE2LM5CG  
Revision:ꢀ2020-03-16,ꢀRev.ꢀ2.1  
Previous Revision  
Revision Date  
Subjects (major changes since last revision)  
2.0  
2.1  
Release of final version  
2019-12-06  
2020-03-16  
Update footnotes and marking  
Trademarks  
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Final Data Sheet  
13  
Rev.ꢀ2.1,ꢀꢀ2020-03-16  

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IQE006NE2LM5CGSC

 英飞凌推出了创新型 源极底置 技术系列扩展的新产品， PQFN 3.3x3.3 源极底置 DSC 封装OptiMOSTM 5 25 V：IQE006NE2LM5CGSC。革命性的源极底置技术引入了倒置式硅芯片，该芯片在组件内部上下颠倒。这种调整使得源极电位（而不是漏极电位）可以通过导热垫与 PCB 连接。因此，它具有几点优势，如热能力增强，先进的功率密度，或具有改善板上布局的可能性。
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IQE008N03LM5

 IQE008N03LM5 是英飞凌对创新性 源极底置 技术的延伸。 OptiMOS™ 5 30V  PQFN 3.3x3.3 源极底置具有 30 V 和极低 0.85 mOhm RDS(on)。革命性的源极底置技术使硅片倒置在元件内部。调整后，源极电位（而非漏极电位）即可通过导热垫连接到 PCB。这样就能提供多项优势，如增强热性能、高功率密度和改善布局。此外，更高的效率、更低的主动散热要求及有效的热管理布局有利于实现系统级优势。RDS(on) 新标杆和创新布局能力使 源极底置 概念在温度管理方面处于领先地位。源极底置产品组合解决了各种应用问题，包括 电机驱动、 电信、 SMPS  或 服务器。目前，有两种不同的产品尺寸采用了这项新技术：源极底置标准栅极和源极底置置中栅极（并行优化）。
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IQE008N03LM5CG

 IQE008N03LM5CG 是英飞凌对创新性 源极底置 技术的延伸。 OptiMOS™ 5 30 V PQFN 3.3x3.3 源极底置具有 30 V 和极低 0.85 mOhm RDS(on)。革命性的源极底置技术使硅片倒置在元件内部。调整后，源极电位（而非漏极电位）即可通过导热垫连接到 PCB。这样就能提供多项优势，如增强热性能、高功率密度和改善布局。此外，更高的效率、更低的主动散热要求及有效的热管理布局有利于实现系统级优势。RDS(on) 新标杆和创新布局能力使 源极底置 概念在温度管理方面处于领先地位。源极底置产品组合解决了各种应用问题，包括 电机驱动、 电信、 SMPS  或 服务器。目前，有两种不同的产品尺寸采用了这项新技术：源极底置标准栅极和源极底置置中栅极（并行优化）。
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IQE013N04LM6

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IQE013N04LM6CG

 IQE013N04LM6，这款 1.35mOhm 的 40V OptiMOS™ 功率 MOSFET 扩展了英飞凌的创新型 Source-Down  产品系列，采用 3.3x3.3 PQFN 封装。该功率 MOSFET 是同类中的佼佼者，突破业界目前的功率密度和形状因数，优化了终端用户的体验。
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IQE013N04LM6CGSC

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IQE013N04LM6SC

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IQE022N06LM5

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IQE022N06LM5CG

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IQE022N06LM5CGSC

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IQE022N06LM5SC

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