IR2189 [INFINEON]
Half Bridge Based MOSFET Driver, 0.35A, CMOS, PDIP8, PLASTIC, DIP-8;
| 型号： | IR2189 |
| 厂家： | 
Infineon |
| 描述： | Half Bridge Based MOSFET Driver, 0.35A, CMOS, PDIP8, PLASTIC, DIP-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总9页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Data Sheet No. PD60163-K
IR2109/IR21094
IR2189
HIGH AND LOW SIDE DRIVER
Features
•
Product Summary
Floating channel designed for bootstrap operation
Fully operational to +600V
V
600V max.
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
(IR2109(4)) or 5 - 20V (2189)
Undervoltage lockout for both channels
5V Schmitt triggered input logic
OFFSET
I +/-
O
120 mA / 250 mA
•
V
10 - 20V
5 - 20V
OUT
•
•
•
•
•
•
•
(IR2109(4))
(IR2189)
Cross-conduction prevention logic
Matched propagation delay for both channels
High side output in phase with IN input
Logic and power ground +/- 5V offset.
Internal 500ns dead-time, and programmable
t
(typ.)
180 ns
500 ns
on/off
Delay matching
(programmable up to 5uS for IR21094)
up to 5us with one external R resistor (IR21094)
DT
Lower di/dt gate driver for better noise immunity
Shut down input turns off both channels.
•
•
Packages
Description
The IR2109(4)/IR2189 are high voltage, high speed
power MOSFET and IGBT drivers with dependant high
and low side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction.The logic input is
compatible with standard CMOS or LSTTL output. The
output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. The
floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high side configura-
8 Lead SOIC
14 Lead SOIC
14 Lead PDIP
8 Lead PDIP
tion which operates up to 600 volts.
Typical Connection
up to 600V
VCC
VCC
IN
VB
HO
VS
IN
TO
LOAD
SD
SD
COM
LO
up to 600V
IR21094
HO
VB
VS
IR2109/IR2189
VCC
IN
VCC
IN
TO
LOAD
SD
DT
VSS
SD
COM
LO
VSS
RDT
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1
IR2109 / IR21094 / IR2189
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
High side floating absolute voltage
High side floating supply offset voltage
High side floating output voltage
Min.
Max.
Units
V
-0.3
625
B
S
V
V
B
- 25
V
+ 0.3
+ 0.3
25
B
V
HO
V
CC
V
S
- 0.3
V
B
Low side and logic fixed supply voltage
Low side output voltage
-0.3
-0.3
V
V
LO
V
V
V
V
+ 0.3
+ 0.3
+ 0.3
+ 0.3
CC
CC
CC
CC
DT
Programmable dead-time pin voltage (IR21094 only)
Logic input voltage (IN & SD)
V
- 0.3
SS
SS
CC
V
IN
V
V
- 0.3
- 25
V
SS
Logic ground (IR21094/IR21894 only)
Allowable offset supply voltage transient
dV /dt
—
50
V/ns
W
S
P
D
Package power dissipation @ T ≤ +25°C (8 Lead PDIP)
—
—
—
—
—
—
—
—
—
-50
—
1.0
0.625
1.6
A
(8 Lead SOIC)
(14 lead PDIP)
(14 lead SOIC)
1.0
Rth
Thermal resistance, junction to ambient
(8 Lead PDIP)
(8 Lead SOIC)
(14 lead PDIP)
(14 lead SOIC)
125
200
75
JA
°C/W
°C
120
150
150
300
T
T
Junction temperature
J
Storage temperature
S
T
Lead temperature (soldering, 10 seconds)
L
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2
IR2109 / IR21094 / IR2189
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V and V offset rating are tested with all supplies biased at 15V differential.
S
SS
Symbol
Definition
Min.
Max.
Units
VB
High side floating supply absolute voltage
IR2109(4)
IR2189
V
+ 10
V
V
+ 20
+ 20
S
S
V
+ 5
S
S
V
High side floating supply offset voltage
High side floating output voltage
Note 1
600
S
V
V
HO
V
V
B
S
V
CC
Low side and logic fixed supply voltage
IR2109(4)
IR2189
10
5
20
20
V
Low side output voltage
0
V
°C
LO
CC
CC
V
Logic input voltage (IN & SD)
V
V
V
IN
SS
SS
DT
Programmable dead-time pin voltage (IR21094 only)
Logic ground (IR21094 only)
V
CC
5
V
-5
SS
T
A
Ambient temperature
-40
125
Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V
.
S
S
BS
Dynamic Electrical Characteristics
V
(V , V ) = 15V, V = COM, C = 1000 pF, T = 25°C, DT = VSS unless otherwise specified.
BIAS CC BS
L
A
SS
Symbol
Definition
Min. Typ. Max. Units Test Conditions
t
t
t
Turn-on propagation delay
—
—
—
—
—
—
680
170
180
0
900
250
270
—
V = 0V
S
on
off
sd
Turn-off propagation delay
V
S
= 0V or 600V
Shut-down propagation delay
MT
Delay matching, HS & LS turn-on/off
nsec
t
t
Turn-on rise time
150
50
220
80
V
V
= 0V
= 0V
r
S
Turn-off fall time
f
S
DT
Deadtime: LO turn-off to HO turn-on(DT
380
4
500
5
620
6
RDT= 0
LO-HO)
HO turn-off to LO turn-on (DT
usec
nsec
RDT = 200k (IR21094)
RDT=0
HO-LO)
HO-LO
MDT
Deadtime matching = DT
- DT
—
0
60
LO - HO
—
0
600
RDT = 200k (IR21094)
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3
IR2109 / IR21094 / IR2189
Static Electrical Characteristics
V
(V , V ) = 15V, V = COM, DT= V
and T = 25°C unless otherwise specified.The V , V and I
SS A IL IH IN
BIAS
CC BS
SS
parameters are referenced to V /COM and are applicable to the respective input leads: IN and SD. The V , I and Ron
SS
O O
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
Logic “1” input voltage for HO & logic “0” for LO
2.7
—
—
0.8
—
V
V
V
V
= 10V to 20V
= 10V to 20V
= 10V to 20V
= 10V to 20V
IH
CC
CC
CC
CC
V
Logic “0” input voltage for HO & logic “1” for LO
—
—
IL
V
—
SD,TH+
SD input positive going threshold
SD input negative going threshold
2.7
—
V
V
—
0.8
1.4
0.6
50
SD,TH-
V
OH
High level output voltage, V
- V
—
—
0.8
0.3
—
I
I
= 20 mA
= 20 mA
BIAS
O
O
O
V
OL
Low level output voltage, V
O
I
LK
Offset supply leakage current
Quiescent V supply current
—
V
= V = 600V
B
S
µA
I
20
0.4
60
1.0
150
1.6
V
= 0V or 5V
= 0V or 5V
QBS
QCC
BS
IN
IN
I
Quiescent V
supply current
mA
V
CC
RDT = 0
I
Logic “1” input bias current
Logic “0” input bias current
—
—
5
1
20
2
IN = 5V, SD = 0V
IN = 0V, SD = 5V
IN+
µA
I
IN-
V
V
and V supply undervoltage positive going
CC BS
CCUV+
V
threshold
IR2109(4)
IR2189
8.0
3.8
8.9
4.4
9.8
5.0
BSUV+
V
V
and V dupply undervoltage negative going
CC BS
CCUV-
V
V
threshold
IR2109(4)
IR2189
7.4
3.5
0.3
8.2
4.1
0.7
9.0
4.7
—
BSUV-
V
Hysteresis
IR2109(4)
CCUVH
V
IR2189
0.1
120
250
0.3
200
350
—
—
—
BSUVH
I
Output high short circuit pulsed vurrent
Output low short circuit pulsed current
V
= 0V, PW ≤ 10 µs
= 15V,PW ≤ 10 µs
O+
O
mA
I
O-
V
O
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4
IR2109 / IR21094 / IR2189
Functional Block Diagrams
VB
UV
DETECT
IR2109/IR2189
HO
R
Q
R
S
PULSE
FILTER
HV
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFT
IN
VS
PULSE
GENERATOR
VCC
LO
DEADTIME
UV
DETECT
+5V
VSS/COM
LEVEL
SHIFT
DELAY
S D
C O M
VB
UV
IR21094
DETECT
HO
R
R
S
Q
PULSE
FILTER
HV
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFT
IN
VS
PULSE
GENERATOR
VCC
LO
DEADTIME
DT
UV
DETECT
+5V
VSS/COM
LEVEL
SHIFT
DELAY
SD
C O M
VSS
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5
IR2109 / IR21094 / IR2189
Lead Definitions
Symbol Description
IN
Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM
for IR2109/IR2189 and VSS for IR21094)
Logic input for shutdown (referenced to COM for IR2109/IR2189 and VSS for IR21094)
Programmable dead-time lead, referenced to VSS. (IR21094 only)
Logic Ground (21094 only)
SD
DT
VSS
V
High side floating supply
B
HO
High side gate drive output
V
V
High side floating supply return
S
Low side and logic fixed supply
CC
LO
Low side gate drive output
COM
Low side return
Lead Assignments
V
V
1
2
3
4
V
B
8
7
1
2
3
4
V
B
8
7
CC
CC
HO
HO
IN
IN
V
S
V
S
SD
6
5
SD
6
5
LO
LO
COM
COM
8 Lead PDIP
8 Lead SOIC
IR2109/IR2189
IR2109S/IR2189S
14
13
12
11
10
9
14
13
12
11
10
9
1
V
1
2
3
4
5
6
7
V
CC
CC
V
V
2
3
4
5
6
7
IN
B
IN
B
HO
HO
SD
SD
V
S
V
S
DT
DT
VSS
COM
LO
VSS
COM
LO
8
8
14 Lead PDIP
14 Lead SOIC
IR21094
IR21094S
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6
IR2109 / IR21094 / IR2189
Case Outlines
8 Lead PDIP
01-3003 01
(MS-012AA) 01-0021 09
8 Lead SOIC
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7
IR2109 / IR21094 / IR2189
14 Lead PDIP
01-3002 03
14 Lead SOIC (narrow body)
01-3063 00
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8
IR2109 / IR21094 / IR2189
IN
IN(LO)
50%
50%
t
SD
IN(HO)
t
t
t
f
on
off
r
90%
90%
HO
LO
LO
HO
10%
10%
Figure 1. Input/Output Timing Diagram
Figure 2. Switching Time Waveform Definitions
SD
50%
50%
50%
IN
t
sd
90%
HO
LO
90%
DT
10%
HO
LO
LO-HO
DT
HO-LO
10%
90%
Figure 3. Shutdown Waveform Definitions
IN(LO)
MDT=
DT
- DT
LO-HO
HO-LO
50%
50%
IN(HO)
Figure 4. Deadtime Waveform Definitions
LO
HO
10%
MT
MT
90%
LO
HO
Figure 5. Delay Matching Waveform Definitions
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd., Whyteleafe, Surrey CR3 0BL, United Kingdom
Tel: ++ 44 (0) 20 8645 8000
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 171-0021 Tel: 8133 983 0086
IR HONG KONG: Unit 308, #F, New East Ocean Centre, No. 9 Science Museum Road, Tsimshatsui East, Kowloon
Hong Kong Tel: (852) 2803-7380
Data and specifications subject to change without notice. 4/17/2000
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9
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