IR2213PBF_15_技术文档

IR2213(S)PBF

High and Low Side Driver

Features

Product Summary



Floating channel designed for bootstrap operation

Fully operational to +1200 V

V_OFFSET(max)

1200 V

1.7 A / 2 A

12 V – 20 V

280 ns / 225 ns

30 ns

Tolerant to negative transient voltage

dV/dt immune

Gate drive supply range from 12 V to 20 V

Undervoltage lockout for both channels

3.3 V logic compatible

Separate logic supply range from 3.3 V to 20 V

Logic and power ground ±5 V offset

CMOS Schmitt-triggered inputs with pull-down

Cycle by cycle edge-triggered shutdown logic

Matched propagation delay for both channels

Outputs in phase with inputs

I

O+/-

V

OUT

t_on/off(typical)

Delay Matching

Description

Package Options

The IR2213(S) is a high voltage, high speed power

MOSFET and IGBT driver with independent high and low

side referenced output channels. Proprietary HVIC and

latch immune CMOS technologies enable ruggedized

monolithic construction. Logic inputs are compatible with

standard CMOS or LSTTL outputs, down to 3.3 V logic.

The output drivers feature a high pulse current buffer stage

designed

for

minimum

driver

cross-conduction.

Propagation delays are matched to simplify use in high

frequency applications. The floating channel can be used

to drive an N-channel power MOSFET or IGBT in the high

side configuration which operates up to 1200 V.

16 Lead SOIC

(Wide Body)

14 Lead PDIP

Ordering Information

Standard Pack

Base Part Number

Package Type

Orderable Part Number

Form

Quantity

45

IR2213SPBF

IR2213PBF

SO16WB

PDIP14

Tube

Tape and Reel

Tube

IR2213SPBF

IR2213STRPBF

IR2213PBF

1000

25

1

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February 4, 2014

IR2213(S)PBF

Typical Connection Diagram

Refer to Lead Assignments for correct pin configuration. This/These diagram(s) show electrical connections

only. Please refer to our Application Notes and Design Tips for proper circuit board layout

2

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February 4, 2014

IR2213(S)PBF

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are

measured under board mounted and still air conditions.

Symbol

V_B

Definition

Min.

-0.3

Max.

1225

Units

High Side Floating Supply Voltage

High Side Floating Supply Offset Voltage

High Side Floating Output Voltage

Low Side Fixed Supply Voltage

Low Side Output Voltage

V_S

V_B- 25

V_S- 0.3

-0.3

V_B+ 0.3

25

V_HO

V_CC

V_LO

V

-0.3

V_CC+ 0.3

V_SS+ 25

V_CC+ 0.3

V_DD+ 0.3

50

V_DD

V_SS

Logic Supply Voltage

-0.3

Logic Supply Offset Voltage

V_CC- 25

V_SS- 0.3

—

V_IN

Logic Input Voltage (HIN, LIN & SD)

Allowable Offset Supply Voltage Transient (Figure 2)

dV /dt

s

V/ns

W

Package Power Dissipation

@ T_A≤ +25˚C

(14 Lead PIDP)

(16 Lead SOIC)

(14 Lead PDIP)

(16 Lead SOIC)

—

1.6

1.25

75

100

P_D

Thermal Resistance, Junction to

Ambient

°C/W

°C

R_THJA

Junction Temperature

StorageTemperature

T_J

T_S

T_L

—

125

-55

150

Lead Temperature (Soldering, 10 seconds)

—

300

Recommended Operating Conditions

The Input / Output logic timing diagram is shown in Figure 1. For proper operation the device should be used

within the recommended conditions. The V_Sand V_SSoffset ratings are tested with all supplies biased at 15 V

differential.

Symbol

V_B

Definition

Min.

Max.

V_S+ 20

1200

V_B

Units

High Side Floating Supply Absolute Voltage

High Side Floating Supply Offset Voltage

High Side Floating Output Voltage

Low Side Fixed Supply Voltage

Low Side Output Voltage

V_S+ 12

†

V_S

V_HO

V_CC

V_LO

V_S

12

20

V

0

V_CC

V_DD

V_SS

Logic Supply Voltage

V_SS+ 3

-5 ^††

V_SS

V_SS+ 20

5

Logic Supply Offset Voltage

Logic Input Voltage (HIN, LIN & SD)

V_IN

V_DD

Logic operational for V_Sof -5 to +1200V. Logic state held for V_Sof -5V to -V_BS. (Please refer to the Design Tip DT97-

3 for more details).

†

When V_DD<5V, the minimum V_SSoffset is limited to -V_DD

††

3

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February 4, 2014

IR2213(S)PBF

Dynamic Electrical Characteristics

V_BIAS(V_CC, V_BS, V_DD) = 15 V, C_L= 1000 pF, T_A= 25 °C and V_SS= COM unless otherwise specified. The dynamic

electrical characteristics are measured using the test circuit shown in Figure 3.

Symbol Definition

Min.

—

Typ.

280

225

Max.

—

Units

Test Conditions

V_S= 0V

Turn-On Propagation Delay

t

on

t

off

Turn-Off Propagation Delay

—

V_S= 1200V

t_sd

Shutdown Propagation Delay

Turn-On Rise Time

—

230

25

—

ns

t

r

Turn-Off Fall Time

17

t

f

Delay Matching, HS & LS Turn-

On/Off

MT

—

30

Static Electrical Characteristics

V_BIAS(V_CC, V_BS, V_DD) = 15 V, T_A= 25 °C and V_SS= COM unless otherwise specified. The V_IN, V_THand I_IN

parameters are referenced to V_SSand are applicable to all three logic input leads: HIN, LIN and SD. The V_Oand

I_Oparameters are referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol Definition

Min.

9.5

—

Typ.

—

Max. Units

Test Conditions

V_IH

V_IL

Logic ―1‖ Input Voltage

—

Logic ―0‖ Input Voltage

—

6.0

V

V_OH

V_OL

I_LK

High Level Output Voltage, V_BIAS- V_O

Low Level Output Voltage, V_O

Offset Supply Leakage Current

Quiescent V_BSSupply Current

Quiescent V_CCSupply Current

Quiescent V_DDSupply Current

Logic ―1‖ Input Bias Current

Logic ―0‖ Input Bias Current

—

1.2

I_O= 0A

—

0.1

50

—

V_B= V_S= 1200V

V_IN= 0V or V_DD

V_IN= V_DD

I_QBS

I_QCC

I_QDD

I_IN+

—

125

180

15

230

—

340

µA

—

30

40

—

20

I_IN-

—

1.0

V_IN= 0V

V_BSSupply Undervoltage Positive

Going Threshold

V_BSUV+

V_BSUV-

V_CCUV+

V_CCUV-

I_O+

8.7

7.9

8.7

7.9

1.7

2.0

10.2

9.3

11.7

V_BSSupply Undervoltage Negative

Going Threshold

10.7

V

V_CCSupply Undervoltage Positive

Going Threshold

10.2

9.3

11.7

10.7

V_CCSupply Undervoltage Negative

Going Threshold

Output High Short Circuit Pulsed

Current

V_O= 0V,V_IN= V_DD

2.0

—

PW

≤ 10 µs

A

V_O= 15V, V_IN= 0V

Output Low Short Circuit Pulsed

Current

I_O-

2.5

—

PW

≤ 10 µs

4

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February 4, 2014

IR2213(S)PBF

Functional Block Diagram

5

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February 4, 2014

IR2213(S)PBF

Lead Definitions

Symbol Description

V_DD

HIN

SD

Logic Supply

Logic Input for High Side Gate Driver Output (HO), In Phase

Logic Input for Shutdown

LIN

Logic Input for Low Side Gate Driver Output (LO), In Phase

V_SS

V_B

HO

V_S

V_CC

LO

COM

Logic Ground

High Side Floating Supply

High Side Gate Drive Output

High Side Floating Supply Return

Low Side Supply

Low Side Gate Drive Output

Low Side Return

Lead Assignments

HO

7

8

HO

9

8

7

6

5

4

3

2

1

V_DD

HIN

9

V_B

V_S

6

5

4

3

2

1

10

11

12

13

14

V_B

V_S

10

11

12

13

14

V_DD

HIN

SD

LIN

V_SS

V_CC

COM

LO

SD

LIN

V_SS

V_CC

COM

LO

15

16

14-Lead PDIP

16-Lead SOIC

(Wide Body)

6

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February 4, 2014

IR2213(S)PBF

Application Information and Additional Information

V_CC= 15V

HV = 10 to 1200V

200µH

+ 100µF

10KF6

0.1µF

10µF

0.1µF

V_DDV_CCV_B

V_S

HIN

HO

LO

SD

dV_S

dt

<50 V/ns

LIN

OUTPUT

MONITOR

10KF6

V_SSCOM

IRF820

Figure 1. Input / Output Timing Diagram

Figure 2. Floating Supply Voltage Transient Test Circuit

V_CC= 15V

V_B

+

0.1µF

10µF

0.1µF

C_L

10µF

15V

-

V_S

V_DDV_CCV_B

V_S

10µF

HIN

(0 to 1200V)

HIN

HO

LO

HO

LO

SD

LIN

C_L

V_SSCOM

Figure 3. Switching Time Test Circuit

Figure 4. Switching Time Waveform Definition

Figure 5. Shutdown Waveform Definitions

Figure 6. Delay Matching Waveform Definitions

7

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February 4, 2014

IR2213(S)PBF

Figure 7A. Turn-On Rise Time vs. Temperature

Figure 8A. Turn-Off Fall Time vs. Temperature

Figure 9A. Logic “1” Input Threshold vs. Temperature

Figure 7B. Turn-On Rise Time vs. Voltage

Figure 8B. Turn-Off Fall Time vs. Voltage

Figure 9B. Logic “1” Input Threshold vs. Voltage

8

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February 4, 2014

IR2213(S)PBF

Figure 10A. Logic “0” Input Threshold vs. Temperature

Figure 10B. Logic “0” Input Threshold vs. Voltage

Figure 11A. High Level Output vs. Temperature

Figure 11B. High Level Outputs vs. Voltage

Figure 12A. Low Level Output vs. Temperature

Figure 12B. Low Level Output vs. Voltage

9

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February 4, 2014

IR2213(S)PBF

Figure 13A. Offset Supply Current vs. Temperature

Figure 13B. Offset Supply Current vs. Voltage

Figure 14A. V_BSSupply Current vs. Temperature

Figure 14B. V_BSSupply Current vs. Voltage

Figure 15A. V_CCSupply Current vs. Temperature

Figure 15B. V_CCSupply Current vs. Voltage

10 www.irf.com

February 4, 2014

IR2213(S)PBF

Figure 16A. V_DDSupply Current vs. Temperature

Figure 16B. V_DDSupply Current vs. V_DDVoltage

Figure 17A. Logic “1” Input Current vs. Temperature

Figure 17B. Logic “1” Input Current vs. V_DDVoltage

Figure 18A. Logic “0” Input Current vs. Temperature

Figure 18B. Logic “0” Input Current vs. V_DDVoltage

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February 4, 2014

IR2213(S)PBF

Figure 19. Maximum V_SNegative Offset vs. V_BSSupply

Voltage

Figure 20. Maximum V_SSPositive Offset vs. V_CCSupply

Voltage

Figure 21. IR2213S vs. Frequency (IRFBC20)

Figure 22. IR2213S vs. Frequency (IRFBC30)

R_gate=33Ω, V_CC=15V

R_gate=22Ω, V_CC=15V

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February 4, 2014

IR2213(S)PBF

Figure 23. IR2213S vs. Frequency (IRFBC40)

Figure 24. IR2213S vs. Frequency (IRFBC50)

R_gate=15Ω, V_CC=15V

R_gate=10Ω, V_CC=15V

Figure 25. IR2213 vs. Frequency (IRFBC20)

Figure 26. IR2213 vs. Frequency (IRFBC30)

R_gate=33Ω, V_CC=15V

R_gate=22Ω, V_CC=15V

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February 4, 2014

IR2213(S)PBF

Figure 27. IR2213 vs. Frequency (IRFBC40)

Figure 28. IR2213 vs. Frequency (IRFBC50)

R_gate=15Ω, V_CC=15V

R_gate=10Ω, V_CC=15V

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February 4, 2014

IR2213(S)PBF

Package Details

16-Lead SOIC (wide body)

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February 4, 2014

IR2213(S)PBF

Tape and Reel Details, SO16WB

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February 4, 2014

IR2213(S)PBF

Part Marking Information

Part number

Date code

IR2213

YWW ?

IR logo

Pin 1

Identifier

? XXXX

Lot Code

(Prod mode –

4 digit SPN code)

?

MARKING CODE

P

Lead Free Released

Non-Lead Free Released

Assembly site code

Per SCOP 200-002

14-Lead PDIP

Part number

Date code

IR2213S

YWW ?

IR logo

Pin 1

Identifier

? XXXX

Lot Code

(Prod mode –

4 digit SPN code)

?

MARKING CODE

P

Lead Free Released

Assembly site code

Per SCOP 200-002

Non-Lead Free Released

16-Lead SOIC (wide body)

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February 4, 2014

IR2213(S)PBF

Qualification Information^†

Industrial^††

(per JEDEC JESD 47)

Qualification Level

Comments: This family of ICs has passed JEDEC’s

Industrial qualification. IR’s Consumer qualification level is

granted by extension of the higher Industrial level.

MSL3^†††

SOIC16WB

(per IPC/JEDEC J-STD 020)

Moisture Sensitivity Level

RoHS Compliant

Not applicable

(non-surface mount package style)

PDIP14

Yes

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

†† Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information.

††† Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility

for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of

other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any

patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This

document supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

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February 4, 2014


型号：	IR2213PBF_15
厂家：	Infineon
描述：	High and Low Side Driver
文件：	总18页 (文件大小：1209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR2213PBF_15 [INFINEON]

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