IRF3305_技术文档

PD - 95879

AUTOMOTIVE MOSFET

IRF3305

Features

HEXFET^®Power MOSFET

O

Designed to support Linear Gate Drive

Applications

D

O

175°C Operating Temperature

V_DSS= 55V

Low Thermal Resistance Junction - Case

Rugged Process Technology and Design

Fully Avalanche Rated

R_DS(on)= 8.0mΩ

G

Description

I_D= 75A

Specificallydesignedforuseinlinear automotive

applicationsthisHEXFETPowerMOSFETutilizes

a rugged planar process technology and device

design,whichgreatlyimprovestheSafeOperating

Area(SOA)ofthedevice.Thesefeatures,coupled

with 175°C junction operating temperature and

low thermal resistance of 0.45C/W make the

IRF3305 an ideal device for linear automotive

applications.

S

TO-220AB

Absolute Maximum Ratings

Parameter

Max.

Units

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

Continuous Drain Current, V_GS@ 10V

Continuous Drain Current, V_GS@ 10V (Package Limited)

Pulsed Drain Current

I

@ T = 25°C

140

D

C

@ T = 100°C

99

75

A

C

@ T = 25°C

C

560

330

DM

P

@T = 25°C Power Dissipation

W

D

C

Linear Derating Factor

Gate-to-Source Voltage

Single Pulse Avalanche Energy

2.2

± 20

W/°C

V

GS

E_{AS (Thermally limited)}

470

860

mJ

Single Pulse Avalanche Energy Tested Value

Avalanche Current

E_AS(Tested )

I_AR

See Fig.12a, 12b, 15, 16

A

Repetitive Avalanche Energy

Operating Junction and

E_AR

mJ

T

-55 to + 175

J

Storage Temperature Range

°C

STG

Soldering Temperature, for 10 seconds

Mounting Torque, 6-32 or M3 screw

300 (1.6mm from case )

10 lbf in (1.1N m)

Thermal Resistance

Parameter

Typ.

–––

Max.

0.45

–––

62

Units

Junction-to-Case

R_θJC

R_θCS

R_θJA

Case-to-Sink, Flat, Greased Surface

Junction-to-Ambient

0.50

–––

°C/W

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1

7/2/04

IRF3305

Electrical Characteristics @ T_J= 25°C (unless otherwise specified)

Parameter

Drain-to-Source Breakdown Voltage

Min. Typ. Max. Units

55 ––– –––

Conditions

V_GS= 0V, I_D= 250µA

V_(BR)DSS

V

∆V_(BR)DSS/∆T_JBreakdown Voltage Temp. Coefficient ––– 0.055 ––– V/°C Reference to 25°C, I_D= 1mA

mΩ

V

R_DS(on)

V_GS(th)

gfs

Static Drain-to-Source On-Resistance

–––

8.0

4.0

–––

25

V_GS= 10V, I_D= 75A

Gate Threshold Voltage

2.0

V_DS= V_GS, I_D= 250µA

V_DS= 25V, I_D= 75A

Forward Transconductance

41

S

I_DSS

Drain-to-Source Leakage Current

–––

µA V_DS= 55V, V_GS= 0V

250

200

V

_DS= 55V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Total Gate Charge

nA V_GS= 20V

––– -200

V

_GS= -20V

I_D= 75A

V_DS= 44V

Q_g

Q_gs

Q_gd

t_d(on)

t_r

100

21

45

16

88

43

34

4.5

150

–––

Gate-to-Source Charge

Gate-to-Drain ("Miller") Charge

Turn-On Delay Time

nC

ns

V_GS= 10V

V_DD= 28V

I_D= 75A

Rise Time

t_d(off)

t_f

Turn-Off Delay Time

R_G= 2.6 Ω

V_GS= 10V

Fall Time

L_D

Internal Drain Inductance

Between lead,

nH 6mm (0.25in.)

from package

L_S

Internal Source Inductance

–––

7.5

–––

and center of die contact

V_GS= 0V

_DS= 25V

pF ƒ = 1.0MHz

C_iss

C_oss

C_rss

C_oss

Input Capacitance

––– 3650 –––

––– 1230 –––

Output Capacitance

V

Reverse Transfer Capacitance

Output Capacitance

–––

––– 4720 –––

––– 930 –––

450

–––

V

_GS= 0V, V_DS= 1.0V, ƒ = 1.0MHz

Output Capacitance

_GS= 0V, V_DS= 44V, ƒ = 1.0MHz

_GS= 0V, V_DS= 0V to 44V

C_osseff.

Effective Output Capacitance

––– 1490 –––

Source-Drain Ratings and Characteristics

Parameter

Min. Typ. Max. Units

Conditions

MOSFET symbol

I

Continuous Source Current

–––

75

S

(Body Diode)

A

showing the

I

Pulsed Source Current

–––

560

integral reverse

SM

(Body Diode)

p-n junction diode.

V

Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

Forward Turn-On Time

–––

57

1.3

86

V

T = 25°C, I = 75A, V = 0V

SD

J S GS

t

ns T = 25°C, I = 75A, V_DD= 28V

J F

rr

di/dt = 100A/µs

Q

130

190

nC

rr

t

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

on

Notes:

C_osseff. is a fixed capacitance that gives the same charging time

Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

as C_osswhile V_DSis rising from 0 to 80% V_DSS

.

Limited by T_Jmax, starting T_J= 25°C, L = 0.17mH

ꢀ

Limited by T_Jmax, see Fig.12a, 12b, 15, 16 for typical repetitive

avalanche performance.

R_G= 25Ω, I_AS= 75A, V_GS=10V. Part not

recommended for use above this value.

Pulse width ≤ 1.0ms; duty cycle ≤ 2%.

C_osseff. is a fixed capacitance that gives the

same charging time as C_osswhile V_DSis rising

This value determined from sample failure population. 100%

tested to this value in production.

R_θis measured at T_Jof approximately 90°C.

from 0 to 80% V_DSS

.

2

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IRF3305

1000

100

10

1000

100

10

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

TOP

BOTTOM

4.5V

≤ 60µs PULSE WIDTH

Tj = 175°C

Tj = 25°C

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000.0

80

T

= 25°C

J

100.0

10.0

1.0

60

40

20

0

T

= 175°C

J

T

= 175°C

J

T

= 25°C

J

V

= 25V

DS

≤ 60µs PULSE WIDTH

V

= 10V

DS

380µs PULSE WIDTH

0.1

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0

20

40

60

80

100 120 140

V

, Gate-to-Source Voltage (V)

GS

I

Drain-to-Source Current (A)

D,

Fig 3. Typical Transfer Characteristics

Fig 4. Typical Forward Transconductance

Vs. Drain Current

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3

IRF3305

7000

V

20

16

12

8

= 0V,

f = 1 MHZ

GS

I = 75A

D

V

= 44V

C

= C + C , C SHORTED

DS

VDS= 28V

iss

gs

gd ds

6000

5000

4000

3000

2000

1000

0

C

= C

rss

gd

C

= C + C

ds

oss

gd

Ciss

Coss

Crss

4

0

40

80

120

160

1

10

100

Q

Total Gate Charge (nC)

G

V

, Drain-to-Source Voltage (V)

DS

Fig 6. Typical Gate Charge Vs.

Fig 5. Typical Capacitance Vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000.0

100.0

10.0

1.0

10000

1000

100

10

OPERATION IN THIS AREA

LIMITED BY R

(on)

DS

T

= 175°C

J

100µsec

1msec

T

J

= 25°C

1

Tc = 25°C

Tj = 175°C

Single Pulse

10msec

DC

V

= 0V

GS

0.1

0.0

0.4

V

0.8

1.2

1.6

2.0

2.4

1

10

100

1000

V

, Drain-toSource Voltage (V)

, Source-to-Drain Voltage (V)

DS

SD

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

4

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IRF3305

2.5

2.0

1.5

1.0

0.5

140

120

100

80

I

= 75A

LIMITED BY PACKAGE

D

V

= 10V

GS

60

40

20

0

25

50

75

100

125

150

175

-60 -40 -20

0

20 40 60 80 100 120 140 160 180

T

, Case Temperature (°C)

C

T

, Junction Temperature (°C)

J

Fig 10. Normalized On-Resistance

Fig 9. Maximum Drain Current Vs.

Vs. Temperature

Case Temperature

1

D = 0.50

0.1

0.20

0.10

0.05

R₁

R₂

R₃

Ri (°C/W) τi (sec)

0.1758 0.00045

0.01

0.001

0.02

0.01

τ

^Jτ_J

τ

^Cτ

τ

¹τ₁

τ

²τ₂

³τ₃

0.228

0.004565

0.0457 0.01858

Ci= τi/Ri

τ /

Notes:

SINGLE PULSE

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

( THERMAL RESPONSE )

0.0001

1E-006

1E-005

0.0001

0.001

0.01

0.1

t

, Rectangular Pulse Duration (sec)

1

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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5

IRF3305

2000

1600

1200

800

400

0

15V

I

D

TOP

18A

26A

75A

DRIVER

+

L

V

BOTTOM

DS

D.U.T

AS

R

G

V

DD

-

I

A

V

20V

GS

0.01

Ω

t

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

25

50

75

100

125

150

175

Starting T , Junction Temperature (°C)

J

I

AS

Fig 12c. Maximum Avalanche Energy

Fig 12b. Unclamped Inductive Waveforms

Vs. Drain Current

Q

G

10 V

Q

4.0

3.5

3.0

2.5

2.0

1.5

1.0

GS

GD

I

= 5.0A

= 1.0A

= 250µA

D

V

G

Charge

Fig 13a. Basic Gate Charge Waveform

L

VCC

DUT

0

-75 -50 -25

0

25 50 75 100 125 150 175

, Temperature ( °C )

1K

T

J

Fig 14. Threshold Voltage Vs. Temperature

Fig 13b. Gate Charge Test Circuit

6

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IRF3305

10000

1000

100

10

Duty Cycle = Single Pulse

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses. Note: In no

case should Tj be allowed to

exceed Tjmax

0.01

0.05

0.10

1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

500

Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP

BOTTOM 1% Duty Cycle

= 75A

Single Pulse

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T_jmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. P_{D (ave)}= Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. I_av= Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

T_jmax(assumed as 25°C in Figure 15, 16).

t_{av =}Average time in avalanche.

I

400

300

200

100

0

D

25

50

75

100

125

150

175

D = Duty cycle in avalanche = t_av·f

Z_thJC(D, t_av) = Transient thermal resistance, see figure 11)

Starting T , Junction Temperature (°C)

J

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

I_av= 2DT/ [1.3·BV·Z_th]

Fig 16. Maximum Avalanche Energy

E_{AS (AR)}= P_{D (ave)}·t_av

Vs. Temperature

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7

IRF3305

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

+

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

-

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

I

SD

Ripple

≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

R_D

V_DS

V_GS

D.U.T.

R_G

⁺V_DD

-

10V

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

V

DS

90%

10%

V

GS

t

r

t

f

d(on)

d(off)

Fig 18b. Switching Time Waveforms

8

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IRF3305

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

10.54 (.415)

10.29 (.405)

- B -

3.78 (.149)

3.54 (.139)

2.87 (.113)

2.62 (.103)

4.69 (.185)

4.20 (.165)

1.32 (.052)

1.22 (.048)

- A -

6.47 (.255)

6.10 (.240)

4

15.24 (.600)

14.84 (.584)

1.15 (.045)

MIN

LEAD ASSIGNMENTS

1 - GATE

1

2

3

2 - DRAIN

3 - SOURCE

4 - DRAIN

14.09 (.555)

13.47 (.530)

4.06 (.160)

3.55 (.140)

0.93 (.037)

0.69 (.027)

0.55 (.022)

0.46 (.018)

3X

1.40 (.055)

3X

1.15 (.045)

0.36 (.014)

M

B A M

2.92 (.115)

2.64 (.104)

2.54 (.100)

2X

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH

3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.

4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

TO-220AB Part Marking Information

EXAMPLE: T HIS IS AN IRF1010

LOT CODE 1789

PART NUMBER

ASS EMBLED ON WW 19, 1997

IN T HE AS S EMBLY LINE "C"

INTERNAT IONAL

RECT IFIER

LOGO

Note: "P" in assembly line

position indicates "Lead-Free"

DAT E CODE

YEAR 7 = 1997

WEEK 19

AS S EMBLY

LOT CODE

LINE C

TO-220AB package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Automotive [Q101]market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 07/04

www.irf.com

9


型号：	IRF3305
厂家：	Infineon
描述：	AUTOMOTIVE MOSFET 汽车MOSFET
文件：	总9页 (文件大小：239K)
中文：	中文翻译
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