IRF7335D1TRPBF_技术文档

PD- 94546

IRF7335D1

•

Co-Pack Dual N-channel HEXFET Power MOSFET

and Schottky Diode

Ideal for Synchronous Buck DC-DC

Converters Up to 11A Peak Output

Low Conduction Losses

Dual FETKY

Co-Packaged Dual MOSFET Plus Schottky Diode

•

Device Ratings (Typ.Values)

Low Switching Losses

Low Vf Schottky Rectifier

Q1

Q2

and Schottky

9.6 mΩ

18 nC

1

2

3

4

5

6

7

14

D1

S1, D2

R_DS

Q_G

13.4 mΩ

13 nC

5.5 nC

1.0V

(on)

13 S1, D2

12 S1, D2

Q1

G1

G2

S2

11

10 S1, D2

S1, D2

Q_sw

V_SD

6.4 nC

0.43V

9

8

S1, D2

Q2

Description

The FETKY^™family of Co-Pack HEXFET MOSFETs and Schottky diodes offers the designer an innovative,

board space saving solution for switching regulator and power management applications. Advanced

HEXFET MOSFETs combined with low forward drop Schottky results in an extremely efficient device suitable

for a wide variety of portable electronics applications.

The SO-14 has been modified through a customized leadframe for enhanced thermal characteristics and

multiple die capability making it ideal in a variety of power applications. With these improvements multiple

devices can be used in an application with dramatically reduced board space. Internal connections enable

easier board layout design with reduced stray inductance.

Absolute Maximum Ratings

Parameter

Max.

Units

V_DS

Drain-Source Voltage

30

V

I_D@ T_A= 25°C

I_D@ T_A= 70°C

I_DM

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

10

8.1

A

81

2.0

P_D@T_A= 25°C

P_D@T_A= 70°C

Power Dissipation

W

Power Dissipation

1.3

Linear Derating Factor

0.02

W/°C

V

V_GS

Gate-to-Source Voltage

± 12

E_AS(6 sigma)

Single Pulse Avalanche Energy ꢀ

Operating Junction and

50

mJ

T_J

-55 to + 150

T_STG

Storage Temperature Range

Soldering Temperature, for 10 seconds

°C

300 (1.6mm from case )

Thermal Resistance

Symbol

Parameter

Typ.

Max.

Units

R_θJL

Junction-to-Drain Lead

20

R_θJA

Junction-to-Ambient

62.5

°C/W

Notes through ꢀare on page 12

9/11/02

IRF7335D1

Q2-Synch FET

& Schottky

Min Typ Max Units

Q1-Control FET

Electrical Characteristics

Parameter

Min Typ Max

Conditions

Drain-to-Source

BV_DSS30

30

V

V_GS= 0V, I_D= 250µA

Breakdown Voltage

Tem. Coefficient

∆BV_DSS/∆T_J0.025

0.033

V

Reference to 25°C, I_D= 1.0mA

Static Drain-Source

on Resistance

R_DS

13.4 17.5

9.6 12.8 mΩ V_GS= 4.5V, I_D= 10A

(on)

Gate Threshold Voltage

V_GS(th)1.0

I_DSS

1.1

28

V

V_DS= V_GS,I_D= 250µA

Drain-Source Leakage

Current

30

10

µA V_DS= 24V, V_GS= 0

0.3

mA V_DS= 24V, V_GS= 0, Tj = 125°C

Gate-Source Leakage

Current

I_GSS

±100

±100 nA V_GS= ±12V

Forward Transconductance

g_FS

21

S

V_GS=5V, I_D=8.0A, V_DS=15V

V_GS=4.5V, I_D=8.0A, V_DS=15V

Total Gate Charge

Pre-Vth

Q_G

13

20

18

27

Q_GS1

3.2

5.8

Gate-Source Charge

Post-Vth

Q_GS2

1.4

1.5

nC

Gate-Source Charge

Gate to Drain Charge

Switch Chg(Q_gs2+ Q_gd)

Output Charge

Q_GD

Q_sw

Q_oss

R_G

4.1

5.5

7.7

4.3

6.8

5.9

19

4.9

6.4

11

nC V_DS= 16V, V_GS= 0

Ω

Gate Resistance

Turn-on Delay Time

Rise Time

10

2.6

8.8

3.3

17

5.0

t_{d (on)}

t_r

V_DD= 16V, I_D= 8.0A

ns V_GS= 4.5V

Clamped Inductive Load

Turn-off Delay Time

Fall Time

t_d

(off)

t_f

9.1

1500

310

140

7.0

2300

450

180

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

C_iss

C_oss

C_rss

pF V_DS= 15V, V_GS= 0

Source-Drain Rating & Characteristics

Parameter

Min Typ Max

Min Typ Max Units

Conditions

MOSFET symbol

D

Continuous Source Current

(Body Diode)

I_S

10

A

showing the

G

Pulse Source Current

(Body Diode)

I_SM

81

intergral reverse

p-n junction diode

S

Diode Forward Voltage

Reverse Recovery Time

V_SD

t_rr

1

1.25

0.43 0.50

31

V

T_J= 25°C, I_S= 1.0A,V_GS= 0V

28

ns T_J= 125°C, I_F= 8.0A, V_R= 15V

Reverse Recovery Charge

Reverse Recovery Time

Q_rr

t_rr

24

29

26

31

nC di/dt = 100A/µs

ns T_J= 125°C, I_F=8.0A, V_R= 15V

Reverse Recovery Charge

Q_rr

26

nC di/dt =100A/µs

2

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IRF7335D1

Typical Characteristics

Q1 - Control FET

Q2 - Synchronous FET & Schottky

1000

100

10

1000

100

10

VGS

12V

10V

8.0V

4.5V

3.5V

3.0V

2.5V

VGS

10V

TOP

5.0V

4.5V

3.0V

2.7V

2.5V

2.2V

BOTTOM 2.25V

BOTTOM 2.0V

1

2.0V

20µs PULSE WIDTH

Tj = 25°C

20µs PULSE WIDTH

Tj = 25°C

2.25V

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000

100

VGS

10V

VGS

12V

TOP

5.0V

4.5V

3.0V

2.7V

2.5V

2.2V

10V

8.0V

4.5V

3.5V

3.0V

2.5V

100

10

1

BOTTOM 2.0V

BOTTOM 2.25V

10

2.25V

2.0V

20µs PULSE WIDTH

Tj = 150°C

20µs PULSE WIDTH

Tj = 150°C

1

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 3. Typical Output Characteristics

Fig 4. Typical Output Characteristics

100.0

10.0

1.0

100.0

10.0

1.0

T

= 150°C

J

T

= 150°C

J

T

= 25°C

J

T

J

= 25°C

0.1

V

= 15V

V

= 15V

DS

20µs PULSE WIDTH

DS

20µs PULSE WIDTH

0.1

0.0

2.0

3.0

, Gate-to-Source Voltage (V)

4.0

2.0

2.5

3.0

3.5

4.0

4.5

V

, Gate-to-Source Voltage (V)

GS

Fig 5. Typical Transfer Characteristics

Fig 6. Typical Transfer Characteristics

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3

IRF7335D1

Typical Characteristics

Q2 - Synchronous FET & Schottky

Q1 - Control FET

80

60

40

20

0

80

60

40

20

0

VGS

7.5V

4.5V

3.5V

2.5V

2.0V

1.5V

1.0V

0.0V

TOP

VGS

7.5V

4.5V

3.5V

2.5V

2.0V

1.5V

1.0V

0.0V

TOP

BOTTOM

20µs PULSE WIDTH

Tj = 25°C

20µs PULSE WIDTH

Tj = 25°C

0.0

0.4

0.8

1.2

1.6

2.0

0.0

0.4

0.8

1.2

1.6

2.0

V

Source-to-Drain Voltage (V)

V

Source-to-Drain Voltage (V)

SD

Fig. 7. Typical Reverse Output Characteristics

Fig. 8. Typical Reverse Output Characteristics

80

VGS

80

VGS

TOP

7.5V

4.5V

3.5V

2.5V

2.0V

1.5V

1.0V

0.0V

TOP

7.5V

4.5V

3.5V

2.5V

2.0V

1.5V

1.0V

0.0V

60

40

20

0

60

40

20

0

BOTTOM

20µs PULSE WIDTH

Tj = 150°C

20µs PULSE WIDTH

Tj = 150°C

0.0

0.4

0.8

1.2

1.6

2.0

0.0

0.4

0.8

1.2

1.6

2.0

V

Source-to-Drain Voltage (V)

SD

V

Source-to-Drain Voltage (V)

SD

Fig. 9. Typical Reverse Output Characteristics

Fig. 10. Typical Reverse Output Characteristics

100.0

T

= 150°C

J

10.0

1.0

T

= 150°C

10.0

1.0

J

T

= 25°C

J

T

= 25°C

J

V

= 0V

V

= 0V

GS

0.1

0.0

0.4

0.8

1.2

1.6

0.0

0.4

0.8

1.2

1.6

2.0

V

, Source-toDrain Voltage (V)

V

, Source-toDrain Voltage (V)

SD

Fig 11. Typical Source-Drain Diode Forward Voltage

Fig 12. Typical Source-Drain Diode Forward Voltage

4

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IRF7335D1

Typical Characteristics

Q2 - Synchronous FET & Schottky

Q1 - Control FET

2500

2000

1500

1000

500

4000

3500

3000

2500

2000

1500

1000

500

V

C

= 0V,

= C

f = 1 MHZ

+ C C

ds

V

C

= 0V,

= C

f = 1 MHZ

GS

+

C

,

C

ds

,

iss

SHORTED

gs

gd

iss

gs

gd

SHORTED

C

= C

gd

C

= C

rss

gd

C

= C + C

C

= C + C

oss

ds gd

oss

Ciss

ds gd

Ciss

Coss

Crss

Coss

Crss

0

1

10

, Drain-to-Source Voltage (V)

100

1

10

, Drain-to-Source Voltage (V)

100

V

DS

V

DS

Fig 13. Typical Capacitance Vs.Drain-to-Source Voltage

Fig 14. Typical Capacitance Vs.Drain-to-Source Voltage

12

I

= 8.0A

D

I

= 8.0A

V

= 24V

V

= 24V

D

DS

VDS= 15V

DS

VDS= 15V

10

8

10

8

6

4

2

0

5

10

15

20

25

30

0

5

10

15

20

25

30

Q

Total Gate Charge (nC)

Q

Total Gate Charge (nC)

G

Fig. 16. Gate-to-Source Voltage vs Typical Gate Charge

Fig. 15. Gate-to-Source Voltage vs Typical Gate Charge

1000

OPERATION IN THIS AREA

LIMITED BY R

(on)

LIMITED BY R (on)

DS

100

10

1

100

100µsec

10

1msec

1

10msec

Tc = 25°C

Tj = 150°C

Single Pulse

0.1

Tc = 25°C

Tj = 150°C

Single Pulse

0.1

1.0

10.0

100.0

1000.0

0.1

1.0

10.0

100.0

1000.0

V

, Drain-toSource Voltage (V)

V

, Drain-toSource Voltage (V)

DS

Fig 17. Maximum Safe Operating Area

Fig 18. Maximum Safe Operating Area

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5

IRF7335D1

Typical Characteristics

Q2 - Synchronous FET & Schottky

Q1 - Control FET

2.0

1.5

1.0

0.5

2.0

1.5

1.0

0.5

0.0

10A

=

I

D

I

= 10A

D

V

= 4.5V

GS

V

= 4.5V

GS

-60 -40 -20

0

20

40

60

80 100 120 140 160

°

-60 -40 -20

T

0

20 40 60 80 100 120 140 160

T

J

, Junction Temperature

( C)

, Junction Temperature (°C)

J

Fig 19. Normalized On-Resistance Vs. Temperature

Fig 20. Normalized On-Resistance Vs. Temperature

0.030

0.011

0.025

0.020

V

= 4.5V

GS

0.010

V

4.5V

GS=

0.015

0.010

0.009

0

20

40

, Drain Current (A)

60

80

0

20

40

60

80

100

I

, Drain Current (A)

D

Fig 21. Typical On-Resistance Vs. Drain Current

Fig 22. Typical On-Resistance Vs. Drain Current

0.03

0.015

I

= 10A

D

0.02

0.010

I

= 10A

D

0.01

0.00

0.005

2.0

4.0

6.0

8.0

10.0

3.0

3.5

4.0

4.5

V

Gate -to -Source Voltage (V)

V

Gate -to -Source Voltage (V)

GS,

Fig 23. Typical On-Resistance Vs. Gate Voltage

Fig 24. Typical On-Resistance Vs. Gate Voltage

6

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IRF7335D1

12

10

8

R_D

V_DS

V_GS

D.U.T.

R_G

⁺V_DD

-

6

V_GS

4

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

2

Fig 26a. Switching Time Test Circuit

V

DS

0

90%

25

50

75

100

125

150

T

, Junction Temperature (°C)

J

Fig 25. Maximum Drain Current Vs.CaseTemperature

10%

V

GS

t

r

t

f

d(on)

d(off)

Fig 26b. Switching Time Waveforms

Current Regulator

Same Type as D.U.T.

Q

G

50KΩ

.3µF

V_GS

.2µF

12V

Q

GD

GS

+

V

DS

D.U.T.

-

V

G

V

GS

3mA

Charge

I

D

G

Current Sampling Resistors

Fig 27a&b. Basic Gate Charge Test Circuit

and Waveform

100

10

D = 0.50

0.20

0.10

0.05

0.02

0.01

1

0.1

0.01

SINGLE PULSE

( THERMAL RESPONSE )

1E-006

1E-005

0.0001

0.001

0.01

0.1

1

10

100

t

, Rectangular Pulse Duration (sec)

1

Fig. 28. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

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7

IRF7335D1

Schottky Diode Characteristics

100000

10000

100

Tj = 150°C

1000

100

10

125°C

100°C

75°C

50°C

25°C

10

1

0.1

0

5

10

15

20

25

30

Reverse Voltage - V

(V)

R

T

= 150°C

= 125°C

= 25°C

J

Fig. 30 - Typical Values of

Reverse Current Vs. Reverse Voltage

1

0.1

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Forward Voltage Drop - V ( V )

F

Fig. 29 - Maximum Forward Voltage Drop

Characteristics

8

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IRF7335D1

Driver Gate Drive

P.W.

D =

D.U.T

Period

+

*

=10V

V

GS

Circuit Layout Considerations

•

Low Stray Inductance

Ground Plane

Low Leakage Inductance

Current Transformer

-

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

-

+

di/dt

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

•

dv/dt controlled by R_G

Driver same type as D.U.T.

I_SDcontrolled by Duty Factor "D"

D.U.T. - Device Under Test

R_G

+

-

Body Diode

Forward Drop

Inductor Curent

I

SD

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig. 31 Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig. 32 Gate Charge Waveform

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9

IRF7335D1

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

drive output

loss

conduction

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

g

Q_oss

2

P_loss= P_conduction+ P_switching+ P_drive+ P_output

+

×V × f + Q × V × f

in rr in

(

)

This can be expanded and approximated by;

*dissipated primarily in Q1.

P

= I ²× R_{ds(on )}

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

Q_gd

Q_gs2

i_g

+ I ×

× V × f + I ×

× V × f

in

i_g

+ Q × V × f

(

)

g

Q_oss

2

+

×V × f

in

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFETdata sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

10

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IRF7335D1

SO-14 Package Details

SO-14 Part Marking

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11

IRF7335D1

SO-14 Tape and Reel

Notes:

Repetitive rating; pulse width limited by max. junction temperature.

Pulse width ≤ 300 µs; duty cycle ≤ 2%.

When mounted on 1 inch square copper board.

Combined Q1,Q2 I_RMS@ Pwr V_outpins. Calculated continuous current based on max allowable junction temperature; switching or other

losses will decrease RMS current capability

ꢀ

Q1 and Q2 is tested 100% in production to 50mJ to stress and eliminate potentially defective parts. This is not a design for use value.

Data and specifications subject to change without notice.

This product has been designed and qualified for the consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.9/02

12

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型号：	IRF7335D1TRPBF
厂家：	Infineon
描述：	Small Signal Field-Effect Transistor, 10A I(D), 30V, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, COPACK, SOP-14 晶体肖特基二极管小信号场效应晶体管开关光电二极管
文件：	总12页 (文件大小：215K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRF7335D1TRPBF [INFINEON]

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