IRFB9N30APBF [INFINEON]
HEXFET㈢ Power MOSFET; HEXFET㈢功率MOSFET
| 型号： | IRFB9N30APBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET㈢ Power MOSFET |
| 文件： | 总8页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD- 95350
IRFB9N30APbF
HEXFET® Power MOSFET
l
l
l
l
l
l
Dynamic dv/dt Rating
Repetitive Avalanche Rated
Fast Switching
Ease of Paraleing
Dynamic dv/dt Rated
Simple Drive Requirements
D
VDSS = 300V
RDS(on) = 0.45Ω
G
l
Lead-Free
ID = 9.3A
S
Description
Third Generation HEXFETs from International Rectifier provide the designer
with the best combination of ast switching, ruggedized device design, low on-
resistance and cost-effectiveness.
The TO-220 package is universally preferred for all commercial-industrial
applications at lower dissipation levels to approximately 50 watts. The low
thermal resistance and low package cost of the TO-220 contribute to its wide
acceptance throughout the industry.
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
9.3
5.9
A
37
PD @TC = 25°C
Power Dissipation
96
W
W/°C
V
Linear Derating Factor
0.77
± 30
160
VGS
EAS
IAR
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
9.3
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
9.6
mJ
V/ns
4.6
-55 to + 150
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torqe, 6-32 or M3 screw
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
1.3
Units
RθJC
RθCS
RθJA
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.50
–––
–––
62
°C/W
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06/01/04
IRFB9N30APbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
300 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.38 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
gfs
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
––– ––– 0.45
Ω
V
S
VGS = 10V, ID = 5.5A
VDS = VGS, ID = 250µA
VDS = 50V, ID = 5.6A
2.0
6.6
––– 4.0
––– –––
Forward Transconductance
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
––– ––– 33
––– ––– 6.9
––– ––– 12
VDS = 300V, VGS = 0V
IDSS
Drain-to-Source Leakage Current
µA
nA
VDS = 240V, VGS = 0V, TJ = 150°C
VGS = 30V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
IGSS
VGS = -30V
Qg
ID = 9.3A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 240V
VGS = 10V, See Fig. 6 and 13
–––
–––
–––
–––
10 –––
25 –––
35 –––
29 –––
VDD = 150V
ID = 9.3A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 12Ω
RD = 16 Ω, See Fig. 10
Between lead,
6mm (0.25in.)
from package
D
–––
–––
4.5
LD
Internal Drain Inductance
nH
pF
G
LS
Internal Source Inductance
–––
–––
7.5
and center of die contact
VGS = 0V
S
Ciss
Input Capacitance
––– 920 –––
––– 160 –––
Coss
Crss
Output Capacitance
Reverse Transfer Capacitance
Input Capacitance
VDS = 25V
–––
––– 1200 –––
––– 52 –––
––– 102 –––
8.7 –––
ƒ = 1.0MHz, See Fig. 5
Coss
Coss
Coss eff.
VGS = 0V, VDS = 1.0V, ƒ = 1.0 MHz
VGS = 0V, VDS = 240V, ƒ = 1.0 MHz
VGS = 0V, VDS = 0V to 240 V ꢀ
Input Capacitance
Input Capacitance
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
D
IS
MOSFET symbol
9.3
––– –––
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
37
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.5
––– 280 420
––– 1.5 2.3
V
TJ = 25°C, IS =9.3A, VGS = 0V
ns
TJ = 25°C, IF = 9.3A
Qrr
ton
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
Starting TJ = 25°C, L = 3.7mH
as Coss while VDS is rising from 0 to 80% VDSS
RG = 25Ω, IAS = 9.3A. (See Figure 12)
ISD ≤ 9.3A, di/dt ≤ 270A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C
,
2
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IRFB9N30APbF
100
10
1
100
10
1
VGS
15V
VGS
15V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
20µs PULSE WIDTH
T = 150 C
J
20µs PULSE WIDTH
°
°
T = 25 C
J
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
9.3A
=
I
D
°
2.5
2.0
1.5
1.0
0.5
0.0
T = 25 C
J
°
T = 150 C
J
10
V
= 50V
DS
V
= 10V
20µs PULSE WIDTH
GS
1
4.0
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
5.0
6.0
7.0 8.0
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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IRFB9N30APbF
100000
20
16
12
8
V
C
C
C
= 0V,
f = 1MHz
GS
iss
I
D
= 9.3A
= C + C
,
C
SHORTED
gs
gd
ds
V
V
V
= 240V
= 150V
= 60V
DS
DS
DS
= C
rss
oss
gd
= C + C
ds
gd
10000
1000
100
10
C
C
iss
oss
C
rss
4
FOR TEST CIRCUIT
SEE FIGURE 13
1
0
A
0
10
20
30
40
1
10
100
1000
Q , Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
100
10
1
100
10
1
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10us
100us
°
T = 150 C
J
1ms
°
T = 25 C
J
10ms
°
T = 25 C
C
°
T = 150 C
Single Pulse
J
V
= 0 V
GS
0.1
0.1
0.0
1
10
100
1000
0.4
0.8
1.2
1.6
V
, Drain-to-Source Voltage (V)
V
,Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFB9N30APbF
RD
10.0
8.0
6.0
4.0
2.0
0.0
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
°
T , Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
1
D = 0.50
0.20
0.10
0.05
0.02
P
2
DM
0.1
0.01
t
1
t
2
SINGLE PULSE
0.01
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
2. Peak T =P
t / t
1
x Z
+ T
C
J
DM
thJC
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFB9N30APbF
400
300
200
100
0
15V
I
D
4.2A
5.9A
TOP
BOTTOM 9.3A
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
°
Starting T , Junction Temperature( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
400
Q
Q
GD
GS
V
G
380
360
340
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
A
0
2
4
6
8
10
V
GS
I
, Avalanche Current (A)
av
3mA
I
I
D
G
Current Sampling Resistors
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Fig 13b. Gate Charge Test Circuit
6
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IRFB9N30APbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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IRFB9N30APbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
3.78 (.149)
- B -
10.29 (.405)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
3.54 (.139)
1.32 (.052)
1.22 (.048)
- A -
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
HEXFET
IGBTs, CoPACK
2- DRAIN
3- SOURCE
1
2
3
1- GATE
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
4- DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1
2
DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
CONTROLLING DIMENSION : INCH
3
4
OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMP LE: T HIS IS AN IRF1 010
LO T CO DE 1789
P ART NUMBER
ASS EMBLED O N WW 19, 1997
IN T HE AS S E MB LY LINE "C"
INTERNATIO NAL
RECTIFIER
LO GO
Note: "P" in assembly line
position indicates "Lead-Free"
DATE CODE
YEAR 7 = 1997
WEEK 19
ASSEMBLY
LO T CO DE
LINE C
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/04
8
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