IRFIB5N50LPBF [INFINEON]
SMPS MOSFET; 开关电源MOSFET
| 型号： | IRFIB5N50LPBF |
| 厂家： | 
Infineon |
| 描述： | SMPS MOSFET |
| 文件： | 总9页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95390
IRFIB5N50LPbF
SMPS MOSFET
HEXFET® Power MOSFET
Applications
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
• Motor Control applications
• Lead-Free
Trr typ.
VDSS RDS(on) typ.
0.67
ID
500V
Ω
73ns 4.7A
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise
immunity.
TO-220 Full-Pak
Absolute Maximum Ratings
Parameter
Max.
4.7
3.0
16
Units
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM
Pulsed Drain Current
PD @TC = 25°C
Power Dissipation
42
W
Linear Derating Factor
Gate-to-Source Voltage
0.33
±30
W/°C
V
VGS
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
13
V/ns
-55 to + 150
TSTG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case )
10lb in (1.1N m)
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
D
I
Continuous Source Current
––– –––
––– –––
––– –––
4.7
MOSFET symbol
S
(Body Diode)
A
showing the
G
I
Pulsed Source Current
16
integral reverse
SM
S
(Body Diode)
p-n junction diode.
T = 25°C, I = 4.0A, V = 0V
J S GS
V
t
Diode Forward Voltage
1.5
110
150
V
SD
T = 25°C, I = 4.0A
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
73
99
ns
rr
J
F
TJ = 125°C, di/dt = 100A/µs
Q
T = 25°C, I = 4.0A, V = 0V
––– 200 310 nC
––– 360 540
rr
J
S
GS
TJ = 125°C, di/dt = 100A/µs
IRRM
T = 25°C
J
Reverse Recovery Current
Forward Turn-On Time
––– 6.7
10
A
t
on
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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1
06/10/04
IRFIB5N50LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
500
–––
–––
3.0
–––
–––
V
∆
∆
V(BR)DSS/ TJ
0.43
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
IDSS
0.67 0.80
V
V
V
GS = 10V, ID = 2.4A
DS = VGS, ID = 250µA
DS = 500V, VGS = 0V
Ω
V
–––
–––
–––
–––
5.0
50
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
µA
2.0
100
mA VDS = 400V, VGS = 0V, TJ = 125°C
nA VGS = 30V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
––– -100
2.0 –––
VGS = -30V
RG
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 2.4A
ID = 4.0A
gfs
Qg
2.8
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
13
–––
S
45
Qgs
Qgd
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
13
nC
V
V
DS = 400V
23
GS = 10V, See Fig. 7 & 16
td(on)
–––
–––
–––
–––
VDD = 250V
D = 4.0A
G = 9.0Ω
GS = 10V, See Fig. 11a & 11b
VGS = 0V
VDS = 25V
tr
17
ns
I
td(off)
Turn-Off Delay Time
Fall Time
26
R
tf
10
V
Ciss
Input Capacitance
––– 1000 –––
Coss
Output Capacitance
–––
–––
110
12
–––
–––
Crss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0MHz, See Fig. 5
Coss
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
––– 1360 –––
pF
Coss
Output Capacitance
–––
–––
–––
31
75
55
–––
–––
–––
Coss eff.
Coss eff. (ER)
Effective Output Capacitance
Effective Output Capacitance
V
GS = 0V,VDS = 0V to 400V
(Energy Related)
Avalanche Characteristics
Symbol
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
140
4.0
Units
mJ
A
EAS
IAR
Avalanche Current
Repetitive Avalanche Energy
EAR
3.0
mJ
Thermal Resistance
Symbol
Parameter
Junction-to-Case
Junction-to-Ambient
Typ.
–––
Max.
3.0
Units
°C/W
RθJC
RθJA
–––
65
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11).
Starting TJ = 25°C, L = 18mH, RG = 25Ω,
IAS = 4.0A, dv/dt = 13V/ns. (See Figure 12a).
Pulse width ≤ 300µs; duty cycle ≤ 2%.
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff.(ER) is a fixed capacitance that stores the same energy
as Coss while VDS is rising from 0 to 80% VDSS
.
ISD ≤ 4.0, di/dt ≤ 280A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C.
,
.
2
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IRFIB5N50LPbF
100
10
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
8.0V
7.0V
6.5V
6.0V
BOTTOM
BOTTOM
5.5V
1
1
5.5V
0.1
5.5V
0.1
0.01
0.01
0.001
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
4.0A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
°
T = 150
C
J
10
°
T = 25
J
C
1
0.1
0.01
V
= 50V
DS
20µs PULSE WIDTH
V
= 10V
GS
-60 -40 -20
0
20
40
60
80 100 120 140 160
5.0
6.0
7.0
8.0
9.0
V
, Gate-to-Source Voltage (V)
GS
Tj, Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
vs. Temperature
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3
IRFIB5N50LPbF
10
9
8
7
6
5
4
3
2
1
0
100000
V
= 0V,
f = 1 MHZ
GS
C
= C + C , C SHORTED
iss
gs gd ds
C
= C
rss
gd
10000
1000
100
10
C
= C + C
ds gd
oss
C
iss
C
C
oss
rss
1
1
10
100
1000
0
100
V
200
300
400
500
600
V
, Drain-to-Source Voltage (V)
DS
Drain-to-Source Voltage (V)
DS,
Fig 5. Typical Capacitance vs.
Fig 6. Typ. Output Capacitance
Drain-to-Source Voltage
Stored Energy vs. VDS
100
12
10
8
I
= 4.0A
D
V
V
V
= 400V
= 250V
= 100V
DS
DS
DS
10
°
6
T = 25
J
C
°
T = 150
J
C
1
4
2
V
= 0 V
GS
1.0
0.1
0
0.2
0.4
0.6
0.8
1.2
0
5
10
15
20
25
30
35
V
,Source-to-Drain Voltage (V)
SD
Q
, Total Gate Charge (nC)
G
Fig 8. Typical Source-Drain Diode
Fig 7. Typical Gate Charge vs.
ForwardVoltage
Gate-to-SourceVoltage
4
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IRFIB5N50LPbF
5.0
4.0
3.0
2.0
1.0
0.0
100
10
1
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100µsec
1msec
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
1000
0.1
25
50
T
75
100
125
150
1
10
100
10000
°
, Case Temperature ( C)
C
V
, Drain-to-Source Voltage (V)
DS
Fig 9. Maximum Safe Operating Area
Fig 10. Maximum Drain Current vs.
CaseTemperature
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+VDD
-
10%
10V
V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
t
t
r
t
t
f
d(on)
d(off)
Fig 11b. Switching Time Waveforms
Fig 11a. Switching Time Test Circuit
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5
IRFIB5N50LPbF
10
D = 0.50
1
0.20
0.10
0.05
P
DM
0.02
0.01
0.1
t
1
SINGLE PULSE
t
(THERMAL RESPONSE)
2
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t , Rectangular Pulse Duration (sec)
1
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
6.0
5.0
I
= 250µA
D
4.0
3.0
2.0
-75 -50 -25
0
25
50
75 100 125 150
T
, Temperature ( °C )
J
Fig 13. Threshold Voltage vs.Temperature
6
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IRFIB5N50LPbF
320
240
160
80
I
D
TOP
1.8A
2.5A
4.0A
BOTTOM
0
25
50
75
100
125
150
°
( C)
Starting Tj, Junction Temperature
Fig 14. Maximum Avalanche Energy
vs. Drain Current
15V
V
(BR)DSS
t
p
DRIVER
L
V
DS
D.U.T
AS
R
G
+
-
V
DD
I
A
20V
0.01Ω
t
p
I
AS
Fig 15b. Unclamped Inductive Waveforms
Fig 15a. Unclamped Inductive Test Circuit
Current Regulator
Same Type as D.U.T.
Q
G
50KΩ
.2µF
12V
10 V
.3µF
Q
Q
GD
GS
+
V
DS
D.U.T.
-
V
V
GS
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 16b. Basic Gate Charge Waveform
Fig 16a. Gate Charge Test Circuit
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7
IRFIB5N50LPbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. For N-Channel HEXFET® Power MOSFETs
8
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IRFIB5N50LPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
EXAMP LE: T H IS IS AN IRF I8 4 0G
W ITH AS S EMBLY
P ART N U MBE R
D ATE C O D E
LO T C O D E 3 4 3 2
IN T ER N AT IO N AL
R EC TIF IER
LO G O
IRFI84 0G
AS S EMB LED O N WW 24 1 9 9 9
IN TH E AS S E MBLY LIN E "K"
9 24 K
3 2
3 4
Note: "P" in assembly line
position indicates "Lead-Free"
YEAR 9
= 1 9 9 9
AS S E M B LY
LO T C O D E
W EEK 2 4
LIN E K
TO-220AB FullPak package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/04
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