IRFS3006TRRPBF [INFINEON]
Power Field-Effect Transistor, 195A I(D), 60V, 0.0025ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, LEAD FREE, D2PAK-3;
| 型号： | IRFS3006TRRPBF |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 195A I(D), 60V, 0.0025ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, LEAD FREE, D2PAK-3 开关 脉冲 晶体管 |
| 文件： | 总10页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 96188
IRFS3006PbF
IRFSL3006PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
D
S
VDSS
RDS(on) typ.
max.
60V
2.0m
2.5m
270A
l Hard Switched and High Frequency Circuits
G
ID
(Silicon Limited)
ID (Package Limited)
195A
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
D
Ruggedness
D
l Fully Characterized Capacitance and Avalanche
SOA
S
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
D
G
G
D2Pak
IRFS3006PbF
TO-262
IRFSL3006PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Parameter
Max.
270
191
195
1080
375
2.5
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current
A
PD @TC = 25°C
W
Maximum Power Dissipation
Linear Derating Factor
W/°C
V
VGS
± 20
10
Gate-to-Source Voltage
Peak Diode Recovery
dv/dt
TJ
V/ns
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
320
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.4
Units
RθJC
Junction-to-Case
°C/W
RθJA
–––
40
Junction-to-Ambient
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1
10/06/08
IRFS/SL3006PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
60 ––– –––
––– 0.07 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
2.0
2.5
4.0
20
VGS = 10V, ID = 170A
VDS = VGS, ID = 250µA
mΩ
V
VGS(th)
–––
IDSS
Drain-to-Source Leakage Current
––– –––
µA
VDS = 60V, VGS = 0V
––– ––– 250
––– ––– 100
––– ––– -100
V
DS = 60V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA VGS = 20V
GS = -20V
V
RG
–––
2.0
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 25V, ID = 170A
280 ––– –––
S
––– 200 300
nC ID = 170A
VDS =30V
Qgs
Qgd
Qsync
td(on)
tr
Gate-to-Source Charge
–––
–––
37
60
–––
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
VGS = 10V
––– 140 –––
––– 16 –––
ID = 170A, VDS =0V, VGS = 10V
Turn-On Delay Time
ns VDD = 39V
ID = 170A
Rise Time
––– 182 –––
––– 118 –––
––– 189 –––
––– 8970 –––
––– 1020 –––
––– 534 –––
––– 1480 –––
––– 1920 –––
td(off)
tf
Turn-Off Delay Time
RG = 2.7Ω
VGS = 10V
Fall Time
Ciss
Coss
Crss
Input Capacitance
pF
VGS = 0V
Output Capacitance
VDS = 50V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0MHz, See Fig. 5
C
oss eff. (ER)
oss eff. (TR)
V
GS = 0V, VDS = 0V to 48V , See Fig. 11
GS = 0V, VDS = 0V to 48V
C
V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
IS
Continuous Source Current
––– –––
A
D
S
270
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
G
ISM
––– ––– 1080
A
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
–––
–––
–––
V
TJ = 25°C, IS = 170A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 51V,
IF = 170A
di/dt = 100A/µs
–––
–––
–––
–––
–––
44
48
63
77
2.4
ns
Qrr
Reverse Recovery Charge
nC
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.022mH
RG = 25Ω, IAS = 170A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 170A, di/dt ≤ 1360A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢀ Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
.
.
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
RθJC value shown is at time zero
2
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IRFS/SL3006PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
VGS
15V
TOP
TOP
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM
BOTTOM
3.5V
60µs PULSE WIDTH
3.5V
1
≤
60µs PULSE WIDTH
≤
Tj = 175°C
Tj = 25°C
1
0.1
1
10
100
0.1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 170A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
V
= 25V
DS
60µs PULSE WIDTH
≤
1
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
16000
12000
8000
4000
0
16
V
= 0V,
= C
f = 1 MHZ
GS
I = 170A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
V
V
= 48V
= 30V
DS
DS
= C
rss
oss
gd
= C + C
12
8
ds
gd
C
iss
4
C
oss
C
rss
0
0
40
80
120 160 200 240 280
1
10
, Drain-to-Source Voltage (V)
100
Q
Total Gate Charge (nC)
G
V
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS/SL3006PbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100
10
1
100µsec
LIMITED BY PACKAGE
1msec
T
J
= 25°C
10msec
DC
1
Tc = 25°C
Tj = 175°C
V
= 0V
GS
Single Pulse
0.1
0.1
0.0
0.4
0.8
1.2
1.6
2.0
0.1
1
10
100
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
80
75
70
65
60
55
300
I
= 5mA
D
Limited By Package
250
200
150
100
50
0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
25
50
75
100
125
150
175
T
, Junction Temperature (°C)
J
T
, Case Temperature (°C)
C
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
1400
2.0
1.5
1.0
0.5
0.0
I
D
1200
1000
800
600
400
200
0
TOP
20A
27A
170A
BOTTOM
0
10
V
20
30
40
50
60
25
50
75
100
125
150
175
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
DS,
J
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFS/SL3006PbF
1
0.1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
τι
0.01
(sec)
Ri (°C/W)
0.02
0.01
τJ
τC
τJ
τ1
0.175365 0.000343
0.22547 0.006073
τ
2τ2
τ1
Ci= τi/Ri
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1% Duty Cycle
= 170A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFS/SL3006PbF
4.0
3.5
3.0
2.5
2.0
1.5
1.0
20
16
12
8
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250µA
I
= 112A
F
V
= 51V
R
4
T
= 125°C
= 25°C
J
J
T
0
100
200
300
400
500
600
700
800
-75 -50 -25
0
J
25 50 75 100 125 150 175
, Temperature ( °C )
di / dt - (A / µs)
T
f
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
20
700
600
500
400
300
16
12
8
I
= 170A
= 51V
I
= 112A
= 51V
200
100
0
F
F
V
V
T
R
4
0
R
T
= 125°C
= 25°C
= 125°C
= 25°C
J
J
T
T
J
J
100
200
300
400
500
600
700
800
100
200
300
400
500
600
700
800
di / dt - (A / µs)
di / dt - (A / µs)
f
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
700
600
500
400
300
200
100
0
I
= 170A
= 51V
F
V
T
R
= 125°C
= 25°C
J
T
J
100
200
300
400
500
600
700
800
di / dt - (A / µs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFS/SL3006PbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFS/SL3006PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
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IRFS/SL3006PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRFS/SL3006PbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2008
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10
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