IRFS7430-7P [INFINEON]

40V 单个 N 通道 HEXFET Power MOSFET, 采用 7引脚 D2-Pak 封装;
IRFS7430-7P
型号: IRFS7430-7P
厂家: Infineon    Infineon
描述:

40V 单个 N 通道 HEXFET Power MOSFET, 采用 7引脚 D2-Pak 封装

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StrongIRFET™  
IRFS7430-7PPbF  
Application  
HEXFET® Power MOSFET  
Brushed Motor drive applications  
BLDC Motor drive applications  
PWM Inverterized topologies  
Battery powered circuits  
Half-bridge and full-bridge topologies  
Electronic ballast applications  
Synchronous rectifier applications  
Resonant mode power supplies  
OR-ing and redundant power switches  
DC/DC and AC/DC converters  
VDSS  
40V  
RDS(on) typ.  
0.55m  
0.75m  
522A  
max  
ID (Silicon Limited)  
ID (Package Limited)  
240A  
Benefits  
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness  
Fully Characterized Capacitance and Avalanche SOA  
Enhanced body diode dV/dt and dI/dt Capability  
Lead-Free, RoHS Compliant  
G
D
S
Gate  
Drain  
Source  
Standard Pack  
Orderable Part Number  
Base part number Package Type  
Form  
Quantity  
50  
Tube  
IRFS7430-7PPbF  
IRFS7430TRL7PP  
IRFS7430-7PPbF  
D2Pak-7Pin  
Tape and Reel Left  
800  
4.0  
600  
500  
400  
300  
200  
100  
I
= 100A  
D
Limited By Package  
3.0  
2.0  
1.0  
0.0  
T
T
= 125°C  
= 25°C  
J
J
0
4
6
8
10 12 14 16 18 20  
25  
50  
75  
100  
125  
150  
175  
T
, Case Temperature (°C)  
V
Gate -to -Source Voltage (V)  
C
GS,  
Fig 2. Maximum Drain Current vs. Case Temperature  
Fig 1. Typical On-Resistance vs. Gate Voltage  
1
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November 6, 2014  
IRFS7430-7PPbF  
Absolute Maximium Rating  
Symbol  
Parameter  
Max.  
522  
369  
Units  
ID @ TC = 25°C  
Continuous Drain Current, VGS @ 10V (Silicon Limited)  
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)  
A
ID @ TC = 25°C  
IDM  
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)  
Pulsed Drain Current   
240  
1200*  
375  
PD @TC = 25°C  
Maximum Power Dissipation  
W
W/°C  
V
Linear Derating Factor  
2.5  
VGS  
Gate-to-Source Voltage  
± 20  
TJ  
TSTG  
Operating Junction and  
Storage Temperature Range  
Soldering Temperature, for 10 seconds (1.6mm from case)  
-55 to + 175  
300  
°C  
Avalanche Characteristics  
EAS (Thermally limited)  
EAS (Thermally limited)  
IAR  
EAR  
764  
1454  
Single Pulse Avalanche Energy   
Single Pulse Avalanche Energy   
Avalanche Current   
mJ  
A
mJ  
See Fig 15, 16, 23a, 23b  
Repetitive Avalanche Energy   
Thermal Resistance  
Symbol  
Parameter  
Typ.  
–––  
–––  
Max.  
0.4  
Units  
Junction-to-Case   
Junction-to-Ambient   
RJC  
RJA  
°C/W  
40  
Static @ TJ = 25°C (unless otherwise specified)  
Symbol  
Parameter  
Min. Typ. Max. Units  
Conditions  
V(BR)DSS  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
40  
––– –––  
V
VGS = 0V, ID = 250µA  
–––  
26 ––– mV/°C Reference to 25°C, ID = 2mA   
V(BR)DSS/TJ  
––– 0.55 0.75  
––– 0.93 –––  
V
V
GS = 10V, ID = 100A   
GS = 6V, ID = 50A   
RDS(on)  
Static Drain-to-Source On-Resistance  
Gate Threshold Voltage  
m  
V
VGS(th)  
2.2  
––– –––  
3.0  
3.9  
1.0  
VDS = VGS, ID = 250µA  
DS =40 V, VGS = 0V  
VDS =40V,VGS = 0V,TJ =125°C  
V
IDSS  
Drain-to-Source Leakage Current  
µA  
––– ––– 150  
––– ––– 100  
––– ––– -100  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Gate Resistance  
V
V
GS = 20V  
GS = -20V  
IGSS  
nA  
RG  
–––  
2.2  
–––  
  
Notes:  
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A  
by source bonding technology. Note that current limitations arising from heating of the device leads may occur with  
some lead mounting arrangements. (Refer to AN-1140)  
Repetitive rating; pulse width limited by max. junction temperature.  
Limited by TJmax, starting TJ = 25°C, L = 153µH, RG = 50, IAS = 100A, VGS =10V.  
ISD 100A, di/dt 1403A/µs, VDD V(BR)DSS, TJ 175°C.  
Pulse width 400µs; duty cycle 2%.  
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS  
.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS  
.
Ris measured at TJ approximately 90°C.  
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 54A, VGS =10V.  
When mounted on 1" square PCB (FR-4 or G-10 Material). Please refer to AN-994 for more details:  
http://www.irf.com/technical-info/appnotes/an-994.pdf  
*Pulse drain current is limited at 960A by source bonding technology.  
2
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November 6, 2014  
IRFS7430-7PPbF  
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)  
Symbol  
gfs  
Parameter  
Forward Transconductance  
Total Gate Charge  
Min. Typ. Max. Units  
Conditions  
VDS = 10V, ID =100A  
ID = 100A  
176 –––  
––– 305  
–––  
460  
–––  
–––  
–––  
–––  
–––  
S
Qg  
Qgs  
Gate-to-Source Charge  
Gate-to-Drain Charge  
Total Gate Charge Sync. (Qg– Qgd)  
Turn-On Delay Time  
–––  
–––  
84  
96  
VDS = 20V  
nC  
Qgd  
VGS = 10V  
Qsync  
td(on)  
tr  
––– 209  
–––  
–––  
28  
79  
VDD = 20V  
ID = 30A  
Rise Time  
ns  
td(off)  
tf  
Turn-Off Delay Time  
Fall Time  
––– 161  
––– 93  
–––  
–––  
RG= 2.7  
VGS = 10V  
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
––– 13975 –––  
––– 2140 –––  
––– 1438 –––  
VGS = 0V  
VDS = 25V  
ƒ = 1.0MHz, See Fig.7  
pF  
Effective Output Capacitance (Energy Relat-  
ed)  
VGS = 0V, VDS = 0V to 32V  
See Fig.11  
Coss eff.(ER)  
––– 2620 –––  
––– 3306 –––  
Coss eff.(TR) Output Capacitance (Time Related)  
VGS = 0V, VDS = 0V to 32V  
Diode Characteristics  
Symbol  
IS  
Parameter  
Continuous Source Current  
(Body Diode)  
Pulsed Source Current  
(Body Diode)  
Min. Typ. Max. Units  
Conditions  
MOSFET symbol  
showing the  
integral reverse  
D
––– ––– 522  
A
––– ––– 1200*  
G
ISM  
S
p-n junction diode.  
VSD  
Diode Forward Voltage  
–––  
0.8  
1.2  
V
TJ = 25°C,IS = 100A,VGS = 0V   
dv/dt  
Peak Diode Recovery dv/dt  
–––  
–––  
–––  
–––  
–––  
–––  
1.6  
50  
58  
59  
72  
2.2  
––– V/ns TJ = 175°C,IS =100A,VDS = 40V  
–––  
–––  
–––  
–––  
–––  
TJ = 25°C  
VDD = 34V  
IF = 100A,  
trr  
Reverse Recovery Time  
ns  
TJ = 125°C  
TJ = 25°C di/dt = 100A/µs   
Qrr  
Reverse Recovery Charge  
Reverse Recovery Current  
nC  
A
TJ = 125°C  
IRRM  
TJ = 25°C  
3
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November 6, 2014  
IRFS7430-7PPbF  
1000  
100  
10  
1000  
100  
10  
VGS  
15V  
10V  
8.0V  
7.0V  
6.0V  
5.5V  
5.0V  
4.5V  
VGS  
15V  
10V  
8.0V  
7.0V  
6.0V  
5.5V  
5.0V  
4.5V  
TOP  
TOP  
BOTTOM  
BOTTOM  
4.5V  
4.5V  
1
60µs  
PULSE WIDTH  
60µs  
PULSE WIDTH  
Tj = 25°C  
Tj = 175°C  
0.1  
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Drain-to-Source Voltage (V)  
DS  
Fig 4. Typical Output Characteristics  
Fig 3. Typical Output Characteristics  
1000  
100  
10  
2.0  
I
= 100A  
= 10V  
D
V
GS  
T
= 175°C  
J
1.6  
1.2  
0.8  
0.4  
T
= 25°C  
J
1
V
= 10V  
DS  
60µs PULSE WIDTH  
0.1  
2
3
4
5
6
7
8
-60  
-20  
T
20  
60  
100  
140  
180  
, Junction Temperature (°C)  
J
V
, Gate-to-Source Voltage (V)  
GS  
Fig 6. Normalized On-Resistance vs. Temperature  
Fig 5. Typical Transfer Characteristics  
14.0  
1000000  
100000  
10000  
1000  
V
C
= 0V,  
f = 1 MHZ  
GS  
I
= 100A  
D
= C + C , C SHORTED  
iss  
gs  
gd ds  
12.0  
10.0  
8.0  
C
= C  
rss  
gd  
V
V
= 32V  
DS  
DS  
C
= C + C  
oss  
ds  
gd  
= 20V  
C
iss  
6.0  
C
oss  
C
rss  
4.0  
2.0  
0.0  
100  
0
50 100 150 200 250 300 350 400  
0.1  
1
10  
100  
Q , Total Gate Charge (nC)  
G
V
, Drain-to-Source Voltage (V)  
DS  
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage  
Submit Datasheet Feedback November 6, 2014  
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage  
4
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IRFS7430-7PPbF  
1000  
100  
10  
10000  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R (on)  
DS  
T
= 175°C  
J
100µsec  
1msec  
T
= 25°C  
J
Limited by Package  
DC  
10msec  
1
1
Tc = 25°C  
Tj = 175°C  
Single Pulse  
V
= 0V  
GS  
0.1  
0.1  
0.1  
1
10  
100  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
V
, Drain-to-Source Voltage (V)  
V
, Source-to-Drain Voltage (V)  
DS  
SD  
Fig 10. Maximum Safe Operating Area  
Fig 9. Typical Source-Drain Diode Forward Voltage  
2.5  
48  
Id = 2.0mA  
47  
2.0  
1.5  
1.0  
0.5  
0.0  
46  
45  
44  
43  
42  
41  
40  
-5  
0
5
10 15 20 25 30 35 40 45  
-60  
-20  
20  
60  
100  
140  
180  
V
Drain-to-Source Voltage (V)  
T
, Temperature ( °C )  
DS,  
J
Fig 12. Typical Coss Stored Energy  
Fig 11. Drain-to–Source Breakdown Voltage  
10.0  
VGS = 5.5V  
VGS = 6.0V  
VGS = 7.0V  
VGS = 8.0V  
VGS = 10V  
8.0  
6.0  
4.0  
2.0  
0.0  
0
100  
200  
300  
400  
500  
I , Drain Current (A)  
D
Fig 13. Typical On-Resistance vs. Drain Current  
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5
November 6, 2014  
IRFS7430-7PPbF  
1
0.1  
D = 0.50  
0.20  
0.10  
0.05  
0.02  
0.01  
0.01  
SINGLE PULSE  
( THERMAL RESPONSE )  
0.001  
0.0001  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
t
, Rectangular Pulse Duration (sec)  
1
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case  
1000  
100  
10  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming Tj = 150°C and  
Tstart =25°C (Single Pulse)  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming  j = 25°C and  
Tstart = 150°C.  
1
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 15. Avalanche Current vs. Pulse width  
800  
700  
600  
500  
400  
300  
200  
100  
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:  
(For further info, see AN-1005 at www.irf.com)  
1.Avalanche failures assumption:  
TOP  
BOTTOM 1.0% Duty Cycle  
= 100A  
Single Pulse  
I
D
Purely a thermal phenomenon and failure occurs at a  
temperature far in excess of Tjmax. This is validated for every  
part type.  
2. Safe operation in Avalanche is allowed as long asTjmax is not  
exceeded.  
3. Equation below based on circuit and waveforms shown in Figures  
23a, 23b.  
4. PD (ave) = Average power dissipation per single avalanche pulse.  
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage  
increase during avalanche).  
6. Iav = Allowable avalanche current.  
7. T = Allowable rise in junction temperature, not to exceed Tjmax  
(assumed as 25°C in Figure 14, 15).  
tav = Average time in avalanche.  
D = Duty cycle in avalanche = tav ·f  
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)  
25  
50  
75  
100  
125  
150  
175  
Starting T , Junction Temperature (°C)  
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC  
I
av = 2T/ [1.3·BV·Zth]  
EAS (AR) = PD (ave)· av  
t
Fig 16. Maximum Avalanche Energy vs. Temperature  
6
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IRFS7430-7PPbF  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
16  
14  
12  
10  
8
I
= 60A  
= 34V  
F
V
R
T = 25°C  
J
T = 125°C  
J
6
ID = 250µA  
ID = 1.0mA  
ID = 1.0A  
4
2
0
-75  
-25  
25  
75  
125  
175  
225  
0
200  
400  
600  
800  
1000  
T
, Temperature ( °C )  
di /dt (A/µs)  
J
F
Fig 17. Threshold Voltage vs. Temperature  
Fig 18. Typical Recovery Current vs. dif/dt  
14  
12  
10  
8
700  
I
= 100A  
= 34V  
I
= 60A  
V = 34V  
R
F
F
600  
500  
400  
300  
200  
100  
0
V
R
T = 25°C  
T = 25°C  
J
J
T = 125°C  
J
T = 125°C  
J
6
4
2
0
200  
400  
600  
800  
1000  
0
200  
400  
600  
800  
1000  
di /dt (A/µs)  
di /dt (A/µs)  
F
F
Fig 20. Typical Stored Charge vs. dif/dt  
Fig 19. Typical Recovery Current vs. dif/dt  
450  
I
= 100A  
F
400  
350  
300  
250  
200  
150  
100  
50  
V
= 34V  
R
T = 25°C  
J
T = 125°C  
J
0
200  
400  
600  
800  
1000  
di /dt (A/µs)  
F
Fig 21. Typical Stored Charge vs. dif/dt  
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November 6, 2014  
IRFS7430-7PPbF  
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs  
V
(BR)DSS  
t
p
15V  
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
-
I
A
20V  
I
0.01  
t
p
AS  
Fig 23a. Unclamped Inductive Test Circuit  
Fig 23b. Unclamped Inductive Waveforms  
Fig 24a. Switching Time Test Circuit  
Fig 24b. Switching Time Waveforms  
Id  
Vds  
Vgs  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 25b. Gate Charge Waveform  
Fig 25a. Gate Charge Test Circuit  
8
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IRFS7430-7PPbF  
D2Pak-7Pin Package Outline (Dimensions are shown in millimeters (inches))  
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/  
9
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IRFS7430-7PPbF  
D2Pak-7Pin Part Marking Information  
D2Pak-7Pin Tape and Reel  
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/  
10  
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November 6, 2014  
IRFS7430-7PPbF  
Qualification Information†  
Qualification Level  
Industrial  
(per JEDEC JESD47F) ††  
D2Pak-7Pin  
MSL1  
Yes  
Moisture Sensitivity Level  
RoHS Compliant  
Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/  
†† Applicable version of JEDEC standard at the time of product release.  
Revision History  
Date  
Comments  
 Updated EAS (L =1mH) = 1454mJ on page 2  
 Updated note 9 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 54A, VGS =10V”. on page 2  
11/6/2014  
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA  
To contact International Rectifier, please visit http://www.irf.com/whoto-call/  
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IMPORTANT NOTICE  
The information given in this document shall in no For further information on the product, technology,  
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please  
characteristics (“Beschaffenheitsgarantie”) .  
contact your nearest Infineon Technologies office  
(www.infineon.com).  
With respect to any examples, hints or any typical  
values stated herein and/or any information  
regarding the application of the product, Infineon  
Technologies hereby disclaims any and all  
warranties and liabilities of any kind, including  
without limitation warranties of non-infringement  
of intellectual property rights of any third party.  
WARNINGS  
Due to technical requirements products may  
contain dangerous substances. For information on  
the types in question please contact your nearest  
Infineon Technologies office.  
In addition, any information given in this document  
is subject to customers compliance with its  
obligations stated in this document and any  
applicable legal requirements, norms and  
standards concerning customers products and any  
use of the product of Infineon Technologies in  
customers applications.  
Except as otherwise explicitly approved by Infineon  
Technologies in a written document signed by  
authorized  
representatives  
of  
Infineon  
Technologies, Infineon Technologies’ products may  
not be used in any applications where a failure of  
the product or any consequences of the use thereof  
can reasonably be expected to result in personal  
injury.  
The data contained in this document is exclusively  
intended for technically trained staff. It is the  
responsibility of customers technical departments  
to evaluate the suitability of the product for the  
intended application and the completeness of the  
product information given in this document with  
respect to such application.  

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IRFS7434PBF

Power Field-Effect Transistor, 195A I(D), 40V, 0.0016ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, LEAD FREE, PLASTIC, D2PAK-3/2
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IRFS7434TRL7PP

Insulated Gate Bipolar Transistor, N-Channel
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IRFS7437

The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. 
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