IRLR9343TRL [INFINEON]

Power Field-Effect Transistor, 20A I(D), 55V, 0.105ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, DPAK-3;


型号：	IRLR9343TRL
厂家：	Infineon
描述：	Power Field-Effect Transistor, 20A I(D), 55V, 0.105ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, DPAK-3 放大器脉冲晶体管
文件：	总10页 (文件大小：240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PD - 95850

DIGITAL AUDIO MOSFET

IRLR9343

IRLU9343

IRLU9343-701

Features

l Advanced Process Technology

Key Parameters

l Key Parameters Optimized for Class-D Audio

Amplifier Applications

l Low R_DSONfor Improved Efficiency

l Low Q_gand Q_swfor Better THD and Improved

Efficiency

l Low Q_rrfor Better THD and Lower EMI

l 175°C Operating Junction Temperature for

Ruggedness

V_DS

R_DS(ON)typ. @ V_GS= -10V

_DS(ON)typ. @ V_GS= -4.5V

-55

°C

150

Q_gtyp.

T_Jmax

175

l Repetitive Avalanche Capability for Robustness and

Reliability

l Multiple Package Options

D-Pak

IRLR9343

I-Pak

IRLU9343

I-Pak Leadform 701

IRLU9343-701

Refer to page 10 for package outline

Description

This Digital Audio HEXFET^®is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the latest

processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery

and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD

and EMI. Additional features of this MosFET are 175°C operating junction temperature and repetitive avalanche capability.

These features combine to make this MosFET a highly efficient, robust and reliable device for Class-D audio amplifier

applications.

Absolute Maximum Ratings

Parameter

Drain-to-Source Voltage

Max.

-55

±20

-20

-14

-60

Units

V_DS

V_GS

Gate-to-Source Voltage

I_D@ T_C= 25°C

I_D@ T_C= 100°C

I_DM

Continuous Drain Current, V_GS@ -10V

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current c

P_D@T_C= 25°C

P_D@T_C= 100°C

Power Dissipation

Linear Derating Factor

Operating Junction and

Storage Temperature Range

Clamping Pressure h

0.53

W/°C

°C

T_J

-40 to + 175

T_STG

–––

Thermal Resistance

Parameter

Typ.

–––

Max.

1.9

Units

Junction-to-Case g

R_θJC

R_θJA

Junction-to-Ambient (PCB Mounted) gj

Junction-to-Ambient (free air) g

°C/W

110

Notes through are on page 10

www.irf.com

4/1/04

IRLR/U9343 & IRLU9343-701

Electrical Characteristics @ T_J= 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

Conditions

BV_DSS

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

-55

–––

-1.0

–––

5.3

–––

-52

–––

V_GS= 0V, I_D= -250µA

∆ΒV_DSS/∆T_J

R_DS(on)

––– mV/°C Reference to 25°C, I_D= -1mA

mΩ

105

170

–––

V_GS= -10V, I_D= -3.4A e

_GS= -4.5V, I_D= -2.7A e

V_DS= V_GS, I_D= -250µA

150

–––

-3.7

–––

V_GS(th)

Gate Threshold Voltage

∆V_GS(th)/∆T_J

I_DSS

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

––– mV/°C

-2.0

-25

µA

V_DS= -55V, V_GS= 0V

V_DS= -55V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

-100

100

–––

nA V_GS= -20V

V_GS= 20V

g_fs

_DS= -25V, I_D= -14A

V_DS= -44V

V_GS= -10V

Q_g

–––

Q_gs

Q_gd

Q_godr

t_d(on)

t_r

Gate-to-Source Charge

Gate-to-Drain Charge

Gate Charge Overdrive

Turn-On Delay Time

7.1

8.5

–––

I_D= -14A

See Fig. 6 and 19

V_DD= -28V, V_GS= -10Vꢀe

I_D= -14A

9.5

Rise Time

t_d(off)

t_f

Turn-Off Delay Time

ns R_G= 2.5Ω

Fall Time

9.5

660

160

C_iss

C_oss

C_rss

C_oss

L_D

Input Capacitance

V_GS= 0V

pF V_DS= -50V

ƒ = 1.0MHz,

Output Capacitance

Reverse Transfer Capacitance

Effective Output Capacitance

Internal Drain Inductance

See Fig.5

280

4.5

V_GS= 0V, V_DS= 0V to -44V

Between lead,

nH 6mm (0.25in.)

L_S

Internal Source Inductance

–––

7.5

–––

from package

and center of die contact f

Avalanche Characteristics

Parameter

Typ.

Max.

Units

Single Pulse Avalanche Energyd

Avalanche Currentꢀi

E_AS

I_AR

–––

120

See Fig. 14, 15, 17a, 17b

Repetitive Avalanche Energy i

E_AR

Diode Characteristics

Parameter

Continuous Source Current

Min. Typ. Max. Units

Conditions

MOSFET symbol

I_S@ T_C= 25°C

–––

-20

(Body Diode)

showing the

I_SM

Pulsed Source Current

(Body Diode)ꢀc

–––

-60

integral reverse

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

–––

-1.2

T_J= 25°C, I_S= -14A, V_GS= 0V e

ns T_J= 25°C, I_F= -14A

Q_rr

di/dt = 100A/µs

120

180

www.irf.com

IRLR/U9343 & IRLU9343-701

100

VGS

-15V

-12V

-10V

-8.0V

-5.5V

-4.5V

-3.0V

-2.5V

TOP

-15V

-12V

-10V

-8.0V

-5.5V

-4.5V

-3.0V

-2.5V

TOP

BOTTOM

-2.5V

≤

60µs PULSE WIDTH

Tj = 175°C

Tj = 25°C

0.1

100

0.1

100

-V , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

100.0

10.0

1.0

2.0

1.5

1.0

0.5

= -14A

= 25°C

= -10V

= 175°C

= -25V

≤

60µs PULSE WIDTH

0.1

0.0

5.0

10.0

15.0

-60 -40 -20

20 40 60 80 100 120 140 160 180

-V , Gate-to-Source Voltage (V)

, Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance vs. Temperature

10000

1000

100

= 0V,

= C

f = 1 MHZ

I = -14A

+ C , C

SHORTED

iss

= -44V

= C

rss

oss

= C + C

VDS= -28V

VDS= -11V

Ciss

Coss

Crss

FOR TEST CIRCUIT

SEE FIGURE 19

-V , Drain-to-Source Voltage (V)

100

Total Gate Charge (nC)

Fig 5. Typical Capacitance vs.Drain-to-Source Voltage

Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage

www.irf.com

IRLR/U9343 & IRLU9343-701

100.0

1000

100

OPERATION IN THIS AREA

LIMITED BY R (on)

= 175°C

10.0

1.0

100µsec

= 25°C

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

= 0V

10msec

0.1

100

1000

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

-V

, Drain-toSource Voltage (V)

-V , Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage

Fig 8. Maximum Safe Operating Area

2.5

2.0

1.5

1.0

= -250µA

100

125

150

175

-75 -50 -25

25 50 75 100 125 150 175

, Junction Temperature (°C)

T , Temperature ( °C )

Fig 10. Threshold Voltage vs. Temperature

Fig 9. Maximum Drain Current vs. Case Temperature

0.1

D = 0.50

0.20

0.10

R₁

R₂

Ri (°C/W) τi (sec)

0.05

^Jτ_J

1.162

0.000512

0.002157

^Cτ

0.02

0.01

¹τ₁

Ci= τi/Ri

²τ₂

0.7370

0.01

SINGLE PULSE

Notes:

( THERMAL RESPONSE )

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com

IRLR/U9343 & IRLU9343-701

500

600

500

400

300

200

100

= -14A

TOP

-4.0A

-5.5A

-14A

400

300

200

100

BOTTOM

= 125°C

= 25°C

4.0

6.0

8.0

10.0

100

125

150

175

-V , Gate-to-Source Voltage (V)

Starting T , Junction Temperature (°C)

Fig 12. On-Resistance Vs. Gate Voltage

Fig 13. Maximum Avalanche Energy Vs. Drain Current

1000

Allowed avalanche Current vs

avalanche pulsewidth, tav

Duty Cycle = Single Pulse

100

∆

assuming

Tj = 25°C due to

avalanche losses. Note: In no

case should Tj be allowed to

exceed Tjmax

0.01

0.05

0.10

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

tav (sec)

Fig 14. Typical Avalanche Current Vs.Pulsewidth

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T_jmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 17a, 17b.

140

120

100

TOP

BOTTOM 1% Duty Cycle

= -14A

Single Pulse

4. P_{D (ave)}= Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. I_av= Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

T_jmax(assumed as 25°C in Figure 14, 15).

t_{av =}Average time in avalanche.

D = Duty cycle in avalanche = t_av·f

Z_thJC(D, t_av) = Transient thermal resistance, see figure 11)

100

125

150

175

Starting T , Junction Temperature (°C)

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

I_av= 2DT/ [1.3·BV·Z_th]

Fig 15. Maximum Avalanche Energy Vs. Temperature

E_{AS (AR)}= P_{D (ave)}·t_av

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IRLR/U9343 & IRLU9343-701

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

=10V

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

Reverse

Recovery

Body Diode Forward

Current

di/dt

D.U.T. V Waveform

Diode Recovery

dv/dt

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

R_G

Body Diode

Forward Drop

Inductor

Inductor Curent

Current

Ripple ≤ 5%

* Reverse Polarity of D.U.T for P-Channel

* V_GS= 5V for Logic Level Devices

Fig 16. Peak Diode Recovery dv/dt Test Circuit for P-Channel

HEXFET^®Power MOSFETs

R_D

V_DS

D.U.T

V_GS

D.U.T.

DRIVER

-V

-20V

R_G

0.01

Ω

V_DD

-10V

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

15V

Fig 18a. Switching Time Test Circuit

Fig 17a. Unclamped Inductive Test Circuit

d(on)

d(off)

10%

90%

(BR)DSS

Fig 18b. Switching Time Waveforms

Fig 17b. Unclamped Inductive Waveforms

Vds

Vgs

VCC

DUT

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 19a. Gate Charge Test Circuit

Fig 19b Gate Charge Waveform

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IRLR/U9343 & IRLU9343-701

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

2.38 (.094)

2.19 (.086)

6.73 (.265)

6.35 (.250)

1.14 (.045)

0.89 (.035)

- A -

1.27 (.050)

5.46 (.215)

0.58 (.023)

0.46 (.018)

0.88 (.035)

5.21 (.205)

6.45 (.245)

5.68 (.224)

6.22 (.245)

5.97 (.235)

10.42 (.410)

9.40 (.370)

1.02 (.040)

1.64 (.025)

LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE

4 - DRAIN

0.51 (.020)

MIN.

- B -

1.52 (.060)

1.15 (.045)

0.89 (.035)

0.64 (.025)

0.58 (.023)

0.46 (.018)

1.14 (.045)

0.25 (.010)

M A M B

0.76 (.030)

NOTES:

2.28 (.090)

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

4.57 (.180)

3 CONFORMS TO JEDEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

D-Pak (TO-252AA) Part Marking Information

Notes: This part marking information applies todevices producedbefore02/26/2001

EXAMPLE: THIS IS AN IRFR120

WIT H AS S E MBLY

LOT CODE 9U1P

INTERNATIONAL

RECTIFIER

LOGO

DATE CODE

YEAR = 0

IRFU120

016

WE EK = 16

AS S E MB L Y

LOT CODE

Notes: This part marking information applies todevices producedafter 02/26/2001

EXAMPLE: THIS IS AN IRFR120

PART NUMBER

WIT H AS S E MBLY

LOT CODE 1234

ASSEMBLED ON WW 16, 1999

IN THE ASSEMBLY LINE "A"

INTERNATIONAL

RECTIFIER

LOGO

DATE CODE

YEAR 9 = 1999

WEE K 16

IRFU120

916A

LINE A

AS S E MBL Y

LOT CODE

www.irf.com

IRLR/U9343 & IRLU9343-701

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

6.73 (.265)

6.35 (.250)

2.38 (.094)

2.19 (.086)

- A -

0.58 (.023)

0.46 (.018)

1.27 (.050)

5.46 (.215)

0.88 (.035)

5.21 (.205)

LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

6.45 (.245)

5.68 (.224)

3 - SOURCE

4 - DRAIN

6.22 (.245)

5.97 (.235)

1.52 (.060)

1.15 (.045)

- B -

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

2.28 (.090)

1.91 (.075)

9.65 (.380)

8.89 (.350)

3 CONFORMS TO JEDEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

1.14 (.045)

0.76 (.030)

1.14 (.045)

0.89 (.035)

0.64 (.025)

0.25 (.010)

M A M B

0.58 (.023)

0.46 (.018)

2.28 (.090)

I-Pak (TO-251AA) Part Marking Information

Notes: This part marking information applies todevices produced before02/26/2001

EXAMPLE: THIS IS AN IRFR120

INTERNATIONAL

DATE CODE

YEAR = 0

WITH ASSEMBLY

LOT CODE 9U1P

RECTIFIER

LOGO

IRFU120

016

WEEK = 16

ASSEMBLY

LOT CODE

Notes: This part marking information applies todevices produced after 02/26/2001

PART NUMBER

EXAMPLE: THIS IS AN IRFR120

WITH ASSEMBLY

INTERNATIONAL

RECTIFIER

LOGO

DATE CODE

YEAR 9 = 1999

WEE K 19

IRFU120

919A

LOT CODE 5678

ASSEMBLED ON WW 19, 1999

IN THE ASSEMBLY LINE "A"

LINE A

ASSEMBLY

LOT CODE

www.irf.com

IRLR/U9343 & IRLU9343-701

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

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IRLR/U9343 & IRLU9343-701

I-Pak Leadform Option 701 Package Outline

Dimensions are shown in millimeters (inches)

Notes:

Contact factory for mounting information

Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information

Repetitive rating; pulse width limited by

max. junction temperature.

Starting T_J= 25°C, L = 1.24mH,

R_G= 25Ω, I_AS= -14A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

This only applies for I-Pak, L_Sof D-Pak is

measured between lead and center of die contact

When D-Pak mounted on 1" square PCB (FR-4 or G-10 Material) .

For recommended footprint and soldering techniques refer to

application note #AN-994

Refer to D-Pak package for Part Marking, Tape and Reel information.

ꢁ R is measured at T_Jof approximately 90°C.

Data and specifications subject to change without notice.

This product has been designed for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.4/04

www.irf.com

IRLR9343TRL [INFINEON]

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