IRLU2703PBF [INFINEON]
Logic-Level Gate Drive;
| 型号： | IRLU2703PBF |
| 厂家： | 
Infineon |
| 描述： | Logic-Level Gate Drive 局域网 栅 开关 脉冲 晶体管 |
| 文件： | 总11页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-95083A
IRLR/U2703PbF
HEXFET® Power MOSFET
l Logic-Level Gate Drive
l Ultra Low On-Resistance
l Surface Mount (IRLR2703)
l Straight Lead (IRLU2703)
l Advanced Process Technology
l Fast Switching
D
VDSS = 30V
RDS(on) = 0.045Ω
G
l Fully Avalanche Rated
l Lead-Free
ID = 23Aꢀ
S
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per
silicon area. This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs are well known for,
provides the designer with an extremely efficient device for use in a wide
variety of applications.
D-Pak
TO-252AA
I-Pak
TO-251AA
The D-PAK is designed for surface mounting using vapor phase, infrared, or
wave soldering techniques. The straight lead version (IRFU series) is for
through-hole mounting applications. Power dissipation levels up to 1.5 watts
are possible in typical surface mount applications.
Absolute Maximum Ratings
Parameter
Max.
23 ꢀ
16
Units
ID @ TC = 25°C
D @ TC = 100°C
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
A
IDM
96
PD @TC = 25°C
Power Dissipation
45
W
W/°C
V
Linear Derating Factor
0.30
± 16
77
VGS
EAS
IAR
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
14
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
4.5
5.0
mJ
V/ns
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Case-to-Ambient (PCB mount)**
Junction-to-Ambient
Typ.
–––
–––
–––
Max.
3.3
50
Units
RθJC
RθJA
RθJA
°C/W
110
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
www.irf.com
1
12/6/04
IRLR/U2703PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
30 ––– –––
––– 0.030 ––– V/°C Reference to 25°C, ID = 1mA
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
––– ––– 0.045
––– ––– 0.065
VGS = 10V, ID = 14A
VGS = 4.5V, ID = 12A
VDS = VGS, ID = 250µA
VDS = 25V, ID = 14A
VDS = 30V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 150°C
VGS = 16V
Ω
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
1.0
6.4
––– –––
––– –––
V
S
Forward Transconductance
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
––– ––– 15
––– ––– 4.6
––– ––– 9.3
IDSS
IGSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
VGS = -16V
Qg
ID = 14A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 24V
VGS = 4.5V, See Fig. 6 and 13
–––
8.5 –––
VDD = 15V
––– 140 –––
ID = 14A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
12 –––
20 –––
RG = 12Ω, VGS = 4.5V
RD = 1.0Ω, See Fig. 10
Between lead,
D
S
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
4.5
–––
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
and center of die contact
VGS = 0V
Ciss
Coss
Crss
Input Capacitance
––– 450 –––
––– 210 –––
––– 110 –––
Output Capacitance
pF
VDS = 25V
Reverse Transfer Capacitance
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
S
IS
––– –––
––– –––
23 ꢀ
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
96
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 65 97
––– 140 210
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
V
TJ = 25°C, IS = 14A, VGS = 0V
ns
TJ = 25°C, IF = 14A
Qrr
ton
nC di/dt = 100A/µs
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 15V, starting TJ = 25°C, L =570µH
RG = 25Ω, IAS = 14A. (See Figure 12)
ꢀ Caculated continuous current based on maximum allowable
junction temperature; Package limitation current = 20A.
This is applied for I-PAK, LS of D-PAK is measured
between
lead and center of die contact.
ISD ≤ 14A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
,
Uses IRL2703 data and test conditions.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
2
www.irf.com
IRLR/U2703PbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
TOP
TOP
12V
10V
8.0V
6.0V
4.0V
3.0V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
1
1
2.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T
= 25°C
T
= 175°C
J
J
0.1
0.1
0.1
0.1
A
A
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
I
=
23A
D
TJ= 25°C
TJ = 175°C
1.5
1.0
0.5
0.0
10
1
V DS= 15V
20µs PULSE WIDTH
V
= 10V
GS
0.1
A
10 A
2
3
4
5
6
7
8
9
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
T , Junction Temperature (°C)
J
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
www.irf.com
3
IRLR/U2703PbF
15
12
9
1000
I
= 14A
V
C
C
C
= 0V,
f = 1MHz
D
GS
iss
rss
oss
= C + C
,
C
SHORTED
V
V
= 24V
= 15V
gs
gd
gd
ds
DS
DS
= C
= C + C
ds
gd
800
600
400
200
0
C
C
iss
oss
6
C
rss
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
A
0
4
8
12
16
20
1
10
100
V
, Drain-to-Source Voltage (V)
Q , Total Gate Charge (nC)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
100
10
1
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T = 175°C
J
10µs
T = 25°C
J
100µs
1ms
T
T
= 25°C
= 175°C
C
J
10ms
V
= 0V
GS
Single Pulse
A
1
A
0.4
0.8
1.2
1.6
2.0
2.4
1
10
100
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
4
www.irf.com
IRLR/U2703PbF
RD
25
20
15
10
5
VDS
LIMITED BY PACKAGE
VGS
D.U.T.
RG
+VDD
-
4.5V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25
50
75
100
125
150
175
°
T , Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
D = 0.50
0.20
1
0.10
0.05
P
0.02
0.01
DM
0.1
t
SINGLE PULSE
1
t
(THERMAL RESPONSE)
2
Notes:
1. Duty factor D = t / t
1
2
2. Peak T = P
DM
x Z
+ T
thJC
C
J
A
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com
5
IRLR/U2703PbF
160
120
80
40
0
I
D
TOP
5.7A
9.9A
BOTTOM 14A
15V
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
= 15V
50
DD
A
175
25
75
100
125
150
Starting T , Junction Temperature (°C)
J
V
(BR)DSS
t
p
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
.2µF
12V
Q
G
.3µF
+
10 V
V
DS
D.U.T.
-
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
6
www.irf.com
IRLR/U2703PbF
Peak Diode Recovery dv/dt Test Circuit
+
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
www.irf.com
7
IRLR/U2703PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
INTERNATIONAL
RECTIFIER
LOGO
DAT E CODE
YEAR 9 = 1999
WE EK 16
IRFU120
916A
12
34
LINE A
Note: "P" in assembly lineposition
ASSEMBLY
LOT CODE
indicates "L ead-F ree"
OR
PART NUMBER
DATE CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
12 34
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEEK 16
A= ASSEMBLY SITE CODE
8
www.irf.com
IRLR/U2703PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
PART NUMBER
EXAMPLE: THIS IS AN IRFU120
INTERNATIONAL
RECTIFIER
LOGO
WITH ASSEMBLY
LOT CODE 5678
ASSEMBLED ON WW19, 1999
IN THE ASSEMBLY LINE "A"
DATE CODE
YEAR 9 = 1999
WEEK 19
IRFU120
919A
78
56
LINE A
AS S EMB L Y
LOT CODE
Note: "P" inassemblyline
position indicates "Lead-Free"
OR
PART NUMBER
DATE CODE
P = DE S IGNAT E S LE AD-F R EE
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
56 78
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEEK 19
A= ASSEMBLY SITE CODE
www.irf.com
9
IRLR/U2703PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
10
www.irf.com
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
相关型号：
IRLU3103PBF
Power Field-Effect Transistor, 20A I(D), 30V, 0.019ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, LEAD FREE, PLASTIC, IPAK-3
INFINEON
©2020 ICPDF网 联系我们和版权申明