IRLU2705 [INFINEON]
HEXFET POWER MOSFET; HEXFET功率MOSFET
| 型号： | IRLU2705 |
| 厂家： | 
Infineon |
| 描述： | HEXFET POWER MOSFET |
| 文件： | 总10页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-91317C
IRLR/U2705
HEXFET® Power MOSFET
l Logic-Level Gate Drive
l Ultra Low On-Resistance
l Surface Mount (IRLR2705)
l Straight Lead (IRLU2705)
l Advanced Process Technology
l Fast Switching
D
VDSS = 55V
R
DS(on) = 0.040Ω
ID = 28Aꢀ
G
S
l Fully Avalanche Rated
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per
silicon area. This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs are well known for,
provides the designer with an extremely efficient device for use in a wide
variety of applications.
D-Pak
TO-252AA
I-Pak
TO-251AA
The D-PAK is designed for surface mounting using vapor phase, infrared, or
wave soldering techniques. The straight lead version (IRFU series) is for
through-hole mounting applications. Power dissipation levels up to 1.5 watts
are possible in typical surface mount applications.
Absolute Maximum Ratings
Parameter
Max.
28
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
20
A
110
68
PD @TC = 25°C
PowerDissipation
W
W/°C
V
LinearDeratingFactor
0.45
± 16
110
16
VGS
EAS
IAR
Gate-to-SourceVoltage
Single Pulse Avalanche Energy
AvalancheCurrent
mJ
A
EAR
dv/dt
TJ
RepetitiveAvalancheEnergy
Peak Diode Recovery dv/dt
OperatingJunctionand
6.8
mJ
V/ns
5.0
-55 to + 175
TSTG
StorageTemperatureRange
SolderingTemperature, for10seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
2.2
50
Units
RθJC
RθJA
RθJA
Case-to-Ambient(PCBmount)**
Junction-to-Ambient
–––
°C/W
–––
110
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
www.irf.com
1
4/1/03
IRLR/U2705
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
55 ––– –––
––– 0.065 ––– V/°C Reference to 25°C, ID = 1mA
Conditions
V(BR)DSS
Drain-to-SourceBreakdownVoltage
V
VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ BreakdownVoltageTemp.Coefficient
––– ––– 0.040
––– ––– 0.051
––– ––– 0.065
VGS = 10V, ID = 17A
VGS = 5.0V, ID = 17A
VGS = 4.0V, ID = 14A
VDS = VGS, ID = 250µA
VDS = 25V, ID = 16A
VDS = 55V, VGS = 0V
VDS = 44V, VGS = 0V, TJ = 150°C
VGS = 16V
RDS(on)
StaticDrain-to-SourceOn-Resistance
W
VGS(th)
gfs
GateThresholdVoltage
1.0
11
––– 2.0
––– –––
V
S
ForwardTransconductance
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
––– ––– 25
––– ––– 5.2
––– ––– 14
IDSS
IGSS
Drain-to-SourceLeakageCurrent
µA
nA
Gate-to-SourceForwardLeakage
Gate-to-SourceReverseLeakage
Total Gate Charge
VGS = -16V
Qg
ID = 16A
Qgs
Qgd
td(on)
tr
Gate-to-SourceCharge
Gate-to-Drain("Miller")Charge
Turn-On Delay Time
Rise Time
nC VDS = 44V
VGS = 5.0V, See Fig. 6 and 13
–––
8.9 –––
VDD = 28V
––– 100 –––
ID = 16A
ns
td(off)
tf
Turn-Off Delay Time
FallTime
–––
–––
21 –––
29 –––
RG = 6.5Ω, VGS = 5.0V
RD = 1.8Ω, See Fig. 10
Betweenlead,
D
LD
LS
InternalDrainInductance
InternalSourceInductance
4.5
nH
6mm(0.25in.)
G
frompackage
––– 7.5 –––
and center of die contact
VGS = 0V
S
Ciss
Coss
Crss
InputCapacitance
––– 880 –––
––– 220 –––
OutputCapacitance
pF
VDS = 25V
ReverseTransferCapacitance
–––
94 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
IS
––– –––
28
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 110
S
p-n junction diode.
VSD
trr
DiodeForwardVoltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 76 110
––– 190 290
V
TJ = 25°C, IS = 17A, VGS = 0V
ns
TJ = 25°C, IF = 16A
Qrr
ton
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 610µH
RG = 25Ω, IAS = 16A. (See Figure 12)
ꢀ Caculated continuous current based on maximum allowable
junction temperature; Package limitation current = 20A.
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact.
ISD ≤ 16A, di/dt ≤ 270A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
,
Uses IRLZ34N data and test conditions.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
2
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IRLR/U2705
1000
100
10
1000
100
10
VGS
15V
VGS
15V
TOP
TOP
12V
12V
10V
10V
8.0V
6.0V
4.0V
3.0V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
1
1
2.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T
= 25°C
T
= 175°C
J
J
0.1
0.1
0.1
0.1
A
A
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
I
= 27A
D
2.5
2.0
1.5
1.0
0.5
0.0
100
10
1
T = 25°C
J
T = 175°C
J
V DS= 25V
20µs PULSE WIDTH
V
= 10V
GS
0.1
A
10A
2
3
4
5
6
7
8
9
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
T , Junction Temperature (°C)
J
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRLR/U2705
15
12
9
1400
I = 16A
D
V
C
C
C
= 0V,
f = 1MHz
GS
iss
rss
oss
= C + C
,
C
ds
SHORTED
gs
gd
= C
gd
V
V
= 44V
= 28V
1200
1000
800
600
400
200
0
DS
DS
= C + C
C
ds
gd
iss
C
oss
6
C
3
rss
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
A
0
4
8
12
16
20
24
28
32
1
10
100
Q , Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
100
10
1
10µs
T = 175°C
J
100µs
T = 25°C
J
1ms
T
T
= 25°C
C
J
= 175°C
Single Pulse
10ms
V
GS
= 0V
1
A
A
1
10
100
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRLR/U2705
RD
30
25
20
15
10
5
VDS
LIMITED BY PACKAGE
VGS
D.U.T.
RG
+VDD
-
5V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25
50
75
100
125
150
175
°
T , Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
D = 0.50
0.20
1
0.10
0.05
P
2
DM
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.1
t
1
t
2
Notes:
1. Duty factor D = t / t
1
2. Peak T =P
x Z
+ T
thJC C
J
DM
0.01
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U2705
250
200
150
100
50
I
D
TOP
6.6A
11A
BOTTOM 16A
15V
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
t
0.01Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
= 25V
50
DD
0
A
175
25
75
100
125
150
Starting T , Junction Temperature (°C)
J
V
(BR)DSS
t
p
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Fig 12b. Unclamped Inductive Waveforms
Same Type as D.U.T.
50KΩ
.2µF
12V
Q
G
.3µF
+
10 V
V
DS
D.U.T.
-
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
6
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IRLR/U2705
Peak Diode Recovery dv/dt Test Circuit
+
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRLR/U2705
Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
- A -
1.27 (.050)
5.46 (.215)
0.58 (.023)
0.46 (.018)
0.88 (.035)
5.21 (.205)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
10.42 (.410)
9.40 (.370)
1.02 (.040)
1.64 (.025)
LEAD ASSIGNMENTS
1 - GATE
1
2
3
2 - DRAIN
0.51 (.020)
MIN.
- B -
3 - SOURCE
4 - DRAIN
1.52 (.060)
1.15 (.045)
0.89 (.035)
0.64 (.025)
3X
0.58 (.023)
0.46 (.018)
1.14 (.045)
0.76 (.030)
2X
0.25 (.010)
M A M B
NOTES:
2.28 (.090)
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
4.57 (.180)
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
Part Marking Information
TO-252AA (D-PARK)
EXAMPLE : THIS IS AN IRFR120
WITH ASSEMBLY
A
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE 9U1P
FIRST PORTION
OF PART NUMBER
IRFR
120
9U 1P
ASSEMBLY
SECOND PORTION
OF PART NUMBER
LOT CODE
8
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IRLR/U2705
Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
- A -
0.58 (.023)
0.46 (.018)
1.27 (.050)
5.46 (.215)
0.88 (.035)
5.21 (.205)
LEAD ASSIGNMENTS
1 - GATE
4
2 - DRAIN
6.45 (.245)
5.68 (.224)
3 - SOURCE
4 - DRAIN
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
- B -
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
2.28 (.090)
1.91 (.075)
9.65 (.380)
8.89 (.350)
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.76 (.030)
1.14 (.045)
0.89 (.035)
3X
0.89 (.035)
0.64 (.025)
3X
0.25 (.010)
M A M B
0.58 (.023)
0.46 (.018)
2.28 (.090)
2X
Part Marking Information
TO-251AA (I-PARK)
EXAMPLE : THIS IS AN IRFU120
WITH ASSEMBLY
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE 9U1P
FIRST PORTION
OF PART NUMBER
IRFU
120
9U 1P
SECOND PORTION
OF PART NUMBER
ASSEMBLY
LOT CODE
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9
IRLR/U2705
Tape & Reel Information
TO-252AA
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
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IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
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http://www.irf.com/
Data and specifications subject to change without notice.
4/03
10
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相关型号：
IRLU3103PBF
Power Field-Effect Transistor, 20A I(D), 30V, 0.019ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, LEAD FREE, PLASTIC, IPAK-3
INFINEON
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