IRLU4343-701TRPBF [INFINEON]
Power Field-Effect Transistor, 26A I(D), 55V, 0.05ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, IPAK-3;型号: | IRLU4343-701TRPBF |
厂家: | Infineon |
描述: | Power Field-Effect Transistor, 26A I(D), 55V, 0.05ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, IPAK-3 |
文件: | 总10页 (文件大小:248K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 95851
IRLR4343
DIGITAL AUDIO MOSFET
IRLU4343
IRLU4343-701
Features
l Advanced Process Technology
Key Parameters
l Key Parameters Optimized for Class-D Audio
Amplifier Applications
l Low RDSON for Improved Efficiency
l Low Qg and Qsw for Better THD and Improved
Efficiency
VDS
RDS(ON) typ. @ VGS = 10V
DS(ON) typ. @ VGS = 4.5V
55
V
m:
m:
42
R
57
Qg typ.
TJ max
l Low Qrr for Better THD and Lower EMI
l 175°C Operating Junction Temperature for
Ruggedness
28
nC
°C
175
l Repetitive Avalanche Capability for Robustness and
Reliability
l Multiple Package Options
D
D-Pak
IRLR4343
I-Pak
IRLU4343
G
I-Pak Leadform 701
IRLU4343-701
S
Refer to page 10 for package outline
Description
This Digital Audio HEXFET® is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the latest
processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery
and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD
and EMI. Additional features of this MosFET are 175°C operating junction temperature and repetitive avalanche capability.
These features combine to make this MosFET a highly efficient, robust and reliable device for Class-D audio amplifier
applications.
Absolute Maximum Ratings
Max.
Parameter
Units
VDS
55
Drain-to-Source Voltage
V
VGS
±20
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current c
Power Dissipation
ID @ TC = 25°C
ID @ TC = 100°C
IDM
26
A
19
80
PD @TC = 25°C
PD @TC = 100°C
79
39
W
Power Dissipation
0.53
Linear Derating Factor
W/°C
°C
TJ
-40 to + 175
Operating Junction and
Storage Temperature Range
Clamping Pressure h
TSTG
–––
N
Thermal Resistance
Parameter
Typ.
–––
–––
–––
Max.
1.9
50
Units
RθJC
RθJA
RθJA
g
Junction-to-Case
Junction-to-Ambient (PCB Mounted)
gj
°C/W
Junction-to-Ambient (free air)
g
110
Notes through are on page 10
www.irf.com
1
3/26/04
IRLR/U4343 & IRLU4343-701
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Conditions
VGS = 0V, ID = 250µA
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
55
–––
15
–––
V
Reference to 25°C, I = 1mA
∆ΒVDSS/∆TJ
RDS(on)
–––
–––
–––
1.0
––– mV/°C
D
VGS = 10V, ID = 4.7A e
VGS = 4.5V, ID = 3.8A e
VDS = VGS, ID = 250µA
42
50
65
mΩ
57
VGS(th)
Gate Threshold Voltage
–––
-4.4
–––
–––
–––
–––
–––
28
–––
V
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
8.8
––– mV/°C
VDS = 55V, VGS = 0V
2.0
25
µA
nA
S
VDS = 55V, VGS = 0V, TJ = 125°C
VGS = 20V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
100
-100
–––
42
VGS = -20V
VDS = 25V, ID = 19A
VDS = 44V
gfs
Qg
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs
Qgd
Qgodr
td(on)
tr
VGS = 10V
Pre-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge Overdrive
Turn-On Delay Time
3.5
9.5
15
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
ID = 19A
See Fig. 6 and 19
VDD = 28V, VGS = 10Vꢀe
ID = 19A
5.7
19
Rise Time
td(off)
tf
RG = 2.5Ω
Turn-Off Delay Time
23
ns
Fall Time
5.3
740
150
59
VGS = 0V
Ciss
Coss
Crss
Coss
LD
Input Capacitance
VDS = 50V
Output Capacitance
pF
ƒ = 1.0MHz,
See Fig.5
Reverse Transfer Capacitance
Effective Output Capacitance
Internal Drain Inductance
VGS = 0V, VDS = 0V to -44V
250
4.5
D
Between lead,
G
nH 6mm (0.25in.)
from package
S
LS
Internal Source Inductance
–––
7.5
–––
and center of die contact f
Avalanche Characteristics
Typ.
Max.
Parameter
Units
mJ
A
EAS
IAR
–––
160
Single Pulse Avalanche Energyd
Avalanche Currentꢀi
See Fig. 14, 15, 17a, 17b
EAR
mJ
Repetitive Avalanche Energy i
Diode Characteristics
Conditions
MOSFET symbol
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
IS @ TC = 25°C
–––
–––
26
showing the
A
ISM
integral reverse
p-n junction diode.
Pulsed Source Current
(Body Diode)ꢀc
–––
–––
80
TJ = 25°C, IS = 19A, VGS = 0V e
TJ = 25°C, IF = 19A
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
52
1.2
78
V
ns
nC
Qrr
di/dt = 100A/µs e
100
150
2
www.irf.com
IRLR/U4343 & IRLU4343-701
1000
100
10
1000
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.5V
2.3V
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.5V
2.3V
TOP
TOP
100
10
1
BOTTOM
BOTTOM
2.3V
2.3V
1
≤
≤
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 25°C
Tj = 175°C
0.1
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000.0
100.0
10.0
1.0
I
= 19A
D
V
= 10V
GS
T
= 25°C
J
T
= 175°C
J
V
= 30V
DS
≤
60µs PULSE WIDTH
0.1
0
2
4
6
8
10
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
, Junction Temperature (°C)
J
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
10000
1000
100
20
V
= 0V,
= C
f = 1 MHZ
GS
I = 19A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
V
= 44V
= C
DS
rss
oss
gd
16
12
8
VDS= 28V
VDS= 11V
= C + C
ds
gd
Ciss
Coss
Crss
4
FOR TEST CIRCUIT
SEE FIGURE 19
0
10
0
10
20
30
40
1
10
, Drain-to-Source Voltage (V)
100
Q
Total Gate Charge (nC)
G
V
DS
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
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3
IRLR/U4343 & IRLU4343-701
1000
100
10
1000.0
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100.0
T
= 175°C
J
10.0
1.0
100µsec
1msec
T
= 25°C
J
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
1.6
GS
10msec
1
0.1
0
1
10
100
1000
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.8
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
30
2.0
1.5
1.0
0.5
25
20
15
10
5
I
= 250µA
D
0
25
50
75
100
125
150
175
-75 -50 -25
0
25 50 75 100 125 150 175
T
, Junction Temperature (°C)
T , Temperature ( °C )
J
J
Fig 10. Threshold Voltage vs. Temperature
Fig 9. Maximum Drain Current vs. Case Temperature
10
1
D = 0.50
0.20
0.10
R1
R1
R2
R2
Ri (°C/W) τi (sec)
0.1
0.05
τ
J τJ
1.359
0.00135
τ
Cτ
0.02
0.01
τ
τ
1τ1
Ci= τi/Ri
2τ2
0.5409
0.003643
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
4
www.irf.com
IRLR/U4343 & IRLU4343-701
700
200
150
100
50
I
I
= 19A
D
2.4A
3.3A
D
TOP
600
500
400
300
200
100
0
BOTTOM 19A
T
T
= 125°C
= 25°C
J
J
0
2.0
4.0
6.0
8.0
10.0
25
50
75
100
125
150
175
V
, Gate-to-Source Voltage (V)
GS
Starting T , Junction Temperature (°C)
J
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13. Maximum Avalanche Energy Vs. Drain Current
1000
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
0.01
∆
assuming
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
10
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 14. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 17a, 17b.
180
160
140
120
100
80
TOP
BOTTOM 1% Duty Cycle
= 19A
Single Pulse
I
D
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
60
40
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
20
0
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
Fig 15. Maximum Avalanche Energy Vs. Temperature
EAS (AR) = PD (ave)·tav
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5
IRLR/U4343 & IRLU4343-701
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
Reverse
Recovery
Body Diode Forward
Current
Current
-
+
di/dt
-
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
+
-
Body Diode
Forward Drop
Inductor
Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
15V
LD
VDS
DRIVER
+
L
V
DS
+
-
VDD
D.U.T
AS
R
G
V
DD
-
D.U.T
I
A
V
GS
VGS
0.01Ω
t
p
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 17a. Unclamped Inductive Test Circuit
Fig 18a. Switching Time Test Circuit
VDS
V
(BR)DSS
t
p
90%
10%
VGS
td(on)
td(off)
tr
tf
I
AS
Fig 18b. Switching Time Waveforms
Fig 17b. Unclamped Inductive Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 19a. Gate Charge Test Circuit
Fig 19b Gate Charge Waveform
6
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IRLR/U4343 & IRLU4343-701
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
- A -
1.27 (.050)
5.46 (.215)
0.58 (.023)
0.46 (.018)
0.88 (.035)
5.21 (.205)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
10.42 (.410)
9.40 (.370)
1.02 (.040)
1.64 (.025)
LEAD ASSIGNMENTS
1
2
3
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
0.51 (.020)
MIN.
- B -
1.52 (.060)
1.15 (.045)
0.89 (.035)
0.64 (.025)
3X
0.58 (.023)
0.46 (.018)
1.14 (.045)
2X
0.25 (.010)
M A M B
0.76 (.030)
NOTES:
2.28 (.090)
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
4.57 (.180)
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
D-Pak (TO-252AA) Part Marking Information
Notes: This part marking information applies todevices producedbefore02/26/2001
EXAMPLE: THIS IS AN IRFR120
WIT H AS S E MBLY
LOT CODE 9U1P
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
YEAR = 0
IRFU120
016
1P
WEE K = 16
9U
ASSEMBLY
LOT CODE
Notes: This part marking information applies todevices producedafter 02/26/2001
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WIT H AS S E MBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
YEAR 9 = 1999
WEE K 16
IRFU120
916A
34
12
LINE A
AS S E MBL Y
LOT CODE
www.irf.com
7
IRLR/U4343 & IRLU4343-701
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
- A -
0.58 (.023)
0.46 (.018)
1.27 (.050)
5.46 (.215)
0.88 (.035)
5.21 (.205)
LEAD ASSIGNMENTS
1 - GATE
4
2 - DRAIN
6.45 (.245)
5.68 (.224)
3 - SOURCE
4 - DRAIN
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
- B -
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
2.28 (.090)
1.91 (.075)
9.65 (.380)
8.89 (.350)
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.76 (.030)
1.14 (.045)
0.89 (.035)
3X
0.89 (.035)
0.64 (.025)
3X
0.25 (.010)
M A M B
0.58 (.023)
0.46 (.018)
2.28 (.090)
2X
I-Pak (TO-251AA) Part Marking Information
Notes: This part marking information applies todevices produced before02/26/2001
EXAMPLE: THIS IS AN IRFR120
INTERNATIONAL
DATE CODE
YEAR = 0
WITH ASSEMBLY
LOT CODE 9U1P
RECTIFIER
LOGO
IRFU120
016
1P
WEEK = 16
9U
ASSEMBLY
LOT CODE
Notes: This part marking information applies todevices produced after 02/26/2001
PART NUMBER
EXAMPLE: THIS IS AN IRFR120
WITH ASSEMBLY
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
YEAR 9 = 1999
WEE K 19
IRFU120
919A
78
LOT CODE 5678
ASSEMBLED ON WW 19, 1999
IN THE ASSEMBLY LINE "A"
56
LINE A
ASSEMBLY
LOT CODE
8
www.irf.com
IRLR/U4343 & IRLU4343-701
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
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9
IRLR/U4343 & IRLU4343-701
I-Pak Leadform Option 701 Package Outline
Dimensions are shown in millimeters (inches)
Notes:
Contact factory for mounting information
Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.93mH,
RG = 25Ω, IAS = 19A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This only applies for I-Pak, LS of D-Pak is
measured between lead and center of die contact
When D-Pak mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
Refer to D-Pak package for Part Marking, Tape and Reel information.
ꢁ R is measured at TJ of approximately 90°C.
θ
Data and specifications subject to change without notice.
This product has been designed for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.3/04
10
www.irf.com
相关型号:
IRLU4343PBF
Power Field-Effect Transistor, 26A I(D), 55V, 0.05ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, LEAD FREE, IPAK-3
VISHAY
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