IRLU7833 [INFINEON]
Power MOSFET; 功率MOSFET
| 型号： | IRLU7833 |
| 厂家： | 
Infineon |
| 描述： | Power MOSFET |
| 文件： | 总11页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 94547A
IRLR7833
IRLU7833
HEXFET® Power MOSFET
Applications
VDSS RDS(on) max
Qg
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
4.5m
30V
33nC
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
D-Pak
IRLR7833
I-Pak
IRLU7833
Absolute Maximum Ratings
Parameter
Max.
Units
VDS
Drain-to-Source Voltage
30
V
V
Gate-to-Source Voltage
± 20
GS
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
140
I
I
I
@ TC = 25°C
@ TC = 100°C
D
D
99
A
560
140
71
DM
Maximum Power Dissipation
Maximum Power Dissipation
P
P
@TC = 25°C
@TC = 100°C
W
D
D
Linear Derating Factor
Operating Junction and
0.95
W/°C
°C
T
-55 to + 175
J
T
Storage Temperature Range
STG
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case)
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
–––
–––
Max.
1.05
50
Units
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
Junction-to-Ambient
°C/W
110
Notes through ꢀ are on page 11
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1
3/19/04
IRLR/U7833
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
∆Β
Drain-to-Source Breakdown Voltage
30
–––
–––
V
VGS = 0V, ID = 250µA
∆
VDSS/ TJ
Breakdown Voltage Temp. Coefficient –––
19
––– mV/°C Reference to 25°C, ID = 1mA
mΩ
RDS(on)
Static Drain-to-Source On-Resistance
–––
–––
1.4
3.6
4.4
–––
-6.0
–––
–––
–––
–––
–––
33
4.5
5.5
2.3
VGS = 10V, ID = 15A
VGS = 4.5V, ID = 12A
VDS = VGS, ID = 250µA
VGS(th)
Gate Threshold Voltage
V
∆
∆
VGS(th)/ TJ
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
66
––– mV/°C
IDSS
1.0
150
100
-100
–––
50
µA
VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
nA VGS = 20V
VGS = -20V
gfs
Qg
S
VDS = 15V, ID = 12A
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
8.7
2.1
13
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
V
DS = 16V
GS = 4.5V
Qgs2
Qgd
nC
V
ID = 12A
Qgodr
Gate Charge Overdrive
9.9
15
See Fig. 16
Qsw
Switch Charge (Qgs2 + Qgd)
Qoss
td(on)
tr
Output Charge
22
nC VDS = 16V, VGS = 0V
DD = 15V, VGS = 4.5V
Turn-On Delay Time
Rise Time
14
V
6.9
23
ID = 12A
td(off)
tf
Turn-Off Delay Time
Fall Time
ns Clamped Inductive Load
15
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 4010 –––
VGS = 0V
pF VDS = 15V
ƒ = 1.0MHz
–––
–––
950
470
–––
–––
Avalanche Characteristics
Parameter
Typ.
–––
–––
–––
Max.
530
20
Units
mJ
A
Single Pulse Avalanche Energy
EAS
IAR
Avalanche Current
Repetitive Avalanche Energy
EAR
14
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
140
D
IS
Continuous Source Current
–––
–––
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
ISM
–––
–––
560
S
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
–––
39
1.0
58
55
V
T = 25°C, I = 12A, V = 0V
J S GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T = 25°C, I = 12A, VDD = 15V
J F
Qrr
ton
di/dt = 100A/µs
37
nC
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRLR/U7833
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
2.25V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
2.25V
BOTTOM
BOTTOM
1
2.25V
2.25V
0.1
0.01
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
1
0.1
1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
1.5
1.0
0.5
1000.0
100.00
10.00
1.00
I
= 30A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
V
= 25V
DS
20µs PULSE WIDTH
0.10
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
2.0
3.0
4.0
5.0
6.0
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
vs. Temperature
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3
IRLR/U7833
6.0
5.0
4.0
3.0
2.0
1.0
0.0
100000
V
= 0V,
f = 1 MHZ
GS
I = 12A
D
C
= C + C , C SHORTED
iss
gs gd ds
C
= C
V
V
= 24V
= 15V
rss
gd
DS
DS
C
= C + C
ds gd
oss
10000
1000
100
C
C
iss
oss
C
rss
0
10
20
30
40
50
1
10
, Drain-to-Source Voltage (V)
100
Q
Total Gate Charge (nC)
V
G
DS
Fig 6. Typical Gate Charge vs.
Fig 5. Typical Capacitance vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.00
100.00
10.00
1.00
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100µsec
1msec
T
= 25°C
J
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
10msec
100
GS
0.10
1
0.0
0.5
1.0
1.5
2.0
2.5
1
10
1000
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRLR/U7833
2.5
2.0
1.5
1.0
0.5
0.0
150
125
100
75
LIMITED BY PACKAGE
I
= 250µA
D
50
25
0
25
50
75
100
125
150
175
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
TC, Case Temperature (°C)
T
J
Fig 9. Maximum Drain Current vs.
Fig 10. Threshold Voltage vs. Temperature
Case Temperature
10
1
D = 0.50
0.20
P
DM
0.10
0.05
0.1
t
1
SINGLE PULSE
0.02
0.01
t
2
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U7833
15V
15000
12500
10000
7500
5000
2500
0
I
D
TOP
8.2A
14A
DRIVER
+
L
V
DS
BOTTOM 20A
D.U.T
AS
R
G
V
DD
-
I
A
2
VGS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
Starting T , Junction Temperature (°C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
RD
VDS
Fig 12b. Unclamped Inductive Waveforms
VGS
D.U.T.
RG
+VDD
-
Current Regulator
VGS
Same Type as D.U.T.
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
50KΩ
.2µF
12V
Fig 14a. Switching Time Test Circuit
.3µF
+
V
DS
V
DS
D.U.T.
-
90%
V
GS
3mA
10%
V
I
I
GS
G
D
Current Sampling Resistors
t
t
r
t
t
f
d(on)
d(off)
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRLR/U7833
Driver Gate Drive
P.W.
P.W.
D =
D.U.T
Period
Period
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
+
-
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRLR/U7833
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
drive output
loss
conduction
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
Qoss
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
in rr in
(
)
2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on )
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
Qgd
ig
Qgs2
ig
+ I ×
× V × f + I ×
× V × f
in
in
+ Q × V × f
(
Qoss
)
g
g
+
×V × f
in
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFETdata sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRLR/U7833
TO-252AA (D-Pak) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
- A -
1.27 (.050)
5.46 (.215)
0.58 (.023)
0.46 (.018)
0.88 (.035)
5.21 (.205)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
10.42 (.410)
9.40 (.370)
1.02 (.040)
1.64 (.025)
LEAD ASSIGNMENTS
1 - GATE
1
2
3
2 - DRAIN
0.51 (.020)
MIN.
- B -
3 - SOURCE
4 - DRAIN
1.52 (.060)
1.15 (.045)
0.89 (.035)
0.64 (.025)
3X
0.58 (.023)
0.46 (.018)
1.14 (.045)
0.76 (.030)
2X
0.25 (.010)
M A M B
NOTES:
2.28 (.090)
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
4.57 (.180)
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
TO-252AA (D-Pak) Part Marking Information
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9
IRLR/U7833
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
- A -
0.58 (.023)
0.46 (.018)
1.27 (.050)
5.46 (.215)
0.88 (.035)
5.21 (.205)
LEAD ASSIGNMENTS
1 - GATE
4
2 - DRAIN
6.45 (.245)
5.68 (.224)
3 - SOURCE
4 - DRAIN
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
- B -
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
2.28 (.090)
1.91 (.075)
9.65 (.380)
8.89 (.350)
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.76 (.030)
1.14 (.045)
0.89 (.035)
3X
0.89 (.035)
0.64 (.025)
3X
0.25 (.010)
M A M B
0.58 (.023)
0.46 (.018)
2.28 (.090)
2X
I-Pak (TO-251AA) Part Marking Information
10
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IRLR/U7833
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Calculated continuous current based on maximum allowable
Repetitive rating; pulse width limited by
max. junction temperature.
junction temperature. Package limitation current is 30A.
Starting TJ = 25°C, L = 2.6mH, RG = 25Ω,
IAS = 20A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/04
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11
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