IRLU7843_技术文档

PD - 94638A

IRLR7843

IRLU7843

HEXFET^®Power MOSFET

Applications

V_DSSR_DS(on)max

Qg

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification

for Telecom and Industrial Use

3.3m

30V

34nC

Benefits

l Very Low RDS(on) at 4.5V V_GS

l Ultra-Low Gate Impedance

l Fully Characterized Avalanche Voltage

and Current

D-Pak

IRLR7843

I-Pak

IRLU7843

Absolute Maximum Ratings

Parameter

Max.

Units

V_DS

Drain-to-Source Voltage

30

V

Gate-to-Source Voltage

± 20

GS

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

161

113

620

I

@ T_C= 25°C

@ T_C= 100°C

D

A

DM

Maximum Power Dissipation

P

@T_C= 25°C

@T_C= 100°C

140

71

W

D

Linear Derating Factor

Operating Junction and

0.95

-55 to + 175

W/°C

°C

T

J

T

Storage Temperature Range

STG

Soldering Temperature, for 10 seconds

300 (1.6mm from case)

Thermal Resistance

Parameter

Typ.

–––

Max.

1.05

50

Units

R_θJC

R_θJA

Junction-to-Case

Junction-to-Ambient (PCB Mount)

Junction-to-Ambient

°C/W

110

Notes through ꢀ are on page 11

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1

12/30/03

IRLR/U7843

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

Conditions

BV_DSS

∆Β

Drain-to-Source Breakdown Voltage

30

–––

V

V_GS= 0V, I_D= 250µA

∆

V

_DSS/ T_J

Breakdown Voltage Temp. Coefficient –––

19

––– mV/°C Reference to 25°C, I_D= 1mA

mΩ

R_DS(on)

Static Drain-to-Source On-Resistance

–––

1.5

2.6

3.2

–––

-5.4

–––

34

3.3

4.0

2.3

V_GS= 10V, I_D= 15A

V_GS= 4.5V, I_D= 12A

V_DS= V_GS, I_D= 250µA

V_GS(th)

Gate Threshold Voltage

V

∆

V

∆

_GS(th)/ T_J

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

–––

37

––– mV/°C

I_DSS

1.0

150

100

-100

–––

50

µA

V_DS= 24V, V_GS= 0V

V_DS= 24V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

nA V_GS= 20V

V_GS= -20V

gfs

Q_g

S

V_DS= 15V, I_D= 12A

–––

Q_gs1

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

9.1

2.5

12

–––

V

_DS= 15V

_GS= 4.5V

Q_gs2

Q_gd

nC

V

I_D= 12A

Q_godr

Gate Charge Overdrive

10

See Fig. 16

Q_sw

Switch Charge (Q_gs2+ Q_gd)

15

Q_oss

t_d(on)

t_r

Output Charge

21

nC V_DS= 15V, V_GS= 0V

_DD= 15V, V_GS= 4.5V

Turn-On Delay Time

Rise Time

25

V

42

I_D= 12A

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

34

ns Clamped Inductive Load

19

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 4380 –––

V_GS= 0V

pF V_DS= 15V

ƒ = 1.0MHz

–––

940

430

–––

Avalanche Characteristics

Parameter

Typ.

–––

Max.

1440

12

Units

mJ

A

Single Pulse Avalanche Energy

E_AS

I_AR

Avalanche Current

Repetitive Avalanche Energy

E_AR

14

mJ

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

MOSFET symbol

161

I_S

Continuous Source Current

–––

(Body Diode)

A

showing the

I_SM

Pulsed Source Current

–––

620

integral reverse

(Body Diode)

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

–––

39

1.0

59

54

V

T = 25°C, I = 12A, V = 0V

J S GS

Reverse Recovery Time

Reverse Recovery Charge

Forward Turn-On Time

ns T = 25°C, I = 12A, V_DD= 15V

J F

Q_rr

t_on

di/dt = 100A/µs

36

nC

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

2

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IRLR/U7843

1000

100

10

1000

100

10

VGS

10V

VGS

10V

TOP

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V

BOTTOM 2.5V

2.5V

1

20µs PULSE WIDTH

Tj = 175°C

20µs PULSE WIDTH

Tj = 25°C

1

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

2.0

1.5

1.0

0.5

1000

100

I

= 30A

D

V

= 10V

GS

T

= 175°C

J

T

= 25°C

J

10

V

= 15V

DS

20µs PULSE WIDTH

1

-60 -40 -20

T

0

20 40 60 80 100 120 140 160 180

2.0

3.0

4.0 5.0

, Junction Temperature (°C)

V

, Gate-to-Source Voltage (V)

J

GS

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

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3

IRLR/U7843

12

10

8

100000

V

= 0V,

f = 1 MHZ

GS

I

= 12A

D

V

= 24V

DS

VDS= 15V

C

= C + C

,

C

SHORTED

iss

gs gd

ds

C

= C

rss

gd

C

= C + C

oss

ds

gd

10000

1000

100

Ciss

6

Coss

Crss

4

2

0

20

G

40

60

80

1

10

, Drain-to-Source Voltage (V)

100

Q

Total Gate Charge (nC)

V

DS

Fig 6. Typical Gate Charge vs.

Fig 5. Typical Capacitance vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000.0

10000

1000

100

10

OPERATION IN THIS AREA

LIMITED BY R

(on)

DS

100.0

10.0

1.0

T

= 175°C

J

100µsec

T

= 25°C

1.0

1msec

J

Tc = 25°C

Tj = 175°C

Single Pulse

V

= 0V

GS

10msec

1

0.1

1.0

10.0

100.0

1000.0

0.0

0.5

1.5

V

, Drain-toSource Voltage (V)

V

, Source-toDrain Voltage (V)

DS

SD

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

4

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IRLR/U7843

2.5

2.0

1.5

1.0

0.5

0.0

160

120

80

LIMITED BY PACKAGE

I

= 250µA

D

40

0

25

50

75

100

125

150

175

-75 -50 -25

0

25 50 75 100 125 150 175

, Temperature ( °C )

T

, Case Temperature (°C)

C

T

J

Fig 9. Maximum Drain Current vs.

Fig 10. Threshold Voltage vs. Temperature

Case Temperature

10

1

0.1

D = 0.50

0.20

0.10

R₁

R₂

Ri (°C/W) τi (sec)

τ_J

τ

^Cτ

0.5084

0.5423

0.000392

0.011108

τ_J

τ

0.05

¹τ₁

Ci= τi/Ri

τ

²τ₂

0.02

0.01

0.001

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

1E-006

1E-005

0.0001

0.001

0.01

0.1

t

, Rectangular Pulse Duration (sec)

1

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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5

IRLR/U7843

15V

6000

5000

4000

3000

2000

1000

0

I

D

TOP

8.6A

9.6A

DRIVER

+

L

V

DS

BOTTOM 12A

D.U.T

AS

R

G

V

DD

-

I

A

2

V0_GV_S

Ω

0.01

t

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

25

50

75

100

125

150

175

Starting T , Junction Temperature (°C)

J

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

I

AS

L_D

V_DS

Fig 12b. Unclamped Inductive Waveforms

+

-

V_DD

D.U.T

Current Regulator

Same Type as D.U.T.

V_GS

Pulse Width < 1µs

Duty Factor < 0.1%

50KΩ

.2µF

12V

.3µF

Fig 14a. Switching Time Test Circuit

V_DS

+

V

DS

D.U.T.

-

90%

V

GS

3mA

10%

V_GS

I

D

G

Current Sampling Resistors

t_d(on)

t_d(off)

t_r

t_f

Fig 13. Gate Charge Test Circuit

Fig 14b. Switching Time Waveforms

6

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IRLR/U7843

Driver Gate Drive

P.W.

D =

D.U.T

Period

+

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

-

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

-

+

di/dt

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

R_G

+

-

Body Diode

Forward Drop

Inductor Curent

I

SD

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 16. Gate Charge Waveform

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7

IRLR/U7843

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

drive output

loss

conduction

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

g



Q_oss



P_loss= P_conduction+ P_switching+ P_drive+ P_output



+

×V × f + Q × V × f

in rr in

(

)

 2



This can be expanded and approximated by;

*dissipated primarily in Q1.

P

= I ²× R_{ds(on )}

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.



Q_gd

i_g



Q_gs2

i_g













+ I ×

× V × f + I ×

× V × f

in







+ Q × V × f

(

 Q_oss



)

g





+

×V × f

in

2

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFETdata sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

8

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IRLR/U7843

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

2.38 (.094)

2.19 (.086)

6.73 (.265)

6.35 (.250)

1.14 (.045)

0.89 (.035)

- A -

1.27 (.050)

5.46 (.215)

0.58 (.023)

0.46 (.018)

0.88 (.035)

5.21 (.205)

4

6.45 (.245)

5.68 (.224)

6.22 (.245)

5.97 (.235)

10.42 (.410)

9.40 (.370)

1.02 (.040)

1.64 (.025)

LEAD ASSIGNMENTS

1 - GATE

1

2

3

2 - DRAIN

0.51 (.020)

MIN.

- B -

3 - SOURCE

4 - DRAIN

1.52 (.060)

1.15 (.045)

0.89 (.035)

0.64 (.025)

3X

0.58 (.023)

0.46 (.018)

1.14 (.045)

0.76 (.030)

2X

0.25 (.010)

M A M B

NOTES:

2.28 (.090)

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

4.57 (.180)

3 CONFORMS TO JEDEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

D-Pak (TO-252AA) Part Marking Information

Notes: This part marking information applies todevices produced before02/26/2001

EXAMPLE: THIS IS AN IRFR120

WITH ASSEMBLY

LOT CODE 9U1P

INTERNATIONAL

RECTIFIER

LOGO

DAT E CODE

YEAR = 0

WE EK = 16

IRFU120

016

1P

9U

AS S E MBL Y

LOT CODE

Notes: This part marking information applies todevices produced after 02/26/2001

EXAMPLE: THIS IS AN IRFR120

PART NUMBER

WITH ASSEMBLY

LOT CODE 1234

ASSEMBLED ON WW 16, 1999

IN THE ASSEMBLY LINE "A"

INTERNATIONAL

RECTIFIER

LOGO

DATE CODE

YEAR 9 = 1999

WE E K 16

IRFU120

916A

34

12

LINE A

AS S E MBL Y

LOT CODE

www.irf.com

9

IRLR/U7843

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

6.73 (.265)

6.35 (.250)

2.38 (.094)

2.19 (.086)

- A -

0.58 (.023)

0.46 (.018)

1.27 (.050)

5.46 (.215)

0.88 (.035)

5.21 (.205)

LEAD ASSIGNMENTS

1 - GATE

4

2 - DRAIN

6.45 (.245)

5.68 (.224)

3 - SOURCE

4 - DRAIN

6.22 (.245)

5.97 (.235)

1.52 (.060)

1.15 (.045)

1

2

3

- B -

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

2.28 (.090)

1.91 (.075)

9.65 (.380)

8.89 (.350)

3 CONFORMS TO JEDEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

1.14 (.045)

0.76 (.030)

1.14 (.045)

0.89 (.035)

3X

0.89 (.035)

0.64 (.025)

3X

0.25 (.010)

M A M B

0.58 (.023)

0.46 (.018)

2.28 (.090)

2X

I-Pak (TO-251AA) Part Marking Information

Notes: This part marking information applies to devices produced before02/26/2001

EXAMPLE: THIS IS AN IRFR120

INTERNATIONAL

DAT E CODE

YEAR = 0

WEE K = 16

WIT H AS S E MB LY

LOT CODE 9U1P

RECTIFIER

LOGO

IRFU120

016

1P

9U

AS S E MBL Y

LOT CODE

Notes: This part marking information applies to devices producedafter 02/26/2001

PART NUMBER

EXAMPLE: THIS IS AN IRFR120

WIT H AS S E MB LY

INTERNATIONAL

RECTIFIER

LOGO

DAT E CODE

YEAR 9 = 1999

WE EK 19

IRFU120

919A

78

LOT CODE 5678

AS S E MBLE D ON WW 19, 1999

IN THE ASSEMBLY LINE "A"

56

LINE A

AS S E MB L Y

LOT CODE

10

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IRLR/U7843

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Notes:

Calculated continuous current based on maximum allowable

Repetitive rating; pulse width limited by

max. junction temperature.

junction temperature. Package limitation current is 30A.

Starting T_J= 25°C, L = 20mH, R_G= 25Ω,

I_AS= 12A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to

application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.12/03

www.irf.com

11


型号：	IRLU7843
厂家：	Infineon
描述：	HEXFET Power MOSFET HEXFET功率MOSFET 晶体晶体管开关脉冲
文件：	总11页 (文件大小：202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRLU7843 [INFINEON]

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