IRMCF143TR_技术文档

IRMCF143S

High Performance Position Servo

Control IC

Description

IRMCF143S is a high performance Flash based motion control IC designed primarily for position servo

applications based on an incremental encoder. IRMCF143S is designed to achieve low cost yet high performance

control solutions for advanced inverterized servo motor control. IRMCF143S contains two computation engines.

One is the Flexible Motion Control Engine (MCE^TM) for sinusoidal Field Oriented Control (FOC) of servo motors;

the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one

monolithic chip. The MCE^TMcontains a collection of control elements implemented in a dedicated computation

engine such as Proportional plus Integral, Vector rotator, Angle estimator, Multiply/Divide, and Low loss SVPWM.

The user can program a motion control algorithm by connecting these control elements using a graphic compiler.

A unique analog/digital circuit and algorithm to fully support two leg shunt current sensing is also provided. The

8051 microcontroller performs 2-cycle instruction execution (15MIPS at 30MHz 8051CLK). The MCE and 8051

microcontroller are connected via dual port RAM for signal monitoring and command input. An advanced graphic

compiler for the MCE^TMis seamlessly integrated into the MATLAB/Simulink environment, while third party JTAG-

based emulator tools are supported for 8051 software development. IRMCF143S comes in a 64 pin QFP package.

Features

Product Summary

Maximum clock input (f_crystal

•

MCE^TM(Flexible Motion Control Engine)

-

Dedicated computation engine for high efficiency

sinusoidal FOC control

)

60MHz

120MHz

30MHz

Maximum Internal clock (SYSCLK)

Maximum 8051 clock (8051CLK)

FOC computation time

•

Built-in hardware peripheral for two shunt current

feedback reconstruction and analog circuits

Supports incremental encoder with Hall effect

position sensor initialization

35 μsec@100MHz

16 bit signed

52KB

MCE^TMcomputation data range

8051 Program Flash

•

24bit position counter

Position capture and compare

Pulse + Direction input

Brake control with gatekill input

8051/MCE Data RAM

MCE Program RAM

4KB

12KB

2 μsec

20 bits/ SYSCLK

8

GateKill latency (digital filtered)

PWM carrier frequency

A/D input channels

A/D converter resolution

A/D converter conversion speed

Analog output (PWM) resolution

UART baud rate (typ)

Encoder interface

Number of digital I/O (max)

Package (lead free)

Loss minimization Space Vector PWM

Three-channel analog outputs (PWM)

Embedded 8-bit high speed microcontroller (8051)

for flexible I/O and man-machine control

JTAG programming port for emulation/debugger

Serial communication interface (UART)

I2C/SPI serial interface

Three general purpose timers, one capture timer

Watchdog timer with independent internal clock

Internal 64 Kbyte flash memory

12 bits

2 μsec

8 bits

57.6K bps

6

•

22

QFP64

5V tolerant I/O

3.3V single supply

Ordering Information

Standard Pack

Orderable Part Number

Package Type

Form

Tape and Reel

Tray

Quantity

2000

IRMCF143TR

IRMCF143TY

LQFP64

2000

1

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IRMCF143S

Table of Contents

1

2

3

4

Overview ..............................................................................................................................................................5

Pinout ...................................................................................................................................................................6

IRMCF143S Block Diagram and Main Functions ................................................................................................7

Application connection and Pin function ..............................................................................................................8

4.1

8051 Peripheral Interface Group..................................................................................................................9

Motion Peripheral Interface Group.............................................................................................................10

Analog Interface Group..............................................................................................................................10

Power Interface Group...............................................................................................................................11

Test Interface Group..................................................................................................................................11

4.2

4.3

4.4

4.5

5

DC Characteristics .............................................................................................................................................11

5.1

Absolute Maximum Ratings .......................................................................................................................12

System Clock Frequency and Power Consumption ..................................................................................12

Digital I/O DC Characteristics ....................................................................................................................13

PLL and Oscillator DC characteristics .......................................................................................................14

Analog I/O DC Characteristics...................................................................................................................14

Under Voltage Lockout DC characteristics................................................................................................15

Itrip comparator DC characteristics ...........................................................................................................15

CMEXT and AREF Characteristics............................................................................................................15

5.2

5.3

5.4

5.5

5.6

5.7

5.8

6

AC Characteristics .............................................................................................................................................16

6.1

Digital PLL AC Characteristics...................................................................................................................16

Analog to Digital Converter AC Characteristics.........................................................................................17

Op amp AC Characteristics .......................................................................................................................18

SYNC to SVPWM and A/D Conversion AC Timing ...................................................................................19

GATEKILL to SVPWM AC Timing .............................................................................................................20

Itrip AC Timing ...........................................................................................................................................20

Interrupt AC Timing....................................................................................................................................21

I²C AC Timing ............................................................................................................................................22

SPI AC Timing............................................................................................................................................23

SPI Write AC timing ...................................................................................................................................23

SPI Read AC Timing..................................................................................................................................24

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10 UART AC Timing .......................................................................................................................................25

6.11 CAPTURE Input AC Timing.......................................................................................................................26

6.12 JTAG AC Timing........................................................................................................................................27

I/O Structure.......................................................................................................................................................28

Pin List................................................................................................................................................................31

Package Dimensions .........................................................................................................................................33

7

8

9

10 Part Marking Information....................................................................................................................................34

11 Qualification Information† ..................................................................................................................................34

1

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IRMCF143S

List of Tables

Table 1. Absolute Maximum Ratings................................................................................................................... 12

Table 2. System Clock Frequency....................................................................................................................... 12

Table 3. Digital I/O DC Characteristics................................................................................................................ 13

Table 4. PLL DC Characteristics ......................................................................................................................... 14

Table 5. Analog I/O DC Characteristics............................................................................................................... 14

Table 6. UVcc DC Characteristics ....................................................................................................................... 15

Table 7. Itrip DC Characteristics.......................................................................................................................... 15

Table 8. CMEXT and AREF DC Characteristics ................................................................................................. 15

Table 9. PLL AC Characteristics.......................................................................................................................... 16

Table 10. A/D Converter AC Characteristics......................................................................................................... 17

Table 11. Current Sensing OP Amp AC Characteristics ....................................................................................... 18

Table 12. SYNC AC Characteristics...................................................................................................................... 19

Table 13. GATEKILL to SVPWM AC Timing......................................................................................................... 20

Table 14. Itrip AC Timing....................................................................................................................................... 20

Table 15. Interrupt AC Timing................................................................................................................................ 21

Table 16. I²C AC Timing ........................................................................................................................................ 22

Table 17. SPI Write AC Timing.............................................................................................................................. 23

Table 18. SPI Read AC Timing.............................................................................................................................. 24

Table 19. UART AC Timing ................................................................................................................................... 25

Table 20. CAPTURE AC Timing............................................................................................................................ 26

Table 21. JTAG AC Timing.................................................................................................................................... 27

Table 22. Pin List................................................................................................................................................... 32

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List of Figures

Figure 1. Typical Application Block Diagram Using IRMCF143S.............................................................................. 5

Figure 2. Pinout of IRMCF143S ................................................................................................................................ 6

Figure 3. IRMCF143S Block Diagram ....................................................................................................................... 7

Figure 4. IRMCF143S Application Diagram .............................................................................................................. 8

Figure 5. Crystal circuit example ............................................................................................................................. 16

Figure 6. Voltage droop and S/H hold time ............................................................................................................. 17

Figure 7. Op amp output capacitor.......................................................................................................................... 18

Figure 8. SYNC timing............................................................................................................................................. 19

Figure 9. Gatekill timing........................................................................................................................................... 20

Figure 10. ITRIP timing............................................................................................................................................ 20

Figure 11. Interrupt timing ....................................................................................................................................... 21

Figure 12. I²C Timing............................................................................................................................................... 22

Figure 13. SPI write timing ...................................................................................................................................... 23

Figure 14. SPI read timing....................................................................................................................................... 24

Figure 15. UART timing........................................................................................................................................... 25

Figure 16. CAPTURE timing.................................................................................................................................... 26

Figure 17. JTAG timing............................................................................................................................................ 27

Figure 18. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH/BRAKE output .............................................. 28

Figure 19. All digital I/O except PWM output........................................................................................................... 28

Figure 20. RESET, GATEKILL I/O .......................................................................................................................... 28

Figure 21. Analog input ........................................................................................................................................... 29

Figure 22. Analog operational amplifier output and AREF I/O structure................................................................. 29

Figure 23. VSS,AVSS pin I/O structure................................................................................................................... 29

Figure 24. VDD1,VDDCAP pin I/O structure........................................................................................................... 30

Figure 25. XTAL0/XTAL1 pins structure.................................................................................................................. 30

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1 Overview

IRMCF143S is a new generation International Rectifier integrated circuit device primarily designed as a one-chip

solution for complete inverter controlled position servo motor control applications. Unlike a traditional

microcontroller or DSP, the IRMCK401 provides a built-in encoder interface and associated Field Oriented

Control algorithm using the unique Flexible Motion Control Engine (MCETM) for a permanent magnet motor. It

contains a flexible 24bit position counter, and separate position capture/compare unit to facilitate indexing

function. The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion control

sequencer and dual port RAM to map internal signal nodes. IRMCK401 also employs additional PWM unit to

control a brake IGBT. Motion control programming is achieved using a dedicated graphical compiler integrated

into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and

upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051

microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical

application schematic using the IRMCF143S.

IRMCF143S contains 64K bytes of Flash program memory and comes in a 64-pin QFP package.

Host

communication

Galvanic

isolation

Passive

EMI

Filter

Motor

(PMSM)

6

7

IRS2630D

IRMCF143S

Power

Supply

3.3V

Encoder

Optional

2

EEPROM

opto isolation

17

Digial I/O

6

Analog Input

Figure 1. Typical Application Block Diagram Using IRMCF143S

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IRMCF143S

2 Pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

XTAL0

XTAL1

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PWMVH

P3.6

P1.0/PULSE/T2/MT1

SCL/SDI-SDO

SDA/CS0

3

P2.1

4

P3.7

5

PWMWH

PWMUL

PWMVL

PWMWL

P3.1/AO2/MT3

VSS

P1.3/SYNC/SCK

P1.4/ENC-A

P1.6/ENC-B

P1.7/ENC-Z

VDD1

6

7

8

9

IRMCF143S

10

11

12

13

14

15

16

(Top View)

VSS

VDD1

VDDCAP

AVSS

P2.0/DIR/NMI

P3.2/INT0

IFBVO

IFBV+

P2.2/CAP

P2.3/MATCH

IFBV-

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 2. Pinout of IRMCF143S

6

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3 IRMCF143S Block Diagram and Main Functions

Mini-Motion

2

D/A

(PWM)

Monitoring

6

To IGBT

gate drive

Control

Engine

(MiniMCE)

Speed

command

Low Loss

SVPWM

Capture

GATEKILL

Timer

Counnter0,1,2

3

From Encoder

From Hall

Encoder

Interface

Watchdog

Timer

Program

Flash

64kB

TXD

RXD

UART

I2C

Brake IGBT

Brake GK

Host

Break

SCL

SDA

Interface

Dual Port

RAM

2kbyte

Motion

Control

Modules

IFBU

IFBV

8bit

CPU

Core

U Phase

V Phase

PORT 1

PORT 2

PORT 3

Leg current

sensing

Digital

I/Os

MCE

Program

RAM

OP1

VBUS

AIN1

AIN2

AIN3

AIN4

Local

RAM

2kbyte

Analog

Input

12kbyte

A/D

MUX

S/H

Interrupt

Control

8bit (8051)

microcontroller

4

Emulator

JTAG

Debugger

Motion Control

Sequencer

2

30MHz

120MHz

Resonator

(4MHz)

Freq

Synthesizer

Figure 3. IRMCF143S Block Diagram

IRMCF143S contains the following functions for AC motor control applications:

Motion Control Engine (MCE^TM)

•

FOC (complete Field Oriented Control)

Proportional plus Integral block

Low pass filter

•

Subtractor

Comparator

Counter

Differentiator and lag (high pass filter)

Ramp

Accumulator

Switch

Limit

Shift

Angle estimate (sensorless control)

Inverse Clark transformation

Vector rotator

ATAN (arc tangent)

Function block (any curve fitting, nonlinear

function)

•

16 bit wide Logic operations (AND, OR,

XOR, NOT, NEGATE)

Bit latch

Peak detect

MCE^TMprogram memory and dual port RAM

(6K byte)

Transition

Multiply-divide (signed and unsigned)

Adder

MCE^TMcontrol sequence

Divide (signed and unsigned)

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IRMCF143S

8051 microcontroller

•

Two 16 bit timer/counters

•

JTAG port (4 pins)

One 16 bit periodic timer

Up to three channels of analog output (8 bit

PWM)

One 16 bit watchdog timer

One 16 bit capture timer

•

UART

I²C/SPI port

Up to 24 discrete digital I/Os

8-channel 12 bit A/D (0 – 1.2V input)

64K byte Flash memory

2K byte data RAM

o

Three buffered channels, two use

for current sensing

o

Five unbuffered channels

4 Application connection and Pin function

XTAL0

4MHz

System

Clock

XTAL1

Crystal

PWMUH

Frequency

Synthesizer

System

clock

PWMUL

Low Loss

PWMVH

Space

PWMVL

Vector

PWM

PWMWH

P1.2/TXD

P1.1/RXD

Host Microcontroller

(UART)

PWMWL

UART

Motion

Control

Modules

GATEKILL

BRAKE

SDA

SCL

Break

Other Communication

(I²C)

BRAKEGK

Encoder

I²C/SPI

Dual

Port

Memory

&

MCE

Memory

(6kB)

3.3V

Encoder

Interface

P1.0/PULIN//T2/MT1

P1.3/SYNC

P1.5

PORT1

Motion

Control

Sequencer

P2.0/PULDIR/NMI

P2.1

HVIC

Gate Drive

IRS2630D

P2.2/CAP

Digital I/O

Control

0.6V

PORT2

PORT3

P2.3/QINDEX

P2.5/INT2

IFBU+

S/H

IFBU-

P3.0/CS1

P3.2/INT0

P3.6

IFBUO

0.6V

IFBV+

P3.7

Timers

S/H

IFBV-

IFBVO

Watchdog

Timer

12bit

A/D

&

P2.6/AOPWM0

P2.7/AOPWM1

P3.1/AOPWM2

OP1+

PWM0

PWM1

PWM2

OP1-

Temperature

feedback

Motor

Local

RAM

2kByte

OP1O

MUX

Analog Output

5

VBUS, AIN1/2/3/4

(0-1.2V)

AREF

Encoder

CMEXT

AVDD

AVSS

TCLK

TDI

Optional External

Voltage Reference

(0.6V)

JTAG Control

(Flash

programming

& Emulation)

Program

RAM

(32kByte)

JTAG

Interface

TSM

TDO

RESET

System

Reset

8051

CPU

VDD1

VSS

3.3V

1.8V

Voltage

Regulator

VDDCAP

1.8V

3.3V

IRMCF143S

Figure 4. IRMCF143S Application Diagram

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4.1 8051 Peripheral Interface Group

UART Interface

P1.2/TXD

P1.1/RXD

Output, Transmit data from IRMCF143S

Input, Receive data to IRMCF143S

Discrete I/O Interface

P1.0/PULSE/T2/MT1 Input/output port 1.0, can be configured as Timer/Counter 2 input or MCE pin timer

1 output, allocated by MCE as Pulse Input

P1.1/RXD

P1.2/TXD

P1.3/SYNC/SCK

P1.4/ENC-A

P1.5

Input/output port 1.1, can be configured as RXD input

Input/output port 1.2, can be configured as TXD output

Input/output port 1.3, can be configured as SYNC output or SPI clock output

Input/output port 1.4, allocated by MCE as Encoder-A input

Input/output port 1.5

P1.6/ENC-B

P1.7/ENC-Z

P2.0/DIR/NMI

Input/output port 1.6, allocated by MCE as Encoder-B input

Input/output port 1.7, allocated by MCE as Encoder-Z input

Input/output port 2.0, can be configured as non-maskable interrupt input, allocated

by MCE as Direction Input

P2.1

Input/output port 2.1

P2.2/CAP

P2.3/MATCH

P2.5/INT2

P2.6/AO0

P2.7/AO1/MT2

P3.0/CS1

P3.1/AO2/MT3

P3.2/INT0

P3.3/HALL-3/INT1

Input/output port 2.2, can be configured as capture timer input

Input/output port 2.3, can be configured as MATCH output

Input/output port 2.5, can be configured as INT2 input

Input/output port 2.6, can be configured as AO0 output

Input/output port 2.7, can be configured as AO1 output or MCE pin timer 2 output

Input/output port 3.0, can be configured as SPI chip select 1

Input/output port 3.1, can be configured as AO2 output or MCE pin timer 3 output

Input/output port 3.2, can be configured as INT0 input

Input/output port 3.3, can be configured as INT1 input, allocated by MCE as Hall-3

input

P3.4/HALL-1/T0

P3.5/HALL-2/T1

Input/output port 3.4, can be configured as Timer 0 input, allocated by MCE as Hall-

1 input

Input/output port 3.5, can be configured as Timer 1 input, allocated by MCE as Hall-

2 input

P3.6

Input/output port 3.6

P3.7

Input/output port 3.7

P5.1/TDI

P5.2/TMS

Input port 5.1, configured as JTAG port by default

Input port 5.2, configured as JTAG port by default

Analog Output Interface

P2.6/AO0

Input/output, can be configured as 8-bit PWM output 0 with programmable carrier

frequency

P2.7/AO1

P3.1/AO2

Input/output, can be configured as 8-bit PWM output 1 with programmable carrier

frequency

Input/output, can be configured as 8-bit PWM output 2 with programmable carrier

frequency

Crystal Interface

XTAL0

Input, connected to crystal

Output, connected to crystal

XTAL1

Reset Interface

RESET

Input and Output, system reset, doesn’t require external RC time constant

Output, I²C clock output, or SPI data

²C Interface

I

SCL/SO-SI

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SDA/CS0

Input/output, I²C Data line or SPI chip select 0

I²C/SPI Interface

SCL/SO-SI

Output, I²C clock output, or SPI data

SDA/CS0

Input/output, I²C data line or SPI chip select 0

P1.3/SYNC/SCK

P3.0/CS1

Input/output port 1.3, can be configured as SYNC output or SPI clock output

Input/output port 3.0, can be configured as SPI chip select 1

4.2 Motion Peripheral Interface Group

PWM

PWMUH

PWMUL

PWMVH

PWMVL

PWMWH

PWMWL

BRAKE

Output, PWM phase U high side gate signal, internally pulled down by 58kΩ,

configured high true at a power up

Output, PWM phase U low side gate signal, internally pulled down by 58kΩ,

configured high true at a power up

Output, PWM phase V high side gate signal, internally pulled down by 58kΩ,

configured high true at a power up

Output, PWM phase V low side gate signal, internally pulled down by 58kΩ,

configured high true at a power up

Output, PWM phase W high side gate signal, internally pulled down by 58kΩ,

configured high true at a power up

Output, PWM phase W low side gate signal, internally pulled down by 58kΩ,

configured high true at a power up

Output, BRAKE output signal, internally pulled up by 70kΩ, configured low true at a

power up

Fault

GATEKILL

Input, upon assertion this negates all six PWM signals, active low, internally pulled

up by 70kΩ

BRAKEGK

Input, upon assertion, this negates BRAKE signal, active low, internally pulled up by

70kΩ

4.3 Analog Interface Group

AVSS

Analog power return, (analog internal 1.8V power is shared with VDDCAP)

AREF

0.6V buffered output

CMEXT

Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected.

OP1+

OP1-

OP1O

Input, Operational amplifier positive input for application sensing

Input, Operational amplifier negative input for application sensing

Output, Operational amplifier output for application sensing

IFBU+

IFBU-

IFBUO

Input, Operational amplifier positive input for U phase current sensing

Input, Operational amplifier negative input for U phase current sensing

Output, Operational amplifier output for U phase current sensing

IFBV+

IFBV-

IFBVO

Input, Operational amplifier positive input for V phase current sensing

Input, Operational amplifier negative input for V phase current sensing

Output, Operational amplifier output for V phase current sensing

VDCBUS

AIN1

Input, Analog input channel (0 – 1.2V), allocated for DC bus voltage input

Input, Analog input channel 1 (0 – 1.2V), allocated by MCE as speed input, needs to

be pulled down to AVSS if unused

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AIN2

AIN3

AIN4

Input, Analog input channel 2 (0 – 1.2V), allocated by MCE as torque input, needs to

be pulled down to AVSS if unused

Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if

unused

Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if

unused

4.4 Power Interface Group

VDD1

Digital power (3.3V)

VDDCAP

Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad

internally

Note: The internal 1.8V supply is not designed to power any external circuits or

devices. Only capacitors should be connected to this pin.

Digital common

VSS

4.5 Test Interface Group

P5.2/TMS

TDO

JTAG test mode input or input digital port

JTAG data output

P5.1/TDI

TCK

JTAG data input, or input digital port

JTAG test clock

4.6 Incremental Encoder/Hall sensor Group

P1.4/ENC-A

P1.6/ENC-B

P1.7/ENC-Z

P3.3/HALL-3/INT1

P3.4/HALL-1/T0

P3.5/HALL-2/T1

Incremental Encoder A input

Incremental Encoder B input

Incremental Encoder Z input

Hall sensor 3 input

Hall sensor 1 input

Hall sensor 2 input

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5 DC Characteristics

5.1 Absolute Maximum Ratings

Symbol

V_DD1

V_IA

Parameter

Supply Voltage

Analog Input Voltage

Digital Input Voltage

Ambient Temperature

Storage Temperature

Min

Typ

Max

3.6 V

1.98 V

6.0 V

85 ˚C

150 ˚C

Condition

Respect to VSS

Respect to AVSS

Respect to VSS

-0.3 V

-40 ˚C

-65 ˚C

-

V_ID

T_A

T_S

Table 1. Absolute Maximum Ratings

Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the

device. These are stress ratings only and function of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications are not implied.

5.2 System Clock Frequency and Power Consumption

C_AREF= 1nF, C_MEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.

Symbol

SYSCLK

P_D

Parameter

System Clock

Power consumption

Min

32

Typ

-

Max

120

-

Unit

MHz

mW

100¹⁾

Table 2. System Clock Frequency

Note 1) The value is based on the condition of MCE clock=100MHz, 8051 clock 20MHz with a actual motor

running by a typical MCE application program and 8051 code.

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5.3 Digital I/O DC Characteristics

Symbol

V_DD1

Parameter

Supply Voltage

Input Low Voltage

Input High Voltage

Input capacitance

Input leakage current

Low level output current

Min

3.0 V

-0.3 V

2.0 V

-

Typ

3.3 V

-

Max

3.6 V

0.8 V

3.6 V

-

Condition

Recommended

V_IL

V_IH

C_IN

I_L

Recommended

(1)

3.6 pF

±10 nA

13.2 mA

±1 μA

15.2 mA

V_O= 3.3 V or 0 V

(2)

I_OL1

8.9 mA

12.4 mA

17.9 mA

24.6 mA

V_OL= 0.4 V

(1)

I_OH1

High level output

current

Low level output current

24.8 mA

26.3 mA

49.5 mA

38 mA

33.4 mA

81 mA

V_OH= 2.4 V

(1)

(3)

I_OL2

V_OL= 0.4 V

(1)

(3)

I_OH2

High level output

current

V_OH= 2.4 V

(1)

Table 3. Digital I/O DC Characteristics

Note:

(1) Data guaranteed by design.

(2) Applied to SCL/SO-SI, SDA/CS0 pins.

(3) Applied to all digital I/O pins except SCL/SO-SI and SDA/CS0 pins.

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5.4 PLL and Oscillator DC characteristics

C_AREF= 1nF, C_MEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.

Symbol

V_{IL OSC}

Parameter

Oscillator (XTAL0,1)

Input Low Voltage

Oscillator (XTAL0,1)

Input High Voltage

Min

0

Typ

-

Max

Condition

0.2* V_DDCAPV_DDCAP= voltage at

VDDCAP pin

V_{IH OSC}

0.8* V_DDCAP

-

V_DDCAP

V_DDCAP= voltage at

VDDCAP pin

Table 4 PLL DC Characteristics

5.5 Analog I/O DC Characteristics

- OP amps for application sensing (OP1+, OP1-, OP1O, OP2+, OP2-, OP2O, OP3+, OP3-, OP3O)

C_AREF= 1nF, C_MEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.

Symbol

V_OFFSET

V_I

Parameter

Input Offset Voltage

Input Voltage Range

OP amp output

operating range

Input capacitance

OP amp feedback

resistor

Min

-

0 V

Typ

-

Max

26 mV

1.2 V

Condition

V_AVDD= 1.8 V

Recommended

V_AVDD= 1.8 V

V_OUTSW

50 mV

-

(1)

C_IN

R_FDBK

-

3.6 pF

-

Requested

between IFBO and

5 kΩ

20 kΩ

IFB-

(1)

OP _GAINCL

CMRR

I_SRC

Operating Close loop

Gain

Common Mode

Rejection Ratio

Op amp output source

current

80 db

-

(1)

-

80 db

1 mA

100 μA

V_OUT= 0.6 V

(1)

I_SNK

Op amp output sink

current

V_OUT= 0.6 V

(1)

Table 5. Analog I/O DC Characteristics

Note:

(1) Data guaranteed by design.

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5.6 Under Voltage Lockout DC characteristics

Unless specified, Ta = 25˚C.

Symbol

UV_CC+

Parameter

UVcc positive going

Threshold

UVcc negative going

Threshold

Min

2.78 V

Typ

3.04 V

Max

3.23 V

Condition

(1)

UV_CC-

UV_CCH

Note:

2.78 V

2.97 V

3.23 V

UVcc Hysteresys

-

73 mV

-

Table 6. UVcc DC Characteristics

(1) Data guaranteed by design.

5.7 Itrip comparator DC characteristics

Unless specified, VDD1=3.3V, Ta = 25˚C.

Symbol

Itrip₊

Parameter

Itrip positive going

Threshold

Min

-

Typ

1.22V

Max

-

Condition

V_DD1= 3.3 V

Itrip_-

Itrip negative going

Threshold

Itrip Hysteresys

-

1.10V

-

V_DD1= 3.3 V

ItripH

-

120mV

Table 7. Itrip DC Characteristics

5.8 CMEXT and AREF Characteristics

C_AREF= 1nF, C_MEXT= 100nF. Unless specified, Ta = 25˚C.

Symbol

V_CM

V_AREF

∆V_o

PSRR

Parameter

CMEXT voltage

Buffer Output Voltage

Load regulation (V_DC-0.6)

Power Supply Rejection Ratio

Min

495 mV

Typ

Max

700 mV

Condition

V_VDD1= 3.3 V

600 mV

1 mV

(1)

-

(1)

75 db

Table 8. CMEXT and AREF DC Characteristics

Note:

(1) Data guaranteed by design.

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6 AC Characteristics

6.1 Digital PLL AC Characteristics

Symbol

F_CLKIN

Parameter

Crystal input

Min

3.2 MHz

Typ

4 MHz

Max

60 MHz

Condition

(1)

frequency

Internal clock

frequency

Sleep mode output

frequency

Short time jitter

Duty cycle

(see figure below)

(1)

F_PLL

32 MHz

50 MHz

-

128 MHz

-

(1)

F_LWPW

F_CLKIN÷ 256

(1)

J_S

D

T_LOCK

-

200 psec

50 %

-

PLL lock time

500 μsec

Table 9. PLL AC Characteristics

Note:

(1) Data guaranteed by design.

R₁=1M

R₂=10

Xtal

C₁=15PF

C₂=15PF

Figure 5. Crystal circuit example

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6.2 Analog to Digital Converter AC Characteristics

Unless specified, Ta = 25˚C.

Symbol

T_CONV

T_HOLD

Parameter

Conversion time

Sample/Hold maximum

hold time

Min

-

Typ

-

Max

2.05 μsec

10 μsec

Condition

(1)

Voltage droop ≤ 15

LSB

(see figure below)

Table 10 . A/D Converter AC Characteristics

Note:

(1) Data guaranteed by design.

Input Voltage

Voltage droop

S/H Voltage

t_SAMPLE

T_HOLD

Figure 6. Voltage droop and S/H hold time

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6.3 Op amp AC Characteristics

Unless specified, Ta = 25˚C.

Symbol

OP_SR

Parameter

OP amp slew rate

Min

-

Typ

10 V/μsec

Max

-

Condition

VDD1 = 3.3 V, CL

= 33 pF ⁽¹⁾

(1) (2)

OP_IMP

T_SET

OP input impedance

Settling time

-

10⁸Ω

400 ns

-

VDD1 = 3.3 V, CL

= 33 pF ⁽¹⁾

Table 11 Current Sensing OP Amp AC Characteristics

Note:

(1) Data guaranteed by design.

(2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a

capacitor of 47pF, see Figure 7.

AVREF

External

components

47pF

Figure 7. Op amp output capacitor

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6.4 SYNC to SVPWM and A/D Conversion AC Timing

t_wSYNC

SYNC

t_dSYNC1

IU,IV,IW

t_dSYNC2

AINx

t_dSYNC3

PWMUx,PWMVx,PWMWx

Figure 8. SYNC timing

Unless specified, Ta = 25˚C.

Symbol

t_wSYNC

t_dSYNC1

t_dSYNC2

t_dSYNC3

Parameter

SYNC pulse width

SYNC to current feedback

conversion time

SYNC to AIN0-AIN4 analog

input conversion time

SYNC to PWM output delay

time

Min

-

Typ

32

-

Max

-

100

Unit

SYSCLK

-

200

2

SYSCLK

(1)

SYSCLK

Table 12. SYNC AC Characteristics

Note:

(1) AIN3, AIN4 and OP1O channels are converted once every 3 SYNC events

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6.5 GATEKILL to SVPWM AC Timing

t_wGK

GATEKILL

t_dGK

PWMUx,PWMVx,PWMWx

Figure 9. Gatekill timing

Unless specified, Ta = 25˚C.

Symbol Parameter

t_wGK

Min

32

-

Typ

-

Max

-

100

Unit

SYSCLK

GATEKILL pulse width

GATEKILL to PWM

output delay

t_dGK

Table 13. GATEKILL to SVPWM AC Timing

6.6 Itrip AC Timing

Itrip

t_Itrip

PWMUH,PWMUL,

PWMVH,PWMVH,

PWMWH,PWMWL

Figure 10. ITRIP timing

Unless specified, Ta = 25˚C.

Symbol

t_ITRIP

Parameter

Itrip propagation delay

Min

-

Typ

-

Max

Unit

SYSCLK+usec

100(sysclk)+1.0usec

Table 14. Itrip AC Timing

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6.7 Interrupt AC Timing

t_wINT

P3.2/INT0

P3.3/INT1

t_dINT

Internal

Program

Counter

Internal Vector Fetch

Figure 11. Interrupt timing

Unless specified, Ta = 25˚C.

Symbol

Parameter

Min

Typ

Max

Unit

t_wINT

INT0, INT1 Interrupt

Assertion Time

INT0, INT1 latency

4

-

SYSCLK

t_dINT

-

4

SYSCLK

Table 15. Interrupt AC Timing

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6.8 I²C AC Timing

T_I2CLK

SCL

t_I2WSETUP

t_I2WHOLD

t_I2RSETUP

t_I2RHOLD

t_I2EN1

t_I2ST1

t_I2ST2

t_I2EN2

SDA

Figure 12. I²C Timing

Unless specified, Ta = 25˚C.

Symbol

T_I2CLK

t_I2ST1

Parameter

Min

10

0.25

Typ

Max

8192

Unit

SYSCLK

T_I2CLK

SYSCLK

I²C clock period

-

I²C SDA start time

I²C SCL start time

I²C write setup time

I²C write hold time

I²C read setup time

I²C read hold time

-

t_I2ST2

t_I2WSETUP

t_I2WHOLD

t_I2RSETUP

t_I2RHOLD

I²C filter time⁽¹⁾

1

Table 16. I²C AC Timing

Note:

(1) I²C read setup time is determined by the programmable filter time applied to I²C communication.

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6.9 SPI AC Timing

SPI Write AC timing

T_SPICLK

P1.3/SYNC/SCK

t_WRDELAY

t_SPICLKHT

t_SPICLKLT

SCL/SO-SI

Bit7(MSB)

Bit0(LSB)

t_CSDELAY

t_CSHOLD

t_CSHIGH

SDA/CS0

P3.0/INT2/CS1

Figure 13. SPI write timing

Unless specified, Ta = 25˚C.

Symbol

T_SPICLK

t_SPICLKHT

t_SPICLKLT

t_CSDELAY

t_WRDELAY

Parameter

SPI clock period

SPI clock high time

SPI clock low time

CS to data delay time

Min

4

-

Typ

Max

-

10

Unit

-

1/2

-

SYSCLK

T_SPICLK

nsec

CLK falling edge to data

delay time

-

nsec

t_CSHIGH

t_CSHOLD

CS high time between two

consecutive byte transfer

CS hold time

1

-

T_SPICLK

-

1

-

Table 17. SPI Write AC Timing

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SPI Read AC Timing

T_SPICLK

P1.3/SYNC/SCK

t_RDHOLD

t_SPICLKHT

t_SPICLKLT

t_RDSU

SCL/SO-SI

Bit7(MSB)

Bit0(LSB)

t_CSRD

t_CSHOLD

t_CSHIGH

SDA/CS0

P3.0/INT2/CS1

Figure 14. SPI read timing

Unless specified, Ta = 25˚C.

Symbol Parameter

T_SPICLK

Min

4

-

10

1

Typ

-

1/2

-

Max

-

10

-

Unit

SPI clock period

SYSCLK

T_SPICLK

nsec

t_SPICLKHT

t_SPICLKLT

t_CSRD

SPI clock high time

SPI clock low time

CS to data delay time

t_RDSU

t_RDHOLD

t_CSHIGH

SPI read data setup time

SPI read data hold time

CS high time between two

consecutive byte transfer

CS hold time

-

T_SPICLK

t_CSHOLD

-

1

-

T_SPICLK

Table 18. SPI Read AC Timing

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6.10 UART AC Timing

T_BAUD

TXD

RXD

Data and Parity Bit

Stop Bit

Start Bit

T_UARTFIL

Figure 15. UART timing

Unless specified, Ta = 25˚C.

Symbol

T_BAUD

T_UARTFIL

Parameter

Min

-

Typ

57600

1/16

Max

-

Unit

bit/sec

T_BAUD

Baud Rate Period

UART sampling filter

period ⁽¹⁾

Table 19. UART AC Timing

Note:

(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 T_BAUD. If

three sampled values do not agree, then UART noise error is generated.

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6.11 CAPTURE Input AC Timing

T_CAPCLK

t_CAPLOW

t_CAPHIGH

P1.4/CAP

t_CRDELAY

CREV(H,L)

Internal

register

t_CLDELAY

CLAST(H,L)

Internal

register

t_INTDELAY

Interrupt

Vector Fetch

Interrupt

Figure 16. CAPTURE timing

Unless specified, Ta = 25˚C.

Symbol Parameter

T_CAPCLK

t_CAPHIGH

t_CAPLOW

t_CRDELAY

Min

Typ

Max

-

4

Unit

CAPTURE input period

CAPTURE input high time

CAPTURE input low time

CAPTURE falling edge to

capture register latch time

CAPTURE rising edge to

capture register latch time

CAPTURE input interrupt

latency time

8

4

-

SYSCLK

t_CLDELAY

t_INTDELAY

-

4

SYSCLK

Table 20. CAPTURE AC Timing

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6.12 JTAG AC Timing

T_JCLK

t_JLOW

t_JHIGH

TCK

t_CO

TDO

t_JSETUP

t_JHOLD

TDI/TMS

Figure 17. JTAG timing

Unless specified, Ta = 25˚C.

Symbol

T_JCLK

t_JHIGH

t_JLOW

t_CO

Parameter

TCK Period

TCK High Period

TCK Low Period

TCK to TDO propagation delay

time

Min

-

10

0

Typ

Max

50

-

5

Unit

MHz

nsec

-

t_JSETUP

t_JHOLD

TDI/TMS setup time

TDI/TMS hold time

4

0

-

nsec

Table 21. JTAG AC Timing

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7 I/O Structure

The following figure shows the PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL/BRAKE)

VDD1

(3.3V)

Internal digital circuit

High true logic

6.0V

270 Ω

6.0V

58k Ω

VSS

Figure 18. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH/BRAKE output

The following figure shows the digital I/O structure except the PWM output

VDD1

(3.3V)

Internal digital circuit

Low true logic

70k Ω

6.0V

270 Ω

6.0V

VSS

Figure 19. All digital I/O except PWM/BRAKE output

The following figure shows RESET and GATEKILL I/O structure.

VDD1

(3.3V)

RESET

GATEKILL

70k Ω

circuit

6.0V

270 Ω

6.0V

VSS

Figure 20. RESET, GATEKILL I/O

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The following figure shows the analog input structure.

VDDCAP(1.8V)

Analog input

6.0V

1

Ω

Analog Circuit

6.0V

AVSS

Figure 21. Analog input

The following figure shows all analog operational amplifier output pins and AREF pin I/O structure.

VDDCAP(1.8V)

Analog output

6.0V

Analog Circuit

6.0V

AVSS

Figure 22. Analog operational amplifier output and AREF I/O structure

The following figure shows the VSS,AVSS pin I/O structure

VDD1

AVDD

6.0V

Figure 23. VSS,AVSS pin I/O structure

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The following figure shows the VDD1,VDDCAP pin I/O structure

6.0V

VSS

Figure 24. VDD1,VDDCAP pin I/O structure

The following figure shows the XTAL0 and XTAL1 pins structure

VDDCAP(1.8V)

6.0V

1

Ω

6.0V

VSS

Figure 25. XTAL0/XTAL1 pins structure

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8 Pin List

Number

Internal Pull-

up / down

Type

I

O

I/O

Pin Name

XTAL0

XTAL1

P1.0/PULSE/T2/MT

1

Description

Crystal input

Crystal output

1

2

3

--

Discrete programmable I/O or Pulse Input or

Timer/Counter 2 input or MCE Pin Timer 1

I²C clock output (open drain, need pull up) or SPI data

I²C data (open drain, need pull up) or SPI Chip Select

0

4

5

SCL/SO-SI

SDA/CS0

--

I/O

6

P1.3/SYNC/SCK

--

I/O

Discrete programmable I/O or SYNC output or SPI

clock output

7

8

9

10

11

12

13

P1.4/ENC-A

P1.6/ENC-B

P1.7/ENC-C

VDD1

VSS

VDDCAP

P2.0/DIR/NMI

--

I/O

P

Discrete programmable I/O or Encoder A input

Discrete programmable I/O or Encoder B input

Discrete programmable I/O or Encoder C input

3.3V digital power

Digital common

Internal 1.8V output, Capacitor(s) to be connected

Discrete programmable I/O or DIR input or Non-

maskable Interrupt input

I/O

14

15

16

17

18

19

P3.2/INT0

P2.2/CAP

P2.3/MATCH

P2.5/INT2

P2.6/AO0

--

I/O

Discrete programmable I/O or Interrupt 0 input

Discrete programmable I/O or Capture Timer input

Discrete programmable I/O or MATCH output

Discrete programmable I/O or Interrupt 2 input

Discrete programmable I/O or PWM 0 digital output

Discrete programmable I/O or PWM 1 digital output or

MCE pin timer 2 output

P2.7/AO1/MT2

20

21

OP1O

OP1-

--

O

I

Op amp output for application sensing, 0-1.2V range

Op amp negative input for application sensing, 0-1.2V

range, needs to be pulled down to AVSS if unused

Op amp positive input for application sensing, 0-1.2V

range, needs to be pulled down to AVSS if unused

Analog input channel (0 – 1.2V), allocated by MCE for

DC bus voltage input

Analog input channel 1, 0-1.2V range, allocated by

MCE as speed input, needs to be pulled down to

AVSS if unused

22

23

24

OP1+

--

I

VDCBUS

AIN1

25

AIN2

--

I

Analog input channel 2, 0-1.2V range, allocated by

MCE as torque input, needs to be pulled down to

AVSS if unused

26

27

28

29

30

AIN3

--

I

Analog input channel 3, 0-1.2V range, needs to be

pulled down to AVSS if unused

Analog input channel 4, 0-1.2V range, needs to be

pulled down to AVSS if unused

Op amp negative input for U phase current sensing, 0-

1.2V range

Op amp positive input for U phase current sensing, 0-

1.2V range

AIN4

IFBU-

IFBU+

IFBUO

I

O

Op amp output for U phase current sensing, 0-1.2V

range

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Number

31

Internal Pull-

up / down

--

Type

O

Pin Name

CMEXT

Description

Unbuffered 0.6V output. Capacitor needs to be

connected.

32

33

AREF

IFBV-

--

O

I

Analog reference voltage output (0.6V)

Op amp negative input for V phase current sensing, 0-

1.2V range

34

35

IFBV+

IFBVO

--

I

Op amp positive input for V phase current sensing, 0-

1.2V range

Op amp output for V phase current sensing, 0-1.2V

range

O

36

37

38

39

40

AVSS

VDDCAP

VDD1

VSS

P3.1/AO2/MT3

--

P

I/O

Analog common

Internal 1.8V output, Capacitor(s) to be connected

3.3V digital power

Digital common

Discrete programmable I/O or PWM 2 digital output or

MCE pin timer 3 output

41

42

43

44

PWMWL

PWMVL

PWMUL

PWMWH

58 kΩ Pull

down

58 kΩ Pull

down

58 kΩ Pull

down

58 kΩ Pull

down

O

PWM gate drive for phase W low side, configurable

either high or low true.

PWM gate drive for phase V low side, configurable

either high or low true

PWM gate drive for phase U low side, configurable

either high or low true

PWM gate drive for phase W high side, configurable

either high or low true

45

46

47

48

P3.7

P2.1

P3.6

PWMVH

--

I/O

O

Discrete programmable I/O

58 kΩ Pull

down

PWM gate drive for phase V high side, configurable

either high or low true

49

PWMUH

58 kΩ Pull

down

O

PWM gate drive for phase U high side, configurable

either high or low true

50

51

52

53

P1.5

BRAKE

BRAKEGK

GATEKILL

I/O

O

I

Discrete programmable I/O.

70 kΩ Pull up

Brake output, configured low true at a power up

Brake shutdown input, active low input.

PWM shutdown input, configurable digital filter, active

low input.

I

54

55

56

57

58

59

60

61

62

P3.0/CS1

TMS /P5.2

TDO

TDI /P5.1

TCK

70 kΩ Pull up

I/O

I

O

I

I/O

Discrete programmable I/O or SPI Chip Select 1

JTAG test mode select or digital input port

JTAG test data output

--

JTAG test data input or digital input port

JTAG test clock

RESET

Reset, low true, Schmitt trigger input

UART receiver input or Discrete programmable I/O

UART transmitter output or Discrete programmable I/O

Hall-1 input or discrete programmable I/O or

Timer/Counter 0 input

P1.1/RXD

P1.2/TXD

HALL-1/P3.4/T0

63

64

HALL-2/P3.5/T1

--

I/O

Hall-2 input or discrete programmable I/O or

Timer/Counter 1 input

Hall-3 input or discrete programmable I/O or Interrupt

1 input

HALL-3/P3.3/INT1

Table 22. Pin List

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IRMCF143S

9 Package Dimensions

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10 Part Marking Information

Part Number

Date Code

IRMCF143

YWWP

IR Logo

Production Lot

XXXXXX

Pin 1

Indentifier

11 Qualification Information†

Qualification Level

Industrial^††

(per JEDEC JESD 47E)

MSL3^†††

Moisture Sensitivity Level

(per IPC/JEDEC J-STD-020C)

Class B

Machine Model

ESD

(per JEDEC standard JESD22-A114D)

Class 2

Human Body Model

(per EIA/JEDEC standard EIA/JESD22-A115-A)

RoHS Compliant

Yes

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

††

Higher qualification ratings may be available should the user have such requirements. Please contact

your International Rectifier sales representative for further information.

††† Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

Note: Test condition for Temperature Cycling test is -40C to 125C.

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Revision History

Rev A (November 22, 2013)

First Revision

Data and Specifications are subject to change without notice

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information

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型号：	IRMCF143TR
厂家：	Infineon
描述：	High Performance Position Servo Control IC
文件：	总35页 (文件大小：539K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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