IRMCF188 [INFINEON]
High Performance Sensorless Motor Control IC;
| 型号： | IRMCF188 |
| 厂家： | 
Infineon |
| 描述： | High Performance Sensorless Motor Control IC |
| 文件： | 总38页 (文件大小：916K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev.B
IRMCF188
High Performance Sensorless Motor Control IC
Description
IRMCF188 is a high performance Flash based motion control IC designed and optimized for complete air
conditioner control which contains two computation engines integrated into one monolithic chip. One is the
Flexible Motion Control Engine (MCETM) for sensorless control of permanent magnet motors or induction motors;
the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm by
connecting these control elements using a graphic compiler. Key components of the complex sensorless control
algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique
analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. IRMCF188
performs a PFC (Power Factor Correction) function in addition to the motor control. IRMCF188 comes in a 64 pin
QFP package.
Features
Product Summary
Maximum clock input (fcrystal
Maximum Internal clock (SYSCLK)
Maximum 8051 clock (8051CLK)
MCETM computation data range
8051 Program Flash
8051/MCE Data RAM
MCE Program RAM
GateKill latency (digital filtered)
PWM carrier frequency
A/D input channels
A/D converter resolution
A/D converter conversion speed
Analog output (PWM) resolution
UART baud rate (typ)
Number of digital I/O (max)
Package (lead free)
MCETM (Flexible Motion Control Engine)
-
Dedicated computation engine for high efficiency
sinusoidal sensorless motor control
Built-in hardware peripheral for single or two shunt
current feedback reconstruction and analog
circuits
Supports induction machine and both interior and
surface permanent magnet motor sensorless
control
)
60 MHz
120MHz
30MHz
16 bit signed
52KB
4KB
12KB
2 μsec
20 bits/ SYSCLK
10
Dedicated PFC PWM for digital PFC control
Loss minimization Space Vector PWM
Three-channel analog output (PWM)
Embedded 8-bit high speed microcontroller (8051)
for flexible I/O and man-machine control
JTAG programming port for emulation/debugger
Serial communication interface (UART)
I2C/SPI serial interface
Three general purpose timers/counters
Two special timers: periodic timer, capture timer
Watchdog timer with independent internal clock
Internal 64 Kbyte flash memory
12 bits
2 μsec
8 bits
57.6 Kbps
24
QFP64
30mA
Typical 3.3V operating current
3.3V single supply
Standard Pack
Base Part Number
Package Type
Orderable Part Number
Form
Tape and Reel
Tray
Quantity
1500
IRMCF188
IRMCF188
LQFP64
LQFP64
IRMCF188TR
IRMCF188TY
1600
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March 10, 2017
IRMCF188
Table of Contents
1
2
3
4
Overview..............................................................................................................................5
Pinout...................................................................................................................................6
IRMCF188 Block Diagram and Main Functions ....................................................................7
Application connection and Pin function ...............................................................................9
4.1 8051 Peripheral Interface Group ........................................................................................10
4.2 Motion Peripheral Interface Group......................................................................................11
4.3 Analog Interface Group ......................................................................................................12
4.4 Power Interface Group .......................................................................................................12
4.5 Test Interface Group ..........................................................................................................12
5
DC Characteristics .............................................................................................................14
5.1 Absolute Maximum Ratings................................................................................................14
5.2 System Clock Frequency and Power Consumption............................................................14
5.3 Digital I/O DC Characteristics.............................................................................................15
5.4 Analog I/O DC Characteristics............................................................................................16
5.5 Under Voltage Lockout DC characteristics .........................................................................17
5.6 Itrip comparator DC characteristics ....................................................................................17
5.7 CMEXT and AREF Characteristics.....................................................................................17
6
AC Characteristics..............................................................................................................18
6.1 Digital PLL AC Characteristics............................................................................................18
6.2 Analog to Digital Converter AC Characteristics ..................................................................19
6.3 Op amp AC Characteristics................................................................................................20
6.4 SYNC to SVPWM and A/D Conversion AC Timing.............................................................21
6.5 GATEKILL to SVPWM AC Timing ......................................................................................22
6.6 Itrip AC Timing ...................................................................................................................22
6.7 Interrupt AC Timing ............................................................................................................23
6.8 I2C AC Timing....................................................................................................................24
6.9 SPI AC Timing....................................................................................................................25
6.10 UART AC Timing ..............................................................................................................27
6.11 CAPTURE Input AC Timing ..............................................................................................28
6.12 JTAG AC Timing...............................................................................................................29
7
8
9
I/O Structure.......................................................................................................................30
Pin List ...............................................................................................................................34
Package Dimensions..........................................................................................................36
10 Part Marking Information ....................................................................................................37
11 Qualification Information.....................................................................................................37
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IRMCF188
List of Tables
Table 1. Analog channel sensing functions in Leg and Single Shunt Modes........................... 12
Table 2. Absolute Maximum Ratings ....................................................................................... 14
Table 3. System Clock Frequency........................................................................................... 14
Table 4. Digital I/O DC Characteristics .................................................................................... 15
Table 6. Analog I/O DC Characteristics................................................................................... 16
Table 7. UVcc DC Characteristics ........................................................................................... 17
Table 8. Itrip DC Characteristics.............................................................................................. 17
Table 9. CMEXT and AREF DC Characteristics...................................................................... 17
Table 10. PLL AC Characteristics............................................................................................ 18
Table 11 . A/D Converter AC Characteristics .......................................................................... 19
Table 12 Current Sensing OP Amp AC Characteristics........................................................... 20
Table 13. SYNC AC Characteristics........................................................................................ 21
Table 14. GATEKILL to SVPWM AC Timing ........................................................................... 22
Table 15. Itrip AC Timing......................................................................................................... 22
Table 16. Interrupt AC Timing.................................................................................................. 23
Table 17. I2C AC Timing ......................................................................................................... 24
Table 18. SPI Write AC Timing................................................................................................ 25
Table 19. SPI Read AC Timing................................................................................................ 26
Table 20. UART AC Timing ..................................................................................................... 27
Table 21. CAPTURE AC Timing.............................................................................................. 28
Table 22. JTAG AC Timing...................................................................................................... 29
Table 23. Pin List..................................................................................................................... 35
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IRMCF188
List of Figures
Figure 1. Typical Application Block Diagram Using IRMCF188 .................................................................................5
Figure 2. Pinout of IRMCF188....................................................................................................................................6
Figure 3. IRMCF188 Block Diagram...........................................................................................................................7
Figure 4. IRMCF188 Leg Shunt Connection Diagram................................................................................................9
Figure 5. IRMCF188 Single Shunt Connection Diagram......................................................................................... 10
Figure 6. Crystal circuit example ............................................................................................................................. 18
Figure 7. Voltage droop and S/H hold time ............................................................................................................. 19
Figure 8 Op amp output capacitor........................................................................................................................... 20
Figure 9. SYNC timing............................................................................................................................................. 21
Figure 10. Gatekill timing......................................................................................................................................... 22
Figure 11. ITRIP timing............................................................................................................................................ 22
Figure 12. Interrupt timing ....................................................................................................................................... 23
Figure 13. I2C Timing............................................................................................................................................... 24
Figure 14. SPI write timing ...................................................................................................................................... 25
Figure 15. SPI read timing....................................................................................................................................... 26
Figure 16. UART timing ........................................................................................................................................... 27
Figure 17. CAPTURE timing.................................................................................................................................... 28
Figure 18. JTAG timing............................................................................................................................................ 29
Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output............................................................ 30
Figure 20. All digital I/O except motor PWM output ................................................................................................ 30
Figure 21. RESET, GATEKILL I/O .......................................................................................................................... 31
Figure 22. Analog input ........................................................................................................................................... 31
Figure 23. ADCL pin input structure ........................................................................................................................ 31
Figure 24 Analog operational amplifier output and AREF I/O structure ................................................................. 32
Figure 25. VSS,AVSS pin I/O structure................................................................................................................... 32
Figure 26. VDD1,VDDCAP pin I/O structure ........................................................................................................... 32
Figure 27. XTAL0/XTAL1 pins structure.................................................................................................................. 33
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IRMCF188
1 Overview
IRMCF188 is a new generation International Rectifier integrated circuit device primarily designed as a one-chip
solution for complete inverterized appliance motor control applications. Unlike a traditional microcontroller or
DSP, the IRMCF188 provides a built-in closed loop sensorless control algorithm using the unique Flexible Motion
Control Engine (MCETM) for permanent magnet motors as well as induction motors. The MCETM consists of a
collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to
map internal signal nodes. IRMCF188 also employs a unique single shunt current reconstruction circuit to
eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC, while still
supporting leg shunt current sensing. Motion control programming is achieved using a dedicated graphical
compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host
communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller.
The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging. Figure 1 shows a
typical application schematic using the IRMCF188 in leg shunt mode.
IRMCF188 contains 64K bytes of Flash program memory and comes in a 64-pin QFP package.
Host
communication
Galvanic
isolation
Appliance Inverter
With PFC
PFC gate drive
Passive
EMI
Filter
Motor
(PMSM or IM)
IRS2630D
IRMCF188
Power
Supply
3.3V
UART interface
to Front Panel
2
22
Digial I/O
6
Analog Input
Figure 1. Typical Application Block Diagram Using IRMCF188
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IRMCF188
2 Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
XTAL0
XTAL1
PWMVH
P2.1
3
P1.0/T2
P3.7
4
SCL/SDI-SDO
SDA/CS0
P1.3/SYNC/SCK
P1.4/CAP
P1.6
PWMWH
PWMUL
PWMVL
PWMWL
P3.1/AOPWM2
VSS
5
6
7
8
9
P1.7
IRMCF188
10
11
12
13
14
15
16
VDD1
VDD1
(Top View)
VSS
VDDCAP
AVSS
VDDCAP
P2.0/NMI
P3.2/INT0
P2.2
OP3O
OP3+
OP3-
P2.3
ADCL
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 2. Pinout of IRMCF188
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IRMCF188
3 IRMCF188 Block Diagram and Main Functions
IRMCF188 block diagram for leg shunt mode is shown in Figure 3.
6
To IGBT
gate drive
Mini- Motion
D/A
(PWM)
2
Low Loss
SVPWM
Monitoring
Control
Engine
(MiniMCE)
GATEKILL
Speed
command
Capture
To IGBT
gate drive
Timer
Counnter0,1,2
PFC PWM
Watchdog
Timer
GATEKILL
Program
Flash
64kB
Motion
Control
Modules
UART
SND
RCV
OP2
OP3
Motor
Current
Reconstruct
3
3
Host
Interface
I2C
SCL
SDA
Dual Port
RAM
2kbyte
PORT1
PORT2
PORT3
8bit
CPU
Core
PFC
Current
Sense
OP1
3
Digital
I/Os
Analog
Input
MCE
Program
RAM
Local
RAM
2kbyte
VDCBUS
AIN1
AIN2
AIN3
AIN4
ADCH
ADCL
12kbyte
S/H
A/D
MUX
Interrupt
Control
8 bit(8051)
microcontroller
Emulator
Debugger
4
JTAG
Motion Control
Sequencer
Ceramic
Resonator
(4MHz)
Freq
Synthesizer
30MHz
120MHz
2
Figure 3. IRMCF188 Block Diagram
IRMCF188 contains the following functions for sensorless AC motor control applications:
Motion Control Engine (MCETM)
8051 microcontroller
Sensorless FOC (complete sensorless field
oriented control)
Two 16 bit timer/counters
One 16 bit periodic timer
One 16 bit watchdog timer
One 16 bit capture timer
Proportional plus Integral block
Low pass filter
Differentiator and lag (high pass filter)
Up to 24 discrete digital I/Os
Ten-channel 12 bit A/D
Ramp
Limit
o
Buffered (current sensing) three
channels (0 – 1.2V input)
Angle estimate (sensorless control)
Inverse Clark transformation
Vector rotator
o
Unbuffered seven channels (0 –
1.2V input)
JTAG port (4 pins)
Bit latch
Up to three channels of analog output (8 bit
PWM)
Peak detect
Transition
UART
I2C/SPI port
Multiply-divide (signed and unsigned)
Adder
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IRMCF188
Divide (signed and unsigned)
Subtractor
64K byte Flash memory
2K byte data RAM
Comparator
Counter
Accumulator
Switch
Shift
ATAN (arc tangent)
Function block (any curve fitting, nonlinear
function)
16 bit wide Logic operations (AND, OR,
XOR, NOT, NEGATE)
MCETM program memory and dual port RAM
(6K byte)
MCETM control sequencer
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IRMCF188
4 Application connection and Pin function
Figure 4 shows the application connections in leg shunt mode. Figure 5 shows the application connections in
single shunt mode.
AC230V
XTAL0
4MHz
Crystal
System
Clock
XTAL1
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
Frequency
Synthesizer
System
clock
Low Loss
Space
Vector
PWM
Motion
Control
Modules
Host
Microcontroller
(RS232C)
P1.2/TXD
P1.1/RXD
RS232C
I2C/SPI
GATEKILL
PFCPWM
PFC GATEKILL
SDA
SCL
Other Communication
(I2C)
Dual
Port
Memory
(2kB)
&
Motor
Current
Reconstruct
Motion
Control
Sequencer
P1.0/T2
P1.3/SYNC
P1.4/CAP
P1.5
P1.6
PORT1
PFC shunt
resistor
MCE
Memory
(12kB)
P1.7
VDCBUS
0.2V
P2.0/NMI
P2.1
VAC+
VAC-
Digital I/O
Control
From AC
Voltage
P2.2
AIN1
PORT2
PORT3
P2.3
VACO
0.6V
P3.0/INT2
P3.2/INT0
P3.3
HVIC
Gate Drive
IRS2336D
OP2+
S/H
OP2-
-
P3.4
Timers
P3.5
OP2O
0.6V
OP3+
Watchdog
Timer
Motor shunt
resistors
P2.6/ AOPWM0
P2.7/ AOPWM1
P3.1/ AOPWM2
S/H
OP3- -
12-bit
A/D &
MUX
PWM0
PWM1
PWM2
OP3O
Local
RAM
0.2V
OP1+
Analog Output
From PFC
shunt
(2kByte)
OP1-
-
OP1O
3
2
Motor
AIN2 – AIN4
Other analog input (0 – 1,2V)
TCLK
TDI
TSM
JTAG Control
OTP programming
& Emulation)
ADCH, ADCL A/D Calibration Reference
Voltages
Program
Flash
(64kByte)
JTAG
Interface
(
TDO
AREF
Optional External Voltage
Reference (0.6V)
CMEXT
RESET
RESET
AVDD
AVSS
System
Reset
8051
CPU
VDD1
VSS
3.3V
1.8V
Voltage
Regulator
VDDCAP
1.8V
3.3V
IRMCF188
Figure 4. IRMCF188 Leg Shunt Connection Diagram
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IRMCF188
AC230V
XTAL0
XTAL1
4MHz
Crystal
System
Clock
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
Frequency
Synthesizer
System
clock
Low Loss
Space
Vector
PWM
Motion
Control
Modules
Host
Microcontroller
(RS232C)
P1.2/TXD
P1.1/RXD
RS232C
I2C/SPI
GATEKILL
PFCPWM
PFC GATEKILL
SDA
SCL
Other Communication
(I2C)
Dual
Port
Memory
(2kB)
&
3.3V
Motor
Current
Reconstruct
Motion
Control
Sequencer
P1.0/T2
P1.3/SYNC
P1.4/CAP
PFC shunt
resistor
PORT1
P1.5
P1.6
MCE
P1.7
Memory
(12kB)
VDCBUS
P2.0/NMI
P2.1
Digital I/O
Control
P2.2
PORT2
PORT3
P2.3
Motor
shunt
resistor
0.6V
P3.0/INT2
P3.2/INT0
P3.3
HVIC
Gate Drive
IRS2336D
OP2+
S/H
OP2-
P3.4
Timers
P3.5
OP2O
0.2V
0.6V
OP3+
Watchdog
Timer
From PFC
shunt
P2.6/ AOPWM0
P2.7/ AOPWM1
P3.1/ AOPWM2
S/H
OP3-
12-bit
A/D &
MUX
PWM0
PWM1
PWM2
OP3O
Local
RAM
(2kByte)
OP1+
Analog Output
From AC
Voltage
OP1-
OP1O
4
2
Motor
AIN1 – AIN4
Other analog input (0 – 1,2V)
TCLK
TDI
TSM
JTAG Control
OTP programming
& Emulation)
ADCH, ADCL A/D Calibration Reference
Voltages
Program
Flash
(64kByte)
JTAG
Interface
(
TDO
AREF
Optional External Voltage
Reference (0.6V)
CMEXT
RESET
RESET
AVDD
AVSS
System
Reset
8051
CPU
VDD1
VSS
3.3V
1.8V
Voltage
Regulator
VDDCAP
1.8V
3.3V
IRMCF188
Figure 5. IRMCF188 Single Shunt Connection Diagram
4.1 8051 Peripheral Interface Group
UART Interface
P1.2/TXD
P1.1/RXD
Output, Transmit data from IRMCF188
Input, Receive data to IRMCF188
Discrete I/O Interface
P1.0/T2
Input/output port 1.0, can be configured as Timer/Counter 2 input
Input/output port 1.1, can be configured as RXD input
Input/output port 1.2, can be configured as TXD output
Input/output port 1.3, can be configured as SYNC output or SPI clock output
Input/output port 1.4, can be configured as Capture Timer input
Input/output port 1.5
P1.1/RXD
P1.2/TXD
P1.3/SYNC/SCK
P1.4/CAP
P1.5
P1.6
Input/output port 1.6
P1.7
Input/output port 1.6
P2.0/NMI
P2.2
Input/output port 2.0, can be configured as non-maskable interrupt input
Input/output port 2.2
P2.3
Input/output port 2.3
P2.6/AOPWM0
Input/output port 2.6, can be configured as AOPWM0 output
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IRMCF188
P2.7/AOPWM1
P3.0/INT2/CS1
P3.1/AOPWM2
P3.2/NINT0
P3.3/NINT1
P3.4/T0
Input/output port 2.7, can be configured as AOPWM1 output
Input/output port 3.0, can be configured as INT2 input or SPI chip select 1
Input/output port 3.1, can be configured as AOPWM2 output
Input/output port 3.2, can be configured as INT0 input
Input/output port 3.3, can be configured as INT1 input
Input/output port 3.4, can be configured as T0 input for counter mode
Input/output port 3.5, can be configured as T1 input for counter mode
Input/output port 3.7
P3.5/T1
P3.7
P5.1/TDI
Input port 5.1, configured as JTAG port by default
P5.2/TMS
Input port 5.2, configured as JTAG port by default
Analog Output Interface
P2.6/AOPWM0
Input/output, can be configured as 8-bit PWM output 0 with programmable carrier
frequency
P2.7/AOPWM1
P3.1/AOPWM2
Input/output, can be configured as 8-bit PWM output 1 with programmable carrier
frequency
Input/output, can be configured as 8-bit PWM output 2 with programmable carrier
frequency
Crystal Interface
XTAL0
Input, connected to crystal
Output, connected to crystal
XTAL1
Reset Interface
RESET
Input and Output, system reset, doesn’t require external RC time constant
I2C Interface
SCL/SO-SI
SDA/CS0
Output, I2C clock output, or SPI data
Input/output, I2C Data line or SPI chip select 0
I2C/SPI Interface
SCL/SO-SI
Output, I2C clock output, or SPI data
SDA/CS0
Input/output, I2C data line or SPI chip select 0
P1.3/SYNC/SCK
P3.0/INT2/CS1
Input/output port 1.3, can be configured as SYNC output or SPI clock output
Input/output port 3.0, can be configured as INT2 input or SPI chip select 1
4.2 Motion Peripheral Interface Group
PWM
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
PFCPWM
Output, PWM phase U high side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase U low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase V high side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase V low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase W high side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PWM phase W low side gate signal, internally pulled down by 58kΩ,
configured high true at a power up
Output, PFCPWM output signal, internally pulled up by 70kΩ, configured low true at a
power up
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IRMCF188
Fault
GATEKILL
Input, upon assertion this negates all six PWM signals, active low, internally pulled up
by 70kΩ
PFCGKILL
Input, upon assertion, this negates PFCPWM signal, active low, internally pulled up by
70kΩ
4.3 Analog Interface Group
AVSS
Analog power return, (analog internal 1.8V power is shared with VDDCAP)
AREF
0.6V buffered output
CMEXT
Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected.
OP1+
OP1-
OP1O
Input, Operational amplifier positive input for application sensing
Input, Operational amplifier negative input for application sensing
Output, Operational amplifier output for application sensing
OP2+
OP2-
OP2O
Input, Operational amplifier positive input for application sensing
Input, Operational amplifier negative input for application sensing
Output, Operational amplifier output for application sensing
OP3+
OP3-
OP3O
Input, Operational amplifier positive input for application sensing
Input, Operational amplifier negative input for application sensing
Output, Operational amplifier output for application sensing
VDCBUS
AIN1
AIN2
AIN3
AIN4
Input, Analog input channel (0 – 1.2V), allocated for DC bus voltage input
Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused
Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to AVSS if unused
Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused
Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if unused
Input, Analog input channel dedicated for A/D compensation (0 – 1.2V), needs to be
pulled down to AVSS if unused
ADCH
ADCL
Input, Analog input channel dedicated for A/D compensation (0 – 1.2V), internally
biased to 0.6V, see Figure 23 for internal structure
Analog Channel
Leg Shunt Mode
PFC Current
Motor U Phase Current
Motor V Phase Current
AC Voltage
Single Shunt Mode
AC Voltage
Motor Shunt Current
PFC Current
Pin number(s)
19, 20, 21
28, 29, 30
34, 35, 36
23
OP1
OP2
OP3
AIN1
Unallocated
Table 1. Analog channel sensing functions in Leg and Single Shunt Modes
4.4 Power Interface Group
VDD1
Digital power (3.3V)
VDDCAP
Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad
internally
Note: The internal 1.8V supply is not designed to power any external circuits or
devices. Only capacitors should be connected to this pin.
Digital common
VSS
4.5 Test Interface Group
P5.2/TMS
JTAG test mode input or input digital port
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IRMCF188
TDO
JTAG data output
P5.1/TDI
TCK
JTAG data input, or input digital port
JTAG test clock
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IRMCF188
5 DC Characteristics
5.1 Absolute Maximum Ratings
Symbol
VDD1
VIA
Parameter
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Ambient Temperature
Storage Temperature
Min
Typ
Max
3.6 V
1.98 V
6.0 V
125 ˚C
150 ˚C
Condition
Respect to VSS
Respect to AVSS
Respect to VSS
-0.3 V
-0.3 V
-0.3 V
-40 ˚C
-65 ˚C
-
-
-
-
-
VID
TA
TS
Table 2. Absolute Maximum Ratings
Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and function of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
5.2 System Clock Frequency and Power Consumption
CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.
Symbol
SYSCLK
PD
Parameter
System Clock
Power consumption
Min
32
Typ
-
Max
120
-
Unit
MHz
mW
1001)
Table 3. System Clock Frequency
Note 1) The value is based on the condition of MCE clock=100MHz, 8051 clock 20MHz with a actual motor and
PFC running by a typical MCE application program and 8051 code.
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IRMCF188
5.3 Digital I/O DC Characteristics
Symbol
VDD1
Parameter
Supply Voltage
Input Low Voltage
Input High Voltage
Input capacitance
Input leakage current
Low level output current
Min
3.0 V
-0.3 V
2.0 V
-
Typ
3.3 V
-
Max
3.6 V
0.8 V
3.6 V
-
Condition
Recommended
Recommended
Recommended
VIL
VIH
CIN
IL
(1)
3.6 pF
±10 nA
13.2 mA
±1 μA
15.2 mA
VO = 3.3 V or 0 V
VOL = 0.4 V
(2)
(2)
IOL1
8.9 mA
12.4 mA
17.9 mA
24.6 mA
(1)
IOH1
High level output
current
Low level output current
24.8 mA
26.3 mA
49.5 mA
38 mA
33.4 mA
81 mA
VOH = 2.4 V
(1)
(3)
IOL2
VOL = 0.4 V
(1)
(3)
IOH2
High level output
current
VOH = 2.4 V
(1)
Table 4. Digital I/O DC Characteristics
Note:
(1) Data guaranteed by design.
(2) Applied to SCL/SO-SI, SDA/CS0 pins.
(3) Applied to all digital I/O pins except SCL/SO-SI and SDA/CS0 pins.
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5.4 Analog I/O DC Characteristics
- OP amps for application sensing (OP1+, OP1-, OP1O, OP2+, OP2-, OP2O, OP3+, OP3-, OP3O)
CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C.
Symbol
VOFFSET
VI
Parameter
Min
-
0 V
Typ
-
Max
26 mV
1.2 V
1.2 V
Condition
VAVDD = 1.8 V
Recommended
VAVDD = 1.8 V
Input Offset Voltage
Input Voltage Range
OP amp output
operating range
Input capacitance
OP amp feedback
resistor
VOUTSW
50 mV
-
(1)
(1)
CIN
RFDBK
-
3.6 pF
-
-
Requested
between IFBO and
5 k
20 k
IFB-
(1)
OP GAINCL
CMRR
ISRC
Operating Close loop
Gain
Common Mode
Rejection Ratio
Op amp output source
current
80 db
-
-
-
-
-
(1)
-
-
-
80 db
1 mA
100 μA
VOUT = 0.6 V
(1)
ISNK
Op amp output sink
current
VOUT = 0.6 V
(1)
Table 5. Analog I/O DC Characteristics
Note:
(1) Data guaranteed by design.
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5.5 Under Voltage Lockout DC characteristics
Unless specified, Ta = 25˚C.
Symbol
UVCC+
Parameter
UVcc positive going
Threshold
UVcc negative going
Threshold
UVcc Hysteresys
Min
2.78 V
Typ
3.04 V
Max
3.23 V
Condition
(1)
(1)
UVCC-
UVCCH
Note:
2.78 V
2.97 V
3.23 V
-
73 mV
-
Table 6. UVcc DC Characteristics
(1) Data guaranteed by design.
5.6 Itrip comparator DC characteristics
Unless specified, VDD1=3.3V, Ta = 25˚C.
Symbol
Itrip+
Parameter
Itrip positive going
Threshold
Min
-
Typ
1.22V
Max
-
Condition
VDD1 = 3.3 V
Itrip-
Itrip negative going
Threshold
Itrip Hysteresys
-
1.10V
-
-
VDD1 = 3.3 V
ItripH
-
120mV
Table 7. Itrip DC Characteristics
5.7 CMEXT and AREF Characteristics
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
VCM
VAREF
Vo
PSRR
Parameter
CMEXT voltage
Buffer Output Voltage
Load regulation (VDC-0.6)
Power Supply Rejection Ratio
Min
495 mV
495 mV
Typ
Max
700 mV
700 mV
Condition
VVDD1 = 3.3 V
VVDD1 = 3.3 V
600 mV
600 mV
1 mV
(1)
-
-
-
-
(1)
75 db
Table 8. CMEXT and AREF DC Characteristics
Note:
(1) Data guaranteed by design.
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6 AC Characteristics
6.1 Digital PLL AC Characteristics
Symbol
FCLKIN
Parameter
Crystal input
Min
3.2 MHz
Typ
4 MHz
Max
60 MHz
Condition
(1)
frequency
Internal clock
frequency
Sleep mode output
frequency
Short time jitter
Duty cycle
(see figure below)
(1)
FPLL
32 MHz
50 MHz
-
128 MHz
-
(1)
FLWPW
FCLKIN ÷ 256
(1)
(1)
(1)
JS
D
TLOCK
-
-
-
200 psec
50 %
-
-
-
PLL lock time
500 μsec
Table 9. PLL AC Characteristics
Note:
(1) Data guaranteed by design.
XTAL0
XTAL1
R1=1MΩ
R2=1KΩ
Xtal
C1=15PF
C2=15PF
Figure 6. Crystal circuit example
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6.2 Analog to Digital Converter AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
TCONV
THOLD
Parameter
Min
-
-
Typ
-
-
Max
2.05 μsec
10 μsec
Condition
(1)
Conversion time
Sample/Hold maximum
hold time
Voltage droop ≤ 15
LSB
(see figure below)
Table 10 . A/D Converter AC Characteristics
Note:
(1) Data guaranteed by design.
Input Voltage
Voltage droop
S/H Voltage
tSAMPLE
THOLD
Figure 7. Voltage droop and S/H hold time
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6.3 Op amp AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
OPSR
Parameter
OP amp slew rate
Min
-
Typ
10 V/μsec
Max
-
Condition
VDD1 = 3.3 V, CL
= 33 pF (1)
(1) (2)
OPIMP
TSET
OP input impedance
Settling time
-
-
108 Ω
400 ns
-
-
VDD1 = 3.3 V, CL
= 33 pF (1)
Table 11 Current Sensing OP Amp AC Characteristics
Note:
(1) Data guaranteed by design.
(2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a
capacitor of 47pF, see Figure 8. Here only Op-amp 1 is shown but all op amp outputs should be loaded
with this capacitor value.
AVREF
IRMCF188 IC
External
components
OP1+
OP1-
OP1O
47pF
Figure 8 Op amp output capacitor
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6.4 SYNC to SVPWM and A/D Conversion AC Timing
twSYNC
SYNC
tdSYNC1
IU,IV,IW
tdSYNC2
AINx
tdSYNC3
PWMUx,PWMVx,PWMWx
Figure 9. SYNC timing
Unless specified, Ta = 25˚C.
Symbol
twSYNC
tdSYNC1
Parameter
Min
-
-
Typ
32
-
Max
-
100
Unit
SYSCLK
SYSCLK
SYNC pulse width
SYNC to current feedback
conversion time
tdSYNC2
SYNC to AIN0-4, ADCH,
ADCL analog input
conversion time
SYNC to PWM output delay
time
-
-
-
-
200
2
SYSCLK
(1)
tdSYNC3
SYSCLK
Table 12. SYNC AC Characteristics
Note:
(1) AIN2 – AIN4, ADCH, ADCL channels are converted once every 5 SYNC events
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6.5 GATEKILL to SVPWM AC Timing
twGK
GATEKILL
tdGK
PWMUx,PWMVx,PWMWx
Figure 10. Gatekill timing
Unless specified, Ta = 25˚C.
Symbol Parameter
twGK
Min
32
-
Typ
-
-
Max
-
100
Unit
SYSCLK
SYSCLK
GATEKILL pulse width
GATEKILL to PWM
output delay
tdGK
Table 13. GATEKILL to SVPWM AC Timing
6.6 Itrip AC Timing
Itrip
tItrip
PWMUH,PWMUL,
PWMVH,PWMVH,
PWMWH,PWMWL
Figure 11. ITRIP timing
Unless specified, Ta = 25˚C.
Symbol
tITRIP
Parameter
Itrip propagation delay
Min
-
Typ
-
Max
Unit
SYSCLK+usec
100(sysclk)+1.0usec
Table 14. Itrip AC Timing
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6.7 Interrupt AC Timing
twINT
P3.2/INT0
P3.3/INT1
tdINT
Internal
Program
Counter
Internal Vector Fetch
Figure 12. Interrupt timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
twINT
INT0, INT1 Interrupt
Assertion Time
4
-
-
SYSCLK
tdINT
INT0, INT1 latency
-
-
4
SYSCLK
Table 15. Interrupt AC Timing
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6.8 I2C AC Timing
TI2CLK
TI2CLK
SCL
tI2WSETUP
tI2WHOLD
tI2RSETUP
tI2RHOLD
tI2EN1
tI2ST1
tI2ST2
tI2EN2
SDA
Figure 13. I2C Timing
Unless specified, Ta = 25˚C.
Symbol
TI2CLK
tI2ST1
Parameter
Min
10
0.25
0.25
0.25
0.25
Typ
Max
8192
Unit
SYSCLK
TI2CLK
TI2CLK
TI2CLK
TI2CLK
SYSCLK
SYSCLK
I2C clock period
-
-
-
-
-
-
-
I2C SDA start time
I2C SCL start time
I2C write setup time
I2C write hold time
I2C read setup time
I2C read hold time
-
-
-
-
-
-
tI2ST2
tI2WSETUP
tI2WHOLD
tI2RSETUP
tI2RHOLD
I2C filter time(1)
1
Table 16. I2C AC Timing
Note:
(1) I2C read setup time is determined by the programmable filter time applied to I2C communication.
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6.9 SPI AC Timing
6.9.1.1 SPI Write AC timing
TSPICLK
P1.3/SYNC/SCK
tWRDELAY
tSPICLKHT
tSPICLKLT
SCL/SO-SI
Bit7(MSB)
Bit0(LSB)
tCSDELAY
tCSHOLD
tCSHIGH
SDA/CS0
P3.0/INT2/CS1
Figure 14. SPI write timing
Unless specified, Ta = 25˚C.
Symbol Parameter
TSPICLK SPI clock period
Min
4
-
-
-
Typ
Max
-
-
-
10
10
Unit
-
1/2
1/2
-
SYSCLK
TSPICLK
TSPICLK
nsec
tSPICLKHT
tSPICLKLT
tCSDELAY
tWRDELAY
SPI clock high time
SPI clock low time
CS to data delay time
CLK falling edge to data
delay time
-
-
nsec
tCSHIGH
tCSHOLD
CS high time between two
consecutive byte transfer
CS hold time
1
-
-
-
-
TSPICLK
TSPICLK
1
Table 17. SPI Write AC Timing
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6.9.1.2 SPI Read AC Timing
TSPICLK
P1.3/SYNC/SCK
tRDHOLD
tSPICLKHT
tSPICLKLT
tRDSU
SCL/SO-SI
Bit7(MSB)
Bit0(LSB)
tCSRD
tCSHOLD
tCSHIGH
SDA/CS0
P3.0/INT2/CS1
Figure 15. SPI read timing
Unless specified, Ta = 25˚C.
Symbol
TSPICLK
tSPICLKHT
tSPICLKLT
tCSRD
tRDSU
tRDHOLD
tCSHIGH
Parameter
SPI clock period
SPI clock high time
SPI clock low time
CS to data delay time
SPI read data setup time
SPI read data hold time
CS high time between two
consecutive byte transfer
CS hold time
Min
4
-
-
-
10
10
1
Typ
-
1/2
1/2
-
-
-
-
Max
-
-
-
10
-
Unit
SYSCLK
TSPICLK
TSPICLK
nsec
nsec
nsec
-
-
TSPICLK
tCSHOLD
-
1
-
TSPICLK
Table 18. SPI Read AC Timing
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6.10 UART AC Timing
TBAUD
TXD
RXD
Data and Parity Bit
Stop Bit
Start Bit
TUARTFIL
Figure 16. UART timing
Unless specified, Ta = 25˚C.
Symbol
TBAUD
TUARTFIL
Parameter
Min
-
-
Typ
57600
1/16
Max
-
-
Unit
bit/sec
TBAUD
Baud Rate Period
UART sampling filter
period (1)
Table 19. UART AC Timing
Note:
(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If
three sampled values do not agree, then UART noise error is generated.
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6.11 CAPTURE Input AC Timing
TCAPCLK
tCAPLOW
tCAPHIGH
P1.4/CAP
tCRDELAY
CREV(H,L)
Internal
register
tCLDELAY
CLAST(H,L)
Internal
register
tINTDELAY
Interrupt
Vector Fetch
Interrupt
Figure 17. CAPTURE timing
Unless specified, Ta = 25˚C.
Symbol Parameter
TCAPCLK
tCAPHIGH
tCAPLOW
tCRDELAY
Min
Typ
Max
-
-
-
4
Unit
CAPTURE input period
CAPTURE input high time
CAPTURE input low time
CAPTURE falling edge to
capture register latch time
CAPTURE rising edge to
capture register latch time
CAPTURE input interrupt
latency time
8
4
4
-
-
-
-
-
SYSCLK
SYSCLK
SYSCLK
SYSCLK
tCLDELAY
tINTDELAY
-
-
-
-
4
4
SYSCLK
SYSCLK
Table 20. CAPTURE AC Timing
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6.12 JTAG AC Timing
TJCLK
tJLOW
tJHIGH
TCK
tCO
TDO
tJSETUP
tJHOLD
TDI/TMS
Figure 18. JTAG timing
Unless specified, Ta = 25˚C.
Symbol
TJCLK
tJHIGH
tJLOW
tCO
Parameter
TCK Period
TCK High Period
TCK Low Period
TCK to TDO propagation delay
time
Min
-
10
10
0
Typ
Max
50
-
-
5
Unit
MHz
nsec
nsec
nsec
-
-
-
-
tJSETUP
tJHOLD
TDI/TMS setup time
TDI/TMS hold time
4
0
-
-
-
-
nsec
nsec
Table 21. JTAG AC Timing
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7 I/O Structure
The following figure shows the PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL/PFCPWM)
VDD1
(3.3V)
Internal digital circuit
High true logic
6.0V
PIN
270
6.0V
58k
VSS
Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH/PFCPWM output
The following figure shows the digital I/O structure except the PWM output
VDD1
(3.3V)
Internal digital circuit
Low true logic
70k
6.0V
PIN
270
6.0V
VSS
Figure 20. All digital I/O except PWM output
The following figure shows RESET and GATEKILL I/O structure.
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IRMCF188
VDD1
(3.3V)
RESET
GATEKILL
circuit
70k
270
6.0V
PIN
6.0V
VSS
Figure 21. RESET, GATEKILL I/O
The following figure shows the analog input structure, except for ADCL.
VDDCAP(1.8V)
Analog input
6.0V
PIN
1
Analog Circuit
6.0V
AVSS
Figure 22. Analog input
The following figure shows the ADCL input structure.
VDD1 (3.3V)
VDDCAP(1.8V)
Analog input
6.0V
37.8 k
8.4 k
PIN
1
Analog Circuit
6.0V
AVSS
Figure 23. ADCL pin input structure
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The following figure shows all analog operational amplifier output pins and AREF pin I/O structure.
VDDCAP(1.8V)
Analog output
6.0V
PIN
Analog Circuit
6.0V
AVSS
Figure 24 Analog operational amplifier output and AREF I/O structure
The following figure shows the VSS,AVSS pin I/O structure
VDD1
AVDD
PIN
6.0V
Figure 25. VSS,AVSS pin I/O structure
The following figure shows the VDD1,VDDCAP pin I/O structure
PIN
6.0V
VSS
Figure 26. VDD1,VDDCAP pin I/O structure
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The following figure shows the XTAL0 and XTAL1 pins structure
VDDCAP(1.8V)
6.0V
PIN
1
6.0V
VSS
Figure 27. XTAL0/XTAL1 pins structure
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IRMCF188
8 Pin List
Pin
Number
Internal Pull-
up /Pull-down
Pin
Type
I
Pin Name
XTAL0
XTAL1
P1.0/T2
SCL/SO-SI
SDA/CS0
Description
Crystal input
Crystal output
1
2
3
4
5
O
I/O
I/O
I/O
Discrete programmable I/O or Timer/Counter 2 input
I2C clock output (open drain, need pull up) or SPI data
I2C data (open drain, need pull up) or SPI Chip Select
0
6
P1.3/SYNC/SCK
I/O
Discrete programmable I/O or SYNC output or SPI
clock output
7
8
P1.4/CAP
P1.6
I/O
I/O
Discrete programmable I/O or Capture timer input
Discrete programmable I/O
9
P1.7
Discrete programmable I/O
10
11
12
13
VDD1
VSS
VDDCAP
P2.0/NMI
P
P
P
3.3V digital power
Digital common
Internal 1.8V output, Capacitor(s) to be connected
Discrete programmable I/O or Non-maskable Interrupt
input
I/O
14
15
16
17
18
19
20
P3.2/INT0
P2.2
P2.3
P2.6/AOPWM0
P2.7/AOPWM1
OP1O
I/O
I/O
I/O
I/O
I/O
O
Discrete programmable I/O or Interrupt 0 input
Discrete programmable I/O
Discrete programmable I/O
Discrete programmable I/O or PWM 0 digital output
Discrete programmable I/O or PWM 1 digital output
Op amp output for application sensing, 0-1.2V range
Op amp negative input for application sensing, 0-1.2V
range, needs to be pulled down to AVSS if unused
Op amp positive input for application sensing, 0-1.2V
range, needs to be pulled down to AVSS if unused
Analog input channel (0 – 1.2V), allocated for DC bus
voltage input, needs to be pulled down to AVSS if
unused
OP1-
I
21
22
OP1+
I
I
VDCBUS
23
24
25
26
27
AIN1
AIN2
AIN3
AIN4
ADCH
I
I
I
I
I
Analog input channel 1, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog input channel 2, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog input channel 3, 0-1.2V range, needs to be
pulled down to AVSS if unused
Analog input channel 4, 0-1.2V range, needs to be
pulled down to AVSS if unused
Input, Analog input channel dedicated for A/D
compensation (0 – 1.2V), needs to be pulled down to
AVSS if unused
28
29
OP2-
I
I
Op amp negative input for application sensing, 0-1.2V
range, needs to be pulled down to AVSS if unused
Op amp positive input for application sensing, 0-1.2V
range, needs to be pulled down to AVSS if unused
Op amp output for application sensing, 0-1.2V range
Unbuffered 0.6V output. Capacitor needs to be
connected.
OP2+
30
31
OP2O
CMEXT
O
O
32
AREF
O
Analog reference voltage output (0.6V)
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IRMCF188
Pin
Number
33
Internal Pull-
up /Pull-down
Pin
Type
I
Pin Name
ADCL
Description
Input, Analog input channel dedicated for A/D
compensation (0 – 1.2V), internally biased to 0.6V, see
Figure 23 for internal structure
34
35
OP3-
I
I
Op amp negative input for application sensing, 0-1.2V
range, needs to be pulled down to AVSS if unused
Op amp positive input for application sensing, 0-1.2V
range, needs to be pulled down to AVSS if unused
Op amp output for application sensing, 0-1.2V range
Analog common
OP3+
36
37
38
39
40
41
42
OP3O
AVSS
VDDCAP
VDD1
VSS
O
P
P
P
P
Internal 1.8V output, Capacitor(s) to be connected
3.3V digital power
Digital common
P3.1/AOPWM2
PWMWL
I/O
O
Discrete programmable I/O or PWM 2 digital output
PWM gate drive for phase W low side, configurable
either high or low true.
58 kΩ Pull
down
43
44
45
PWMVL
PWMUL
PWMWH
58 kΩ Pull
down
58 kΩ Pull
down
58 kΩ Pull
down
O
O
O
PWM gate drive for phase V low side, configurable
either high or low true
PWM gate drive for phase U low side, configurable
either high or low true
PWM gate drive for phase W high side, configurable
either high or low true
46
47
48
P3.7
P2.1
PWMVH
I/O
I/O
O
Discrete programmable I/O
Discrete programmable I/O
PWM gate drive for phase V high side, configurable
either high or low true
58 kΩ Pull
down
49
PWMUH
58 kΩ Pull
down
O
PWM gate drive for phase U high side, configurable
either high or low true
50
51
52
53
P1.5
I/O
I/O
I
I
Discrete programmable I/O.
PFCPWM
PFCGKILL
GATEKILL
PFC PWM gate drive , configurable either high or low
PFCPWM shutdown input, active low input.
PWM shutdown input, configurable digital filter, active
low input.
70 kΩ Pull up
70 kΩ Pull up
54
P3.0/INT2/CS1
70 kΩ Pull up
I/O
Discrete programmable I/O or external interrupt 2 input
or SPI Chip Select 1
55
56
57
58
59
60
61
62
63
64
P5.2/TMS
TDO
P5.1/TDI
TCK
RESET
P1.1/RXD
P1.2/TXD
P3.4/T0
P3.5/T1
P3.3/INT1
I
O
I
I
JTAG test mode select or digital input port
JTAG test data output
JTAG test data input or digital input port
JTAG test clock
I
Reset, low true, Schmitt trigger input
UART receiver input or Discrete programmable I/O
UART transmitter output or Discrete programmable I/O
Discrete programmable I/O or Timer/Counter 2 input
Discrete programmable I/O or Timer/Counter 2 input
Interrupt 1 input or Discrete I/O
I/O
I/O
I/O
I/O
I/O
Table 22. Pin List
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© 2014 International Rectifier
March 10, 2017
IRMCF188
9 Package Dimensions
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© 2014 International Rectifier
March 10, 2017
IRMCF188
10 Part Marking Information
Part Number
Date Code
IRMCF188
YWWP
IR Logo
Production Lot
XXXXXX
Pin 1
Indentifier
11 Qualification Information
Qualification Level
Industrial††
(per JEDEC JESD 47E)
MSL3†††
Moisture Sensitivity Level
(per IPC/JEDEC J-STD-020C)
Class B
Machine Model
ESD
(per JEDEC standard JESD22-A114D)
Class 2
Human Body Model
(per EIA/JEDEC standard EIA/JESD22-A115-A)
RoHS Compliant
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
††
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
Note: Test condition for Temperature Cycling test is -40C to 125C.
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© 2014 International Rectifier
March 10, 2017
IRMCF188
Data and Specifications are subject to change without notice
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
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© 2014 International Rectifier
March 10, 2017
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