IRMCK201_技术文档

Data Sheet No. PD60224 Rev.B

IRMCK201

High Performance Configurable Digital AC

Servo Control IC

Features

Product Summary

•

Complete closed loop current control

(Synchronously Rotating Frame Field Orientation)

Max. Clock Input (Sysclk)

33.3 MHz

Max. PLL clock for current feedback

133.3 MHz

•

Versatile Space Vector PWM

Direct interface to IR2175 current sensing high

voltage IC

Closed loop current control computation time6 µsec max

Closed loop current loop bandwidth (-3 dB)

Closed loop velocity loop update rate

PWM carrier frequency

5.5 kHz

5 / 10 kHz

83.3 kHz max

12 bit

•

Direct Encoder interface with multiplexed/non-

multiplexed Hall A/B/C signals

•

Direct interface to IR213x 3-phase gate driver IC

Closed loop velocity control

PWM counter resolution

Configurable architecture

o

Supports AC PM motor or Induction motor

Closed loop or open loop control

Current feedback temp drift/offset

Max SPI clock

calibrated

8 MHz

•

Asynchronous serial communication interface

(RS232C, RS422)

Package: QFP100

•

Fast SPI interface

4 channel 12-bit A/D interface with simultaneous

sample/hold

•

8-bit parallel bus interface for microcontroller

expansion (supports most 8-bit microprocessors)

Integrated brake IGBT control

ServoDesigner^TM(Configuration Tool) available

•

Description

IRMCK201 is a complete AC servo motor control IC. It contains closed loop current control for sinusoidal AC current, and

closed loop velocity control based on encoder position feedback interface. A standard communication port is provided for

RS232C or RS422, in addition to a fast SPI communication interface. Unlike a traditional DSP or a microcontroller, the

IRMCK201 does not require any programming effort to complete the complex control algorithm. It allows users to configure

the algorithm for specific application needs. Permanent magnet motor or AC induction motor are supported. IRMCK201

facilitates high performance servo design together with the IR2175 current sensing IC and IR213x high voltage 3-phase gate

driver IC, which simplifies the hardware design while minimizing cost. For multi-axis applications, IRMCK201 can be used

as a multi-drop slave drive based on the SPI protocol. The package is available in a 100-pin QFP.

IRMCK201

Overview

IRMCK201 is a new International Rectifier integrated circuit device designed as a one-chip solution for complete

closed loop current control and velocity control for a high performance servo drive system. Unlike a traditional

microcontroller or DSP, IRMCK201 does not require any programming to complete complex AC servo algorithm

development. Combined with International Rectifier's high voltage gate drive and current sensing IC, the user can

implement a complete AC servo control with minimum component count and virtually no design effort. Although

IRMCK201 contains dedicated logic to perform closed loop control of AC current and velocity, it has a wide range of

application coverage through its flexible configuration ability. The drive can be easily configured for induction

machine closed loop vector control or permanent magnet motor servo drive. Rich motion peripherals, analog and

digital I/O can also be configured. Host communication logic contains an asynchronous RS232C or RS422

communication interface, a fast slave SPI interface and an 8-bit-wide Host Parallel Interface. All communication ports

have the same access capability to the host register set. The user can write to and read from the predefined registers to

configure and monitor the drive through these communication ports.

IRMCK201 Main Features

IRMCK201 contains the following functions for AC servo motor control applications:

•

Complete closed loop current control based on Synchronously Rotating Frame Field Orientation

Configurable update rate with PWM carrier frequency

Configurable parameters (all PI controller gains, PI output limit range, current feedback scaling, encoder

feedback scaling)

•

Configurable control structure for Induction machine or AC Permanent Magnet machine (Disable/enable slip

gain)

•

Closed loop velocity control with configurable update rate

Enable/disable velocity loop

Selectable reference input for torque and speed input

Analog reference input

RS232C/RS422 reference input

Dynamic braking control for excess DC bus voltage

Cycle-by-cycle on/off Control for Brake IGBT

DC bus voltage feedback

Standard Encoder interface with Hall ABC support

A/B quadrature signal input up to 1 MHz

Choice of separate or multiplexed Hall A/B/C signal input

Auto-initialization with Hall A/B/C plus Z pulse input

Adaptable for any line count encoder from 200 PPR to 10,000 PPR

1/T counter (1 MHz) for low speed performance improvement

Space Vector PWM with deadtime insertion

IR2175 current sensing IC interface

IR213x high voltage gate driver IC interface

Low cost serial 12 bit A/D interface with multiplexer and sample/hold circuit

4 channel analog output by PWM

0-3.3 V, 120 kHz output

•

EEPROM for startup initialization of internal data/parameters through host register interface

AT24C01A, 128 x 8

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

2

IRMCK201

•

Versatile host communication interface

RS232C or RS422 host interface

Fast SPI slave host interface with multi-drop capability

Parallel Host interface (total 12 pins)

Multiplexed data/address bus

Address Enable

RD/WR

Discrete I/O

•

Start (Input)

Stop (Input)

IFBCAL (Input)

Fault Clear (Input)

Fault (Output)

SYNC (Output)

PWM Active (Output)

LED

•

Two-bit bi-color

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

3

IRMCK201

Table of Contents

Overview ..........................................................................................................................................................................2

IRMCK201 Main Features ............................................................................................................................................2

IRMCK201 Block Diagrams..........................................................................................................................................7

Basic Block Diagram ....................................................................................................................................................7

Detailed Block Diagram................................................................................................................................................8

Input/Output of IRMCK201..........................................................................................................................................9

Typical Application Connections.................................................................................................................................13

IC Crystal Clock Circuitry ..........................................................................................................................................14

Low Pass Filter............................................................................................................................................................15

Implementing the Low Pass Filter Shield ...............................................................................................................16

Cp Rp and Cs Component Values...........................................................................................................................16

PLL Reset....................................................................................................................................................................16

DC Electrical Characteristics and Operating Conditions.........................................................................................17

Absolute Maximum Ratings........................................................................................................................................17

Recommended Operating Conditions .........................................................................................................................17

DC Characteristics ......................................................................................................................................................18

Common Quiescent and Leakage Current ..................................................................................................................18

Input Characteristics – Non Schmitt Trigger Inputs ...................................................................................................18

Input Characteristics – Schmitt Trigger Inputs ...........................................................................................................18

Output Characteristics.................................................................................................................................................18

Output Characteristics OSC2CLK ..............................................................................................................................19

Pin and I/O Characteristic Table.................................................................................................................................20

Power Consumption....................................................................................................................................................22

AC Electrical Characteristics and Operating Conditions.........................................................................................23

System Level AC Characteristics................................................................................................................................23

Sync Pulse to Sync Pulse Timing............................................................................................................................23

FAULT and REDLED Response to GATEKILL ...................................................................................................24

Host Interface AC Characteristics...............................................................................................................................25

SPI Timing ..............................................................................................................................................................25

Host Parallel Timing ...................................................................................................................................................26

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4

IRMCK201

Host Parallel Read Cycle.........................................................................................................................................26

Host Parallel Write Cycle........................................................................................................................................27

Discrete I/O Electrical Characteristics ........................................................................................................................28

Motion Peripheral Electrical Characteristics...............................................................................................................29

PWM Electrical Characteristics ..............................................................................................................................29

IR2175 Interface .....................................................................................................................................................29

Encoder Electrical Characteristics...........................................................................................................................30

Analog To Digital Interface Electrical Characteristics ...............................................................................................31

ADC Timing............................................................................................................................................................31

PLL Interface Electrical Characteristics......................................................................................................................33

Appendix A Host Register Map ...............................................................................................................................34

Host Parallel Access................................................................................................................................................34

SPI Register Access ................................................................................................................................................34

RS-232 Register Access..........................................................................................................................................34

Write Register Definitions ..........................................................................................................................................40

QuadratureDecode Register Group (Write Registers).............................................................................................40

PwmConfig Register Group (Write Registers) .......................................................................................................41

CurrentFeedbackConfig Register Group (Write Registers) ....................................................................................42

SystemControl Register Group (Write Registers)...................................................................................................43

CurrentLoopConfig Register Group (Write Registers)...........................................................................................44

VelocityControl Register Group (Write Registers).................................................................................................45

FaultControl Register Group (Write Registers) ......................................................................................................47

SVPWMScaler Register Group (Write Registers)..................................................................................................47

DiagnosticPwmControl Register Group (Write Registers).....................................................................................48

SystemConfig Register Group (Write Registers)....................................................................................................49

DirectHostVoltageControl Register Group (Write Registers) ................................................................................49

32bitQuadDecode Register Group (Write Registers)..............................................................................................50

EepromControl Registers (Write Registers)............................................................................................................51

HallSensorEncoderInit (Write Registers – EEPROM only) ...................................................................................52

Read Register Definitions ...........................................................................................................................................53

QuadratureDecodeStatus Register Group (Read Registers)....................................................................................53

SystemStatus Register Group (Read Registers) ......................................................................................................53

DcBusVoltage Register Group (Read Registers)....................................................................................................54

FocDiagnosticData Register Group (Read Registers).............................................................................................54

FaultStatus Register Group (Read Registers)..........................................................................................................56

VelocityStatus Register Group (Read Registers) ....................................................................................................56

CurrentFeedbackOffset Register Group (Read Registers) ......................................................................................57

32bitQuadDecodeStatus Register Group (Read Registers).....................................................................................57

EepromStatus Registers (Read Registers)...............................................................................................................58

FOCDiagnosticDataSupplement Register Group (Read Registers)........................................................................59

Appendix B Package .................................................................................................................................................60

Appendix C Errata....................................................................................................................................................62

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5

IRMCK201

List of Figures

Figure 1. Basic Block Diagram of IRMCK201.............................................................................................................7

Figure 2. Detailed Block Diagram of IRMCK201 ........................................................................................................8

Figure 3. Input/Output of IRMCK201 ..........................................................................................................................9

Figure 4. Typical Connection of IRMCK201..............................................................................................................13

Figure 5. Oscillator Circuit..........................................................................................................................................14

Figure 6. PLL Low Pass Filter Shielding....................................................................................................................15

Figure 7. System Level SYNC-to-SYNC Timing.......................................................................................................23

Figure 8. FAULT and REDLED Response to GATEKILL........................................................................................24

Figure 9. SPI Timing...................................................................................................................................................25

Figure 10. Host Parallel Read Cycle Timing...............................................................................................................26

Figure 11. Host Parallel Write Cycle Timing..............................................................................................................27

Figure 12. Discrete I/O Timing ...................................................................................................................................28

Figure 13. PWM Timing .............................................................................................................................................29

Figure 14. IR2175 Interface ........................................................................................................................................29

Figure 15. Encoder Timing .........................................................................................................................................30

Figure 16. Top Level ADC Timing.............................................................................................................................31

Figure 17. ADC Specific Timing ................................................................................................................................32

List of Tables

Table 1: Typical Values for the Clock Circuit ................................................................................................................14

Table 2: PLL Test Pin Assignments................................................................................................................................15

Table 3: PLL Low Pass Filter Values .............................................................................................................................16

Table 4: Absolute Maximum Ratings .............................................................................................................................17

Table 5: Recommended Operating Conditions ...............................................................................................................17

Table 6: DC Characteristics ............................................................................................................................................18

Table 7: Non Schmitt Trigger Input Characteristics .......................................................................................................18

Table 8: Schmitt Trigger Input Characteristics...............................................................................................................18

Table 9: Output Characteristics.......................................................................................................................................18

Table 10: Output Characteristics OSC2CLK..................................................................................................................19

Table 11 ..........................................................................................................................................................................20

Table 12: Pin and I/O Characteristics .............................................................................................................................22

Table 13: IRMCK201 Power Consumption....................................................................................................................22

Table 14: System Level SYNC-to-SYNC Timing..........................................................................................................24

Table 15: FAULT and REDLED Response to GATEKILL...........................................................................................24

Table 16: SPI Timing......................................................................................................................................................25

Table 17: Host Parallel Read Cycle Timing....................................................................................................................26

Table 18: Host Parallel Write Cycle Timing...................................................................................................................27

Table 19: Discrete I/O Timing ........................................................................................................................................28

Table 20: PWM Timing ..................................................................................................................................................29

Table 21: IR2175 Interface .............................................................................................................................................29

Table 22: Encoder Timing ..............................................................................................................................................30

Table 23: Top Level ADC Timing..................................................................................................................................31

Table 24: ADC Specific Timing .....................................................................................................................................32

Table 25: PLL Electrical Characteristics.........................................................................................................................33

Table 26: QFP100 Package.............................................................................................................................................60

Table 27: QFP100 Dimensions.......................................................................................................................................61

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6

IRMCK201

IRMCK201 Block Diagrams

Basic Block Diagram

Figure 1 shows the basic block diagram of the IRMCK201 surrounded by various Accelerator ICs. Host

communications are provided over SPI, RS-232C or Host parallel ports. Two current sensing ICs (IR2175) and a

three phase high voltage gate drive typically implement the high voltage / current interface between the IRMCK201 IC

and motor.

The IRMCK201 can operate in a “stand-alone” mode without the host controller. A serial EEPROM could be

utilized to load motor-specific parameters into the IC.

AC Power

EEPROM

Analog Speed

Reference

TM

iMOTION Chip Set

select

IRMCK201

A/D

interface

A/D MUX

DC bus feedback

DC bus dynamic

brake control

RS232C

or

RS422

IGBT

module

BRAKE

Multi-Axis

Host

+

IRAMX16UP60A

Space

e^j^θ

Dead

time

-

Vector

PWM

Host

Register

Interface

SPI

Interface

+

or

-

FAULT

other host

controller

Parallel

Interface

+

Configuration

Registers

Ks

dt

Monitoring

Registers

Period/Duty

counters

IR2175

e^j^θ

2/3

Period/Duty

counters

1/T counter

speed

measurement

Quadrature

Decoding

Encoder

Motor

Figure 1. Basic Block Diagram of IRMCK201

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7

IRMCK201

Detailed Block Diagram

Figure 2 shows a detailed block diagram or the IRMCK201. All logic and algorithms are pre-programmed, and the

user does not need to make any effort to develop code, alleviating the tedious design process. If needed, the user can

configure the drive to tailor the control per specific needs to meet the required specification. This configuration is

easily done by accessing the host register set through the communication interface.

2

Closed Loop Velocity Control, Sequencing Control

Closed Loop Current Control

MUX

Update Rate = PWM carrier frequency / 2

Update Rate = PWM carrier frequency x1 or x 2

8 channel

Serial

A/D

EXT_REF

I1 x I2

I3

O

ADS7818

A/D

interface

I1

CNVST

CLK

DCV_FDBK

Feedforward

I2

I3

Interface

DATA

+/-16383 = +/-max_speed

path enable

2

4096

REF scale

Optional

Current Sense

INT_VQ

VQLIM

SPDKI

DC bus dynamic

brake control

Velocity

Control

BRAKE

- VQLIM

CURKI

SPDKP

Enable

IQREF

GSenseL

GSenseU

CURKP

INT_REF

ModScl

+

Reference

Select

6

VQS

VDS

+

VQ

Gate

Signals

START

PI

RAMP

Dea

d

time

-

e^jθ

STOP

DIR

Space Vector

PWM

VD

Sequence

Control

+

IQLIM-

IQLIM+

FLTCLR

SYNC

IDREF

PI

FAULT

Accel Rate

-

INT_VD

FAULT

- VDLIM

VDLIM

Decel

Rate

VD enable

PWMmode

PWMen

2Pen

Dtime

PWM ACTIVE

AngleScale MaxEncCount

Slip gain 4096

Slip gain

enable

RCV

SND

SpdScale InitZval

RS232C/

^I2I1 x I2^I3

I3

RS422

Interface

3

+

RTS

CTS

Encoder

A/B/Z

I1

O

dt

Configuration

Registers

Quadrature

Decoding

Encoder

Hall A/B/C

3

0

SCK

SDO

SDI

SPI

Slave

Interface

EncType

Host Register

Interface

IQ scale

4096

Zpol

InitZ

Optional

CurrentSense

CS

^I2I1 x I2^I3

I3

IR2175

interface

Motor

Phase

Current V

IQ

IV

O

I1

Monitoring

Registers

e^jθ

Data

Address

Control

2/3

17

Motor

Phase

Current W

ID

IW

Parallel

Interface

I1 x I2

I3

IR2175

interface

I1

I2

I3

Current

Offset W

Current

Offset V

4096

ID scale

DAC_PWM1

INT_DAC1

INT_DAC2

INT_DAC3

INT_DAC4

4ch

DAC module

DAC_PWM2

DAC_PWM3

+/-16383 = +/-4X of rated current for IQ

+/-4095 = +/-rated ID for IM field flux

Communication Modules

DAC_PWM4

Figure 2. Detailed Block Diagram of IRMCK201

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8

IRMCK201

Input/Output of IRMCK201

Figure 3 shows the interface signals divided into sub-groups. For detailed pin assignment, please refer to Table 12

in this data sheet.

SYSCLK

RESETN

PWMUH

PWMUL

PWMVH

PWMVL

PWMWH

PWMWL

BRAKE

XPD

PLL

&

System Clock

BYPASSMODE

BYPASSCLK

OSC1CLK

OSC2CLK

PLLTEST

CHGO

PWM gate signal

Interface

GATEKILL

LPVSS

IFB0

IFB1

IR2175 Interface

Encoder Interface

SCLK

MISO

MOSI

CSN

ENA

ENB

Host

Communication

Interface

HP_nOE

HP_nWE

HP_D[0-7]

HP_A

ENZ

HALLA

HALLB

HALLC

IRMCK201

HP_nCS

TX

RX

ADCLK

ADOUT

BAUDSEL

SYNC

ADCOVST

A/D Interface

ADMUX0

ADMUX1

START

STOP

RESSAMPLE

IFBCAL

Discrete I/O

FLTCLR

PWMACTIVE

FAULT

REDLED

LED

GREENLED

SCA

SCL

PID[0-1]

POWER ID

Serial EEPROM

Figure 3. Input/Output of IRMCK201

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9

IRMCK201

Host Interface Group

Low (L) /

High (H) True

Input (I) /

Output (O)

Signal

Function

Asserted

Positive edge

SCLK

I

SPI clock

sensitive

MISO

MOSI

CSN

HP_nOE

HP_nWE

HP_D [7:0]

HP_A

O

I

-

L

Master input and slave output

Master output and slave input

SPI chip select

Parallel data output enable

Parallel data write cycle

identification

Parallel data

Parallel data address cycle

identification

I

I/O

I

L

-

H

HP_nCS

TX

RX

I

O

I

L

-

Chip select

RS-232 data out

RS-232 data in

RS-232 baud rate: 0 = 57,600; 1

= 1,031,250 bps

Start of PWM cycle

BAUDSEL

SYNC

I

H

L

O

Discrete I/O Group

Low (L) /

High (H) True

Input (I) /

Output (O)

Signal

Function

Asserted

IFBCAL

START

STOP

FLTCLR

PWMACTIVE

FAULT

I

O

H

Current offset calibration signal

Start command

Stop command

Fault clear command

PWM state

Fault state

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10

IRMCK201

Motion Peripheral Group

Low (L) /

Input (I) /

Signal

PWMUH

PWMUL

PWMVH

PWHVL

PWMWH

PWMWL

BRAKE

High (H) True

Output (O)

Function

Asserted

O

PWM phase U high side

PWM phase U low side

PWM phase V high side

PWM phase V low side

PWM phase W high side

PWM phase W low side

IGBT gate

Varies, Based on

Write Register

0x0D

L

Varies, Based on

Write Register

When asserted, negates all six

PWM signals, host writeable

GATEKILL

I

0x0C Bit 7

IFB0

IFB1

ENA

ENB

I

-

Channel 0 (phase V)

Channel 1 (phase W)

Encoder A

Encoder B

Encoder Z

Hall A

Hall B

Hall C

ENZ

HALLA

HALLB

HALLC

Analog Interface Group

Low (L) /

High (H) True

Input (I) /

Output (O)

Signal

Function

Asserted

Negative Edge

ADCLK

O

Clock to ADS7818

Sensitive

ADOUT

I

-

L

H

Serial data from ADS7818

Diagnostic DAC

Conversion start to ADS7818

Analog input mux select

DAC [3:0]

ADCONVST

ADMUX0

ADMUX1

O

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11

IRMCK201

PLL Interface Group

Low (L) /

High (H) True

Input (I) /

Output (O)

Signal

Function

Asserted

XPD

RESETN

I

L

PLL reset

Digital logic reset

Internal test pin – force to logic

low

Internal test pin – force to logic

low

BYPASSCLK

I

H

BYPASSMODE

OSC1CLK

OSC2CLK

I

-

33.33 MHz crystal input

Internal test pin – force to logic

low

PLLTEST

I

H

CHGO

LPVSS

I/O

-

Low pass filter

Low pass filter ground

Miscellaneous Group

Low (L) /

High (H) True

Asserted

Input (I) /

Output (O)

Signal

Function

Varies, Based on

Write Register

0x0C Bit 1

-

Positive Edge

Sensitive

SD

O

Shut down, host writeable

SCA

SCL

I/O

O

EEPROM data

EEPROM clock

Power ID to SystemStatus

register, host readable

LED signal

PID[0:1]

I

-

GREENLED

REDLED

O

H

LED signal

Power Supply Group

Signal

Function

LVDD

IC Logic +3.3V power supply

IC Analog +3.3V power supply

IC Phase +3.3V Lock Loop power supply

IC Phase Lock Loop power supply return

AVCC

MVDD

VSSHC

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

12

IRMCK201

Typical Application Connections

Typical application connection is shown in Figure 4. In order to complete a high performance servo drive control,

all necessary components are shown in connection to IRMCK201.

System Clock

SYSCLK

PWMUH

PWMUL

PWMVH

PWMVL

PWMWH

PWMWL

BRAKE

33MHz

Crystal

Isolator

SCLK

MISO

MOSI

CSN

Gate Drive

or

SPI Interface

Intelligent IGBT

power module

(IRAMX16UP60A)

TX

RX

5V

GATEKILL

Isolator

To PC

RS232C

MAX232A

FAULTCLR

BAUDSEL

5V

PARALLEL DATA

Optional

Microcontroller

8051

uP

CONTROL SIGNALS

IFB0

IFB1

PO

Isolator

Motor Current

Sensing

IR2175

START

STOP

IFBCAL

Input

Switches

Anaog reference input

DC bus voltage

FLTCLR

PWMACTIVE

SYNC

ADCLK

ADOUT

Optional Current

1/4

IRMCK201

sensing

ADS7818

4066

SCA

ADCONVST

AT24C01A

SCL

1/4

Optional Current

sensing

Serial EEPROM

4052

4066

REDLED

GREENLED

PID[0-1]

Bi-Color

LED

ADMUX0

ADMUX1

RESSAMPLE

HALLA

HALLB

HALLC

ENA

ENB

ENZ

DS3486

Encoder Interface

Analog Output

DAC0

DAC1

DAC2

DAC3

Figure 4. Typical Connection of IRMCK201

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13

IRMCK201

IC Crystal Clock Circuitry

The clock input to the IC is a 33.33 MHz crystal oscillator. Two shunt capacitors and possibly a series resistor is

required to terminate the crystal to the IC.

The values of the R/C will vary based on actual PCB attributes, and some empirical analysis may be required to get the

PLL to start oscillating. Once oscillating, verify that the signal waveforms at the OSC1CLK and OSC2CLK pins are

sinusoidal rather than trapezoidal. Refer to Table 1 for suggested R/C values. Most low-cost crystals can be used

in this application. An example is a Citizen Part number CM309B33.333MABJT available from Digi-Key under

part number 300-4160-1-ND.

IRMCK201

OSC1CLK

C1

XTAL

R2

OSC2CLK

R1

C2

Figure 5. Oscillator Circuit

Component

Value

33.33

5

Units

MHz

pF

XTAL

C1

C2

5

pF

R1

0

3.9K

Ω

R2

Table 1: Typical Values for the Clock Circuit

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14

IRMCK201

PLL Clock Circuitry

The IRMCK201 contains a PLL that creates a 2X and 4X clock from the input 33.33 MHz input clock pin. There

are a number of pins on the IC allocated for factory testing purposes, which need to be left unconnected. Table 2

shows required PCB signal connections for these pins. Note that N/C is for factory use only.

Pin Number

PCB Connection

VSS

1

2

7

VSS

15

16

17

18

23

24

25

41

45

56

89

N/C

Table 2: PLL Test Pin Assignments

Low Pass Filter

The low pass filter for this PLL resides between the CHGO and LPVSS pins. Three passive components are

required to implement this filter: Cp, Rp and Cs. Figure 6 shows how to place these components around the IC.

A shield should be placed below Rp, Cp and Cs made out of copper etch.

Shielded by LPVSS

CHGO

Rp

IRMCK201

Cs

Cp

LPVSS

Figure 6. PLL Low Pass Filter Shielding

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15

IRMCK201

Implementing the Low Pass Filter Shield

Make all connections between CHGO, Rp, Cp, Cs and LPVSS as short as possible. Create the underlining shield by

“copper filling” a larger area in the signal plane of the PCB. Connect this shield to the LPVSS pin of the IC. Do

not connect this shield to signal ground (VSS).

Cp Rp and Cs Component Values

For a typical FR4 PCB, the values of the passive components are shown in Table 3.

Component

Value

3.9K

Units

Ω

pF

-

Rp

Cp

Cs

1000

Not Installed

Table 3: PLL Low Pass Filter Values

PLL Reset

There are two reset pins on the IC, XPD and RESETN both low true. XPD holds the PLL circuitry in reset when

low. Upon XPD going high, the PLL circuitry begins to lock onto the 33.33 MHz clock input. The PLL circuit

may take up to 1 ms to become stable. RESETN asserted low holds the internal DSP logic in reset. Upon

RESETN going high, the IC digital logic becomes active.

RESETN should be held low during and at least 1 ms after XPD goes high false to hold the internal DSP logic in reset

while the PLL becomes stable.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

16

IRMCK201

DC Electrical Characteristics and Operating Conditions

Absolute Maximum Ratings

Note: VSS = 0 Volt

UNIT

PARAMETER

SYMBOL

LIMITS

VSS-0.3 to 4.0

NOTE

S

Power Supply

Voltage

VDD

V

Non 5 Volt

VSS-0.3 to VDD+0.5

V

Tolerant Pins

Only on 5 Volt

Tolerant Pins

Input Voltage

VI

VSS-0.3 to 7

VSS-0.3 to VDD+0.5

+/- 30

V

Output Voltage

Output Current

per Pin

VO

IOUT

mA

Storage

Tstg

-65 to 150

°C

Temperature

Table 4: Absolute Maximum Ratings

Recommended Operating Conditions

Note: VSS = 0 Volt

PARAMETER SYMBOL

MIN TYP MAX UNITS

NOTE

Power Supply

VDD

3.0

VSS

-40

3.3

3.6

VDD

5.5

V

Voltage

Non 5 Volt Tolerant Pins

Only on 5 Volt Tolerant

Pins

Input Voltage

VI

Ta

-

Ambient

-

85

°C

Note 1

Temperature

Table 5: Recommended Operating Conditions

Notes:

1. The ambient temperature range is recommended for Tj = -40 to 125 °C

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

17

IRMCK201

DC Characteristics

Common Quiescent and Leakage Current

PARAMETER SYMBOL

CONDITIONS

VI=VDD or VSS

VDD=MAX

IOH=IOL=0

Ta=Tj=85°C

VDD=MAX

VIH=VDD

MIN TYP MAX

UNITS

Quiescent

IDDS

-

0.35

1

uA

Current

Input Leakage

ILI

-1

-

uA

Current

VIL=VSS

Table 6: DC Characteristics

Input Characteristics – Non Schmitt Trigger Inputs

PARAMETER SYMBOL

CONDITIONS

VDD=MAX

VDD=MIN

MIN TYP MAX

UNITS

High Level

VIH1

2.0

-

V

Input Voltage

Low Level

VIL1

-

0.8

V

Input Voltage

Table 7: Non Schmitt Trigger Input Characteristics

Input Characteristics – Schmitt Trigger Inputs

PARAMETER SYMBOL

CONDITIONS

VDD=MAX

MIN TYP MAX

UNITS

High Level

VT1+

1.1

0.6

0.1

-

2.4

1.8

-

V

Input Voltage

Low Level

VT1-

VDD=MIN

V

Input Voltage

Hysteresis

VH1

Voltage

Table 8: Schmitt Trigger Input Characteristics

Output Characteristics

UNIT

S

PARAMETER SYMBOL CONDITIONS

MIN

VDD - 0.4

-

TYP

MAX

-

High Level

VDD=MIN

IOH=-12mA

VDD=MIN

IOH = 12mA

VOH3

VOL3

-

V

Output Voltage

Low Level

VSS + 0.4

V

Output Voltage

Table 9: Output Characteristics

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

18

IRMCK201

Output Characteristics OSC2CLK

PARAMETER SYMBOL CONDITIONS MIN

TYP MAX

UNITS

V

High Level

LVOH

VDD=MIN

IOH=-530uA

VDD=MIN

IOH = 730uA

VDD - 0.4

-

Output Voltage

Low Level

LVOL

-

VSS + 0.4

V

Output Voltage

Table 10: Output Characteristics OSC2CLK

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

19

IRMCK201

Pin and I/O Characteristic Table

INTERNAL IC

RESISTOR

TERMINATION

40K-240K Pull

Down

5.50 VOLT

TOLERANT CHARACTERISTIC

INPUT DC

OUTPUT DC

CHARACTERISTIC

TABLE

Number

Type

Pin Name

INPUT

TABLE

1

2

BYPASSMODE

BYPASSCLK

I

-

Table 8

-

40K-240K Pull

Down

-

Table 8

3

4

5

6

OSC1CLK

LVDD

OSC2CLK

VSS

I

-

Table 7

-

P

O

P

-

Table 11

-

20K-120K Pull

Down

7

PLLTEST

I

-

Table 7

-

8

9

XPD

VSSHC

MVDD

VSSHC

AVDD

CHGO

LPVSS

I

-

Table 7

-

P

O

P

I

P

O

P

I

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

-

N.C. (CLKI)

N.C. (CLKSEL)

N.C. (CPT0)

N.C. (CPT1)

LVDD

REDLED

GREENLED

VSS

N.C. (TSTCLK)

N.C. (TSTSEL)

N.C. (OLAP)

PWMWL

PWMWH

PWMVL

LVDD

PWMVH

PWMUL

VSS

Table 8

-

Table 9

-

Table 8

I

Table 8

O

P

O

P

O

-

Table 9

-

Table 9

-

PWMUH

BRAKE

Table 9

-

20K -120K Pull

Up

35

36

37

RESETN

FLTCLR

I

O

I

-

Table 8

-

Table 9

20K -120K Pull

Up

GATEKILL

Table 8

-

38

39

IFB0

IFB1

I

YES

Table 8

-

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

20

IRMCK201

INTERNAL IC

RESISTOR

TERMINATION

5.50 VOLT

TOLERANT CHARACTERISTIC

INPUT DC

OUTPUT DC

CHARACTERISTIC

Number

Type

Pin Name

SD

INPUT

TABLE

Table 9

-

40

41

O

I

-

N.C. (D0)

Table 8

20K -120K Pull

42

43

PID0

I

-

Table 8

-

Up

20K -120K Pull

Up

PID1

Table 8

44

45

46

47

48

49

50

51

52

LVDD

N.C. (D3)

CSN

P

I

P

I

O

I

-

YES

-

YES

-

YES

-

YES

Table 8

VSS

MOSI

MISO

SCLK

TX

Table 8

-

Table 9

Table 8

-

Table 8

-

O

I

Table 9

RX

-

20K -120K Pull

Down

53

BAUDSEL

I

YES

Table 7

-

54

55

56

57

58

59

60

61

62

63

64

LVDD

P

O

I

P

O

I

-

ADMUX0

N.C. (N2)

VSS

ADMUX1

RESSAMPLE

ADCONVST

ADCLK

ADOUT

SYNC

FAULT

Table 9

-

Table 8

-

Table 9

-

Table 9

-

YES

-

Table 8

O

-

20K -120K Pull

Down

20K -120K Pull

Down

20K -120K Pull

Down

20K -120K Pull

Down

65

66

67

68

START

STOP

I

YES

Table 8

-

IFBCAL

FLTCLR

69

70

71

72

73

74

75

LVDD

P

O

P

O

-

PWMACTIVE

DAC[3]

VSS

DAC[2]

DAC[1]

DAC[0]

Table 9

-

Table 9

20K -120K Pull

Down

20K -120K Pull

Down

76

77

HP_D[0]

HP_D[1]

B

-

Table 7

Table 9

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

21

IRMCK201

INTERNAL IC

5.50 VOLT

TOLERANT CHARACTERISTIC

INPUT DC

OUTPUT DC

CHARACTERISTIC

TABLE

Number

Type

Pin Name

HP_D[2]

RESISTOR

TERMINATION

20K -120K Pull

Down

INPUT

TABLE

Table 7

-

78

79

80

B

P

B

-

Table 9

-

VDD

20K -120K Pull

Down

HP_D[3]

Table 7

Table 9

20K -120K Pull

Down

81

82

83

HP_D[4]

VSS

B

P

B

-

Table 7

-

Table 9

-

20K -120K Pull

Down

HP_D[5]

Table 7

Table 9

20K -120K Pull

Down

20K -120K Pull

Down

84

85

HP_D[6]

HP_D[7]

B

-

Table 7

Table 9

86

87

88

89

90

91

92

93

94

95

96

97

98

99

HP_nOE

HP_nWE

HP_A

N.C. (N11)

HP_nCS

ENCZ

ENCB

ENCA

LVDD

HALLC

HALLB

VSS

HALLA

SCL

I

P

I

YES

-

YES

-

YES

-

YES

-

Table 8

-

Table 8

-

Table 8

-

I

P

I

-

O

Table 9

20K -120K Pull

Up

100

SDA

B

-

Table 7

Table 9

Table 12: Pin and I/O Characteristics

Power Consumption

PARAMETER SYMBOL

CONDITIONS

VDD=3.3V

MIN TYP MAX

0.927

UNITS

WATT

P_Total

PTOTAL

-

Table 13: IRMCK201 Power Consumption

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

22

SYMBOL

DESCRIPTION

Current Feedback Sample Delay from SYNC Pulse

Falling Edge

TIME

UNITS

t₁

4.32

µs

Closed Loop Computation Time

(current control only including PWM computation)

Closed Loop Computation Time (current and

velocity control including PWM calculation time)

Minimum SYNC-to-SYNC time

(current control only including PWM calculation

time)

Minimum SYNC-to-SYNC time

(current and velocity control including PWM

calculation time)

6.33

7.68

t₂

µs

10.65

12.0

t₃

Table 14: System Level SYNC-to-SYNC Timing

FAULT and REDLED Response to GATEKILL

GATEKILL

t₃

t₁

FAULT

t₂

REDLED

t₄

FLTCLR

Figure 8. FAULT and REDLED Response to GATEKILL

SYMBOL

DESCRIPTION

FAULT Response to GATEKILL

REDLED Response to

TYP

685

UNITS

ns

t₁

t₂

715

ns

GATEKILL

t₃

t₄

FAULT Response to FLTCLR

REDLED Response to FLTCLR

145

175

ns

Table 15: FAULT and REDLED Response to GATEKILL

IRMCK201

Host Interface AC Characteristics

SPI Timing

t_SCLK

SCLK

CS

t_CSS

t_MOSIS

MOSI

MISO

t_MISO

t_MISOZ

Figure 9. SPI Timing

SYMBOL

f_SCLK

DESCRIPTION

ADC Clock Frequency

ADC Clock Period

MIN

MAX

UNITS

MHz

ns

8

t_SCLK

125

20

72

15

t_CSS

CS to SCLK high Setup

MOSI to SCLK low Setup

SCLK to MISO Valid

ns

t_MOSIS

ns

t_MISO

ns

t_MIOZ

CS to MISO High Impedance

35

ns

Table 16: SPI Timing

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

25

IRMCK201

Host Parallel Timing

Host Parallel Read Cycle

t_HPCSN

HP_nCS

HP_nWE

HP_A

t_HPWENS

t_HPA

t_HPAS

t_AHPD

VALID

t_HPDZ

HP_D[7:0]

t_HPZD

t_HPOENS

t_HPOENH

t_HPOEN

HP_nOE

Figure 10. Host Parallel Read Cycle Timing

SYMBOL

t_HPCSN

DESCRIPTION

MIN

MAX

UNIT

S

NOTE

HP_nCS Period

70

10

60

0

ns

t_HPWENS

HP_nWE Setup

ns

t_HPAS

HP_A Setup

ns

t_AHPD

HP_D [7:0] Access

HP_D [7:0] Active

HP_D [7:0] High Impedance

HP_nOE Hold

105

9

6

ns

T_HPZD

t_HPDZ

ns

0

ns

t_HPOENH

t_HPOENS

t_HPOEN

10

70

ns

Note 3

HP_nOE Setup

HP_nOE Period

ns

Table 17: Host Parallel Read Cycle Timing

Note:

3. HP_nOE must be stable before and after the high to low transition of HP_nCS.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

26

IRMCK201

Host Parallel Write Cycle

t_HPCSN

HP_nCS

t_HPWENS

t_HPWEN

HP_nWE

t_HPAS

t_HPA

HP_A

t_HPD[7:0]

HP_D[7:0]

t_HPD[7:0]S

t_HPOEN

HP_nOE

t_HPOENS

Figure 11. Host Parallel Write Cycle Timing

SYMBOL

t_HPCSN

DESCRIPTION

HP_nCS Period

HP_nWE Setup

HP_nWE Period

HP_A Setup

MIN

70

UNITS

ns

NOTE

t_HPWENS

t_HPWEN

t_HPAS

10

ns

70

ns

-10

70

ns

t_HPA

HP_A Period

ns

t_HPD[7:0]

t_HPOENS

t_HPOEN

HP_D [7:0] Setup

HP_nOE Setup

HP_nOE Period

-10

10

ns

70

ns

Note 4

Table 18: Host Parallel Write Cycle Timing

Note:

4. HP_nOE must be asserted high while HP_nCS low during a Host Parallel Write Cycle.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

27

IRMCK201

Discrete I/O Electrical Characteristics

IFBCAL

START

STOP

FLTCLR

GATEKILL

t_L

Figure 12. Discrete I/O Timing

SYMBOL

DESCRIPTION

MIN

100

1

UNITS

ms

NOTE

t_L

Pulse Width IFBCAL

Pulse Width START

Pulse Width STOP

Pulse Width FLTCLR

Pulse Width GATEKILL

ns

us

490

ns

Note 5

Table 19: Discrete I/O Timing

Note:

5. GATEKILL can be programmed to be low or high true. Shown above is a low true gate kill. The timing

specification is the same.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

28

IRMCK201

Motion Peripheral Electrical Characteristics

PWM Electrical Characteristics

t_{DEADTIMERESOLUTION}

SYNC

PWMUH

PWMUL

PWMVH

PWMVL

PWMWH

PWMWL

Figure 13. PWM Timing

SYMBOL

t_{DEADTIMERESOLUTION}

DESCRIPTION

Deadtime Insertion Logic Resolution

VALUE

UNITS

30

ns

Table 20: PWM Timing

IR2175 Interface

t_IFB

t_IFBH

IFB0

IFB1

t_IFBL

Figure 14. IR2175 Interface

SYMBOL

DESCRIPTION

MIN

95

10.52

500 ns

MAX

165

UNITS

kHz

µs

f_IFB

t_IFB

Current Feedback Input Frequency

Current Feedback Period

6.06

t_IBH

t_IFBH

Current Feedback High Pulse Width

Current Feedback Low Pulse Width

10 us

Table 21: IR2175 Interface

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

29

IRMCK201

Encoder Electrical Characteristics

Table 22 shows the input timing characteristics of the encoder inputs. Please refer to the IRMCK201 Application

Developer’s Guide for an example encoder input circuit that drives the IRMCK201.

t_ENCODER

t_ENCH

ENA

ENB

ENZ

t_ENCL

HALLA

HALLB

HALLC

VALID

t_HALLABCS

RESETN

Figure 15. Encoder Timing

SYMBOL

f_ENCODER

t_ENCODER

DESCRIPTION

Encoder Input Frequency

ENA ENB ENZ Period

ENA ENB ENZ Pulse Width

HALLA HALLB HALLC Setup to

RESETN

MIN

TYP

MAX

1

UNITS

MHz

µs

1

t_ENCL

500

1

ns

t_ENCH

t_HALLABCS

ns

µs

Table 22: Encoder Timing

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30

PLL Interface Electrical Characteristics

CONDITION

PARAMETER SYMBOL

MIN TYP MAX

UNITS

µA

S

Current

IDDS

Static

-

170

Consumption

Current

IDD

Dynamic

-

5

-

mA

Consumption

Peak jitter

Tpj

Tcj

Tlock

-

-500

-

1000

+500

1

ps

ms

Cycle jitter

Lock-up Time

Recommended

operating

PLL Reset

Period

Trst

10

-

ns

condition

Table 25: PLL Electrical Characteristics

IRMCK201

Appendix A Host Register Map

A host computer controls the IRMCK201 using its slave-mode Full-Duplex SPI port, a standard RS-232 port or a 8-bit

parallel port for connection to a microprocessor. All interfaces are always active and can be used interchangeably,

although not simultaneously. Control/status registers are mapped into a 128-byte address space.

Host Parallel Access

The IRMCK201 contains an address register that is updated with the Host Register address when HP_A = 1. After

each subsequent data byte is either read or written, the internal address register is incremented. The diagram below

shows that Data Bytes 0 to N would access register locations initially specified by the Address Byte. The Address

Bye with the HP_A signal can be asserted at any time.

…………….

Data Byte N

HP_A = 0

Address Byte

HP_A = 1

Data Byte 0

HP_A = 0

Host Parallel Data Transfer Format

SPI Register Access

When configured as an SPI device read only and read/write operations are performed using the following transfer

format:

…………….

Data Byte N

Command Byte

Data Byte 0

Data Transfer Format

Bit Position

7

6

5

4

3

2

1

0

Read

Only

Register Map Starting Address

Command Byte Format

Data transfers begin at the address specified in the command byte and proceed sequentially until the SPI transfer

completes. As in the Host Parallel Access, the internal address register is incremented after each SPI byte is

transferred. Note that accesses are read/write unless the “read only” bit is set.

RS-232 Register Access

The IRMCK201 includes an RS-232 interface channel that allows operation using a direct connection to the host PC.

This interface implements a simple protocol that checks the validity of data prior to being written into a register. The

protocol is explained below.

RS-232 Register Write Access

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

34

IRMCK201

A Register write operation consists of a command/address byte, byte count, register data and checksum. When the

IRMCK201 receives the register data, it validates the checksum, writes the register data, and transmits and

acknowledgement to the host.

Command / Address Byte

Byte Count

1-6 bytes of register data

Checksum

Register Write Operation

Command Acknowledgement Byte

Checksum

Register Write Acknowledgement

Bit Position

7

6

5

4

3

2

1

0

1=Read/

0=Write

Register Map Starting Address

Command/Address Byte Format

Bit Position

7

6

5

4

3

2

1

0

1=Error/

0=OK

Register Map Starting Address

Command Acknowledgement Byte Format

The following example shows a command sequence sent from the host to the IRMCO201 requesting a two-byte

register write operation:

0x2F

0x02

0x00

0x04

0x35

Write operation beginning at offset 0x2F

Byte count of register data is 2

Data byte 1

Data byte 2

Checksum (sum of preceding bytes, overflow discarded)

A good reply from the IRMCK201 would appear as follows:

0x2F

Write completed OK at offset 0x2F

Checksum

An error reply to the command would have the following format:

0xAF

Write at offset 0x2F completed in error

Checksum

RS-232 Register Read Access

A register read operation consists of a command/address byte, byte count and checksum. When the IRMCK201

receives the command, it validates the checksum and transmits the register data to the host.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

35

IRMCK201

Command / Address Byte

Byte Count

Checksum

Register Read Operation

Command Acknowledgement Byte

Register Data (Byte Count bytes)

Register Read Acknowledgement (transfer OK)

Command Acknowledgement Byte

Checksum

Register Read Acknowledgement (error)

The following example shows a command sequence sent from the host to the IRMCK201 requesting four bytes of read

register data:

0xA0

0x04

0xA4

Read operation beginning at offset 0x20 (high-order bit selects read operation)

Requested data byte count is 4

Checksum

A good reply from the IRMCK201 might appear as follows:

0x20

0x11

0x22

0x33

0x44

0xCA

Read completed OK at offset 0x20

Data byte 1

Data byte 2

Data byte 3

Data byte 4

Checksum

An error reply to the command would have the following format:

0xA0

Read at offset 0x20 completed in error

Checksum

RS-232 Timeout

The IRMCK201 receiver includes a timer that automatically terminates transfers from the host to the IRMCK201 after

a period of 32 msec.

RS-232 Transfer Examples

The following example shows a normal exchange executing a register write access.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

37

IRMCK201

The example below shows a normal register read access exchange.

The following example shows a register write request that is repeated by the host due to a negative acknowledgement

from the IRMCK201.

In the final example, the host repeats a register read access request when it receives no response to its first attempt.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

38

IRMCK201

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

39

IRMCK201

Write Register Definitions

QuadratureDecode Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

EncCntW (LSBs)

(W)

0x0

0x1

0x3

0x4

0x6

0x7

0x9

0xA

0xB

EncCntW (MSBs)

(W)

MaxEncCnt (LSBs)

(W)

MaxEncCnt (MSBs)

(W)

ZEncCnt (LSBs)

(W)

ZEncCnt (MSBs)

(W)

EncAngScl (LSBs)

(W)

EncAngScl (MSBs)

(W)

RedSig

(W)

PwrOn

RedSig

(W)

ZPulse

Enb

ZPulsePol

(W)

CntEnb

(W)

SPARE

(W)

QuadratureDecode Write Register Map

Field

Name

Access Field Description

(R/W)

EncCntW

W

New value for 16-bit Quadrature Decoder counter.

Maximum value of 16-bit Quadrature Decoder counter. The

encoder count is reset to 0 after this count has been reached.

This maximum should be set to correspond to a 360-degree

physical angle.

Encoder count value when the Z-pulse occurs. This value is

loaded automatically in hardware when the Z-pulse occurs.

(See ZPulseEnb and ZPulsePol fields below.)

MaxEncCnt

ZEncCnt

W

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

40

IRMCK201

Field

Name

Access Field Description

(R/W)

This value should be set to ((MtrPoles / 2) * (4096 * 4096) /

(MaxEncCnt + 1), where MtrPoles is the number of motor

poles. The value is used to convert the encoder count to an

angle ranging from 0 - 4095 using the equation: Angle =

((MtrPoles / 2) * 4096 * (encoder count) / (MaxEncCnt + 1))

MOD 4096. (The current encoder count can be read from

the EncCntR feld of the QuadratureDecodeStatus read

register group.)

EncAngScl

W

CntEnb

ZPulsePol

W

Encoder counter enable.

ZPULSE polarity. 1= load ZEncCnt on rising Z-pulse edge.

0= load ZEncCnt on falling Z-pulse edge.

ZPULSE count initialization enable. When this bit is set, the

encoder count is set to the ZEncCnt value at each Z-pulse

edge as determined by the ZPulsePol field.

ZPulseEnb

W

PowerOn Reduced signal enable.

Set this bit in the

EEPROM to enable EEPROM standalone initialization for a

wire-saving encoder. When this bit is set, the EEPROM

initialization uses the PwrOnHallA, PwrOnHallB, PwrOnHallC

bits instead of the HallA, HallB, HallC bits to determine initial

PwrOnRedSig

motor angle.

(The Hall bits can be read from the

QuadratureDecodeStatus read register group.)

Reduced signal encoder enable. 1 = read Hall A/B/C fields

from encoder A/B/Z wires.

RedSig

W

QuadratureDecode Write Register Field Definitions

PwmConfig Register Group (Write Registers)

Byte

Offset

Bit Position

7

Gatekill

Sns

6

5

Gate

SnsL

(W)

4

Gate

SnsU

(W)

3

2

1

0

SPARE

SD

(W)

SPARE

0xC

0xD

0xE

0xF

(W)

PwmPeriod (LSBs)

(W)

SPARE

PwmConfig

(W)

PwmPeriod (MSBs)

(W)

PwmDeadTm

(W)

PwmConfig Write Register Map

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

41

IRMCK201

Field

Access Field Description

Name

SD

(R/W)

W

Shutdown control output to IR213x.

GateSnsU

W

Upper IGBT gate sense. 1 = active high gate control, 0 = active low

gate control.

GateSnsL

GatekillSns

PwmPeriod

W

Lower IGBT gate sense. 1 = active high gate control, 0 = active low

gate control.

GATEKILL signal sense. 1 = active high GATEKILL, 0 = active low

GATEKILL.

This field is used to set the desired PWM frequency using the

following equation:

PwmPeriod = 33,333,000 / ( 2 * (PWM frequency)) – 1,

where 33,333,000 is the system clock frequency (33.333MHz).

Note that while "PwmPeriod" is the name of this field, the actual

PWM carrier period is 2 * (PwmPeriod + 1) * (System Clock Period

= 30ns).

PwmConfig

W

PWM Configuration. 0 = Asymmetrical center aligned PWM, 1 =

Symmetrical Center aligned PWM.

Gate drive dead time in units of system clock cycles (e.g., 30 ns

with 33 MHz clock).

PwmDeadTm

PwmConfig Write Register Field Definitions

CurrentFeedbackConfig Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

IfbOffsV (LSBs)

(W)

0x10

0x11

IfbOffsW (LSBs)

(W)

IfbOffsV (MSBs)

(W)

IfbOffsW (MSBs)

(W)

0x12

0x13

0x14

0x15

0x16

IdScl (LSB)

(W)

IdScl (MSB)

(W)

IqScl (LSB)

(W)

IqScl (MSB)

(W)

CurrentFeedbackConfig Write Register Map

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

42

IRMCK201

Field

Access Field Description

Name

(R/W)

12-bit signed value for V phase current feedback offset. When the

IfbOffsEnb bit in the SystemControl write register group is "0" this

value is automatically added to each current measurement in

hardware.

12-bit signed value for W phase current feedback offset. When the

IfbOffsEnb bit in the SystemControl write register group is "0” this

value is automatically added to each current measurement in

hardware.

Rotating frame Id component current feedback scale factor. Constant

used to scale current measurements before they are used in the field

orientation calculation. This is a 15-bit fixed-point signed number with

10 fractional bits that ranges from –16 to + 16 + 1023 / 1024.

Rotating frame Iq component current feedback scale factor. Constant

used to scale current measurements before they are used in the field

orientation calculation. This is a 15-bit fixed-point signed number with

10 fractional bits that ranges from –16 to + 16 + 1023 / 1024.

IfbOffsV

IfbOffsW

IdScl

W

IqScl

CurrentFeedbackConfig Write Register Field Definitions

SystemControl Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

DcComp

Enb

IfbOffs

Enb

SPARE

Reserved

Foc

EnbW

Pwm

EnbW

0x17

SystemControl Write Register Map

Field

Name

Access Field Description

(R/W)

PWM Enable bit. Setting this bit to 1 or 0 sets the IGBT gate control

signals to their active or inactive states. At power up the gate control

output signals remain in a high-Z state. After PwmEnbW is set for the

first time, the gate controls are driven to their active or inactive states

according to the value of PwmEnbW. A fault condition clears this bit

automatically in hardware.

PwmEnbW

W

Field Orientated Control Enable bit. Setting this bit to 1 enables the

FOC algorithm. Setting this bit to 0 resets the FOC algorithm and

causes zero output voltage to be applied to the motor. A fault

condition clears this bit automatically in hardware.

FocEnbW

Reserved

W

This field should is reserved and should be set to 0.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

43

IRMCK201

Field

Access Field Description

Name

(R/W)

When IFB PwmEnbW = 1, and FocEnbW = 0, the Current feedback

offset is calculated and saved in the CurrentFeedbackOffset read

register group. When IfbOffsEnb = 1, the Current feedback offset

values in the CurrentFeedbackOffset Read registers are applied to

each current feedback measurement. When IfbOffsEnb = 0, the

Current feedback offset values in the CurrentFeedbackConfig Write

registers are applied to each current feedback measurement.

DC Bus Compensation enable. When this bit is set to "1", PWM

output is compensated for using the following formula:

IfbOffsEnb

W

DcCompEnb

W

PWM (comp) = PWM * 310 / DCBUSVOLTS

where PWM (comp) is the compensated PWM output voltage; PWM

is the uncompensated PWM output voltage; 310 is the nominal DC

bus voltage; and DCBUSVOLTS is the actual DC bus voltage.

SystemControl Write Register Field Definitions

CurrentLoopConfig Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

IqRefW – Quadrature Reference Current (LSBs)

(W)

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

IqRefW – Quadrature Reference Current (MSBs)

(W)

KpIreg – Current Loop Proportional Gain (LSBs)

(W)

KpIreg – Current Loop Proportional Gain (MSBs)

(W)

KxIreg – Current Loop Integral Gain (LSBs)

(W)

KxIreg – Current Loop Integral Gain (MSBs)

(W)

IdRef – Direct/Magnetizing Reference Current (LSBs)

(W)

IdRef – Direct/Magnetizing Reference Current (MSBs)

(W)

SlipGn (LSBs)

(W)

SlipGn (MSBs)

(W)

VqLim – Quadrature Current Output Limit (LSBs)

(W)

VqLim – Quadrature Current Output Limit (MSBs)

(W)

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

44

IRMCK201

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

VdLim – Direct Current Output Limit (LSBs)

(W)

0x26

0x27

VdLim – Direct Current Output Limit (MSBs)

(W)

CurrentLoopConfig Write Register Map

Field

Access Field Description

Name

IqRefW

KpIreg

(R/W)

W

15-bit signed quadrature current reference input from velocity loop.

15-bit signed current loop PI controller proportional gain. Scaled with

14 fractional bits for an effective range of 0 – 1.

W

KxIreg

IdRef

W

15-bit signed current loop PI controller integral gain. Scaled with 19

fractional bits for an effective range of 0 - .03125.

15-bit signed direct/magnetized current to D-axis current loop PI

controller.

This parameter controls the slip speed for induction motor

applications. SlipGn should be set to 2048 * 2048 * (Rated slip

speed in Hz) / (Current loop update frequency). SlipGn MUST be

set to 0 if slip is not desired.

SlipGn

W

VqLim

VdLim

W

16-bit Quadrature current PI controller voltage output limit.

16-bit Direct current PI controller voltage output limit.

CurrentLoopConfig Write Register Field Definitions

VelocityControl Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

SPARE

SpdLpRate

SpdLpEnb

0x31

0x32

KpSreg – Velocity loop proportional gain (LSBs)

(W)

KpSreg – Velocity loop proportional gain (MSBs)

(W)

0x33

0x34

0x35

0x36

0x37

KxSreg – Velocity loop integral gain (LSBs)

(W)

KxSreg – Velocity loop integral gain (MSBs)

(W)

SregLimP – Velocity loop positive Limit (LSBs)

(W)

SregLimP – Velocity loop positive Limit (MSBs)

(W)

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

45

IRMCK201

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

SregLimN – Velocity loop negative Limit (LSBs)

(W)

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

SregLimN – Velocity loop negative Limit (MSBs)

(W)

SpdScl – Speed Scale Factor (LSBs)

SpdScl – Speed Scale Factor (MSBs)

TargetSpd – Setpoint/target speed (LSBs)

TargetSpd – Setpoint/target speed (MSBs)

SpdAccRate – Acceleration

SpdDecRate – Deceleration

VelocityControl Write Register Map

Field

Name

Access Field Description

(R/W)

SpdLpEnb

W

Speed loop enable: 1 = enable speed loop PI controller. 0 = Reset

Speed loop PI controller.

Speed loop update rate: 0 = disabled, N = update speed loop

immediately before every Nth current loop update.

15-bit velocity loop proportional gain, in fixed point with 5 fractional

bits. Range = 0 - 512.

SpdLpRate

KpSreg

KxSreg

15-bit velocity loop integral gain, in fixed point with 13 fractional bits.

Range = 0 - 2.

SregLimP

SregLimN

W

16-bit speed PI controller output positive limit.

16-bit speed PI controller output negative limit (2's complement).

Motor Speed Scale factor. The user should set SpdScl = 60 *

16383 * (33.333MHz/32) / (Max RPM * Encoder PPR) / 2, which will

result in a Speed value ranging ±16384 corresponding to ± Max

RPM.

SpdScl

W

TargetSpd

W

Velocity loop speed setpoint in SPEED units, which are determined

by the user via the SpdScl register setting.

Velocity loop acceleration in units of SPEED / Velocity loop execution

or SPEED / (SpdLpRate / PWM period).

Velocity loop deceleration in units of SPEED / Velocity loop execution

or SPEED / (SpdLpRate / PWM period).

SpdAccRate

SpdDecRate

VelocityControl Write Register Field Definitions

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

46

IRMCK201

FaultControl Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

FltClr

0

DcBusM

Enb

SPARE

0x42

FaultControl Write Register Map

Field

Name

Access Field Description

(R/W)

DC Bus monitor enable. 1 = Monitor DC bus voltage and generate

appropriate brake signal control and disable PWM output when

voltage fault conditions occur. GatekillFlt and OvrSpdFlt faults

cannot be disabled. DC bus voltage thresholds are as follows:

Overvoltage – 410V

DcBusMEnb

W

Brake On – 380V

Brake Off – 360V

Nominal – 310V

Undervoltage off – 140V

Undervoltage – 120V

This bit clears all active fault conditions. The user should monitor

the FaultStatus read register group to determine fault status and set

this bit to “1” to clear any faults that have occurred. A fault condition

automatically clears the PwmEnbW and FocEnbW bits in the

SystemControl write register group. Note that this bit also directly

controls the output 2137 FLTCLR pin. After clearing a fault, the

user must explicitly set this bit to “0” to re-enable fault processing.

FaultControl Write Register Field Definitions

FltClr

W

SVPWMScaler Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

ModScl (LSBs)

(W)

0x44

0x45

ModScl (MSBs)

(W)

SVPWMScaler Write Register Map

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

47

IRMCK201

Field

Access Field Description

Name

(R/W)

Space vector modulator scale factor.

This register, which

depends on the PWM carrier frequency, should be set as follows:

ModScl = PwmPeriod * sqrt(3) * 4096 / 2355

ModScl

W

where PwmPeriod is the value in the PwmConfig write register

group’s PwmPeriod register.

SVPWMScaler Write Register Field Definitions

DiagnosticPwmControl Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

PwmData1Sel

PwmData0Sel

0x4E

0x4F

PwmData3Sel

PwmData2Sel

DiagnosticPwmControl Write Register Map

Field

Name

Access Field Description

(R/W)

Selects diagnostic data items for output on DAC PWM pins 0-3.

These pins are intended for use with external RC filters for

oscilloscope diagnostic display:

1 = DC Bus Voltage

2 = V phase current

3 = W phase current

PwmData0Sel,

PwmData1Sel,

PwmData2Sel,

PwmData3Sel

5 = Speed PI Reference

6 = Speed PI Feedback

7 = Speed PI Error

8 = IQ Ref

W

9 = Q axis voltage Qv

10 = D axis voltage Dv

11 = 12-bit electrical angle

12 = Q axis current Qi

13 = D axis current Di

14 = A axis (stationary frame) voltage Av

15 = B axis (stationary frame) voltage Bv

DiagnosticPwmControl Write Register Field Definitions

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

48

IRMCK201

SystemConfig Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

ExtCtrlW

SpdRefSel

IqRefSel

HostAng

Enb

HostVd

Enb

RmpRef

Sel

0x50

SystemConfig Write Register Map

Field

Name

Access Field Description

(R/W)

RmpRefSel

W

Speed Ramp reference select. 0= TargetSpd field of the

VelocityControl write register group, 1 = External analog reference.

Host D-Axis current control enable. When this bit is set, the D-Axis

PI Controller is disconnected from the forward path vector rotator,

which then takes its input from the VdSfwd field of the

DirectHostVoltageControl write register group.

HostVdEnb

W

Host electrical angle control enable. When this bit is set, the vector

rotator takes its angle input from the ElecAngW field of the

DirectHostVoltageControl write register group.

Selects the source for the Q-Axis PI controller IQREF input:

0 = Speed PI controller output

HostAngEnb

IqRefSel

W

1 = IqRefW field of the CurrentLoopConfig write register group

2 = Reference A/D converter input.

Selects the source for the Speed PI controller reference input:

0 = Internal Accel/Deccel ramp generator

1 = TargetSpd field of the VelocityControl write register group

2 = Reference A/D converter input.

Setting this bit to “1” enables direct control of basic motor operation

via the external User Interface pins. When this bit is “1”, the

FocEnbW and PwmEnbW bits in the SystemControl write register

group are ignored.

SpdRefSel

ExtCtrlW

W

SystemConfig Write Register Field Definitions

DirectHostVoltageControl Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

VdSfwd (LSBs)

(W)

0x52

0x53

VqSfwd (LSBs)

(W)

VdSfwd (MSBs)

(W)

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

49

IRMCK201

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

VqSfwd (MSBs)

(W)

0x54

0x55

0x56

ElecAngW (LSBs)

(W)

SPARE

ElecAngW (MSBs)

(W)

DirectHostVoltage Control Write Register Map

Field

Name

Access Field Description

(R/W)

VdSfwd

W

12-bit signed value for synchronous frame direct current

when host direct current control is enabled. This field is

typically used for V/Hz control.

12-bit signed value for synchronous frame quadrature

voltage that is added to the Q-Axis PI-controller output.

This field is typically used for feedforward or V/Hz control.

12-bit electrical angle used when host electrical angle control

is enabled. This field is typically used for V/Hz control.

VqSfwd

ElecAngW

DirectHostVoltageControl Write Register Field Definitions

32bitQuadDecode Register Group (Write Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

EncCnt32bW (bits 0-7)

(W)

0x58

0x59

0x5A

0x5B

EncCnt32bW (bits 8-15)

(W)

EncCnt32bW (bits 16-23)

(W)

EncCnt32bW (bits 24-31)

(W)

32bitQuadDecode Write Register Map

Field

Name

Access Field Description

(R/W)

EncCnt32bW

W

New value for 32-bit Quadrature Decoder counter.

32bitQuadDecode Write Register Field Definitions

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50

IRMCK201

EepromControl Registers (Write Registers)

At power up, the write registers can be optionally initialized with values stored in EEPROM. The EepromControl

write register group and EepromStatus read register group are used to read and write these EEPROM values. Since

the EeAddrW write register (which selects the EEPROM offset to read or write) does not require initialization at

power up, the location corresponding to that register in EEPROM (at offset 0x5D) is used to store a register map

version code. At power on, the IRMCK201 initializes the write registers from EEPROM only if the version code

stored at this offset in EEPROM matches its internal register map version code (which can be read from the

RegMapVer field of the EepromStatus read register group).

To enable write register initialization at power up, write the appropriate register map version code to EEPROM at

offset 0x5D. To disable write register initialization at power up, write a zero (or any non-matching version code) to

offset 0x5D of the EEPROM.

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

SPARE

EeWrite

EeRead

EeRst

0x5C

0x5D

EeAddrW / RegMapVersCode

(W)

EeDataW

(W)

0x5E

EepromControl Write Register Map

Field

Name

Access Field Description

(R/W)

EeRst

W

Self-clearing EEPROM reset. Writing a "1" to this bit resets the I2C

EEPROM interface.

EeRead

W

Self-clearing I2c EEPROM Read. Writing a "1" to this bit initiates an

EEPROM read from the byte located at EEPROM address EeAddrW.

After setting this bit the user should poll the EeBusy bit in the

EepromStatus read register group to determine when the read

completes and then read the data from EeDataR in the

EepromStatus read register group.

EeWrite

W

Self-clearing EEPROM Write. Writing a "1" to this bit initiates an

EEPROM write from the data byte in EeDataW to the EEPROM

address EeAddrW.

EeAddrW

EeDataW

W

EEPROM Address Register. Contains the address for the next

EEPROM read or write operation.

EEPROM Data Register. Contains the data for the next EEPROM

write operation.

EepromControl Write Register Field Definitions

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

51

IRMCK201

HallSensorEncoderInit (Write Registers – EEPROM only)

These values must be set in the EEPROM for initial encoder count/angle initialization in the EEPROM standalone (i.e.

operation without a host program). EEPROM initialization logic automatically loads the appropriate value into the

encoder counter at power-on based on the HALL A/B/C sensor values. These values are present only in the

EEPROM since they serve no purpose after power on.

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

HallCBA001(LSBs)

HallCBA001(MSBs)

HallCBA010 (LSBs)

HallCBA010 (MSBs)

HallCBA011(LSBs)

HallCBA011(MSBs)

HallCBA100 (LSBs)

HallCBA100 (MSBs)

HallCBA101(LSBs)

HallCBA101(MSBs)

HallCBA110 (LSBs)

HallCBA 110 (MSBs)

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

HallSensorEncoderInit Register Map

Field

Access

Field Description

Name

(R/W)

W

HallCBAnnn

(EEPROM Initial encoder count for Hall Sensor [C, B, A] value [n, n, n].

ONLY)

HallSensorEncoderInit Field Definitions

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

52

IRMCK201

Read Register Definitions

QuadratureDecodeStatus Register Group (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

EncCntR (LSBs)

(R)

0x0

0x1

0x3

EncCntR (MSBs)

(R)

SPARE

PwrOn

HallC

PwrOn

HallB

PwrOn

HallA

SPARE

HallC

HallB

HallA

QuadratureDecodeStatus Read Register Map

Field

Name

Access Field Description

(R/W)

EncCntR

HallA, HallB,

HallC

R

Current value of 16-bit Quadrature Decoder counter.

Hall Sensor A/B/C values.

PwrOnHallA,

PwrOnHallB,

PwrOnHallC

Hall Sensor A/B/C values at power-on for reduced-wire encoder

interface.

R

QuadratureDecodeStatus Read Register Field Definitions

SystemStatus Register Group (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

Start

Stop

SPARE

PwrID

GateKill

Foc

EnbR

Pwm

EnbR

0x7

0x8

0x9

RevCode (LSBs)

RevCode (MSBs)

SystemStatus Read Register Map

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

53

IRMCK201

Field

Access Field Description

Name

(R/W)

PwmEnbR

FocEnbR

GateKill

R

PWM Enable bit status.

FOC Enable bit status.

GATEKILL status. This bit is set by the Gatekill input from the

IR2137. Once set, this bit remains set until it is cleared by writing a

“1” to the FaultClr bit in the FaultControl write register group.

Power ID. 0 = 3 kW, 1 = 2 kW, 2 = 500 W.

User Interface "STOP" digital input status.

User Interface "START" digital input status.

IC Revision Code. Revision code format is “XX.XX”, where each “X”

is a 4-bit hexadecimal number.

PwrID

Stop

Start

R

RevCode

SystemStatus Read Register Field Definitions

DcBusVoltage Register Group (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

DcBusVolts (LSBs)

Brake

0xA

0xB

SPARE

DcBusVolts (MSBs)

DcBusVoltage Read Register Map

Field

Name

Access Field Description

(R/W)

DcBusVolts

R

DC Bus Voltage. Data range is 0 - 4095, which corresponds to a

DC bus voltage between 0 and 500 volts.

Brake

R

Brake signal status. 0 = Brake signal active.

DcBusVoltage Read Register Field Definitions

FocDiagnosticData Register Group (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

IvFbk - V Phase IFB Raw Current (LSBs)

(R)

0xC

0xD

IwFbk - W Phase IFB Raw Current (LSBs)

(R)

IvFbk - V Phase IFB Raw Current (MSBs)

(R)

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

54

IRMCK201

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

IwFbk - W Phase IFB Raw Current (MSBs)

(R)

0xE

0xF

Id – Synchronous Frame Direct Current (LSBs)

(R)

Id – Synchronous Frame Direct Current (MSBs)

(R)

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

Iq – Synchronous Frame Quadrature Current (LSBs)

(R)

Iq – Synchronous Frame Quadrature Current (MSBs)

(R)

Ud – Synchronous Frame Direct Voltage (LSBs)

(R)

Ud – Synchronous Frame Direct Voltage (MSBs)

(R)

Uq – Synchronous Frame Quadrature Voltage (LSBs)

(R)

Uq – Synchronous Frame Quadrature Voltage (MSBs)

(R)

UAlpha – Stationary Frame Alpha Voltage (LSBs)

(R)

UBeta – Stationary Frame Beta Voltage (LSBs)

(R)

UAlpha – Stationary Frame Alpha Voltage (MSBs)

(R)

UBeta – Stationary Frame Beta Voltage (MSBs)

(R)

FocDiagnosticData Read Register Map

Field

Access Field Description

Name

(R/W)

Offset-corrected V and W phase raw current from the IR2175 current

sensor. Values range from 0 - 4096, where 2048 corresponds to 0

current. The current feedback scale factors IdScl and IqScl in the

CurrentFeedbackConfig write register group and the current sense

resistor value determine the full scale current value.

IvFbk, IwFbk

R

Synchronous or rotating frame direct and quadrature current values

in 2’s complement representation. The full scale current values range

from –16384 to 16383.

Synchronous or rotating frame direct and quadrature voltage values

in 2’s complement representation. Data ranges are ± VdLim for Ud

and ± VqLim for Uq as specified in the CurrentLoopConfig write

register group.

Id, Iq

R

Ud, Uq

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

55

IRMCK201

UAlpha,

UBeta

R

Stationary frame Alpha and Beta voltage output component values.

Data range is ± VdLim or ± VqLim (as specified in the

CurrentLoopConfig write register group), whichever is larger.

FocDiagnosticData Read Register Field Definitions

FaultStatus Register Group (Read Registers)

The Fault Status register records fault conditions that occur during drive operation. When any of these fault

conditions occur, the PWM output is automatically disabled. The user should monitor this register continuously for

fault conditions. A fault condition can be cleared by writing a “1” to the FaultClr bit in the FaultControl write

register group. (This does not automatically re-enable PWM output.)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

SPARE

ExecTm

Flt

OvrSpdFlt

OvFlt

LvFlt

GatekillFlt

0x1E

FaultStatus Read Register Map

Field

Name

Access Field Description

(R/W)

GatekillFlt

LvFlt

R

Filtered and latched version of IR213x FAULT output.

DC bus low voltage fault. This fault occurs if the DC bus drops

below 120V.

OvFlt

R

DC bus overvoltage fault. This fault occurs if the DC bus voltage

exceeds 410V.

Over speed fault. This fault occurs whenever the motor reaches the

positive or negative limits. The user should use the scale factor in

the SpdScl field of the VelocityControl write register group to scale

the motor speed so that it falls between -16384 and +16383 with

these limits as the over speed condition.

OvrSpdFlt

ExecTmFlt

R

Execution time fault.

FaultStatus Read Register Field Definitions

VelocityStatus Register Group (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

Spd (LSBs)

Spd (MSBs)

0x26

0x27

VelocityStatus Read Register Map

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

56

IRMCK201

Field

Name

Spd

Access Field Description

(R/W)

R

Current motor speed in SPEED units. (See the description of SpdScl

in the VelocityControl write register group.)

VelocityStatus Read Register Field Definitions

CurrentFeedbackOffset Register Group (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

IfbVOffs (LSBs)

(R)

0x30

0x31

0x32

IfbWOffs (LSBs)

(R)

IfbVOffs (MSBs)

(R)

IfbWOffs (MSBs)

(R)

CurrentFeedbackOffset Read Register Map

Field

Access Field Description

Name

(R/W)

Current feedback offset values from the last IFB Offset calculation.

These values are automatically applied to each current feedback

measurement value whenever the IfbOffsEnb bit in the

SystemControl write register group is set.

IfbVOffs,

IfbWOffs

R

CurrentFeedbackOffset Read Register Field Definitions

32bitQuadDecodeStatus Register Group (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

EncCnt32bR (bits 0-7)

(R)

0x34

0x35

0x36

0x37

EncCnt32bR (bits 8-15)

(R)

EncCnt32bR (bits 16-23)

(R)

EncCnt32bR (bits 24-31)

(R)

32bitQuadDecodeStatus Read Register Map

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

57

IRMCK201

Field

Name

EncCnt32bR

Access

(R/W)

R

Field Description

Current value of 32-bit Quadrature Decoder counter.

32bitQuadDecodeStatus Read Register Field Definitions

EepromStatus Registers (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

SPARE

EeBusy

0x38

0x39

0x3A

0x3B

EeDataR

(R)

EeAddrR

(R)

RegMapVer

(R)

EepromStatus Read Register Map

Field

Name

Access Field Description

(R/W)

EeBusy

R

I2C EEPROM Interface busy bit. The user should wait for this bit to

clear before initiating EEPROM read or write operations.

EeDataR

EeAddrR

R

EEPROM Data Register. Contains the data from the last EEPROM

read operation.

Note that writing to the EeRst field in the

EepromControl write register group invalidates this register.

EEPROM Address read register shows the value stored in EEPROM

at the offset of the EeAddrW write register (0x5D). Since this

address in the EEPROM contains the IRMCK201 register map

version, the user can read this field to determine whether or not the

write registers were initialized at power on.

R

RegMapVer

Current register map version code.

EepromStatus Read Register Field Definitions

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

58

IRMCK201

FOCDiagnosticDataSupplement Register Group (Read Registers)

Byte

Offset

Bit Position

7

6

5

4

3

2

1

0

ElecAngR (LSBs)

(R)

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

SPARE

ElecAngR (MSBs)

(R)

SpdRef (LSBs)

(R)

SpdRef (MSBs)

(R)

SpdErr (LSBs)

(R)

SpdErr (MSBs)

(R)

IqRefR (LSBs)

(R)

IqRefR (MSBs)

(R)

FOCDiagnosticDataSupplement Read Register Map

Field

Name

Access Field Description

(R/W)

ElecAngR

SpdRef

SpdErr

IqRefR

R

Electrical angle.

Speed PI controller reference input.

Speed PI controller error.

Speed PI controller output.

FOCDiagnosticDataSupplement Read Register Field Definitions

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

59

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IRMCK201

DIMENSION IN MILIMETERS

DIMENSION IN INCHES*

SYMBOL

Min.

13.9

Nom.

14

Max.

14.1

1.7

Min.

Nom.

(0.551)

Max.

E

D

(0.548)

(0.555)

(0.066)

14

A

A1

A2

e

0.1

1.4

(0.004)

(0.055)

(0.020)

(0.007)

(0.005)

1.3

1.5

(0.052)

(0.059)

0.5

b

0.13

0.1

0º

0.18

0.125

0.28

0.175

10º

(0.006)

(0.004)

(0º)

(0.011)

(0.006)

(10º)

C

θ

L

0.3

0.5

1

0.7

(0.012)

(0.20)

(0.039)

(0.020)

(0.630)

(12º)

(0.027)

L1

L2

H_E

H_D

O2

O3

R

0.5

16

15.6

16.4

(0.615)

(0.645)

16

12º

0.2

(12º)

(0.008)

R1

Table 27: QFP100 Dimensions

* For reference

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

61

IRMCK201

Appendix C Errata

1. Using the ADS7818 A/D converter interface as the current feedback source is not supported

2. The scaling is too large by a factor of 16 for the following Diagnostic DAC PWM selections: Reference Speed

(PWM data select value of 5), Motor Speed (PWM data select value of 6), IQREF (PWM data select value of 8).

The scaling is too large by a factor of 8 for the following Diagnostic DAC PWM selections: IQ (PWM data select

value of 12), ID (PWM data select value of 13).

The scaling is too large by a factor of 4 for the following Diagnostic DAC PWM selections: Av (PWM data select

value of 14), Bv (PWM data select value of 15).

These values will work at small data ranges, but overflow otherwise. To extract the correct data for these items,

use the parallel port and diagnostic data registers.

3. When the IRMCK201 is implemented in conjunction with the ADS7818, note that the IRMCK201 ADCLK is

specified at 120 ns while the ADS7818 is specified at 125 ns.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

62

IRMCK201

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105

http://www.irf.com

Data and specifications subject to change without notice. 6/1/2004

Sales Offices, Agents and Distributors in Major Cities Throughout the World.

This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

63


型号：	IRMCK201
厂家：	Infineon
描述：	High Performance Configurable Digital AC Servo Control IC 高性能的可配置数字交流伺服控制IC 运动控制电子器件信号电路电动机控制
文件：	总62页 (文件大小：1894K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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