IRMCK311TY_技术文档

Data Sheet No. PD60338

IRMCK311

Dual Channel Sensorless Motor Control IC for

Appliances

Features

Product Summary

MCE^TM(Motion Control Engine) - Hardware based

computation engine for high efficiency sinusoidal

sensorless control of permanent magnet AC motor

Integrated Power Factor Correction control

Supports both interior and surface permanent

magnet motors

Maximum crystal frequency

60 MHz

Maximum internal clock (SYSCLK) frequency 128 MHz

Maximum 8051 clock frequency

Sensorless control computation time

MCE^TMcomputation data range

8051 OTP Program memory

MCE program and Data RAM

GateKill latency (digital filtered)

PWM carrier frequency counter

A/D input channels

33 MHz

11 μsec typ

16 bit signed

56K bytes

8K bytes

2 μsec

Built-in hardware peripheral for single shunt

current feedback reconstruction

No external current or voltage sensing operational

amplifier required

Dual channel three/two-phase Space Vector PWM

Three-channel analog output (PWM)

Embedded 8-bit high speed microcontroller (8051)

for flexible I/O and man-machine control

JTAG programming port for emulation/debugger

Two serial communication interface (UART)

I²C/SPI serial interface

Watchdog timer with independent analog clock

Three general purpose timers/counters

Two special timers: periodic timer, capture timer

16 bits/ SYSCLK

6

A/D converter resolution

12 bits

A/D converter conversion speed

8051 instruction execution speed

Analog output (PWM) resolution

UART baud rate (typ)

2 μsec

2 SYSCLK

8 bits

57.6K bps

14

Number of I/O (max)

Package (lead-free)

QFP64

Internal ‘One-Time Programmable’ (OTP) memory

and internal RAM for final production usage

Operating temperature

-40°C ~ 85°C

Pin compatible with IRMCF311 RAM version

1.8V/3.3V CMOS

Description

IRMCK311 is a high performance OTP based motion control IC designed primarily for appliance applications. IRMCK311 is

designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control.

IRMCK311 contains two computation engines. One is Motion Control Engine (MCE^TM) for sensorless control of permanent

magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one

monolithic chip. The MCE^TMcontains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle

estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by

connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as

the Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital

circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-

cycle instruction execution (16MIPS at 33MHz). The MCE and 8051 microcontroller are connected via dual port RAM to

process signal monitoring and command input. An advanced graphic compiler for the MCE^TMis seamlessly integrated into the

MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments.

IRMCK311 comes with a small QFP64 pin lead-free package.

Rev 1.0

IRMCK311

TABLE OF CONTENTS

1

2

3

4

Overview...................................................................................................................................... 5

IRMCK311 Block Diagram and Main Functions........................................................................ 6

Pinout........................................................................................................................................... 8

Input/Output of IRMCK311 ........................................................................................................ 9

4.1 8051 Peripheral Interface Group......................................................................................... 10

4.2 Motion Peripheral Interface Group..................................................................................... 10

4.3 Analog Interface Group ...................................................................................................... 11

4.4 Power Interface Group........................................................................................................ 11

4.5 Test Interface....................................................................................................................... 12

Application Connections ........................................................................................................... 13

DC Characteristics..................................................................................................................... 14

6.1 Absolute Maximum Ratings ............................................................................................... 14

6.2 System Clock Frequency and Power Consumption............................................................ 14

6.3 Digital I/O DC Characteristics............................................................................................ 15

6.4 PLL and Oscillator DC Characteristics............................................................................... 15

6.5 Analog I/O DC Characteristics ........................................................................................... 16

6.6 Under Voltage Lockout DC Characteristics ....................................................................... 17

6.7 AREF Characteristics.......................................................................................................... 17

AC Characteristics..................................................................................................................... 18

7.1 PLL AC Characteristics ...................................................................................................... 18

7.2 Analog to Digital Converter AC Characteristics ................................................................ 19

7.3 Op Amp AC Characteristics ............................................................................................... 19

7.4 SYNC to SVPWM and A/D Conversion AC Timing......................................................... 20

7.5 GATEKILL to SVPWM AC Timing.................................................................................. 21

7.6 Interrupt AC Timing ........................................................................................................... 21

7.7 I²C AC Timing.................................................................................................................... 22

7.8 SPI AC Timing.................................................................................................................... 23

7.8.1 SPI Write AC timing .................................................................................................... 23

7.8.2 SPI Read AC Timing.................................................................................................... 24

7.9 UART AC Timing .............................................................................................................. 25

5

6

7

7.10

7.11

7.12

CAPTURE Input AC Timing .......................................................................................... 26

JTAG AC Timing ............................................................................................................ 27

OTP Programming Timing.............................................................................................. 28

8

9

10

11

12

I/O Structure .............................................................................................................................. 29

Pin List....................................................................................................................................... 32

Package Dimensions............................................................................................................... 35

Part Marking Information....................................................................................................... 36

Ordering Information ............................................................................................................. 36

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IRMCK311

TABLE OF FIGURES

Figure 1. Typical Application Block Diagram Using IRMCK311 .......................................5

Figure 2. IRMCK311 Internal Block Diagram ...................................................................6

Figure 3. IRMCK311 Pin Configuration............................................................................8

Figure 4. Input/Output of IRMCK311................................................................................9

Figure 5. Application Connection of IRMCK311.............................................................13

Figure 6. Clock Frequency vs. Power Consumption ......................................................14

Figure 7 Crystal oscillator circuit ....................................................................................18

Figure 8 Voltage droop of sample and hold ...................................................................19

Figure 9 SYNC to SVPWM and A/D conversion AC Timing...........................................20

Figure 10 GATEKILL to SVPWM AC Timing ....................................................................21

Figure 11 Interrupt AC Timing........................................................................................21

Figure 12 I²C AC Timing ................................................................................................22

Figure 13 SPI AC Timing ...............................................................................................23

Figure 14 SPI Read AC Timing......................................................................................24

Figure 15 UART AC Timing............................................................................................25

Figure 16 CAPTURE Input AC Timing ...........................................................................26

Figure 17 JTAG AC Timing............................................................................................27

Figure 18 OTP Programming Timing .............................................................................28

Figure 19 All digital I/O except motor PWM output ...........................................................29

Figure 20 RESET, GATEKILL I/O.....................................................................................29

Figure 21 Analog input......................................................................................................30

Figure 22 Analog operational amplifier output and AREF I/O structure..........................30

Figure 23 VPP programming pin I/O structure.............................................................30

Figure 24 VSS and AVSS pin structure ............................................................................31

Figure 25 VDD1 and VDDCAP pin structure ....................................................................31

Figure 26 XTAL0/XTAL1 pins structure..........................................................................31

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IRMCK311

TABLE OF TABLES

Table 1. Absolute Maximum Ratings............................................................................................ 14

Table 2. System Clock Frequency................................................................................................. 14

Table 3. Digital I/O DC Characteristics........................................................................................ 15

Table 4. PLL DC Characteristics .................................................................................................. 15

Table 5. Analog I/O DC Characteristics ....................................................................................... 16

Table 6. UVcc DC Characteristics ................................................................................................ 17

Table 7. AREF DC Characteristics ............................................................................................... 17

Table 8. PLL AC Characteristics .................................................................................................. 18

Table 9. A/D Converter AC Characteristics.................................................................................. 19

Table 10. Current Sensing OP Amp AC Characteristics............................................................... 19

Table 11. SYNC AC Characteristics............................................................................................. 20

Table 12. GATEKILL to SVPWM AC Timing............................................................................ 21

Table 13. Interrupt AC Timing...................................................................................................... 21

Table 14. I²C AC Timing .............................................................................................................. 22

Table 15. SPI Write AC Timing.................................................................................................... 23

Table 16. SPI Read AC Timing..................................................................................................... 24

Table 17. UART AC Timing......................................................................................................... 25

Table 18. CAPTURE AC Timing ................................................................................................. 26

Table 19. JTAG AC Timing.......................................................................................................... 27

Table 20. OTP Programming Timing............................................................................................ 28

Table 21. Pin List .......................................................................................................................... 32

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IRMCK311

1 Overview

IRMCK311 is a new International Rectifier integrated circuit device primarily designed as a one-

chip solution for complete inverter controlled appliance dual motor control applications. Unlike a

traditional microcontroller or DSP, the IRMCK311 provides a built-in closed loop sensorless

control algorithm using the unique Motion Control Engine (MCE^TM) for permanent magnet motors.

The MCE^TMconsists of a collection of control elements, motion peripherals, a dedicated motion

control sequencer and dual port RAM to map internal signal nodes. IRMCK311 also employs a

unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and

enables a direct shunt resistor interface to the IC. The sensorless control is the same for both

motors with a single shunt current sensing capability. Motion control programming is achieved

using a dedicated graphical compiler integrated into the MATLAB/Simulink^TMdevelopment

environment. Sequencing, user interface, host communication, and upper layer control tasks can

be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is

equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical

application schematic using IRMCK311.

IRMCK311 is intended for volume production purpose and contains 64K bytes of OTP (One Time

Programming) ROM, which can be programmed through a JTAG port. For a development

purpose use, IRMCF311 contains a 48k byte of RAM in place of program OTP to facilitate an

application development work. Both IRMCF311 and IRMCK311 come in the same 64-pin QFP

package with identical pin configuration to facilitate PC board layout and transition to mass

production

Figure 1. Typical Application Block Diagram Using IRMCK311

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IRMCK311

2 IRMCK311 Block Diagram and Main Functions

IRMCK311 block diagram is shown in Figure 2.

Figure 2. IRMCK311 Internal Block Diagram

IRMCK311 contains the following functions for sensorless AC motor control applications:

•

Motion Control Engine (MCE^TM)

o Proportional plus Integral block

o Low pass filter

o Differentiator and lag (high pass filter)

o Ramp

o Limit

o Angle estimate (sensorless control)

o Inverse Clark transformation

o Vector rotator

o Bit latch

o Peak detect

o Transition

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IRMCK311

o Multiply-divide (signed and unsigned)

o Divide (signed and unsigned)

o Adder

o Subtractor

o Comparator

o Counter

o Accumulator

o Switch

o Shift

o ATAN (arc tangent)

o Function block (any curve fitting, nonlinear function)

o 16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE)

o MCE^TMprogram and data memory (6K byte). ^{Note 1}

o MCE^TMcontrol sequencer

•

8051 microcontroller

o Three 16-bit timer/counters

o 16-bit periodic timer

o 16-bit analog watchdog timer

o 16-bit capture timer

o Up to 36 discrete I/Os

o Eleven-channel 12-bit A/D

Five buffered channels (0 – 1.2V input)

One unbuffered channel (0 – 1.2V input)

o JTAG port (4 pins)

o Up to three channels of analog output (8-bit PWM)

o Two UART

o I²C/SPI port

o 64K byte ^{Note 1}program One-Time Programmable memory

o 2K byte data RAM. ^{Note 2}

Note 1: Total size of OTP memory is 64K byte, however MCE program occupies

maximum 8K byte which will be loaded into internal RAM at a powerup/boot

process. Therefore only 56K byte OTP memory area is usable for 8051

microcontroller.

Note 2: Total size of RAM is 8K byte including MCE program, MCE data, and 8051

data. Different sizes can be allocated depending on applications.

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IRMCK311

3 Pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

XTAL0

XTAL1

P3.0/INT2/CS1

CPWMUH

CPWMUL

CPWMVH

CPWMVL

CPWMWH

CPWMWL

CGATEKILL

VDD1

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P1.1/RXD

P1.2/TXD

P1.3/SYNC/SCK

P1.4/CAP

VDD2

3

4

5

6

7

VSS

8

VDD1

9

FGATEKILL

FPWMWL

FPWMWH

FPWMVL

FPWMVH

FPWMUL

FPWMUH

VSS

10

11

12

13

14

15

16

(Top View)

IPFC-

IPFC+

IPFCO

VACO

VAC-

VAC+

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 3. IRMCK311 Pin Configuration

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IRMCK311

4 Input/Output of IRMCK311

All I/O signals of IRMCK311 are shown in Figure 4. All I/O pins are 3.3V logic interface except

A/D interface pins.

Figure 4. Input/Output of IRMCK311

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IRMCK311

4.1 8051 Peripheral Interface Group

UART Interface

P1.1/RXD

P1.2/TXD

P3.6/RXD1

P3.7/TXD1

Input, Receive data to IRMCK311, can be configured as P1.1

Output, Transmit data from IRMCK311, can be configured as P1.2

Input, 2^ndchannel Receive data to IRMCK311, can be configured as P3.6

Output, 2^ndchannel Transmit data from IRMCK311, can be configured as

P3.7

Discrete I/O Interface

P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock

P1.4/CAP Input/output port 1.4, can be configured as Capture Timer input

P3.0/INT2/CS1 Input/output port 3.0, can be configured as external interrupt 2 or SPI

chip select 1

P3.2/INT0

Input/output port 3.2, can be configured as external interrupt 0

Analog Output Interface

P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with

programmable carrier frequency

P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with

programmable carrier frequency

Crystal Interface

XTAL0

XTAL1

Input, connected to crystal

Output, connected to crystal

Reset Interface

RESET

Inout, system reset, needs to be pulled up to VDD1 but doesn’t require

external RC time constant

I²C/SPI Interface

SCL/SO-SI/VPP Output, I²C clock output, SPI SO-SI

SDA/CS0

Input/output, I²C Data line, Chip Select 0 of SPI

P3.0/INT2/CS1 Input/output port 3.0, can be configured as external interrupt 2 or SPI

chip select 1

P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock

4.2 Motion Peripheral Interface Group

PWM

CPWMUH

CPWMUL

CPWMVH

CPWMVL

CPWMWH

CPWMWL

FPWMUH

FPWMUL

Output, motor 1 PWM phase U high side gate signal

Output, motor 1 PWM phase U low side gate signal

Output, motor 1 PWM phase V high side gate signal

Output, motor 1 PWM phase V low side gate signal

Output, motor 1 PWM phase W high side gate signal

Output, motor 1 PWM phase W low side gate signal

Output, motor 2 PWM phase U high side gate signal

Output, motor 2 PWM phase U low side gate signal

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IRMCK311

FPWMVH

FPWMVL

FPWMWH

FPWMWL

PFCPWM

Output, motor 2 PWM phase V high side gate signal

Output, motor 2 PWM phase V low side gate signal

Output, motor 2 PWM phase W high side gate signal

Output, motor 2 PWM phase W low side gate signal

Output, PFC PWM

Fault

CGATEKILL

Input, upon assertion, this negates all six PWM signals for motor 1,

programmable logic sense

P5.0/PFCGKILL Input, upon assertion, this negates PFCPWM signal, programmable logic

sense, can be configured as discrete I/O in which case CGATEKILL

negates PFCPWM

FGATEKILL

Input, upon assertion, this negates all six PWM signals for motor 2,

programmable logic sense

4.3 Analog Interface Group

AVDD

AVSS

AREF

CMEXT

Analog power (1.8V)

Analog power return

Buffered 0.6V output

Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be

connected.

IFBC+

IFBC-

IFBCO

IFBF+

IFBF-

Input, Operational amplifier positive input for shunt resistor current

sensing of motor 1

Input, Operational amplifier negative input for shunt resistor current

sensing of motor 1

Output, Operational amplifier output for shunt resistor current sensing of

motor 1

Input, Operational amplifier positive input for shunt resistor current

sensing of motor 2

Input, Operational amplifier negative input for shunt resistor current

sensing of motor 2

IFBFO

Output, Operational amplifier output for shunt resistor current sensing of

motor 2

IPFC+

IPFC-

IPFO

VAC+

VAC-

VACO

VDC+

VDC-

Input, Operational amplifier positive input for PFC current sensing

Input, Operational amplifier negative input for PFC current sensing

Output, Operational amplifier output for PFC current sensing

Input, Operational amplifier positive input for PFC AC voltage sensing

Input, Operational amplifier negative input for PFC AC voltage sensing

Output, Operational amplifier output for PFC AC voltage sensing

Input, Operational amplifier positive input for DC bus voltage sensing

Input, Operational amplifier negative input for DC bus voltage sensing

Input/Output, Analog input channel 0 or Operational amplifier output for

DC bus voltage sensing

AIN0/VDCO

AIN1

Input, Analog input channel 1 (0-1.2V), needs to be pulled down to AVSS

if unused

4.4 Power Interface Group

VDD1

VDD2

Digital power for I/O (3.3V)

Digital power for core logic (1.8V)

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IRMCK311

VSS

PLLVDD

PLLVSS

Digital common

PLL power (1.8V)

PLL ground return

SCL/SO-SI/VPP OTP programming supply. Can be left open in OTP read mode (normal)

4.5 Test Interface

P5.3/TDI

P5.1/TMS

TCK

Input, JTAG test data input

Input, JTAG test mode select

Input, JTAG test clock

P5.2/TDO

Output, JTAG test data output

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IRMCK311

5 Application Connections

Typical application connection is shown in Figure 5. All components necessary to implement a

complete sensorless drive control algorithm are shown connected to IRMCK311.

CPWMUH

XTAL0

XTAL1

CPWMUL

CPWMVH

CPWMVL

CPWMWH

CPWMWL

System

Clock

4 MHz

Crystal

Low Loss

Space

Vector

PWM

PLL

Logic

PLLVDD(1.8V)

PLLVSS

System

clock

Motion

Control

Modules

CGATEKILL

FPWMUH

FPWMUL

FPWMVH

FPWMVL

FPWMWH

FPWMWL

FGATEKILL

P1.2/TXD

P1.1/RXD

To indoor unit

Microcontroller (UART)

UART0

UART1

I²C

Low Loss

Space

Vector

PWM

Dual

Port

Memory

(512B)

&

MCE

Memory

(5.5KB)

P3.7/TXD1

P3.6/RXD1

To other Host (UART)

SDA/CS0

Other communication

(I²C)

SCL/SO-SI

Motion

Control

Sequencer

PFCPWM

PFCGKILL

PFC

PWM

P1.3/SYNC/SCK

P1.4/CAP

0.6V

PORT1

PORT3

Digital I/O

Control

IFBC+

Compressor

DC bus shunt

resistor

IFBC-

IFBCO

IFBF+

S/H

P3.0/INT2/CS1

0.6V

FAN motor

DC bus shunt

resistor

IFBF-

IFBFO

IPFC+

S/H

Timer

RESET

0.6V

RESET

System

Reset

PFC

DC bus shunt

resistor

Watchdog

Timer

IPFC-

IPFCO

VAC+

Local

RAM

(2KB)

AC line

voltage

12bit

A/D

&

VAC-

P2.6/AOPWM0

P2.7/AOPWM1

TCK

VACO

PWM0

PWM1

DC bus

voltage

MUX

AIN0

Analog Output

Program

OTP ROM

(64KB)

AIN1

AREF

Other analog input (0-1.2V)

Optional External Voltage

Reference (0.6V)

CMEXT

System

Clock

P5.3/TDI

P5.1/TMS

JTAG

Interface

Control

P5.2/TDO

AVDD(1.8V)

AVSS

8051

CPU

Clock

divider

SCL/SO-SI/VPP

VDD1

6.75V

3.3V

1.8V

Power

VDD2

VSS

Figure 5. Application Connection of IRMCK311

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IRMCK311

6 DC Characteristics

6.1 Absolute Maximum Ratings

Symbol

V_DD1

Parameter

Supply Voltage

OTP Programming

Voltage

Min

-0.3 V

-0.3V

Typ

Max

3.6 V

1.98 V

7.0V

Condition

-

Respect to VSS

V_DD2

V_PP

V_IA

V_ID

T_A

Analog Input Voltage

Digital Input Voltage

Ambient Temperature

Storage Temperature

-0.3 V

-40 ˚C

-65 ˚C

-

1.98 V

3.65 V

85 ˚C

Respect to AVSS

Respect to VSS

T_S

150 ˚C

Table 1. Absolute Maximum Ratings

Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent

damage to the device. These are stress ratings only and function of the device at these or any

other conditions beyond those indicated in the operational sections of the specifications are not

implied.

6.2 System Clock Frequency and Power Consumption

Symbol

SYSCLK

8051CLK

Parameter

System Clock

8051 Clock

Min

32

-

Typ

-

Max

128

32

Unit

MHz

Table 2. System Clock Frequency

Power Consumption

180

160

140

120

100

80

1.8V

3.3V

60

Total Power

40

20

0

20

40

60

80

100

120

140

MCE Frequency (MHz)

Figure 6. Clock Frequency vs. Power Consumption

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IRMCK311

6.3 Digital I/O DC Characteristics

Symbol

V_DD1

V_DD2

V_PP

Parameter

Min

3.0 V

1.62 V

6.50V

Typ

3.3 V

1.8 V

6.75V

Max

3.6 V

1.98 V

7.0V

Condition

Supply Voltage

OTP Programming

voltage

Recommended

V_IL

V_IH

C_IN

I_L

Input Low Voltage

Input High Voltage

Input capacitance

Input leakage current

Low level output

current

High level output

current

Low level output

current

-0.3 V

2.0 V

-

0.8 V

3.6 V

-

±1 μA

15.2 mA

Recommended

(1)

3.6 pF

±10 nA

13.2 mA

V_O= 3.3 V or 0 V

(2)

I_OL1

8.9 mA

12.4 mA

17.9 mA

24.6 mA

V_OL= 0.4 V

(1)

(2)

I_OH1

24.8 mA

26.3 mA

49.5 mA

38 mA

33.4 mA

81 mA

V_OH= 2.4 V

(1)

(3)

I_OL2

V_OL= 0.4 V

(1)

(3)

I_OH2

High level output

current

V_OH= 2.4 V

(1)

Table 3. Digital I/O DC Characteristics

Note:

(1) Data guaranteed by design.

(2) Applied to SCL/SO-SI, SDA/CS0 pins.

(3) Applied to P1.1/RXD, P1.2/TXD, P1.3/SYNC/SCK, P1.4/CAP, P2.6/AOPWM0,

P2.7/AOPWM1, P3.0/INT2/CS1, P3.2/INT0, P3.6/RXD1, P3.7/TXD1, P5.0/PFCGKILL,

P5.1/TMS, P5.2/TDO, P5.3/TDI, CGATEKILL, FGATEKILL, CPWMUL, CPWMUH,

CPWMVL, CPWMVH, CPWMWL, CPWMWH, FPWMUL, FPWMUH, FPWMVL, FPWMVH,

FPWMWL, FPWMWH, and PFCPWM pins.

6.4 PLL and Oscillator DC Characteristics

Symbol

V_PLLVDD

V_{IL OSC}

Parameter

Min

1.62 V

V_PLLVSS

Typ

1.8 V

-

Max

1.92 V

0.2*

V_PLLVDD

Condition

Recommended

V_PLLVDD= 1.8 V

Supply Voltage

Oscillator Input Low

Voltage

Oscillator Input High

Voltage

(1)

V_{IH OSC}

0.8*

V_PLLVDD

V_PLLVDD= 1.8 V

(1)

Table 4. PLL DC Characteristics

Note:

(1) Data guaranteed by design.

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IRMCK311

6.5 Analog I/O DC Characteristics

- OP amps for current sensing (IFBC+, IFBC-, IFBCO, IFBF+, IFBF-, IFBFO, IPFC+, IPFC-,

IPFCO)

C_AREF= 1nF, C_MEXT= 100nF. Unless specified, Ta = 25˚C.

Symbol

Parameter

Min

1.71 V

-

Typ

1.8 V

-

Max

1.89 V

26 mV

1.2 V

Condition

Recommended

V_AVDD= 1.8 V

Recommended

V_AVDD= 1.8 V

V_AVDD

V_OFFSET

V_I

Supply Voltage

Input Offset Voltage

Input Voltage Range

OP amp output

operating range

Input capacitance

OP amp feedback

resistor

0 V

V_OUTSW

50 mV

-

1.2 V

(1)

C_IN

R_FDBK

-

3.6 pF

-

Requested

between op amp

output and

5 kΩ

20 kΩ

negative input

(1)

OP _GAINCL

CMRR

I_SRC

Operating Close loop

Gain

80 db

-

(1)

Common Mode

Rejection Ratio

Op amp output

source current

Op amp output sink

current

-

80 db

1 mA

100 μA

V_OUT= 0.6 V

(1)

I_SNK

V_OUT= 0.6 V

(1)

Table 5. Analog I/O DC Characteristics

Note: (1) Data guaranteed by design.

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6.6 Under Voltage Lockout DC Characteristics

- Based on AVDD (1.8V)

Unless specified, Ta = 25˚C.

Symbol

Parameter

Min

Typ

Max

Condition

UV_CC+

UVcc positive going

1.53 V

1.66 V

1.71 V

V_DD1= 3.3 V

Threshold¹⁾

UV_CC-

UV_CCH

Note:

UVcc negative going

Threshold

UVcc Hysteresys

1.52 V

1.62 V

1.71 V

V_DD1= 3.3 V

-

40 mV

-

Table 6. UVcc DC Characteristics

1) Data guaranteed by design.

6.7 AREF Characteristics

C_AREF= 1nF, C_MEXT= 100nF. Unless specified, Ta = 25˚C.

Symbol

V_AREF

ΔV_o

Parameter

Min

495 mV

Typ

600 mV

1 mV

Max

700 mV

Condition

V_AVDD= 1.8 V

AREF Output Voltage

Load regulation (V_DC-0.6)

Power Supply Rejection

Ratio

(1)

-

(1)

PSRR

75 db

Table 7. AREF DC Characteristics

Note:

(1) Data guaranteed by design.

Rev 1.0

IRMCK311

7 AC Characteristics

7.1 PLL AC Characteristics

Symbol

F_CLKIN

Parameter

Crystal input

Min

3.2 MHz

Typ

4 MHz

Max

60 MHz

Condition

(1)

frequency

Internal clock

frequency

Sleep mode output F_CLKIN÷ 256

frequency

Short time jitter

Duty cycle

(see figure below)

(1)

F_PLL

32 MHz

50 MHz

-

128 MHz

-

(1)

F_LWPW

(1)

J_S

D

T_LOCK

-

200 psec

50 %

-

PLL lock time

500 μsec

Table 8. PLL AC Characteristics

Note:

(1) Data guaranteed by design.

R₁=1M

R₂=10

Xtal

C₁=30PF

C₂=30PF

Figure 7 Crystal oscillator circuit

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18

IRMCK311

7.2 Analog to Digital Converter AC Characteristics

Unless specified, Ta = 25˚C.

Symbol

T_CONV

T_HOLD

Parameter

Conversion time

Sample/Hold

maximum hold time

Min

-

Typ

-

Max

2.05 μsec

10 μsec

Condition

(1)

Voltage droop ≤

15 LSB

(see figure below)

Table 9. A/D Converter AC Characteristics

Note:

(1) Data guaranteed by design.

Input Voltage

Voltage droop

S/H Voltage

t_SAMPLE

T_HOLD

Figure 8 Voltage droop of sample and hold

7.3 Op Amp AC Characteristics

- OP amps for current sensing (IFBC+, IFBC-, IFBCO, IFBF+, IFBF-, IFBFO, IPFC+, IPFC-,

IPFCO)

Unless specified, Ta = 25˚C.

Symbol

Parameter

Min

Typ

Max

Condition

OP_SR

OP amp slew rate

-

10 V/μsec

-

V_AVDD= 1.8 V, CL

= 33 pF ⁽¹⁾

(1)

OP_IMP

T_SET

OP input impedance

Settling time

-

10⁸Ω

400 ns

-

V_AVDD= 1.8 V, CL

= 33 pF ⁽¹⁾

Table 10. Current Sensing OP Amp AC Characteristics

Note:

(1) Data guaranteed by design.

www.irf.com

19

IRMCK311

7.4 SYNC to SVPWM and A/D Conversion AC Timing

t_wSYNC

SYNC

t_dSYNC1

IU,IV,IW

t_dSYNC2

AINx

t_dSYNC3

PWMUx,PWMVx,PWMWx

Figure 9 SYNC to SVPWM and A/D conversion AC Timing

Unless specified, Ta = 25˚C.

Symbol

t_wSYNC

Parameter

Min

-

Typ

32

-

Max

-

100

Unit

SYSCLK

SYNC pulse width

SYNC to current

feedback conversion

time

SYNC to AIN0-6

analog input

conversion time

SYNC to PWM output

delay time

t_dSYNC1

t_dSYNC2

t_dSYNC3

Note:

-

200

2

SYSCLK

(1)

SYSCLK

Table 11. SYNC AC Characteristics

(1) AIN1 through AIN6 channels are converted once every 6 SYNC events

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20

IRMCK311

7.5 GATEKILL to SVPWM AC Timing

Figure 10 GATEKILL to SVPWM AC Timing

Unless specified, Ta = 25˚C.

Symbol

t_wGK

t_dGK

Parameter

Min

32

-

Typ

-

Max

-

100

Unit

SYSCLK

GATEKILL pulse width

GATEKILL to PWM

output delay

Table 12. GATEKILL to SVPWM AC Timing

7.6 Interrupt AC Timing

Figure 11 Interrupt AC Timing

Unless specified, Ta = 25˚C.

Symbol

Parameter

Min

Typ

Max

Unit

t_wINT

INT0, INT1 Interrupt

Assertion Time

4

-

SYSCLK

t_dINT

INT0, INT1 latency

-

4

SYSCLK

Table 13. Interrupt AC Timing

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21

IRMCK311

7.7 I²C AC Timing

T_I2CLK

SCL

t_I2WSETUP

t_I2WHOLD

t_I2RSETUP

t_I2RHOLD

t_I2EN1

t_I2ST1

t_I2ST2

t_I2EN2

SDA

Figure 12 I²C AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_I2CLK

t_I2ST1

t_I2ST2

t_I2WSETUP

t_I2WHOLD

t_I2RSETUP

t_I2RHOLD

Parameter

Min

10

0.25

Typ

Max

8192

Unit

SYSCLK

T_I2CLK

SYSCLK

I²C clock period

-

I²C SDA start time

I²C SCL start time

I²C write setup time

I²C write hold time

I²C read setup time

I²C read hold time

-

I²C filter time⁽¹⁾

1

Table 14. I²C AC Timing

Note:

(1) I²C read setup time is determined by the programmable filter time applied to I²C

communication.

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22

IRMCK311

7.8 SPI AC Timing

7.8.1 SPI Write AC timing

Figure 13 SPI AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_SPICLK

t_SPICLKHT

t_SPICLKLT

t_CSDELAY

t_WRDELAY

Parameter

SPI clock period

SPI clock high time

SPI clock low time

CS to data delay time

CLK falling edge to data

delay time

Min

4

-

Typ

Max

-

10

Unit

-

1/2

-

SYSCLK

T_SPICLK

nsec

-

nsec

t_CSHIGH

t_CSHOLD

CS high time between two

consecutive byte transfer

CS hold time

1

-

T_SPICLK

1

Table 15. SPI Write AC Timing

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23

IRMCK311

7.8.2 SPI Read AC Timing

Figure 14 SPI Read AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_SPICLK

t_SPICLKHT

t_SPICLKLT

t_CSRD

t_RDSU

t_RDHOLD

t_CSHIGH

Parameter

SPI clock period

SPI clock high time

SPI clock low time

CS to data delay time

SPI read data setup time

SPI read data hold time

CS high time between two

consecutive byte transfer

CS hold time

Min

4

-

10

1

Typ

-

1/2

-

Max

-

10

-

Unit

SYSCLK

T_SPICLK

nsec

T_SPICLK

-

t_CSHOLD

-

1

-

T_SPICLK

Table 16. SPI Read AC Timing

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24

IRMCK311

7.9 UART AC Timing

T_BAUD

TXD

Data and Parity Bit

Stop Bit

Start Bit

RXD

T_UARTFIL

Figure 15 UART AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_BAUD

T_UARTFIL

Parameter

Min

-

Typ

57600

1/16

Max

-

Unit

bit/sec

T_BAUD

Baud Rate Period

UART sampling filter

period ⁽¹⁾

Table 17. UART AC Timing

Note:

(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval

of 1/16 T_BAUD. If three sampled values do not agree, then UART noise error is generated.

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25

IRMCK311

7.10 CAPTURE Input AC Timing

Figure 16 CAPTURE Input AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_CAPCLK

t_CAPHIGH

Parameter

Min

8

4

Typ

-

Max

-

Unit

SYSCLK

CAPTURE input period

CAPTURE input high

time

t_CAPLOW

t_CRDELAY

CAPTURE input low

time

CAPTURE falling edge

to capture register latch

time

4

-

SYSCLK

4

t_CLDELAY

CAPTURE rising edge

to capture register latch

time

CAPTURE input

interrupt latency time

-

4

SYSCLK

t_INTDELAY

Table 18. CAPTURE AC Timing

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26

IRMCK311

7.11 JTAG AC Timing

T_JCLK

t_JLOW

t_JHIGH

TCK

t_CO

TDO

t_JSETUP

t_JHOLD

TDI/TMS

Figure 17 JTAG AC Timing

Unless specified, Ta = 25˚C.

Symbol

T_JCLK

t_JHIGH

t_JLOW

t_CO

Parameter

TCK Period

TCK High Period

TCK Low Period

TCK to TDO propagation

delay time

Min

-

10

0

Typ

Max

50

-

5

Unit

MHz

nsec

-

t_JSETUP

t_JHOLD

TDI/TMS setup time

TDI/TMS hold time

4

0

-

nsec

Table 19. JTAG AC Timing

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27

IRMCK311

7.12 OTP Programming Timing

Figure 18 OTP Programming Timing

Unless specified, Ta = 25˚C.

Symbol

T_VPS

T_VPH

Parameter

VPP Setup Time

VPP Hold Time

Min

10

15

Typ

-

Max

-

Unit

nsec

Table 20. OTP Programming Timing

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28

IRMCK311

8 I/O Structure

The following figure shows the motor PWM and digital I/O structure except the motor PWM output

Figure 19 All digital I/O except motor PWM output

The following figure shows RESET and GATEKILL I/O structure.

Figure 20 RESET, GATEKILL I/O

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29

IRMCK311

The following figure shows the analog input structure.

AVDD

Analog input

6.0V

100

Analog Circuit

6.0V

AVSS

Figure 21 Analog input

The following figure shows all analog operational amplifier output pins and AREF pin I/O structure.

1.8V

Analog output

6.0V

Analog Circuit

6.0V

AVSS

Figure 22 Analog operational amplifier output and AREF I/O structure

The following figure shows the VPP pin I/O structure

Figure 23 VPP programming pin I/O structure

The following figure shows the VSS, AVSS and PLLVSS pin structure

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30

IRMCK311

Figure 24 VSS, AVSS and PLLVSS pin structure

The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure

6.0V

VSS

Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure

The following figure shows the XTAL0 and XTAL1 pins structure

Figure 26 XTAL0/XTAL1 pins structure

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31

IRMCK311

9 Pin List

Number Pin Name

Internal IC Pin

Pull-up

Type Description

/Pull-down

1

2

3

4

5

XTAL0

XTAL1

P1.1/RXD

P1.2/TXD

P1.3/SYNC/

SCK

I

O

I/O

Crystal input

Crystal output

Discrete programmable I/O or UART receive input

Discrete programmable I/O or UART transmit output

Discrete programmable I/O or SYNC output or SPI

clock

6

7

8

9

10

P1.4/CAP

VDD2

VSS

VDD1

FGATEKILL

I/O

P

I

Discrete programmable I/O or Capture Timer input

1.8V digital power

Digital common

3.3V digital power

Fan PWM shutdown input, 2-μsec digital filter,

configurable either high or low true.

Fan PWM gate drive for phase W low side,

configurable either high or low true

Fan PWM gate drive for phase W high side,

configurable either high or low true

Fan PWM gate drive for phase V low side,

configurable either high or low true

Fan PWM gate drive for phase V high side,

configurable either high or low true

Fan PWM gate drive for phase U low side,

configurable either high or low true

Fan PWM gate drive for phase U high side,

configurable either high or low true

Discrete programmable I/O or analog output 0

(PWM)

11

12

13

14

15

16

17

18

FPWMWL

FPWMWH

FPWMVL

FPWMVH

FPWMUL

FPWMUH

70 kΩ Pull up

O

P2.6/

AOPWM0

P2.7/

AOPWM1

VDD2

VSS

I/O

Discrete programmable I/O or analog output 1

(PWM)

1.8V digital power

19

20

21

22

23

24

P

I

O

I

Digital common

IFBF-

Fan single shunt current sensing OP amp input (-)

Fan single shunt current sensing OP amp input (+)

Fan single shunt current sensing OP amp output

Analog input channel 0, 0-1.2V range, needs to be

pulled down to AVSS if unused

IFBF+

IFBFO

AIN0

25

26

27

AVDD

AVSS

AIN1

P

I

1.8V analog power

Analog common

Analog input channel 1, 0-1.2V range, needs to be

pulled down to AVSS if unused

28

29

AREF

CMEXT

O

Analog reference voltage output (0.6V)

Unbuffered analog reference voltage output (0.6V)

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32

IRMCK311

Internal IC Pin

Number Pin Name

Pull-up

Type Description

/Pull-down

30

31

32

IFBC-

IFBC+

IFBCO

I

Compressor single shunt current sensing OP amp

input (-)

Compressor single shunt current sensing OP amp

input (+)

Compressor single shunt current sensing OP amp

output

O

33

34

35

36

37

38

39

40

41

VAC-

VAC+

VACO

IPFCO

IPFC+

IPFC-

VSS

VDD1

CGATEKILL

I

O

I

AC input voltage sensing OP amp input (-)

AC input voltage sensing OP amp input (+)

AC input voltage sensing OP amp output

PFC shunt current sensing OP amp output

PFC shunt current sensing OP amp input (+)

PFC shunt current sensing OP amp input (-)

Digital common

I

P

I

3.3V digital power

Compressor PWM shutdown input, 2-μsec digital

filter, configurable either high or low true.

Compressor PWM gate drive for phase W low side,

configurable either high or low true

Compressor PWM gate drive for phase W high side,

configurable either high or low true

Compressor PWM gate drive for phase V low side,

configurable either high or low true

Compressor PWM gate drive for phase V high side,

configurable either high or low true

Compressor PWM gate drive for phase U low side,

configurable either high or low true

Compressor PWM gate drive for phase U high side,

configurable either high or low true

Discrete programmable I/O or INT2 digital input

Discrete programmable I/O or PFC PWM shutdown

input, 2-μsec digital filter, configurable either high or

low true.

42

43

44

45

46

47

CPWMWL

CPWMWH

CPWMVL

CPWMVH

CPWMUL

CPWMUH

70 kΩ Pull up

O

48

49

P3.0/INT2

P5.0/

PFCGKILL

I/O

I

50

PFCPWM

70 kΩ Pull up

O

PFC PWM gate drive, configurable either high or

low true

51

52

P3.2/INT0

P3.6/RXD1

I/O

Discrete programmable I/O or INT0 input

Discrete programmable I/O or 2^ndUART receive

input

53

P3.7/TXD1

I/O

Discrete programmable I/O or 2^ndUART transmit

output

54

55

VSS

SCL/SO-

SI/VPP

SDA/CS0

P5.1/TMS

P

I/O

P

I/O

Digital common

I²C clock output or SPI data or OTP programming

voltage

56

57

I²C data or SPI chip select 0

Discrete programmable I/O or JTAG test mode

select

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33

IRMCK311

Internal IC Pin

Number Pin Name

Pull-up

Type Description

/Pull-down

58

P5.2/TDO

I/O

Discrete programmable I/O or JTAG port test data

output

59

60

61

62

63

64

P5.3/TDI

TCK

N.C.

RESET

PLLVDD

PLLVSS

I/O

I

-

I/O

P

Discrete programmable I/O or JTAG test data input

JTAG test clock

No connection

Reset , low true, Schmitt trigger input

1.8 V PLL power

PLL ground

Table 21. Pin List

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34

IRMCK311

10 Package Dimensions

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35

IRMCK311

11 Part Marking Information

12 Ordering Information

Lead-Free Part in 64-lead QFP

Moisture sensitivity rating – MSL3

Part number

Order quantities

IRMCK311TY

1600 parts on trays (160 parts per tray) in dry pack

The LQFP-100 is MSL3 qualified

This product has been designed and qualified for the industrial level

Qualification standards can be found at www.irf.com <http://www.irf.com>

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105

Data and specifications subject to change without notice. 12/25/2007

www.irf.com

36


型号：	IRMCK311TY
厂家：	Infineon
描述：	Dual Channel Sensorless Motor Control IC for Appliances 双通道无传感器电机控制IC，适用于家电运动控制电子器件传感器信号电路电机
文件：	总36页 (文件大小：666K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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