IRMCK343 [INFINEON]
Sensorless Motor Control IC for Appliances; 无传感器电机控制IC,适用于家电型号: | IRMCK343 |
厂家: | Infineon |
描述: | Sensorless Motor Control IC for Appliances |
文件: | 总35页 (文件大小:654K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet No. PD60336
IRMCK343
Sensorless Motor Control IC for Appliances
Features
Product Summary
MCETM (Motion Control Engine) - Hardware based
computation engine for high efficiency sinusoidal
sensorless control of permanent magnet AC motor
Integrated Power Factor Correction control
Supports both interior and surface permanent
magnet motors
Maximum crystal frequency
60 MHz
Maximum internal clock (SYSCLK) frequency 128 MHz
Maximum 8051 clock frequency
Sensorless control computation time
MCETM computation data range
8051 OTP Program memory
MCE program and Data RAM
GateKill latency (digital filtered)
PWM carrier frequency counter
A/D input channels
33 MHz
11 μsec typ
16 bit signed
56K bytes
8K bytes
2 μsec
Built-in hardware peripheral for single shunt
current feedback reconstruction
No external current or voltage sensing operational
amplifier required
Three/two-phase Space Vector PWM
Three-channel analog output (PWM)
Embedded 8-bit high speed microcontroller (8051)
for flexible I/O and man-machine control
JTAG programming port for emulation/debugger
Serial communication interface (UART)
I2C/SPI serial interface
Watchdog timer with independent analog clock
Three general purpose timers/counters
Two special timers: periodic timer, capture timer
16 bits/ SYSCLK
5
A/D converter resolution
12 bits
A/D converter conversion speed
8051 instruction execution speed
Analog output (PWM) resolution
UART baud rate (typ)
2 μsec
2 SYSCLK
8 bits
57.6K bps
23
Number of I/O (max)
Package (lead-free)
QFP64
Internal ‘One-Time Programmable’ (OTP) memory
and internal RAM for final production usage
Operating temperature
-40°C ~ 85°C
Pin compatible with IRMCK343, RAM version
1.8V/3.3V CMOS
Description
IRMCK343 is a high performance OTP based motion control IC designed primarily for appliance applications. IRMCK343 is
designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control.
IRMCK343 contains two computation engines. One is Motion Control Engine (MCETM) for sensorless control of permanent
magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one
monolithic chip. The MCETM contains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle
estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by
connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as the
Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital circuit
and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle
instruction execution (60MIPS at 120MHz). The MCE and 8051 microcontroller are connected via dual port RAM to process
signal monitoring and command input. An advanced graphic compiler for the MCETM is seamlessly integrated into the
MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments.
IRMCK343 comes with a small QFP64 pin lead-free package.
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.
© 2007 International Rectifier
IRMCK343
TABLE OF CONTENTS
1
2
3
4
Overview....................................................................................................................................5
IRMCK343 Block Diagram and Main Functions.........................................................................6
Pinout.........................................................................................................................................8
Input/Output of IRMCK343.........................................................................................................9
4.1 8051 Peripheral Interface Group.........................................................................................9
4.2 Motion Peripheral Interface Group ....................................................................................10
4.3 Analog Interface Group .....................................................................................................11
4.4 Power Interface Group ......................................................................................................11
4.5 Test Interface Group .........................................................................................................11
Application Connections ..........................................................................................................12
DC Characteristics...................................................................................................................13
6.1 Absolute Maximum Ratings...............................................................................................13
6.2 System Clock Frequency and Power Consumption..........................................................13
6.3 Digital I/O DC Characteristics............................................................................................14
6.4 PLL and Oscillator DC Characteristics..............................................................................14
6.5 Analog I/O DC Characteristics ..........................................................................................15
6.6 Under Voltage Lockout DC Characteristics.......................................................................16
6.7 AREF Characteristics........................................................................................................16
AC Characteristics ...................................................................................................................17
7.1 PLL AC Characteristics .....................................................................................................17
7.2 Analog to Digital Converter AC Characteristics.................................................................18
7.3 Op Amp AC Characteristics ..............................................................................................18
7.4 SYNC to SVPWM and A/D Conversion AC Timing...........................................................19
7.5 GATEKILL to SVPWM AC Timing.....................................................................................20
7.6 Interrupt AC Timing ...........................................................................................................20
7.7 I2C AC Timing....................................................................................................................21
7.8 SPI AC Timing...................................................................................................................22
7.8.1 SPI Write AC timing....................................................................................................22
7.8.2 SPI Read AC Timing...................................................................................................23
7.9 UART AC Timing...............................................................................................................24
5
6
7
7.10
7.11
7.12
CAPTURE Input AC Timing ...........................................................................................25
JTAG AC Timing ............................................................................................................26
OTP Programming Timing .............................................................................................27
8
9
10
11
12
I/O Structure.............................................................................................................................28
Pin List .....................................................................................................................................31
Package Dimensions............................................................................................................34
Part Marking Information ......................................................................................................35
Order Information .................................................................................................................35
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IRMCK343
TABLE OF FIGURES
Figure 1 Typical Application Block Diagram Using IRMCK343......................................................5
Figure 2. IRMCK343 Internal Block Diagram.................................................................................6
Figure 3. IRMCK343 Pin Configuration..........................................................................................8
Figure 4. Input/Output of IRMCK343 .............................................................................................9
Figure 5. Application Connection of IRMCK343 ..........................................................................12
Figure 6. Clock Frequency vs. Power Consumption....................................................................13
Figure 7 Crystal oscillator circuit..................................................................................................17
Figure 8 Voltage droop of sample and hold.................................................................................18
Figure 9 SYNC to SVPWM and A/D Conversion AC Timing .......................................................19
Figure 10 GATEKILL to SVPWM AC Timing ...............................................................................20
Figure 11 Interrupt AC Timing .....................................................................................................20
Figure 12
I2C AC Timing ............................................................................................................21
Figure 13 SPI write AC Timing.....................................................................................................22
Figure 14 SPI read AC Timing.....................................................................................................23
Figure 15 UART AC Timing .........................................................................................................24
Figure 16 CAPTURE Input AC Timing.........................................................................................25
Figure 17 JTAG AC Timing..........................................................................................................26
Figure 18 OTP Programming Timing...........................................................................................27
Figure 19 All digital I/O and motor PWM output .............................................................................28
Figure 20 RESET, GATEKILL I/O ..................................................................................................28
Figure 21 Analog input ...................................................................................................................29
Figure 22 Analog operational amplifier output and AREF I/O structure.......................................29
Figure 23 VPP programming pin.................................................................................................29
Figure 24 VSS, AVSS and PLLVSS pin structure ..........................................................................30
Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure ...........................................................30
Figure 26 XTAL0/XTAL1 pins structure .......................................................................................30
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IRMCK343
TABLE OF TABLES
Table 1. Absolute Maximum Ratings ...........................................................................................13
Table 2. System Clock Frequency...............................................................................................13
Table 3. Digital I/O DC Characteristics........................................................................................14
Table 4. PLL DC Characteristics .................................................................................................14
Table 5. Analog I/O DC Characteristics.......................................................................................15
Table 6. UVcc DC Characteristics ...............................................................................................16
Table 7. AREF DC Characteristics ..............................................................................................16
Table 8. PLL AC Characteristics..................................................................................................17
Table 9. A/D Converter AC Characteristics .................................................................................18
Table 10. Current Sensing OP amp Amp AC Characteristics......................................................18
Table 11. SYNC AC Characteristics ............................................................................................19
Table 12. GATEKILL to SVPWM AC Timing ...............................................................................20
Table 13. Interrupt AC Timing......................................................................................................20
Table 14. I2C AC Timing ..............................................................................................................21
Table 15. SPI Write AC Timing....................................................................................................22
Table 16. SPI Read AC Timing....................................................................................................23
Table 17. UART AC Timing .........................................................................................................24
Table 18. CAPTURE AC Timing..................................................................................................25
Table 19. JTAG AC Timing..........................................................................................................26
Table 20. OTP Programming Timing ...........................................................................................27
Table 21. Pin List.........................................................................................................................33
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IRMCK343
1 Overview
IRMCK343 is a new International Rectifier integrated circuit device primarily designed as a one-
chip solution for complete inverter controlled appliance motor control applications. Unlike a
traditional microcontroller or DSP, the IRMCK343 provides a built-in closed loop sensorless
control algorithm using the unique Motion Control Engine (MCETM) for permanent magnet motor.
The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion
control sequencer and dual port RAM to map internal signal nodes. IRMCK343 also employs a
unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and
enables a direct shunt resistor interface to the IC. Motion control programming is achieved using
a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment.
Sequencing, user interface, host communication, and upper layer control tasks can be
implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped
with a JTAG port to facilitate emulation and debugging tools.
Figure 1 shows a typical application schematic using the IRMCK343.
IRMCK343 is intended for volume production purpose and contains 64K bytes of OTP (One Time
Programming) ROM, which can be programmed through a JTAG port. For a development
purpose use, IRMCF343 contains a 48k byte of RAM in place of program OTP to facilitate an
application development work. Both IRMCF343 and IRMCK343 come in the same 64-pin QFP
package with identical pin configuration to facilitate PC board layout and transition to mass
production
Figure 1 Typical Application Block Diagram Using IRMCK343
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IRMCK343
2 IRMCK343 Block Diagram and Main Functions
IRMCK343 block diagram is shown in Figure 2.
Figure 2. IRMCK343 Internal Block Diagram
IRMCK343 contains the following functions for sensorless AC motor control applications:
•
Motion Control Engine (MCETM)
o Proportional plus Integral block
o Low pass filter
o Differentiator and lag (high pass filter)
o Ramp
o Limit
o Angle estimate (sensorless control)
o Inverse Clark transformation
o Vector rotator
o Bit latch
o Peak detect
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IRMCK343
o Transition
o Multiply-divide (signed and unsigned)
o Divide (signed and unsigned)
o Adder
o Subtractor
o Comparator
o Counter
o Accumulator
o Switch
o Shift
o ATAN (arc tangent)
o Function block (any curve fitting, nonlinear function)
o 16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE)
o MCETM program and data memory (6K byte). Note 1
o MCETM control sequencer
•
8051 microcontroller
o Three 16-bit timer/counters
o 16-bit periodic timer
o 16-bit analog watchdog timer
o 16-bit capture timer
o Up to 23 discrete I/Os
o Five-channel 12-bit A/D
Three buffered channels (0 – 1.2V input)
Two unbuffered channels (0 – 1.2V input)
o JTAG port (4 pins)
o Up to three channels of analog output (8-bit PWM)
o UART
o I2C/SPI port
o 64K byte program OTP
o 2K byte data RAM. Note 1
Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051
data. Different sizes can be allocated depending on applications.
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IRMCK343
3 Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
XTAL0
P3.0/INT2/CS1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
XTAL1
P1.0/T2
P1.1/RXD
P1.2/TXD
P1.3/SYNC/SCK
P1.4/CAP
P1.5
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
GATEKILL
VDD1
3
4
5
6
7
8
P1.6
9
P1.7
VSS
10
11
12
13
14
15
16
(Top View)
VDD2
IPFC-
VSS
IPFC+
VDD1
IPFCO
VACO
P2.0/NMI
P2.1
VAC-
P2.2
VAC+
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. IRMCK343 Pin Configuration
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IRMCK343
4 Input/Output of IRMCK343
All I/O signals of IRMCK343 are shown in Figure 4. All I/O pins are 3.3V logic interface except
A/D interface pins.
XTAL0
Crystal
XTAL1
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
GATEKILL
P1.2/TXD
P1.1/RXD
Motor PWM
gate signal
Interface
RS232C
Interface
Other communication
SDA/CS0
SCL/SO-SI/VPP
P3.0/INT2/CS1
P1.3/SYNC/SCK
(SPI&I2C)
&
OTP Programming
PFC PWM
gate signal
Interface
PWMWL
GATEKILL
P1.0/T2
P1.4/CAP
P1.5
AREF
CMEXT
IPFC+
IPFC-
IPFCO
IFB+
P1.6
P1.7
Discrete I/O
P2.0/NMI
P2.1
P2.2
IRMCK343
P2.3
IFB-
P2.4
IFBCO
VAC+
VAC-
A/D Interface
P2.5
P3.2/NINT0
VACO
AIN0
P2.6/AOPWM0
P2.7/AOPWM1
P3.1/AOPWM2
D/A Interface
(PWM output)
AIN1
AVDD
AVSS
Analog power/
ground
RESET
System Reset
JTAG port
P5.1/TMS
P5.2/TDO
P5.3/TDI
TCK
VDD1
VDD2
VSS
Digital power/
ground
PLLVDD
PLLVSS
PLL power/
ground
Test mode
TSTMOD
Figure 4. Input/Output of IRMCK343
4.1 8051 Peripheral Interface Group
UART Interface
P1.2/TXD
P1.1/RXD
Output, Transmit data from IRMCK343
Input, Receive data to IRMCK343
Discrete I/O Interface
P1.0/T2
Input/output port 1.0, can be configured as Timer/Counter 2 input
P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock
P1.4/CAP
P1.5
Input/output port 1.4, can be configured as Capture Timer input
Input/output port 1.5
P1.6
Input/output port 1.6
P1.7
Input/output port 1.7
P2.0/NMI
P2.1
Input/output port 2.0, can be configured as Non-maskable interrupt input
Input/output port 2.1
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IRMCK343
P2.2
P2.3
P2.4
P2.5
Input/output port 2.2
Input/output port 2.3
Input/output port 2.4
Input/output port 2.5
P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select
1
P3.2/INT0
Input/output port 3.2, can be configured as INT0 input
Analog Output Interface
P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with
programmable carrier frequency
P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with
programmable carrier frequency
P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with
programmable carrier frequency
Crystal Interface
XTAL0
XTAL1
Input, connected to crystal
Output, connected to crystal
Reset Interface
RESET
Input/output, system reset, needs to be pulled up to VDD1 but doesn’t
require external RC time constant
I2C/SPI Interface/OTP Programming
SCL/SO-SI/VPP Output or Power, I2C clock output or SPI data or OTP Programming
SDA/CS0
Input/output, I2C data line or SPI chip select 0
P3.0/INT2/CS1 Input/output, INT2 or SPI chip select 1
P1.3/SYNC/SCK Input/output, SYNC output or SPI clock, needs to be pulled up to VDD1
in order to boot from I2C EEPROM
4.2 Motion Peripheral Interface Group
PWM
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
PFCPWM
Output, PWM phase U high side gate signal
Output, PWM phase U low side gate signal
Output, PWM phase V high side gate signal
Output, PWM phase V low side gate signal
Output, PWM phase W high side gate signal
Output, PWM phase W low side gate signal
Output, PFC PWM gate signal
Fault
GATEKILL
Input, upon assertion, this negates all six PWM signals, programmable
logic sense
P5.0/PFCGKILL Input, upon assertion, this negates PFCPWM signal, programmable logic
sense, can be configured as discrete I/O in which case CGATEKILL
negates PFCPWM
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IRMCK343
4.3 Analog Interface Group
AVDD
AVSS
Analog power (1.8V)
Analog power return
CMEXT
Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be
connected.
AREF
IFB+
0.6V buffered output
Input, Operational amplifier positive input for shunt resistor current
sensing
IFB-
Input, Operational amplifier negative input for shunt resistor current
sensing
IFBO
IPFC+
IPFC-
IPFO
VAC+
VAC-
VACO
AIN0
Output, Operational amplifier output for shunt resistor current sensing
Input, Operational amplifier positive input for PFC current sensing
Input, Operational amplifier negative input for PFC current sensing
Output, Operational amplifier output for PFC current sensing
Input, Operational amplifier positive input for PFC AC voltage sensing
Input, Operational amplifier negative input for PFC AC voltage sensing
Output, Operational amplifier output for PFC AC voltage sensing
Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus
voltage input
AIN1
Input, analog input channel 1 (0 – 1.2V), needs to be pulled down to
AVSS if unused
4.4 Power Interface Group
VDD1
Digital power for I/O (3.3V)
VDD2
VSS
Digital power for core logic (1.8V)
Digital common
PLLVDD
PLLVSS
PLL power (1.8V)
PLL ground return
4.5 Test Interface Group
TSTMOD
P5.3/TDI
P5.1/TMS
TCK
Must be tied to VSS, used only for factory testing.
Input, JTAG test data input
Input, JTAG test mode select
Input, JTAG test clock
P5.2/TDO
Output, JTAG test data output
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IRMCK343
5 Application Connections
Typical application connection is shown in Figure 5. All components necessary to implement a
complete sensorless drive control algorithm are shown connected to IRMCK343.
Figure 5. Application Connection of IRMCK343
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IRMCK343
6 DC Characteristics
6.1 Absolute Maximum Ratings
Symbol
VDD1
VDD2
VIA
Parameter
Supply Voltage
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Ambient Temperature
Storage Temperature
Min
Typ
Max
3.6 V
1.98 V
1.98 V
3.65 V
85 ˚C
Condition
-0.3 V
-0.3 V
-0.3 V
-0.3 V
-40 ˚C
-65 ˚C
-
-
-
-
-
-
Respect to VSS
Respect to VSS
Respect to AVSS
Respect to VSS
VID
TA
TS
150 ˚C
Table 1. Absolute Maximum Ratings
Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only and function of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications are not
implied.
6.2 System Clock Frequency and Power Consumption
Symbol
SYSCLK
8051CLK
Parameter
System Clock
8051 Clock
Min
32
-
Typ
-
-
Max
128
32
Unit
MHz
MHz
Table 2. System Clock Frequency
Power Consumption
180
160
140
120
100
80
1.8V
3.3V
60
Total Power
40
20
0
0
20
40
60
80
100
120
140
MCEFrequency (MHz)
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IRMCK343
6.3 Digital I/O DC Characteristics
Symbol
VDD1
Parameter
Supply Voltage
Supply Voltage
Input Low Voltage
Input High Voltage
Input capacitance
Input leakage current
Low level output
current
High level output
current
Low level output
current
Min
3.0 V
1.62 V
-0.3 V
2.0 V
-
Typ
3.3 V
1.8 V
-
Max
3.6 V
1.98 V
0.8 V
3.6 V
-
Condition
Recommended
Recommended
Recommended
VDD2
VIL
VIH
CIN
IL
Recommended
(1)
3.6 pF
±10 nA
13.2 mA
±1 μA
15.2 mA
VO = 3.3 V or 0 V
VOL = 0.4 V
(2)
IOL1
8.9 mA
12.4 mA
17.9 mA
24.6 mA
(1)
(2)
IOH1
24.8 mA
26.3 mA
49.5 mA
38 mA
33.4 mA
81 mA
VOH = 2.4 V
(1)
(3)
IOL2
VOL = 0.4 V
(1)
(3)
IOH2
High level output
current
VOH = 2.4 V
(1)
Table 3. Digital I/O DC Characteristics
Note:
(1) Data guaranteed by design.
(2) Applied to SCL/SO-SI, SDA/CS0 pins.
(3) Applied to P1.0/T2, P1.1/RXD, P1.2/TXD, P1.3/SYNC/SCK, P1.4/CAP, P1.5, P1.6, P1.7,
P2.0/NMI, P2.1, P2.2, P2.3, P2.4, P2.5, P2.6/AOPWM0, P2.7/AOPWM1, P3.0/INT2/CS1,
P3.1/AOPWM2, P3.2/INT0, P5.0/PFCGKILL, P5.1/TMS, P5.2/TDO, P5.3/TDI, GATEKILL,
PWMUL, PWMUH, PWMVL, PWMVH, PWMWL, PWMWH, and PFCPWM pins.
6.4 PLL and Oscillator DC Characteristics
Symbol
VPLLVDD
VIL OSC
Parameter
Supply Voltage
Oscillator Input Low
Voltage
Min
1.62 V
VPLLVSS
Typ
1.8 V
-
Max
1.92 V
0.2*
Condition
Recommended
VPLLVDD = 1.8 V
(1)
VPLLVDD
VIH OSC
Oscillator Input High
Voltage
0.8*
VPLLVDD
VPLLVDD
VPLLVDD = 1.8 V
(1)
Table 4. PLL DC Characteristics
Note:
(1) Data guaranteed by design.
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IRMCK343
6.5 Analog I/O DC Characteristics
- OP amps for current sensing (IFB+, IFB-, IFBO, IPFC+, IPFC-, IPFCO)
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
Parameter
Supply Voltage
Input Offset Voltage
Input Voltage Range
OP amp output
operating range
Input capacitance
OP amp feedback
resistor
Min
1.71 V
-
Typ
1.8 V
-
Max
1.89 V
26 mV
1.2 V
Condition
VAVDD
VOFFSET
VI
Recommended
VAVDD = 1.8 V
Recommended
VAVDD = 1.8 V
0 V
VOUTSW
50 mV
-
1.2 V
(1)
(1)
CIN
RFDBK
-
3.6 pF
-
-
Requested
between op amp
output and
5 kΩ
20 kΩ
negative input
(1)
OP GAINCL
CMRR
ISRC
Operating Close loop
Gain
80 db
-
-
-
-
-
(1)
Common Mode
Rejection Ratio
Op amp output
source current
Op amp output sink
current
-
-
-
80 db
1 mA
100 μA
VOUT = 0.6 V
(1)
ISNK
VOUT = 0.6 V
(1)
Table 5. Analog I/O DC Characteristics
Note:
(1) Data guaranteed by design.
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6.6 Under Voltage Lockout DC Characteristics
- Based on AVDD (1.8V)
Unless specified, Ta = 25˚C.
Symbol
UVCC+
Parameter
UVcc positive going
Threshold1)
Min
1.53 V
Typ
1.66 V
Max
1.71 V
Condition
VDD1 = 3.3 V
UVCC-
UVcc negative going
Threshold
1.52 V
1.62 V
1.71 V
VDD1 = 3.3 V
UVCCH
UVcc Hysteresys
-
40 mV
-
Table 6. UVcc DC Characteristics
Note:
(1) Data guaranteed by design.
6.7 AREF Characteristics
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
VAREF
ΔVo
Parameter
AREF Output Voltage
Load regulation (VDC-0.6)
Power Supply Rejection
Ratio
Min
495 mV
Typ
600 mV
1 mV
Max
700 mV
Condition
VAVDD = 1.8 V
(1)
-
-
-
-
(1)
PSRR
75 db
Table 7. AREF DC Characteristics
Note:
(1) Data guaranteed by design.
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IRMCK343
7 AC Characteristics
7.1 PLL AC Characteristics
Symbol
FCLKIN
Parameter
Crystal input
frequency
Internal clock
frequency
Sleep mode output FCLKIN ÷ 256
frequency
Short time jitter
Duty cycle
Min
3.2 MHz
Typ
4 MHz
Max
60 MHz
Condition
(1)
(see figure below)
(1)
FPLL
32 MHz
50 MHz
-
128 MHz
-
(1)
FLWPW
(1)
(1)
(1)
JS
D
TLOCK
-
-
-
200 psec
50 %
-
-
-
PLL lock time
500 μsec
Table 8. PLL AC Characteristics
Note:
(1) Data guaranteed by design.
R1=1M
R2=10
Xtal
C1=30PF
C2=30PF
Figure 7 Crystal oscillator circuit
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© 2007 International Rectifier
17
IRMCK343
7.2 Analog to Digital Converter AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
TCONV
THOLD
Parameter
Conversion time
Sample/Hold
Min
-
-
Typ
-
-
Max
2.05 μsec
10 μsec
Condition
(1)
Voltage droop ≤
15 LSB
maximum hold time
(see figure below)
Table 9. A/D Converter AC Characteristics
Note:
(1) Data guaranteed by design.
Input Voltage
Voltage droop
S/H Voltage
tSAMPLE
THOLD
Figure 8 Voltage droop of sample and hold
7.3 Op Amp AC Characteristics
- OP amps for current sensing (IFB+, IFB-, IFBO, IPFC+, IPFC-, IPFCO)
Unless specified, Ta = 25˚C.
Symbol
OPSR
Parameter
OP amp slew rate
Min
-
Typ
10 V/μsec
Max
-
Condition
VAVDD = 1.8 V, CL
= 33 pF (1)
(1)
OPIMP
TSET
OP input impedance
Settling time
-
-
108 Ω
400 ns
-
-
VAVDD = 1.8 V, CL
= 33 pF (1)
Table 10. Current Sensing OP amp Amp AC Characteristics
Note:
(1) Data guaranteed by design.
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© 2007 International Rectifier
18
IRMCK343
7.4 SYNC to SVPWM and A/D Conversion AC Timing
twSYNC
SYNC
tdSYNC1
IU,IV,IW
tdSYNC2
AINx
tdSYNC3
PWMUx,PWMVx,PWMWx
Figure 9 SYNC to SVPWM and A/D Conversion AC Timing
Unless specified, Ta = 25˚C.
Symbol
twSYNC
Parameter
SYNC pulse width
SYNC to current
feedback conversion
time
SYNC to AIN0-6
analog input
conversion time
SYNC to PWM output
delay time
Min
-
-
Typ
32
-
Max
-
100
Unit
SYSCLK
SYSCLK
tdSYNC1
tdSYNC2
tdSYNC3
-
-
-
-
200
2
SYSCLK
(1)
SYSCLK
Table 11. SYNC AC Characteristics
Note:
(1) AIN1 through AIN6 channels are converted once every 6 SYNC events
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19
IRMCK343
7.5 GATEKILL to SVPWM AC Timing
Figure 10 GATEKILL to SVPWM AC Timing
Unless specified, Ta = 25˚C.
Symbol
twGK
tdGK
Parameter
GATEKILL pulse width
GATEKILL to PWM
output delay
Min
32
-
Typ
-
-
Max
-
100
Unit
SYSCLK
SYSCLK
Table 12. GATEKILL to SVPWM AC Timing
7.6 Interrupt AC Timing
Figure 11 Interrupt AC Timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
Unit
twINT
INT0, INT1 Interrupt
Assertion Time
INT0, INT1 latency
4
-
-
SYSCLK
tdINT
-
-
4
SYSCLK
Table 13. Interrupt AC Timing
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© 2007 International Rectifier
20
IRMCK343
7.7 I2C AC Timing
TI2CLK
TI2CLK
SCL
tI2WSETUP
tI2WHOLD
tI2RSETUP
tI2RHOLD
tI2EN1
tI2ST1
tI2ST2
tI2EN2
SDA
Figure 12
I2C AC Timing
Unless specified, Ta = 25˚C.
Symbol
TI2CLK
tI2ST1
Parameter
Min
10
0.25
0.25
0.25
0.25
Typ
Max
8192
Unit
SYSCLK
TI2CLK
TI2CLK
TI2CLK
TI2CLK
SYSCLK
SYSCLK
I2C clock period
-
-
-
-
-
-
-
I2C SDA start time
I2C SCL start time
I2C write setup time
I2C write hold time
I2C read setup time
I2C read hold time
-
-
-
-
-
-
tI2ST2
tI2WSETUP
tI2WHOLD
tI2RSETUP
tI2RHOLD
I2C filter time(1)
1
Table 14. I2C AC Timing
Note:
(1) I2C read setup time is determined by the programmable filter time applied to I2C
communication.
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© 2007 International Rectifier
21
IRMCK343
7.8 SPI AC Timing
7.8.1 SPI Write AC timing
Figure 13 SPI write AC Timing
Unless specified, Ta = 25˚C.
Symbol
TSPICLK
tSPICLKHT
tSPICLKLT
tCSDELAY
tWRDELAY
Parameter
SPI clock period
SPI clock high time
SPI clock low time
CS to data delay time
CLK falling edge to data
delay time
Min
4
-
-
-
Typ
Max
-
-
-
10
10
Unit
-
1/2
1/2
-
SYSCLK
TSPICLK
TSPICLK
nsec
-
-
nsec
tCSHIGH
tCSHOLD
CS high time between two
consecutive byte transfer
CS hold time
1
-
-
-
-
TSPICLK
TSPICLK
1
Table 15. SPI Write AC Timing
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© 2007 International Rectifier
22
IRMCK343
7.8.2 SPI Read AC Timing
Figure 14 SPI read AC Timing
Unless specified, Ta = 25˚C.
Symbol
TSPICLK
tSPICLKHT
tSPICLKLT
tCSRD
tRDSU
tRDHOLD
tCSHIGH
Parameter
SPI clock period
SPI clock high time
Min
4
-
-
-
10
10
1
Typ
-
1/2
1/2
-
-
-
-
Max
-
-
-
10
-
Unit
SYSCLK
TSPICLK
TSPICLK
nsec
nsec
nsec
TSPICLK
SPI clock low time
CS to data delay time
SPI read data setup time
SPI read data hold time
CS high time between two
consecutive byte transfer
CS hold time
-
-
tCSHOLD
-
1
-
TSPICLK
Table 16. SPI Read AC Timing
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© 2007 International Rectifier
23
IRMCK343
7.9 UART AC Timing
TBAUD
TXD
Data and Parity Bit
Stop Bit
Start Bit
RXD
TUARTFIL
Figure 15 UART AC Timing
Unless specified, Ta = 25˚C.
Symbol
TBAUD
TUARTFIL
Parameter
Baud Rate Period
UART sampling filter
period (1)
Min
-
-
Typ
57600
1/16
Max
-
-
Unit
bit/sec
TBAUD
Table 17. UART AC Timing
Note:
(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval
of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated.
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© 2007 International Rectifier
24
IRMCK343
7.10 CAPTURE Input AC Timing
Figure 16 CAPTURE Input AC Timing
Unless specified, Ta = 25˚C.
Symbol Parameter
TCAPCLK
Min
8
4
Typ
-
-
Max
-
-
Unit
SYSCLK
SYSCLK
SYSCLK
SYSCLK
CAPTURE input period
CAPTURE input high
time
tCAPHIGH
tCAPLOW
tCRDELAY
CAPTURE input low
time
CAPTURE falling edge
to capture register latch
time
4
-
-
-
-
4
tCLDELAY
CAPTURE rising edge
to capture register latch
time
CAPTURE input
interrupt latency time
-
-
-
-
4
4
SYSCLK
SYSCLK
tINTDELAY
Table 18. CAPTURE AC Timing
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© 2007 International Rectifier
25
IRMCK343
7.11 JTAG AC Timing
TJCLK
tJLOW
tJHIGH
TCK
tCO
TDO
tJSETUP
tJHOLD
TDI/TMS
Figure 17 JTAG AC Timing
Unless specified, Ta = 25˚C.
Symbol
TJCLK
tJHIGH
tJLOW
tCO
Parameter
TCK Period
TCK High Period
TCK Low Period
TCK to TDO propagation
delay time
Min
-
10
10
0
Typ
Max
50
-
-
5
Unit
MHz
nsec
nsec
nsec
-
-
-
-
tJSETUP
tJHOLD
TDI/TMS setup time
TDI/TMS hold time
4
0
-
-
-
-
nsec
nsec
Table 19. JTAG AC Timing
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© 2007 International Rectifier
26
7.12 OTP Programming Timing
Figure 18 OTP Programming Timing
Unless specified, Ta = 25˚C.
Symbol Parameter
TVPS
Min
10
15
Typ
-
-
Max
-
-
Unit
nsec
nsec
VPP Setup Time
VPP Hold Time
TVPH
Table 20. OTP Programming Timing
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.
© 2007 International Rectifier
IRMCK343
8 I/O Structure
The following figure shows the motor PWM and digital I/O structure
VDD1
(3.3V)
Internal digital circuit
Low true logic
70k
6.0V
PIN
100
6.0V
VSS
Figure 19 All digital I/O and motor PWM output
The following figure shows RESET and GATEKILL I/O structure.
VDD1
(3.3V)
RESET
GATEKILL
70k
I/O
6.0V
PIN
100
6.0V
VSS
Figure 20 RESET, GATEKILL I/O
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28
IRMCK343
The following figure shows the analog input structure.
AVDD
Analog input
6.0V
PIN
100
Analog Circuit
6.0V
AVSS
Figure 21 Analog input
The following figure shows all analog operational amplifier output pins and AREF pin I/O structure.
1.8V
Analog output
6.0V
PIN
Analog Circuit
6.0V
AVSS
Figure 22 Analog operational amplifier output and AREF I/O structure
The following figure shows the VPP pin I/O structure
VPP input
PIN
100
Analog Circuit
8.0V
VSS
Figure 23 VPP programming pin
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© 2007 International Rectifier
29
IRMCK343
The following figure shows the VSS, AVSS and PLLVSS pin structure
Figure 24 VSS, AVSS and PLLVSS pin structure
The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure
Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure
The following figure shows the XTAL0 and XTAL1 pins structure
VDD1
6.0V
PIN
6.0V
VSS
Figure 26 XTAL0/XTAL1 pins structure
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© 2007 International Rectifier
30
IRMCK343
9 Pin List
Pin
Internal IC
Pull-up
Pin
Number Pin Name
Type Description
/Pull-down
1
2
3
XTAL0
XTAL1
P1.0/T2
I
O
I/O
Crystal input
Crystal output
Discrete programmable I/O or Timer/Counter 2
input
4
5
6
7
P1.1/RXD
P1.2/TXD
I/O
I/O
I/O
I/O
Discrete programmable I/O or UART receive
input
Discrete programmable I/O or UART transmit
output
Discrete programmable I/O or SYNC output or
SPI clock
Discrete programmable I/O or Capture Timer
input
P1.3/SYNC/
SCK
P1.4/CAP
8
9
P1.5
P1.6
P1.7
VDD2
VSS
I/O
I/O
I/O
P
P
P
Discrete programmable I/O
Discrete programmable I/O
Discrete programmable I/O
1.8V digital power
Digital common
3.3V digital power
10
11
12
13
14
VDD1
P2.0/NMI
I/O
Discrete programmable I/O or Non-maskable
Interrupt input
15
16
17
18
19
20
P2.1
P2.2
P2.3
P2.4
I/O
I/O
I/O
I/O
I/O
I/O
Discrete programmable I/O
Discrete programmable I/O
Discrete programmable I/O
Discrete programmable I/O
Discrete programmable I/O
Discrete programmable I/O or PWM 0 output
P2.5
P2.6/
AOPWM0
P2.7/
AOPWM1
VDD2
VSS
21
I/O
Discrete programmable I/O or PWM 1 output
22
23
24
P
P
I
1.8V digital power
Digital common
Analog input channel 0, 0-1.2V range, needs to
be pulled down to AVSS if unused
1.8V analog power
AIN0
25
26
27
AVDD
AVSS
AIN1
P
P
I
Analog common
Analog input channel 1, 0-1.2V range, needs to
be pulled down to AVSS if unused
Unbuffered 0.6V output. Capacitor needs to be
connected.
28
CMEXT
O
29
30
31
AREF
IFB-
IFB+
O
I
I
Analog reference voltage output (0.6V)
Single shunt current sensing OP amp input (-)
Single shunt current sensing OP amp input (+)
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© 2007 International Rectifier
31
IRMCK343
Pin
Internal IC
Pull-up
Pin
Number Pin Name
Type Description
/Pull-down
32
33
34
35
36
37
38
39
40
41
IFBO
VAC+
VAC-
VACO
IFPCO
IFPC+
IFPC-
VSS
O
I
I
O
O
I
Single shunt current sensing OP amp output
AC input voltage sensing OP amp input (+)
AC input voltage sensing OP amp input (-)
AC input voltage sensing OP amp output
PFC shunt current sensing OP amp output
PFC shunt current sensing OP amp input (+)
PFC shunt current sensing OP amp input (-)
Digital common
I
P
P
I
VDD1
GATEKILL
3.3V digital power
PWM shutdown input, 2-μsec digital filter,
configurable either high or low true.
PWM gate drive for phase W low side,
configurable either high or low true
PWM gate drive for phase W high side,
configurable either high or low true
PWM gate drive for phase V low side,
configurable either high or low true
PWM gate drive for phase V high side,
configurable either high or low true
PWM gate drive for phase U low side,
configurable either high or low true
PWM gate drive for phase U high side,
configurable either high or low true
Discrete programmable I/O or external interrupt 2
input or SPI chip select 1
42
43
44
45
46
47
48
49
PWMWL
PWMWH
PWMVL
PWMVH
PWMUL
PWMUH
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
O
O
O
O
O
O
P3.0/INT2/
CS1
P5.0/
I/O
I/O
Discrete programmable I/O or PFC PWM
shutdown input, 2-μsec digital filter, configurable
either high or low true.
PFCGKILL
50
51
PFCPWM
P3.1/
AOPWM2
P3.2/INT0
VSS
VDD1
SCL/
SO-SI/VPP
SDA/CS0
O
I/O
PFC PWM output
Discrete programmable I/O or PWM analog
output 2
Discrete programmable I/O or Interrupt 0 input
Digital common
52
53
54
55
I/O
P
P
I/O
P
I/O
3.3V digital power
I2C clock output (open drain, need pull up) or SPI
data or OTP Programming
56
57
58
59
60
I2C data (open drain, need pull up) or SPI chip
select 0
P5.1/TMS
P5.2/TDO
P5.3/TDI
TCK
I/O
I/O
I/O
I
Discrete programmable I/O or JTAG test mode
select
Discrete programmable I/O or JTAG test data
output
Discrete programmable I/O or JTAG test data
input
JTAG test clock
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© 2007 International Rectifier
32
IRMCK343
Pin
Internal IC
Pull-up
Pin
Number Pin Name
Type Description
/Pull-down
58 kΩ pull
down
61
TSTMOD
I
Test mode. Must be tied to VSS. Factory use
only
62
63
64
RESET
PLLVDD
PLLVSS
I/O
P
P
Reset, low true, Schmitt trigger input
1.8V PLL power
PLL ground
Table 21. Pin List
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© 2007 International Rectifier
33
IRMCK343
10 Package Dimensions
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© 2007 International Rectifier
34
IRMCK343
11 Part Marking Information
12 Order Information
Lead-Free Part in 64-lead QFP
Moisture Sensitivity Rating – MSL3
Part number
IRMCK343TR
IRMCK343TY
Order quantities
1500 parts on tape and reel in dry pack
1600 parts on trays (160 parts per tray) in dry pack
The LQFP-64 is MSL3 qualified
This product has been designed and qualified for the industrial level
Qualification standards can be found at www.irf.com <http://www.irf.com>
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/25/2007
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© 2007 International Rectifier
35
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