IRU3013CQ [INFINEON]
VRM 8.5 COMPATIBLE 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC WITH TRIPLE LDO CONTROLLER; VRM 8.5兼容5位可编程同步降压控制器三重LDO控制器IC
| 型号： | IRU3013CQ |
| 厂家： | 
Infineon |
| 描述： | VRM 8.5 COMPATIBLE 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC WITH TRIPLE LDO CONTROLLER |
| 文件： | 总6页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD94249
IRU3013
VRM 8.5 COMPATIBLE
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK
CONTROLLER IC WITH TRIPLE LDO CONTROLLER
DESCRIPTION
FEATURES
Meets Latest VRM 8.5 Specification
The IRU3013 controller IC is specifically designed for
Provides Single Chip Solution for Vcore, 1.2V AGTL+, Intel Pentium III microprocessor applications as de-
scribed in the VRM 8.5 specification. The IC provides
1.8V and VDDQ
On-Board 5-Bit DAC and Decoder programs the out- a single chip solution for the Vcore, 1.2V AGTL+,
put voltage from 1.050V to 1.825V
Loss-less Short Circuit Protection
1.8V and a third uncommitted LDO controller that
can be used either as 1.2V power good detector or
Synchronous operation allows maximum efficiency to provide 1.5V AGP bus in applications that this
Patented architecture allows fixed frequency opera- voltage is required. The IRU3013 features a patented
tion as well as 100% duty cycle when operating with topology that, in combination with a few external com-
a changing load
ponents, (*Note: See application current in figure 3) will
provide in excess of 30A of output current for an on-
board Vcore synchronous converter while automatically
Minimum Part Count, No External Compensation
Soft-Start
High current totem pole driver for directly driving an providing the output voltage specified in VRM 8.5 speci-
external Power MOSFET
Power Good Function
fication. The IRU3013 also features, loss-less current
sensing by using the RDS(ON) of the high side Power
MOSFET as the sensing resistor, a Power Good win-
dow comparator that switches its open collector output
low when the output is outside of a ±10% window. Other
features of the device are: Under-voltage lockout for both
5V and 12V supplies, an external programmable soft-
start function, and the ability to program the oscillator
frequency by connecting an external capacitor.
APPLICATIONS
Pentium III with VRM 8.5 Specification
DC to DC Converters
VRM 8.5 VID
5V
TYPICAL APPLICATION
3.3V
LINEAR
CONTROL
SWITCHER
V
OUT
1
V
OUT
2
CONTROL
IRU3013
LINEAR
LINEAR
V
OUT
3
V
OUT
4
CONTROL
CONTROL
Figure 1 - Typical application of IRU3013.
Note: Pentium III is trade mark of Intel Corp.
PACKAGE ORDER INFORMATION
TA (°C)
0 To 70
0 To 70
DEVICE
PACKAGE
IRU3013CW
IRU3013CQ
24-Pin Plastic SOIC WB
24-Pin Plastic QSOP
Rev. 1.2
09/06/01
1
IRU3013
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage .................................................... 10V
V12 Supply Voltage .................................................. 20V
All Other Pins .......................................................... 7V
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range ..................... 0°C To 125°C
PACKAGE INFORMATION
24-PIN WIDE BODY PLASTIC SOIC (W)
24-PIN PLASTIC QSOP (Q)
TOP VIEW
TOP VIEW
Ct
1
2
24 Lin2
23 D0
Ct
1
2
24 Lin2
23
22
D0
D1
Lin1
VFB1
VFB2
V5
Lin1
VFB1
VFB2
V5
3
22
3
D1
4
21 D2
20 D3
19 D25
4
21 D2
20 D3
19 D25
5
5
OVP
6
OVP
6
7
18
7
18
VFB3
VFB3
17 SS
16
PGd
CS-
PGd
CS-
8
17 SS
8
9
16 Lin4
15 VFB4
14 V12
13 LDrv
9
Lin4
CS+
HDrv
PGnd
Gnd
CS+
HDrv
PGnd
Gnd
10
11
12
10
11
12
15 VFB4
14 V12
13 LDrv
θJA =80°C/W
θJA =88°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70°C. Typical values refer
to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
VID Section
DAC Output Voltage (Note 1)
DAC Output Line Regulation
0.98Vs
Vs
1.02Vs
V
4.5<Vcc<5.5
10.5<V12<13V
0.2
0.5
%
%
V
DAC Output Temp Variation
VID Input LO
0.4
2
VID Input HI
V
VID Input Internal Pull-up
Resistor to 5V
27
KΩ
Power Good Section
Under-Voltage Lower Trip Point
Under-Voltage Upper Trip Point
UV Hysteresis
Over-Voltage Upper Trip Point
Over-Voltage Lower Trip Point
OV Hysterises
VOUT Ramping Down
VOUT Ramping Up
0.90Vs
0.92Vs
0.02Vs
1.10Vs
1.08Vs
0.02Vs
0.3
V
V
V
V
V
V
V
V
VOUT Ramping Up
VOUT Ramping Down
Power Good Output LO
Power Good Output HI
Soft-Start Section
RL = 3mA
RL = 5K Pull-Up to 5V
4.95
Soft-Start Current
CS+ = 0V, CS- = 5V
10
µA
Rev. 1.2
09/06/01
2
IRU3013
PARAMETER
SYM
TEST CONDITION
Supply Ramping Up
Supply Ramping Up
MIN
TYP
MAX
UNITS
UVLO Section
UVLO Threshold - 12V
UVLO Hysteresis - 12V
UVLO Threshold - 5V
UVLO Hysteresis - 5V
Error Comparator Section
Input Offset Voltage
9
0.5
4
V
V
V
V
0.3
-2
+2
mV
ns
Delay to Output
VDIFF = 10mV
100
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
120
-5
150
200
+5
2
µA
mV
%
Css = 0.1µF
Supply Current Section
Operating Supply Current
CL = 3000pF
V5
20
14
V12
mA
Output Drivers Section
Rise Time
CL = 3000pF
CL = 3000pF
CL = 3000pF
70
70
100
130
ns
ns
ns
Fall Time
Dead Band Time
Oscillator Section
Osc Frequency
200
Ct = 150pF
220
V5
KHz
V
Osc Valley
0.2
2
Osc Peak
V
LDO Controller Section
VFB1 and VFB2 (Pins 3 and 4)
VFB4 (Pin 15)
1.200
0.800
V
Input Bias Current
Lin 1, 2, 3 Drive Current
OVP Section
µA
mA
30
OVP Threshold
1.17Vs
5
V
OVP Source Current
mA
Note: Vs refers to the set point voltage given in table 1.
D25
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
D25
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
0
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.050
1.100
1.150
2.200
2.250
1.325
1.375
1.425
1.475
1.525
1.575
1.625
1.675
1.725
1.775
1.825
1.075
1.125
1.175
1.225
1.275
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 1 - Set point voltage vs. VID codes.
Rev. 1.2
09/06/01
3
IRU3013
PIN DESCRIPTIONS
PIN# PIN SYMBOL
PIN DESCRIPTION
1
Ct
This pin programs the oscillator frequency in the range of 50 KHz to 500KHz by means of
an external capacitor connected from this pin to the ground.
2
3
4
5
6
Lin1
VFB1
VFB2
V5
Controls the gate of an external MOSFET for the AGTL+ linear regulator or 1.8V supply.
This pin provides the feedback for the linear regulator that its output drive is Lin1 pin.
This pin provides the feedback for the linear regulator that its output drive is Lin2 pin.
5V supply voltage.
OVP
This pin provides an over voltage flag when the feedback pin VFB3 voltage exceeds 17%(Typi-
cal) of the set point for the Vcore output.
7
PGd
This pin is an open collector output that switches LO when the output of the converter is
not within ±10% (typ) of the nominal output voltage. When PGd pin switches LO the
output saturation voltage is less than 0.4V at 3mA.
8
9
CS-
This pin is connected to the Source of the power MOSFET for the Core supply and it is
the negative input for the internal current sensing circuitry.
CS+
This pin is connected to the Drain of the power MOSFET of the Core supply. It provides the
positive sensing input for the internal current sensing circuitry. An external resistor pro-
grams the CS threshold depending on the RDS of the power MOSFET. An external capaci-
tor is placed in parallel with the programming resistor to provide high frequency noise
filtering.
10
11
HDrv
Output driver for the high side power MOSFET.
PGnd
This is the power ground pin and must be connected directly to the gnd plane close to the
source of the synchronous MOSFET. A high frequency capacitor (typically 1µF) must be
connected from V12 pin to this pin for noise free operation.
12
Gnd
This pin must be connected directly to the ground plane. A high frequency capacitor (0.1
to 1µF) must be connected from V5 and V12 pins to this pin for noise free operation.
Output driver for the power MOSFET, which is used as a synchronous switched rectifier.
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (0.1 to 1µF) must be connected directly from this pin
to Gnd pin in order to supply large instantaneous current pulses to the power MOSFET
during the transitions.
13
14
LDrv
V12
15
16
VFB4
Lin4
This pin provides the feedback for the linear regulator that its output drive is Lin4 pin.
This pin controls the gate of an external MOSFET for either the AGP Bus linear regulator
or can be used as Power good detector for 1.2V AGTL+ bus.
17
SS
This pin provides the soft-start for the switching regulator. An internal current source
charges an external capacitor that is connected from this pin to the ground which ramps
up the outputs of the switching regulator, preventing the outputs from overshooting as well
as limiting the inrush current. The second function of the Soft-Start cap is to provide long
off time (HICCUP) for the synchronous MOSFET during current limiting.
This pin is connected directly to the output of the Core supply to provide feedback to the
Error comparator.
18
19
20
21
22
23
24
VFB3
D25
D3
This pin programs the output voltage in 25mV steps based on the VID table. 40K internal
pull-up to Vcc.
MSB input to the DAC that programs the output voltage. This pin can be pulled-up exter-
nally by a 10K resistor to either 3.3V or 5V supply. 40K internal pull-up to Vcc.
Input to the DAC that programs the output voltage. This pin can be pulled-up externally by
a 10K resistor to either 3.3V or 5V supply. 40K internal pull-up to Vcc.
Input to the DAC that programs the output voltage. This pin can be pulled-up externally by
a 10KΩ resistor to either 3.3V or 5V supply. 40K internal pull-up to Vcc.
LSB input to the DAC that programs the output voltage. This pin can be pulled-up exter-
nally by a 10K resistor to either 3.3V or 5V supply. 40K internal pull-up to Vcc.
Controls the gate of an external MOSFET for the AGTL+ linear regulator or 1.8V supply.
D2
D1
D0
Lin2
Rev. 1.2
09/06/01
4
IRU3013
BLOCK DIAGRAM
18
V 3
FB
Enable
V12
V12
Vset
Enable
10
11
HDrv
14
V12
UVLO
PWM
5
V5
PGnd
+
Control
Vset
13
Slope
Comp
LDrv
23
22
21
20
19
Enable
D0
D1
Osc
5Bit
DAC,
Ctrl
8
9
CS-
D2
Over
Current
Soft
Start &
Fault
CS+
Logic
D3
200uA
D25
Logic
Enable
1
Ct
3
2
V 1
FB
17
SS
1.17Vset
Lin1
6
OVP
1.2V
0.8V
24
4
Lin2
1.1Vset
FB
V 2
7
PGd
Gnd
16
15
12
Lin4
FB
V 4
0.9Vset
Figure 2 - Simplified block diagram of the IRU3013.
Rev. 1.2
09/06/01
5
IRU3013
TYPICAL APPLICATION
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.2
09/06/01
6
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