IRU3038CSTR [INFINEON]
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| 型号： | IRU3038CSTR |
| 厂家： | 
Infineon |
| 描述： | 暂无描述 控制器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD94250
IRU3038
SYNCHRONOUS PWM CONTROLLER
FOR TERMINATION POWER SUPPLY APPLICATIONS
PRELIMINARY DATA SHEET
FEATURES
DESCRIPTION
Synchronous Controller in 14-Pin Package
Operating with single 5V or 12V supply voltage
200KHz to 400KHz operation set by an external
resistor
The IRU3038 controller IC is designed to provide a low
cost synchronous Buck regulator for voltage tracking
applications such DDR memory and general purpose
on-board DC to DC converter. Modern micro processors
combined with DDR memory, need high-speed bandwidth
data bus which requires a particular bus termination volt-
age. This voltage will be tightly regulated to track the
half of chipset voltage for best performance. The IRU3038
together with dual N-channel MOSFETs such as IRF7313,
provide a low cost solution for such applications. This
device features a programmable frequency set from
200KHz to 400KHz, under-voltage lockout for both Vcc
and Vc supplies, an external programmable soft-start
function as well as output under-voltage detection that
latches off the device when an output short is detected.
Soft-Start Function
Fixed Frequency Voltage Mode
500mA Peak Output Drive Capability
Uncommitted Error Amplifier available for DDR
voltage tracking application
1.25V Reference Voltage
Protects the output when control FET is shorted
APPLICATIONS
DDR memory source sink Vtt application
Low cost on-board DC to DC such as
5V to 3.3V, 2.5V or 1.8V
Graphic Card
Hard Disk Drive
TYPICAL APPLICATION
5V
12V
L1
VDDQ
(2.5V)
1uH
C1
0.1uF
C2
1uF
C4
47uF
C3
10TPB100M,
100uF, 55m
Ω
Vcc
Vc
R1
1K
DDR
Memory
VREF
Q1
1/2 of IRF7313
HDrv
VP
D1
BAT54
or1N4148
L2
R2
1K
SS
U1
IRU3038
Vtt
1.25V @ 3A
C6
2x 6TPB150M,
D03316P-103, 10uH, 3.9A
1/2 of IRF7313
C5
Q2
0.1uF
LDrv
PGnd
150uF, 55m
Ω
Rt
Comp
C7
2200pF
Fb
Gnd
R3
33K
Figure 1 - Typical application of IRU3038 when Vtt tracks the VDDQ.
PACKAGE ORDER INFORMATION
TA (°C)
0 To 70
0 To 70
DEVICE
IRU3038CF
IRU3038CS
PACKAGE
14-Pin Plastic TSSOP (F)
14-Pin Plastic SOIC NB (S)
Rev. 2.0
09/12/02
www.irf.com
1
IRU3038
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage .................................................. 25V
Vc Supply Voltage ..................................................... 30V (not rated for inductive load)
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C
PACKAGE INFORMATION
14-PIN PLASTIC TSSOP (F)
14-PIN PLASTIC SOIC (S)
Fb 1
14 NC
13 SS
14
13
12
11
10
9
Fb 1
NC
V
P
2
3
VP
2
3
SS
V
REF
12 Comp
11 Rt
VREF
Comp
Rt
Vcc 4
NC 5
Vcc 4
10 Vc
5
6
Vc
NC
LDrv 6
Gnd 7
9 HDrv
8 PGnd
LDrv
HDrv
PGnd
7
8
Gnd
θJA=888C/W
θJA=1008C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, Vc=12V and TA=0 to 70°C. Typical values refer
to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Reference Voltage
VREF Voltage
VFB
1.225
1.250
0.2
1.275
0.35
V
LREG
Fb Voltage Line Regulation
UVLO
5<Vcc<12
%
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - Vc
UVLO Hysteresis - Vc
UVLO Threshold - Fb
UVLO Hysteresis - Fb
Supply Current
UVLO Vcc Supply Ramping Up
UVLO Vc Supply Ramping Up
4
4.2
0.25
3.3
0.2
0.6
0.1
4.4
3.5
0.8
V
V
V
V
V
V
3.1
0.4
UVLO Fb
Fb Ramping Down
Dyn Icc
Dyn Ic
ICCQ
Vcc Dynamic Supply Current
Vc Dynamic Supply Current
Vcc Static Supply Current
Vc Static Supply Current
Soft-Start Section
Charge Current
Freq=200KHz, CL=1500pF
Freq=200KHz, CL=1500pF
SS=0V
2
2
1
5
7
3.5
1
8
10
6
mA
mA
mA
mA
ICQ
SS=0V
0.5
4.5
SSIB
SS=0V
-10
-20
-30
µA
Rev. 2.0
09/12/02
www.irf.com
2
IRU3038
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Error Amp
Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
VP Voltage Range
Transconductance
Oscillator
SS=3V, Fb=1V
SS=0V, Fb=1V
-0.1
-64
µA
µA
V
IFB1
IFB2
1.5
0.8
450
600
µmho
gm
750
Frequency
Freq Rt=Open
Rt=Gnd
200
400
1.25
220
440
1.275
KHz
V
180
360
1.225
Ramp Amplitude
Output Drivers
Rise Time
VRAMP
CLOAD=1500pF
50
50
150
90
0
ns
ns
ns
%
%
Tr
Tf
100
100
250
95
Fall Time
CLOAD=1500pF
Dead Band Time
Max Duty Cycle
Min Duty Cycle
TDB
TON
50
85
0
Fb=1V, Freq=200KHz
TOFF Fb=1.5V
PIN DESCRIPTIONS
PIN#
PIN SYMBOL
PIN DESCRIPTION
1
Fb
This pin is connected directly to the output of the switching regulator via resistor divider to
provide feedback to the Error amplifier.
2
3
4
VP
VREF
Vcc
Non-inverting input of error amplifier.
Reference Voltage.
This pin provides biasing for the internal blocks of the IC as well as power for the low side
driver. A minimum of 1µF, high frequency capacitor must be connected from this pin to
ground to provide peak drive current capability.
5
14
6
NC
No Connection.
LDrv
Gnd
Output driver for the synchronous power MOSFET.
Analog ground for internal reference and control circuitry. Connect to PGnd with a short
trace.
7
8
9
PGnd
HDrv
Vc
This pin serves as the separate ground for MOSFET's drivers and should be connected to
system's ground plane. A high frequency capacitor (0.1 to 1µF) must be connected from
Vcc and Vc pins to this pin for noise free operation.
Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148,
from this pin to ground for the application when the inductor current goes negative (Source/
Sink), soft-start at no load and for the fast load transient from full load to no load.
This pin is connected to a voltage that must be at least 4V higher than the bus voltage of
the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A
minimum of 1µF, high frequency capacitor must be connected from this pin to ground to
provide peak drive current capability.
10
11
Rt
The switching frequency can be Programmed between 200KHz and 400KHz by connect-
ing a resistor between Rt and Gnd. Floating the pin set the switching frequency to 200KHz
and grounding the pin set the switching frequency to 400KHz.
12
13
Comp
SS
Compensation pin of the error amplifier. An external resistor and capacitor network is
typically connected from this pin to ground to provide loop compensation.
This pin provides soft-start for the switching regulator. An internal current source charges
an external capacitor that is connected from this pin to ground which ramps up the output
of the switching regulator, preventing it from overshooting as well as limiting the input
current. The converter can be shutdown by pulling this pin below 0.5V.
Rev. 2.0
09/12/02
www.irf.com
3
IRU3038
BLOCK DIAGRAM
Vcc
3V
Bias
Generator
1.25V
0.25V
V
REF 3
1.25V
P O R
4V
Vc
3V
0.2V
11 Rt
10 Vc
20uA
3.5V
SS 13
64uA Max
Rt
Ct
Oscillator
9
HDrv
S
R
P O R
Q
Error Comp
Error Amp
25K
25K
4
6
Vcc
V
P
2
1
Reset Dom
LDrv
Fb
FbLo Comp
0.6V
Comp 12
8
7
PGnd
Gnd
P O R
Figure 2 - Simplified block diagram of the IRU3038.
THEORY OF OPERATION
Introduction
threshold (3.3V and 4.2V respectively) and generates
The IRU3038 is a fixed frequency, voltage mode syn- the Power On Reset (POR) signal. Soft-start function
chronous controller and consists of a precision refer- operates by sourcing an internal current to charge an
ence voltage, an uncommitted error amplifier, an internal external capacitor to about 3V. Initially, the soft-start func-
oscillator, a PWM comparator, 0.5A peak gate driver, tion clamps the E/A’s output of the PWM converter. As
soft-start and shutdown circuits (see Block Diagram).
the charging voltage of the external capacitor ramps up,
the PWM signals increase from zero to the point the
The output voltage of the synchronous converter is set feedback loop takes control.
and controlled by the output of the error amplifier; this is
the amplified error signal from the sensed output voltage Short-Circuit Protection
and the voltage on non-inverting input of error amplifier(VP). The outputs are protected against the short-circuit. The
This voltage is compared to a fixed frequency linear IRU3038 protects the circuit for shorted output by sens-
sawtooth ramp and generates fixed frequency pulses of ing the output voltage (through the external resistor di-
variable duty-cycle, which drives the two N-channel ex- vider). The IRU3038 shuts down the PWM signals, when
ternal MOSFETs.
the output voltage drops below 0.6V.
The timing of the IC is provided through an internal oscil- The IRU3038 also protects the output from over-voltaging
lator circuit which uses on-chip capacitor. The oscilla- when the control FET is shorted. This is done by turning
tion frequency is programmable between 200 to 400KHz on the sync FET with the maximum duty cycle.
by using an external resistor. Figure 12 shows switch-
ing frequency vs. external resistor (Rt).
Under-Voltage Lockout
The under-voltage lockout circuit assures that the
MOSFET driver outputs remain in the off state whenever
Soft-Start
The IRU3038 has a programmable soft-start to control the supply voltage drops below set parameters. Lockout
the output voltage rise and limit the current surge at the occurs if Vc and Vcc fall below 3.3V and 4.2V respec-
start-up. To ensure correct start-up, the soft-start se- tively. Normal operation resumes once Vc and Vcc rise
quence initiates when the Vc and Vcc rise above their above the set values.
Rev. 2.0
09/12/02
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4
IRU3038
APPLICATION INFORMATION
Design Example:
Soft-Start Programming
The following example is a typical application for IRU3038, The soft-start timing can be programmed by selecting
the schematic is Figure 11 on page 12.
the soft-start capacitance value. The start-up time of the
converter can be calculated by using:
VIN = 5V
VOUT = 2.5V
IOUT = 8A
∆VOUT = 100mV
fS = 200KHz
t
START = 75×Css (ms)
---(2)
Where CSS is the soft-start capacitor (µF)
For a start-up time of 7.5ms, the soft-start capacitor will
Output Voltage Programming
be 0.1µF. Choose a ceramic capacitor at 0.1µF.
Output voltage is programmed by reference voltage and
external voltage divider. The Fb pin is the inverting input Shutdown
of the error amplifier, which is referenced to the voltage The converter can be shutdown by pulling the soft-start
on non-inverting pin of error amplifier. For this applica- pin below 0.5V. The control MOSFET turns off and the
tion, this pin (VP) is connected to reference voltage (VREF). synchronous MOSFET turns on during shutdown.
The output voltage is defined by using the following equa-
tion:
Boost Supply Vc
R6
R5
To drive the high-side switch it is necessary to supply a
gate voltage at least 4V greater than the bus voltage.
This is achieved by using a charge pump configuration
as shown in Figure 11. The capacitor is charged up to
VOUT = VP × 1 +
---(1)
( )
VP = VREF = 1.25V
When an external resistor divider is connected to the approximately twice the bus voltage. A capacitor in the
output as shown in Figure 3.
range of 0.1µF to 1µF is generally adequate for most
applications. In application, when a separate voltage
source is available the boost circuit can be avoided as
shown in Figure 1.
V
OUT
IRU3038
R
6
Input Capacitor Selection
VREF
Fb
The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The
ripple current generated during the on time of control
MOSFET should be provided by input capacitor. The RMS
value of this ripple is expressed by:
R
5
VP
Figure 3 - Typical application of the IRU3038 for
programming the output voltage.
IRMS = IOUT
D×(1-D)
---(3)
Equation (1) can be rewritten as:
Where:
D is the Duty Cycle, D=VOUT/VIN.
IRMS is the RMS value of the input capacitor current.
IOUT is the output current for each channel.
VOUT
R6 = R5 ×
- 1
( VP )
Choose R5 = 1KΩ
This will result toR6 = 1KΩ
For VIN=5V, IOUT=8A and D=0.5, the IRMS=4A
For higher efficiency, a low ESR capacitor is recom-
If the high value feedback resistors are used, the input mended. Choose two Poscap from Sanyo 10TPB100ML
bias current of the Fb pin could cause a slight increase (10V, 100µF, 55mΩ) with a maximum allowable ripple
in output voltage. The output voltage set point can be current of 1.9A.
more accurate by using precision resistor.
Rev. 2.0
09/12/02
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5
IRU3038
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
If ∆i = 30%(IO), then the output inductor will be:
L = 2.6µH
(ESR). In general, the output capacitor must have low The Coilcraft DO5022HC series provides a range of in-
enough ESR to meet output ripple and load transient ductors in different values, low profile suitable for large
requirements, yet have high enough ESR to satisfy sta- currents, 3.3µH, 10A is a good choice for this applica-
bility requirements. The ESR of the output capacitor is tion. This will result to a ripple approximately 26.5% of
calculated by the following relationship:
output current.
∆VO
∆IO
ESR ≤
---(4)
Power MOSFET Selection
The IRU3038 uses two N-Channel MOSFETs. The se-
lections criteria to meet power transfer requirements is
based on maximum drain-source voltage (VDSS), gate-
source drive voltage (VGS), maximum output current, On-
resistance RDS(ON) and thermal management.
Where:
∆VO = Output Voltage Ripple
∆IO = Output Current
∆VO=100mV and ∆IO=4A
This results to: ESR=25mΩ
The Sanyo TPC series, Poscap capacitor is a good choice. The MOSFET must have a maximum operating voltage
The 6TPC150M 150µF, 6.3V has an ESR 40mΩ. Se- (VDSS) exceeding the maximum input voltage (VIN).
lecting two of these capacitors in parallel, results to an
ESR of @ 20mΩ which achieves our low ESR goal.
The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistor can be used and cau-
The capacitor value must be high enough to absorb the tion should be taken with devices at very low VGS to pre-
inductor's ripple current. The larger the value of capaci- vent undesired turn-on of the complementary MOSFET,
tor, the lower will be the output ripple voltage.
which results a shoot-through current.
Inductor Selection
The total power dissipation for MOSFETs includes con-
The inductor is selected based on output power, operat- duction and switching losses. For the Buck converter,
ing frequency and efficiency requirements. Low inductor the average inductor current is equal to the DC load cur-
value causes large ripple current, resulting in the smaller rent. The conduction loss is defined as:
size, but poor efficiency and high output noise. Gener-
2
PCOND (Upper Switch) = ILOAD × RDS(ON) × D × ϑ
ally, the selection of inductor value can be reduced to
desired maximum ripple current in the inductor (Di). The
optimum point is usually found between 20% and 50%
ripple of the output current.
2
PCOND (Lower Switch) = ILOAD × RDS(ON) × (1 - D) × ϑ
ϑ = RDS(ON) Temperature Dependency
For the buck converter, the inductor value for desired
operating ripple current can be determined using the fol- The RDS(ON) temperature dependency should be consid-
lowing relation:
ered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
∆i
∆t
1
fS
VOUT
VIN
VIN - VOUT = L×
; ∆t = D×
; D =
VOUT
L = (VIN - VOUT)×
---(5)
VIN×∆i×fS
Choose IRF7460 for both control MOSFET and synchro-
nous MOSFET. This device provides low on-resistance
in a compact SOIC 8-Pin package.
Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage
Di = Inductor Ripple Current
fS = Switching Frequency
Dt = Turn On Time
D = Duty Cycle
Rev. 2.0
09/12/02
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6
IRU3038
The MOSFET has the following data:
Feedback Compensation
The IRU3038 is a voltage mode controller; the control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast transient
response and accurate output regulation, a compensa-
tion circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 458).
IRF7460
VDSS = 20V
ID = 10A @ 758C
RDS(ON) = 10mΩ @ VGS=10V
ϑ = 1.8 for 1508C (Junction Temperature)
The total conduction losses will be:
PCON(TOTAL) = 1.152W
The switching loss is more difficult to calculate, even The output LC filter introduces a double pole, –40dB/
though the switching transition is well understood. The decade gain slope above its corner resonant frequency,
reason is the effect of the parasitic components and and a total phase lag of 1808 (see Figure 5). The Reso-
switching times during the switching procedures such nant frequency of the LC filter is expressed as follows:
as turn-on / turnoff delays and rise and fall times. With a
1
linear approximation, the total switching loss can be ex-
pressed as:
FLC =
---(7)
2π× LO×CO
VDS(OFF)
tr + tf
PSW =
×
× ILOAD
---(6)
Figure 5 shows gain and phase of the LC filter. Since we
already have 1808 phase shift just from the output filter,
the system risks being unstable.
T
2
Where:
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
Gain
0dB
Phase
T = Switching Period
08
ILOAD = Load Current
-40dB/decade
The switching time waveform is shown in Figure 4.
DS
V
-180
8
90%
FLC Frequency
FLC Frequency
Figure 5 - Gain and phase of LC filter.
The IRU3038’s error amplifier is a differential-input
transconductance amplifier. The output is available for
DC gain control or AC phase compensation.
10%
VGS
t
d
(ON)
td(OFF)
tr
tf
The E/A can be compensated with or without the use of
local feedback. When operated without local feedback,
the transconductance properties of the E/A become evi-
dent and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
from Comp pin to ground as shown in Figure 6.
Figure 4 - Switching time waveforms.
From IRF7460 data sheet we obtain:
tr = 6.9ns
tf = 4.3ns
These values are taken under a certain condition test.
For more detail please refer to the IRF7460 data sheet.
By using equation (6), we can calculate the total switch-
ing losses.
PSW(TOTAL) = 44.8mW
Rev. 2.0
09/12/02
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7
IRU3038
Note that this method requires that the output capacitor
should have enough ESR to satisfy stability requirements.
In general, the output capacitor’s ESR generates a zero
typically at 5KHz to 50KHz which is essential for an
acceptable phase margin.
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R6 = Resistor Dividers for Output Voltage
Programming
The ESR zero of the output capacitor expressed as fol-
lows:
gm = Error Amplifier Transconductance
1
FESR =
---(8)
2π×ESR×Co
For:
VIN = 5V
VOUT
VOSC = 1.25V
Fo = 30KHz
FESR = 26.5KHz
FLC = 5KHz
R5 = 1K
R6 = 1K
gm = 600µmho
R
6
Fb
Comp
Ve
E/A
R5
C9
Vp=VREF
R4
This results to R4=26.52KΩ. Choose R4=26.1KΩ
Gain(dB)
To cancel one of the LC filter poles, place the zero be-
fore the LC filter resonant frequency pole:
H(s) dB
FZ @ 75%FLC
Frequency
F
Z
1
FZ @ 0.75 ×
---(13)
Figure 6 - Compensation network without local
feedback and its asymptotic gain plot.
2π LO × CO
For:
Lo = 10µH
Co = 300µF
FZ = 3.8KHz
R4 = 26.1KΩ
The transfer function (Ve / VOUT) is given by:
R5
1 + sR4C9
sC9
H(s) = gm×
×
---(9)
(
)
R6 + R5
Using equations (11) and (13) to calculate C9, we get:
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:
C9 @ 1800pF
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to suppress the switching noise. The additional
pole is given by:
R5
R6 × R5
|H(s)| = gm ×
× R4
---(10)
1
FZ =
---(11)
1
2π × R4 × C9
FP =
C9 × CPOLE
2π × R4 ×
The gain is determined by the voltage divider and E/A's
transconductance gain.
C9 + CPOLE
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
First select the desired zero-crossover frequency (Fo):
Fo > FESR and FO ≤ (1/5 ~ 1/10)× fS
1
1
CPOLE =
@
π × R4 × fS
1
C9
Use the following equation to calculate R4:
π × R4 × fS -
1
VOSC
VIN
Fo×FESR
R5 + R6
R5
fS
2
R4 =
×
×
×
---(12)
for FP <<
2
FLC
gm
Rev. 2.0
09/12/02
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8
IRU3038
For a general solution for unconditionally stability for
ceramic capacitor with very low ESR and any type of
output capacitors, in a wide range of ESR values we
should implement local feedback with a compensation
network. The typically used compensation network for
voltage-mode controller is shown in Figure 7.
FP1 = 0
FP2 =
1
2π×R8×C10
1
1
FP3 =
@
2π×R7×C12
C12×C11
(C12+C11 )
2π×R7×
VOUT
ZIN
C12
1
FZ1 =
FZ2 =
2π×R7×C11
C10
R7
C11
1
1
@
R8
R6
Zf
2π×C10×(R6 + R8)
2π×C10×R6
Cross Over Frequency:
Fb
Ve
E/A
VIN
FO = R7×C10×
VOSC
1
Comp
R5
---(15)
×
2π×Lo×Co
Vp=VREF
Where:
Gain(dB)
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
H(s) dB
Co = Total Output Capacitors
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (14) regarding transconduc-
tance error amplifier.
Frequency
F
Z
1
F
Z
2
F
P
2
FP3
Figure 7 - Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
1) Select the crossover frequency:
1 - gmZf
1 + gmZIN
Ve
VOUT
=
Fo < FESR and Fo ≤ (1/10 ~ 1/6)× fS
2
The error amplifier gain is independent of the transcon- 2) Select R7, so that R7 >>
ductance under the following condition:
gm
3) Place first zero before LC’s resonant frequency pole.
gmZf >> 1
and
gmZIN >>1
---(14)
FZ1 @ 75% FLC
By replacing ZIN and Zf according to Figure 7, the trans-
former function can be expressed as:
1
C11 =
2π × FZ1 × R7
(1+sR7C11)×[1+sC10(R6+R8)]
1
4) Place third pole at the half of the switching frequency.
×
H(s) =
sR6(C12+C11)
C12C11
[ (C12+C11)]
fS
FP3 =
2
1+sR7
×(1+sR8C10)
1
C12 =
As known, transconductance amplifier has high imped-
ance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the ampli-
fier will not be able to swing its output voltage over the
necessary range.
2π × R7 × FP3
C12 > 50pF
If not, change R7 selection.
5) Place R7 in equation (15) and calculate C10:
2π × Lo × FO × Co
VOSC
VIN
The compensation network has three poles and two ze-
ros and they are expressed as follows:
C10 ≤
×
R7
Rev. 2.0
09/12/02
www.irf.com
9
IRU3038
6) Place second pole at the ESR zero.
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
FP2 = FESR
1
R8 =
2π × C10 × FP2
1
Check if R8 >
gm
Start to place the power components. Make all the con-
If R8 is too small, increase R7 and start from step 2. nections in the top layer with wide, copper filled areas.
The inductor, output capacitor and the MOSFET should
7) Place second zero around the resonant frequency. be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
FZ2 = FLC
switching currents through them. Place input capacitor
1
directly to the drain of the high-side MOSFET. To reduce
the ESR, replace the single input capacitor with two par-
allel units. The feedback part of the system should be
kept away from the inductor and other noise sources
and be placed close to the IC. In multilayer PCB, use
one layer as power ground plane and have a separate
R6 =
- R8
2π × C10 × FZ2
8) Use equation (1) to calculate R5:
VREF
R5 =
× R6
VOUT - VREF
These design rules will give a crossover frequency ap- control circuit ground (analog ground), to which all sig-
proximately one-tenth of the switching frequency. The nals are referenced. The goal is to localize the high cur-
higher the band width, the potentially faster the load tran- rent path to a separate loop that does not interfere with
sient speed. The gain margin will be large enough to the more sensitive analog control function. These two
provide high DC-regulation accuracy (typically -5dB to - grounds must be connected together on the PC board
12dB). The phase margin should be greater than 458 for layout at a single point.
overall stability.
IC Quiescent Power Dissipation
Power dissipation for IC controller is a function of ap-
plied voltage, gate driver loads and switching frequency.
The IC's maximum power dissipation occurs when the
IC operating with single 12V supply voltage (Vcc=12V
and Vc@24V) at 400KHz switching frequency and maxi-
mum gate loads.
This IC's power dissipation results to an excessive tem-
perature rise and should be considered when using
IRU3038 for such an application.
Rev. 2.0
09/12/02
www.irf.com
10
IRU3038
TYPICAL PERFORMANCE CHARACTERISTICS
IRU3038
IRU3038
Output Voltage
Transconductance (GM)
1.3
1.28
1.26
1.24
1.22
1.2
900
800
700
600
500
400
300
200
100
Max
Min
0
-40°C -25°C
0°C
+25°C +50°C +75°C +100°C +125°C +150°C
-40°C
-25°C
0°C
+25°C
+50°C
+75°C
+100°C
Output Voltage
Spec Max.
Spec Min.
Transconductance (GM)
Figure 8 - Output voltage of IRU3038.
Figure 9 - Transconductance of IRU3038.
IRU3038
Rise Time / Fall Time
CL = 1500pF
50
45
40
35
30
25
20
15
10
5
0
-40°C
-25°C
0°C
+25°C
+50°C
+75°C
+100°C
Rise Time
Fall time
Figure 10 - Rise and fall time of IRU3038.
www.irf.com
Rev. 2.0
09/12/02
11
IRU3038
TYPICAL APPLICATION
Single Supply 5V Input
5V
D1
BAT54S
L1
1uH
C2
2x 10TPB100ML,
100uF, 55m
C1
33uF
Tantalum
C5
0.1uF
C4
1uF
C3
0.1uF
Ω
Vcc
REF
Vc
HDrv
V
Q1
IRF7460
V
P
L2
D05022P-103, 3.3uH, 10A
U1
2.5V
@ 8A
SS
IRU3038
C8
0.1uF
Q2
IRF7460
C7
2x 6TPC150M,
150uF, 40m
LDrv
PGnd
Ω
Rt
R6
1K, 1%
Fb
Comp
C9
1800pF
Gnd
R5
1K, 1%
R4
26.1K
Figure 11 - Typical application of IRU3038 in an on-board DC-DC converter
using a single 5V supply.
450
400
350
300
250
200
150
0
50
100
150
200
250
Rt (KΩ)
Figure 12 - Switching frequency vs. Rt.
Rev. 2.0
09/12/02
www.irf.com
12
IRU3038
TYPICAL APPLICATION
5V
12V
L1
5V
1uH
C1
0.1uF
C2
1uF
C3
C4
47uF
10TPB100M,
100uF, 55m
Ω
Vcc
Vc
Q1
1/2 of IRF7313
HDrv
LDrv
Fb
SS
C6
0.1uF
L2
U1
IRU3037
VDDQ
2.5V @ 3A
D03316P-103, 10uH, 3.9A
Q1
C7
1/2 of IRF7313
2x 6TPC150M,
150uF, 40m
Ω
Comp
R1
1K
C8
2200pF
Gnd
R2
33K
R3
1K
5V
12V
C9
0.1uF
C10
1uF
C11
10TPB100M,
100uF, 55m
Ω
Vcc
Vc
R4
1K
VREF
Q2
HDrv
1/2 of IRF7313
VP
D1
BAT54
L3
R5
1K
SS
U2
IRU3038
Vtt
or 1N4148
D03316P-103, 10uH, 3.9A
Q2
1/2 of IRF7313
(1.25V @ 3A)
C12
0.15uF
LDrv
C13
2x 6TPC150M
150uF, 40m
PGnd
Fb
Rt
Ω
Comp
C14
2200pF
Gnd
R6
33K
Figure 13 - Typical application of IRU3038 for DDR memory when the termination voltage
tracks the core voltage generated by IRU3037.
Rev. 2.0
09/12/02
www.irf.com
13
IRU3038
DEMO-BOARD APPLICATION
5V to 2.5V @ 8A
5V
D1
L1
1uH
C18
C2
C1
47uF
47uF
33uF
70m
Ω
70mΩ
VREF
C4
1uF
C6
1uF
C3
1uF
C5
0.1uF
R12
Short
Vcc
VREF
Vc
HDrv
Q1
Q2
R13
Open
R2
L2
3.3uH
Short
U1
IRU3038
VDDQ
VP
2.5V
@ 8A
R1
Open
C9
470pF
SS
C8
0.1uF
LDrv
R6
4.7
C12
1uF
C11
150uF
40mΩ
C10
150uF
40m
Ω
PGnd
Fb
Ω
Rt
R8
Comp
Gnd
C15
1K, 1%
Gnd
1800pF
R11
1K, 1%
R9
26.1K
Figure 14 - Demo-board application of IRU3038.
Application Parts List
Ref Desig Description
Value
20V, 10mΩ, 12A
Synchronous PWM
Fast Switching,
Schottky
Qty
2
1
Part#
IRF7460
IRU3038
BAT54S
Manuf
Web site (www.)
irf.com
Q1, Q2
U1
MOSFET
Controller
Diode
IR
IR
IR
D1
1
L1
Inductor
Inductor
Cap, Tantalum 33µF, 16V
Cap, Poscap
Cap, Poscap
Cap, Ceramic 0.1µF, Y5V, 25V
Cap, Ceramic 1µF, X7R, 25V
Cap, Ceramic 1800pF, X7R, 50V
Cap, Ceramic 470pF, X7R
1µH, 10A
1
1
1
2
2
2
1
1
1
3
1
1
2
D03316P-102HC
D05022P-332HC
ECS-T1CD336R
16TPB47M
Coilcraft
Coilcraft
coilcraft.com
L2
C1
C2,C18
C10,C11
C5,C8
C4
3.3µH, 12A
Panasonic maco.panasonic.co.jp
Sanyo
Sanyo
Panasonic maco.panasonic.co.jp
Panasonic
47µF, 16V, 70mΩ
150µF, 6.3V, 40mΩ
sanyo.com/industrial
6TPC150M
ECJ-2VF1E104Z
ECJ-3YB1E105K
ECJ-2VB1H182K
ECJ-2VB2D471K
ECJ-2VF1C105Z
C15
C9
Panasonic
Panasonic
Panasonic
C3,C6,C12 Cap, Ceramic 1µF, Y5V, 16V
R9
R6
R8,R11
Resistor
Resistor
Resistor
26.1K, 5%
4.7Ω, 5%
1K, 1%
Rev. 2.0
09/12/02
www.irf.com
14
IRU3038
TYPICAL PERFORMANCE CHARACTERISTICS
VIN
94
92
90
88
86
84
82
80
Vss
VOUT
0
1
2
3
4
5
6
7
8
9
Output Current (A)
Figure 15 - Efficiency for IRU3038 Evaluation Board.
VIN=5V, VOUT=2.5V
Figure 16 - Start-up time @ IOUT=5A.
Vss
VOUT
IOUT
Figure 17 - Shutdoown the output by
pulling down the soft-start.
Figure 18 - 3.3V output voltage ripple @ IOUT=5A.
2A
4A
0A
0A
Figure 20 - Transient response @ IOUT=0 to 4A.
Figure 19 - Transient response @ IOUT=0 to 2A.
Rev. 2.0
09/12/02
www.irf.com
15
IRU3038
(F) TSSOP Package
14-Pin
A
L
Q
R1
C
B
1.0 DIA
R
E
N
M
P
O
PIN NUMBER 1
F
D
DETAIL A
DETAIL A
G
J
H
K
SYMBOL
14-PIN
DESIG
A
MIN
NOM
0.65 BSC
MAX
4.50
0.30
B
4.30
0.19
4.40
6.40 BSC
---
C
D
E
1.00
1.00
5.00
---
F
G
H
4.90
---
5.10
1.10
0.95
0.15
J
0.85
0.05
0.90
---
K
L
128 REF
128 REF
---
M
N
08
88
O
P
1.00 REF
0.60
0.20
---
0.50
0.75
Q
R
0.09
0.09
---
---
R1
---
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 2.0
09/12/02
www.irf.com
16
IRU3038
(S) SOIC Package
14-Pin Surface Mount, Narrow Body
H
A
B
C
E
DETAIL-A
L
D
PIN NO. 1
DETAIL-A
I
0.38± 0.015 x 458
K
T
F
J
G
14-PIN
SYMBOL
MIN
MAX
A
B
C
D
E
F
G
H
I
8.56
8.74
1.27 BSC
0.51 REF
0.36
0.46
3.99
1.72
0.25
3.81
1.52
0.10
78 BSC
0.19
5.80
08
0.25
6.20
88
J
K
L
0.41
1.37
1.27
1.57
T
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 2.0
09/12/02
www.irf.com
17
IRU3038
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
PARTS
T & R
DESIG
DESCRIPTION
COUNT
PER TUBE
PER REEL
Orientation
F
S
TSSOP Plastic
SOIC, Narrow Body
14
14
100
55
2500
2500
Fig A
Fig B
1
1
1
1
1
1
Feed Direction
Figure A
Feed Direction
Figure B
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 2.0
09/12/02
www.irf.com
18
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