IRU3073 [INFINEON]
SYNCHRONOUS PWM CONTROLLER WITH OVER-CURRENT PROTECTION / LDO CONTROLLER; 同步PWM控制器提供过电流保护/ LDO控制器
| 型号： | IRU3073 |
| 厂家： | 
Infineon |
| 描述： | SYNCHRONOUS PWM CONTROLLER WITH OVER-CURRENT PROTECTION / LDO CONTROLLER |
| 文件： | 总21页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD94699
IRU3073
SYNCHRONOUS PWM CONTROLLER WITH
OVER-CURRENT PROTECTION / LDO CONTROLLER
FEATURES
DESCRIPTION
Synchronous Controller plus one LDO controller
Current Limit using MOSFET Sensing
Single 5V/12V Supply Operation
Programmable Switching Frequency up to
400KHz
The IRU3073 controller IC is designed to provide a low
cost synchronous Buck regulator for on-board DC to DC
converter for multiple output applications.
The outputs can be programmed as low as 0.8V for low
voltage applications.
Soft-Start Function
Fixed Frequency Voltage Mode
Precision Reference Voltage Available
Uncommitted Error Amplifier available for DDR
voltage tracking application
Selectable over-current protection is provided by using
external MOSFET's on-resistance for optimum cost and
performance.
This device features a programmable frequency set from
200KHz to 400KHz, under-voltage lockout for all input
supplies, an external programmable soft-start function
as well as output under-voltage detection that latches
off the device when an output short is detected.
APPLICATIONS
DDR memory source sink VTT application
Low cost on-board DC to DC such as
12V/5V to output voltages as low as 0.8V
Graphic Card
Hard Disk Drive
Multi-Output Applications
TYPICAL APPLICATION
3.3V
Vcc
12V
Q1
Drv2
Fb2
R1
VOUT2
VcH
VcL
C2
L1
R2
C1
+5V
U1
C6
C7
IRU3073
HDrv
Q4
Q5
V
P1
C3
0.1uF
D1
VREF
L2
C4
C9
R7
OCSet
LDrv
VOUT1
R8
Comp
C10
R9
Rt
SS/SD
R10
C11
Fb1
Gnd
PGnd
R11
Figure 1 - Typical application of IRU3073.
PACKAGE ORDER INFORMATION
TA (°C)
DEVICE
PACKAGE
0 To 70
IRU3073CQ
16-Pin Plastic QSOP NB (Q)
Rev. 1.0
09/17/03
www.irf.com
1
IRU3073
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage ................................................... -0.5 - 25V
VcL, VcH Supply Voltage .......................................... -0.5 - 25V
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.
PACKAGE INFORMATION
16-PIN PLASTIC QSOP NB (Q)
Fb2 1
Drv2 2
Rt 3
16 OCSet
15 VcH
14 HDrv
13 Gnd
12 PGnd
11 LDrv
10 VcL
SS/SD 4
5
6
7
8
Comp
Fb1
VP1
9 Vcc
VREF
θJA=1128C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, VcL=VcH=12V and TA=0°C to 70°C. Low duty
cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX UNITS
Feedback Voltage
Fb Voltage
Fb Voltage Line Regulation
Reference Voltage
Ref Voltage Initial Accuracy
Drive Current
VFB
0.784
0.8
0.2
0.816
0.625
V
%
LREG
5<Vcc<12
VREF
IREF
0.784
0.8
2
0.816
V
µA
Note 1
UVLO
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - VcH
UVLO Hysteresis - VcH
UVLO Threshold - Fb1
UVLO Hysteresis - Fb1
Supply Current
UVLO VCC Supply Ramping Up
UVLO VCH Supply Ramping Up
UVLO Fb1 Fb Ramping Down
3.9
3.3
0.3
4.4
0.25
3.5
0.2
0.4
0.1
4.8
3.7
0.5
V
V
V
V
V
V
Vcc Dynamic Supply Current
Vc Dynamic Supply Current
Vcc Static Supply Current
Vc Static Supply Current
Soft-Start Section
Charge Current
Dyn ICC
Dyn IC
ICCQ
Freq=200KHz, CL=1500pF
Freq=200KHz, CL=1500pF
SS=0V
5
5
10
15
10
5
mA
mA
mA
mA
3.5
3
ICQ
SS=0V
SS IB
SS=0V
10
25
30
µA
Rev. 1.0
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IRU3073
PARAMETER
SYM
TEST CONDITION
SS=3V
MIN
TYP
MAX UNITS
Error Amp
Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
VP Voltage Range
Transconductance
Oscillator
IFB1
IFB2
VP
-0.1
55
µA
µA
+5
75
-5
35
SS=0V
Note 1
1.5
V
0.8
700
µmho
Frequency
Freq
Rt=100K
Rt=50K
Note 1
210
400
1.25
240
460
KHz
180
340
Ramp Amplitude
Output Drivers
Rise Time
VRAMP
VPP
Tr
Tf
TDB
DMAX
DMIN
CLOAD=1500pF
CLOAD=1500pF
50
50
100
90
ns
ns
ns
%
%
100
100
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
LDO Controller Section
Drive Current
Fb=0.7V, Freq=200KHz
Fb=0.9V
85
0
Drv1
65
mA
V
µA
8C
40
0.784
-1
Fb Voltage
0.8
-0.1
150
0.816
+1
Input Bias Current
Thermal Shutdown
Current Limit
Note 1
OC Threshold Set Current
OC Comp Off-Set Voltage
IOCSET
30
0
40
+5
µA
mV
20
-5
VOC(OFFSET)
Note 1: Guaranteed by design but not tested in production.
PIN DESCRIPTIONS
PIN#
PIN SYMBOL
PIN DESCRIPTION
1
2
3
Fb2
Drv2
Rt
These pins provide feedback for the linear regulator controllers.
Outputs of the linear regulator controllers.
A resistor should be connected from this pin to ground for setting the switching frequency.
This pin provides soft-start for the switching regulator. An internal current source charges
an external capacitor that is connected from this pin to ground which ramps up the output
of the switching regulator, preventing it from overshooting as well as limiting the input
current. The converter can be shutdown by pulling this pin down below 0.4V.
Compensation pin of the error amplifier. An external resistor and capacitor network is
typically connected from this pin to ground to provide loop compensation.
This pin is connected directly to the output of the switching regulator via resistor divider to
provide feedback to the Error amplifier.
4
SS / SD
5
6
Comp
Fb1
7
8
9
VP1
VREF
Vcc
Non-inverting input of error amplifier.
Reference voltage.
This pin provides biasing for the internal blocks of the IC as well as powers the LDO
controller. A minimum of 1µF, high frequency capacitor must be connected from this pin
to ground to provide peak drive current capability.
10
11
VcL
This pin powers the low side output driver and can be connected either to Vcc or separate
supply. A minimum of 1µF, high frequency capacitor must be connected from this pin to
ground to provide peak drive current capability.
LDrv
Output driver for the synchronous power MOSFET.
Rev. 1.0
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IRU3073
PIN#
PIN SYMBOL
PIN DESCRIPTION
12
PGnd
This pin serves as the separate ground for MOSFET's driver and should be connected to
system's ground plane.
13
14
Gnd
This pin serves as analog ground for internal reference and control circuitry. A high fre-
quency capacitor must be connected from Vcc pin to this pin for noise free operation.
Output driver for the high side power MOSFET. This pin should not go negative (below
ground), this may cause problem for the gate drive circuit. It can happen when the inductor
current goes negative (Source/Sink), soft-start at no load and for the fast load transient
from full load to no load. To prevent negative voltage at gate drive, a low forward voltage
drop diode might be connected between this pin and ground.
HDrv
15
16
VcH
This pin is connected to a voltage that must be at least 4V higher than the bus voltage of
the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A
minimum of 1µF, high frequency capacitor must be connected from this pin to ground to
provide peak drive current capability.
This pin is connected to the Drain of the lower MOSFET via an external resister and it
provides the positive sensing for the internal current sensing circuitry. The external resis-
tor programs the current limit threshold depending on the RDS(ON) of the power MOSFET.
An external capacitor can be placed in parallel with the programming resistor to provide
high frequency noise filtering.
OCSet
BLOCK DIAGRAM
0.8V
VREF
Vcc 9
3V
1.25V
8
Bias
Generator
1.25V
3V
20uA
POR
4.2V / 4.0V
3.5V / 3.3V
UVLO
3 Rt
Vcc
15 VcH
VcH
SS/SD 4
Rt
Ct
64uA
Max
Oscillator
En
HDrv
14
POR
S
R
Error Comp
Q
Comp 5
Error Amp
25K
25K
VcL
10
11
VP1
7
Reset Dom
LDrv
Fb1 6
3V
OCSet
0.4V
20uA
PGnd
12
CS Comp
POR
16
FbLo Comp
Vcc
TSD
0.8V
2
Drv2
Gnd
Fb2 1
13
Figure 2 - Simplified block diagram of the IRU3073.
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Rev. 1.0
09/17/03
4
IRU3073
THEORY OF OPERATION
Introduction
3V
20uA
The IRU3073 is designed for a two output application
and it includes one synchronous buck controller and a
linear regulator controller. The PWM section is a fixed
frequency, voltage mode and consists of a precision ref-
erence voltage, an uncommitted error amplifier, an inter-
nal oscillator, a PWM comparator, an internal regulator,
a comparator for current limit, gate drivers, soft-start and
shutdown circuits (see Block Diagram).
HDrv
SS/SD
POR
64uA
Max
Comp
0.8V
Error Amp
LDrv
25K
25K
The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier; this is
the amplified error signal from the sensed output voltage
and the voltage on non-inverting input of error amplifier(VP).
This voltage is compared to a fixed frequency linear
sawtooth ramp and generates fixed frequency pulses of
variable duty-cycle, which drives the two N-channel ex-
ternal MOSFETs.
Fb1
0.4V
64uA×
25K=1.6V
When SS=0
POR
Feeback
UVLO Comp
The timing of the IC is provided through an internal oscil-
lator circuit which uses on-chip capacitor. The oscilla-
Figure 3 - IRU3073 soft-start diagram.
tion frequency is programmable between 200KHz to The magnitude of this current is inversely proportional to
400KHz by using an external resistor. Figure 14 shows the voltage at soft-start pin.
switching frequency vs. external resistor (Rt).
The 20µA current source starts to charge up the exter-
Soft-Start
nal capacitor. In the mean time, the soft-start voltage
The IRU3073 has a programmable soft-start to control ramps up, the current flowing into Fb1 pin starts to de-
the output voltage rise and limit the current surge at the crease linearly and so does the voltage at the positive
start-up. To ensure correct start-up, the soft-start se- pin of feedback UVLO comparator and the voltage nega-
quence initiates when the input supplies rise above their tive input of E/A.
threshold and generates the Power On Reset (POR) sig-
nal. Soft-start function operates by sourcing an internal When the soft-start capacitor is around 1V, the current
current to charge an external capacitor to about 3V. Ini- flowing into the Fb1 pin is approximately 32µA. The volt-
tially, the soft-start function clamps the E/A’s output of age at the positive input of the E/A is approximately:
the PWM converter and disables the short circuit pro-
tection. During the power up of the buck converter, the
32µA×25K = 0.8V
output starts at zero and voltage at Fb1 is below 0.4V. The E/A will start to operate and the output voltage starts
The feedback UVLO is disabled during this time by in- to increase. As the soft-start capacitor voltage contin-
jecting a current (64µA) into the Fb1. This generates a ues to go up, the current flowing into the Fb1 pin will
voltage about 1.6V (64µA×25K) across the negative keep decreasing. Because the voltage at pin of E/A is
input of E/A and positive input of the feedback UVLO regulated to reference voltage 0.8V, the voltage at the
comparator (see Fig3).
Fb1 is:
VFB1 = 0.8-25K×(Injected Current)
Rev. 1.0
09/17/03
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IRU3073
The feedback voltage increases linearly as the injecting LDO Controller
current goes down. The injecting current drops to zero The LDO section is powered directly from Vcc. The out-
when soft-start voltage is around 2V and the output volt- put of LDO can be set as low as 0.8V and can be pro-
age goes into steady state.
grammed to higher voltages by using two external resis-
tors.
As shown in Figure 4, the positive pin of feedback UVLO
comparator is always higher than 0.4V, therefore, feed- Supply Voltage Under-Voltage Lockout
back UVLO is not functional during soft-start.
The under-voltage lockout circuit assures that the
MOSFET driver outputs, remain in the off state when-
ever the supply voltage drops below set parameters. Lock-
out occurs if Vcc or VcH fall below 4.0V and 3.3V re-
spectively. Normal operation resumes once these volt-
ages rise above the set values.
Output of UVLO
POR
3V
@2V
@1V
Soft-Start
Voltage
0V
Shutdown
The PWM section can be shutdown by pulling the soft-
start pin below 0.4V. The control MOSFET turns off and
the synchronous MOSFET turns on during shutdown.
64uA
Current flowing
into Fb1 pin
0uA
@
1.6V
Voltage at negative input
of Error Amp and Feedback
UVLO comparator
Over-Current Protection
0.8V
0.8V
Over-current protection is achieved with a cycle by cycle
scheme and it is performed by sensing current through
the RDS(ON) of low side MOSFET. As shown in Figure 5,
an external resistor (RSET) is connected between OCSet
pin and the drain of low side MOSFET (Q2) and sets the
current limit set point. The internal current source devel-
ops a voltage across RSET. When the low side switch is
turned on, the inductor current flows through the Q2 and
results a voltage which is given by:
0V
Voltage at Fb1 pin
Figure 4 - Theoretical operation waveforms
during Soft-Start.
From this analysis, the output start-up time is defined
as when soft-start capacitor voltage increases from 1V
to 2V. The start-up time will be dependent on the size of
the external soft-start capacitor and can be estimated
by:
VOCSET = IOCSET×RSET-RDS(ON)×iL
---(1)
I
OCSET
IRU3073
Q1
Q2
L1
VOUT
RSET
OCSet
20µA×TSTART/CSS = 2V-1V
Osc
For a given start up time, the soft-start capacitor can be
calculated as:
CSS = 20µA×TSTART/1V
Figure 5 - Diagram of the over current sensing.
MOSFET Drivers
The driver capabilities of both high and low side drivers When voltage VOCSET is below zero, the current sensing
are optimized to maintain fast switching transitions. They comparator flips and disables the oscillator. The high
are sized to drive a MOSFET that can deliver up to 20A side MOSFET is turned off and the low side MOSFET is
output current.
turned on until the inductor current reduces to below
current set value. The critical inductor current can be
The low side MOSFET diver is supplied directly by VCC calculated by setting:
while the high side driver is supplied by VC.
VOCSET = IOCSET×RSET - RDS(ON)×IL = 0
An internal dead time control is implemented to prevent
cross-conduction and allows the use of several kinds of
MOSFETs.
RSET×IOCSET
ISET = IL(CRITICAL) =
---(2)
RDS(ON)
Rev. 1.0
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IRU3073
If the over-current condition is temporary and goes away
quickly, the IRU3073 will resume its normal operation.
i
L(PEAK)
L(AVG)
Inductor
Current
i
If output is shorted or over-current condition persists,
the output voltage will keep going down until it is below
0.4V. Then the output under-voltage lock out comparator
goes high and turns off both MOSFETs. The operation
waveforms are shown in Figure 6.
I
SET=iL(VALLEY)
Current Limit
Comparator Output
HDrv
V
REF
Feedback
voltage
tOFF
t
ON
0.4V
Figure 7 - Operation waveforms during current limit.
FS(NOM)
IOUT
Switching
frequency
From Figure 7, the average inductor current during the
current limit mode is:
∆IPK-PK(LIM)
I
OUT
MAX/FS(NOM)
IO(LIM) = ISET +
---(4)
D
V
OUT
2
High Side MOSFET
F
S(NOM)×VIN
The inductor's ripple current can be expressed as:
turn on time (tON
)
I
OUT
(VIN - VOUT)×VOUT
∆IPK-PK(LIM) =
VIN×L×fS
<IL>=IOUT
Average Inductor
Current
Combination of above equation and (4) results in:
(VIN-VOUT)×VOUT
ISET = IO(LIM) -
---(5)
I
O(LIM)
I
O(MAX)
I
OUT
(
)
2×fS×L×VIN
Normal
operation
Over Current
Shutdown
Limit Mode by UVLO
Combination of equations (5) and (2) results in the rela-
tionship between RSET and output current limit:
Figure 6 - Diagram of over-current operation.
RDS(ON)
IOCSET
(VIN-VOUT)×VOUT
RSET =
× IO(LIM) -
---(6)
[ ( 2×fS×L×VIN )]
Operation in current limit is shown in Figure 7, the high
side MOSFET is turned off and inductor current starts to
decrease. Because the output inductor current is higher
than the current limit setpoint (ISET), the over-current com-
parator keeps high until the inductor current decreases
to be below ISET. Then another cycle starts.
Where:
IO(LIM) = The Output Current Limit -typical is 50%
higher than nominal output current.
VIN = Maximum Input Voltage
VOUT = Output Voltage
fS = Switching Frequency
L = Output Inductor
RDS(ON) = RDS(ON) of Low Side MOSFET
IOCSET = OC Threshold Set Current
During over-current mode, the valley inductor current is:
iL(VALLEY) = ISET
The peak inductor current is given as:
From the above analysis, the current limit is not only
dependent on the current setting resistor RSET and RDS(ON)
of low side MOSFET but it is also dependent on the
input voltage, output voltage, inductance and switching
frequency as well.
IL(PEAK) = ISET+(VIN-VOUT)×tON/L
---(3)
To avoid undesirable trigger of over-current protection,
this relationship must be satisfied:
∆IPK-PK(NOM)
ISET / IO(NOM) -
2
The cycle-by-cycle over-current limit will hold for a cer-
tain amount of time, until the output voltage drops below
0.4V, the under-voltage lock out activates and latches
off the output driver. The operation waveform is shown in
Figure 4. Normal operation will resume after IRU3073 is
powered up again.
Rev. 1.0
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IRU3073
APPLICATION INFORMATION
Design Example:
For a start-up time of 5ms, the soft-start capacitor will
The following example is a typical application for IRU3073, be 0.1µF. Choose a ceramic capacitor at 0.1µF.
the schematic is Figure 17 on page 16.
Supply VcL and VcH
Supply Voltage
VCC=VCL=VCH=12V
Switcher
VIN = 5V
VOUT = 2.5V
IOUT = 8A
∆VOUT = 50mV
fS = 200KHz
Linear Regulator
VIN = 2.5V
VOUT = 1.6V
IOUT = 2A
To drive the high side switch, it is necessary to supply a
gate voltage at least 4V greater than the Bus voltage.
For this application, VcL and VcH are biased with a sepa-
rate 12V supply.
Input Capacitor Selection
Output Voltage Programming
The input filter capacitor should be based on how much
Output voltage is programmed by reference voltage and ripple the supply can tolerate on the DC input line. The
external voltage divider. The Fb pin is the inverting input ripple current generated during the on time of upper
of the error amplifier, which is referenced to the voltage MOSFET should be provided by input capacitor. The RMS
on non-inverting pin of error amplifier. For this applica- value of this ripple is expressed by:
tion, this pin (VP) is connected to reference voltage (VREF).
IRMS = IOUT
D×(1-D)
---(9)
The output voltage is defined by using the following equa-
Where:
tion:
R6
R5
VOUT = VP × 1 +
---(7)
D is the Duty Cycle, D=VOUT/VIN.
IRMS is the RMS value of the input capacitor current.
IOUT is the output current for each channel.
( )
VP = VREF = 0.8V
When an external resistor divider is connected to the
output as shown in Figure 8.
For VIN=5V, IOUT=8A and D=0.5, the IRMS=4A
For higher efficiency, a low ESR capacitor is recom-
mended. Choose two Poscap from Sanyo 6TPB47M
(16V, 47µF) with a max allowable ripple current of 5.2A.
V
OUT
IRU3073
R
6
VREF
Fb
Inductor Selection
R5
The inductor is selected based on operating frequency,
transient performance and allowable output voltage ripple.
VP
Figure 8 - Typical application of the IRU3039 for
programming the output voltage.
Low inductor value results to faster response to step
load (high di/dt) and smaller size but will cause larger
output ripple due to increase of inductor ripple current.
As a rule of thumb, select an inductor that produces a
ripple current of 10-40% of full load DC.
Equation (7) can be rewritten as:
VOUT
R6 = R5 ×
- 1
( VP )
For the buck converter, the inductor value for desired
operating ripple current can be determined using the fol-
Choose R5 = 1K. This will result toR6 = 2.15K
If the high value feedback resistors are used, the input lowing relation:
bias current of the Fb pin could cause a slight increase
∆i
∆t
1
fS
VOUT
VIN
VIN - VOUT = L×
; ∆t = D×
; D =
in output voltage. The output voltage set point can be
more accurate by using precision resistor.
VOUT
L = (VIN - VOUT)×
---(11)
VIN×∆i×fS
Soft-Start Programming
Where:
The soft-start timing can be programmed by selecting
the soft-start capacitance value. The start-up time of the
converter can be calculated by using:
VIN = Maximum Input Voltage
VOUT = Output Voltage
Di = Inductor Ripple Current
fS = Switching Frequency
Dt = Turn On Time
Css @ 20×tSTART (µF)
---(8)
Where tSTART is the desirable start-up time (s)
D = Duty Cycle
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IRU3073
If ∆i = 25%(IO), then the output inductor will be:
L = 3.125µH
The total power dissipation for MOSFETs includes con-
duction and switching losses. For the Buck converter,
the average inductor current is equal to the DC load cur-
The Coilcraft DO5022HC series provides a range of in- rent. The conduction loss is defined as:
ductors in different values, low profile suitable for large
2
currents. 3.3µH is a good choice for this application.
This will result to a ripple approximately 23% of output
current.
PCOND(Upper Switch) = ILOAD×RDS(ON)×D×ϑ
2
PCOND(Lower Switch) = ILOAD×RDS(ON)×(1 - D)×ϑ
ϑ = RDS(ON) Temperature Dependency
Output Capacitor Selection
The criteria to select the output capacitor is normally The RDS(ON) temperature dependency should be consid-
based on the value of the Effective Series Resistance ered for the worst case operation. This is typically given
(ESR). In general, the output capacitor must have low in the MOSFET data sheet. Ensure that the conduction
enough ESR to meet output ripple and load transient losses and switching losses do not exceed the package
requirements, yet have high enough ESR to satisfy sta- ratings or violate the overall thermal budget.
bility requirements. The ESR of the output capacitor is
calculated by the following relationship:
Choose IRF7832 for both control MOSFET and synchro-
nous MOSFET. This device provides low on-resistance
in a compact SOIC 8-Pin package.
∆VO
ESR ≤
---(10)
∆IO
Where:
The MOSFETs have the following data:
∆VO = Output Voltage Ripple
∆i = Inductor Ripple Current
IRF7832
∆VO = 50mV and ∆I @ 23% of 8A = 1.89A
This results to: ESR=26.5mΩ
VDSS = 30V
ID = 16A @ 708C
RDS(ON) = 4mΩ
The Sanyo TPC series, Poscap capacitor is a good choice.
The 6TPC330M, 330µF, 6.3V has an ESR 40mΩ. Se- The total conduction losses will be:
lecting two of these capacitors in parallel, results to an
ESR of @ 20mΩ which achieves our low ESR goal.
PCON(TOTAL) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL) = 0.38W
The capacitor value must be high enough to absorb the The switching loss is more difficult to calculate, even
inductor's ripple current. The larger the value of capaci- though the switching transition is well understood. The
tor, the lower will be the output ripple voltage.
reason is the effect of the parasitic components and
switching times during the switching procedures such
as turn-on / turnoff delays and rise and fall times. The
Power MOSFET Selection
The IRU3073 uses two N-Channel MOSFETs. The se- control MOSFET contributes to the majority of the switch-
lections criteria to meet power transfer requirements is ing losses in synchronous Buck converter. The synchro-
based on maximum drain-source voltage (VDSS), gate- nous MOSFET turns on under zero voltage conditions,
source drive voltage (VGS), maximum output current, On- therefore, the turn on losses for synchronous MOSFET
resistance RDS(ON) and thermal management.
can be neglected. With a linear approximation, the total
switching loss can be expressed as:
The MOSFET must have a maximum operating voltage
(VDSS) exceeding the maximum input voltage (VIN).
VDS(OFF)
tr + tf
T
PSW =
×
×ILOAD
---(12)
2
Where:
The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistor can be used and cau-
tion should be taken with devices at very low VGS to pre-
vent undesired turn-on of the complementary MOSFET,
which results a shoot-through current.
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
T = Switching Period
ILOAD = Load Current
The switching time waveform is shown in Figure 9.
Rev. 1.0
09/17/03
www.irf.com
9
IRU3073
V
DS
The output LC filter introduces a double pole, –40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 1808 (see Figure 10). The Reso-
nant frequency of the LC filter is expressed as follows:
90%
1
FLC =
---(13)
2π× LO×CO
10%
Figure 10 shows gain and phase of the LC filter. Since
we already have 1808 phase shift just from the output
filter, the system risks being unstable.
VGS
t
d(ON)
td(OFF)
tr
tf
Figure 9 - Switching time waveforms.
Gain
Phase
08
0dB
From IRF7832 data sheet we obtain:
-40dB/decade
IRF7832
tr = 12.3ns
tf = 21ns
-180
8
These values are taken under a certain condition test.
For more details please refer to the IRF7832 datasheet.
F
LC
Frequency
FLC Frequency
Figure 10 - Gain and phase of LC filter.
By using equation (12), we can calculate the total switch-
ing losses.
The IRU3073’s error amplifier is a differential-input
transconductance amplifier. The output is available for
DC gain control or AC phase compensation.
PSW(TOTAL) = 133mW
Programming the Over-Current Limit
The over-current threshold can be set by connecting a The E/A can be compensated with or without the use of
resistor (RSET) from drain of low side MOSFET to the local feedback. When operated without local feedback,
OCSet pin. The resistor can be calculated by using equa- the transconductance properties of the E/A become evi-
tion (2).
dent and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
The RDS(ON) has a positive temperature coefficient and it from Comp pin to ground as shown in Figure 11.
should be considered for the worse case operation.
Note that this method requires that the output capacitor
should have enough ESR to satisfy stability requirements.
RDS(ON) = 4mΩ×1.5 = 6mΩ
ISET @ IO(LIM) = 8A×1.5 = 12A
In general, the output capacitor’s ESR generates a zero
(50% over nominal output current)
typically at 5KHz to 50KHz which is essential for an
This results to: RSET @ 4.8KΩ
Select: RSET = 5KΩ
acceptable phase margin.
Feedback Compensation
The ESR zero of the output capacitor expressed as fol-
The IRU3073 is a voltage mode controller; the control lows:
loop is a single voltage feedback path including error
1
FESR =
---(14)
amplifier and error comparator. To achieve fast transient
response and accurate output regulation, a compensa-
tion circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 458).
2π×ESR×Co
Rev. 1.0
09/17/03
www.irf.com
10
IRU3073
VOUT
For:
VIN = 5V
FLC = 3.41KHz
R5 = 1K
R6 = 2.15K
gm = 700µmho
R
6
VOSC = 1.25V
Fo = 20KHz
FESR = 12KHz
Fb
Comp
Ve
E/A
R5
C
9
This results to R4=23.14K
Choose R4=24K
Vp=VREF
R4
CPOLE
Gain(dB)
To cancel one of the LC filter poles, place the zero be-
fore the LC filter resonant frequency pole:
H(s) dB
FZ @ 75%FLC
1
FZ @ 0.75×
---(19)
Frequency
FZ
2π LO × CO
For:
Lo = 3.3µH
Co = 660µF
Figure 11 - Compensation network without local
feedback and its asymptotic gain plot.
FZ = 2.5KHz
R4 = 24K
The transfer function (Ve / VOUT) is given by:
Using equations (17) and (19) to calculate C9, we get:
R5
1 + sR4C9
sC9
H(s) = gm×
×
---(15)
( )
R6 + R5
C9 @ 2590pF; Choose C9=2200pF
The (s) indicates that the transfer function varies as a One more capacitor is sometimes added in parallel with
function of frequency. This configuration introduces a gain C9 and R4. This introduces one more pole which is mainly
and zero, expressed by:
used to suppress the switching noise. The additional
pole is given by:
R5
R6×R5
|H(s=j×2π×FO)| = gm×
×R4
---(16)
1
FP =
C9×CPOLE
2π×R4×
C9 + CPOLE
1
FZ =
---(17)
2π×R4×C9
|H(s)| is the gain at zero cross frequency.
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
First select the desired zero-crossover frequency (Fo):
1
1
Fo > FESR and FO ≤ (1/5 ~ 1/10)×fS
CPOLE =
@
π×R4×fS
1
C9
π×R4×fS -
Use the following equation to calculate R4:
1
fS
2
for FP <<
VOSC
VIN
Fo×FESR
R5 + R6
R5
R4 =
×
×
×
---(18)
2
gm
FLC
For a general solution for unconditionally stability for
ceramic capacitor with very low ESR and any type of
output capacitors, in a wide range of ESR values we
should implement local feedback with a compensation
network. The typically used compensation network for
voltage-mode controller is shown in Figure 12.
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R6 = Resistor Dividers for Output Voltage
Programming
gm = Error Amplifier Transconductance
Rev. 1.0
09/17/03
www.irf.com
11
IRU3073
V
OUT
1
Z
IN
FZ1 =
FZ2 =
C12
2π×R7×C11
C
10
1
1
R7
C11
@
2π×C10×(R6 + R8)
2π×C10×R6
R8
R
6
Z
f
Cross Over Frequency:
Fb
VIN
FO = R7×C10×
VOSC
1
Ve
E/A
---(21)
×
Comp
2π×Lo×Co
R5
Where:
Vp=VREF
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Gain(dB)
H(s) dB
Co = Total Output Capacitors
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (20) regarding transconduc-
tance error amplifier.
Frequency
F
Z
1
F
Z
2
FP
2
FP3
Figure 12 - Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
sient speed. The gain margin will be large enough to
Ve
1 - gmZf
=
VOUT
1 + gmZIN
The error amplifier gain is independent of the transcon- provide high DC-regulation accuracy (typically -5dB to -
ductance under the following condition:
12dB). The phase margin should be greater than 458 for
overall stability.
gmZf >> 1
and
gmZIN >>1
---(20)
By replacing ZIN and Zf according to Figure 7, the trans- Based on the frequency of the zero generated by ESR
former function can be expressed as:
versus crossover frequency, the compensation type can
be different. The table below shows the compensation
type and location of crossover frequency.
(1+sR7C11)×[1+sC10(R6+R8)]
1
H(s) =
×
sR6(C12+C11)
C12C11
1+sR7
×(1+sR8C10)
[ (C12+C11)]
Compensator
Type
Location of Zero
Crossover Frequency
(FO)
Typical
Output
As known, transconductance amplifier has high imped-
ance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the ampli-
fier will not be able to swing its output voltage over the
necessary range.
Capacitor
Electrolytic,
Tantalum
Tantalum,
Ceramic
Type II (PI)
FPO < FZO < FO < fS/2
Type III (PID)
Method A
FPO < FO < FZO < fS/2
FPO < FO < fS/2 < FZO
Type III (PID)
Method B
Ceramic
The compensation network has three poles and two ze-
ros and they are expressed as follows:
Table - The compensation type and location of zero
crossover frequency.
FP1 = 0
1
FP2 =
Detail information is dicussed in application Note AN-
1043 which can be downloaded from the IR Web-Site.
2π×R8×C10
1
1
FP3 =
@
2π×R7×C12
C12×C11
(C12+C11 )
2π×R7×
Rev. 1.0
09/17/03
www.irf.com
12
IRU3073
LDO Section
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
Output Voltage Programming
Output voltage for LDO is programmed by reference volt- pickup and can cause a good design to perform with
age and external voltage divider. The Fb2 pin is the in- less than expected results.
verting input of the error amplifier, which is internally ref-
erenced to 0.8V. The divider is ratioed to provide 0.8V at Start to place the power components. Make all the con-
the Fb2 pin when the output is at its desired value. The nections in the top layer with wide, copper filled areas.
output voltage is defined by using the following equation The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
R7
VOUT2 = VREF× 1+
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET. To reduce
the ESR, replace the single input capacitor with two par-
allel units. The feedback part of the system should be
kept away from the inductor and other noise sources
and be placed close to the IC. In multilayer PCB, use
one layer as power ground plane and have a separate
control circuit ground (analog ground), to which all sig-
nals are referenced. The goal is to localize the high cur-
rent path to a separate loop that does not interfere with
the more sensitive analog control function. These two
grounds must be connected together on the PC board
layout at a single point.
( )
R10
For:
VOUT2 = 1.6V
VREF = 0.8V
R10 = 1KΩ
Results to R7=1KΩ
V
OUT2
IRU3073
R7
Fb2
R10
500
450
400
350
300
250
200
150
100
50
Figure 13 - Programming the output voltage for LDO.
LDO Power MOSFET Selection
The first step in selecting the power MOSFET for the
linear regulator is to select the maximum RDS(ON) based
on the input to the dropout voltage and the maximum
load current.
VIN(LDO) - VOUT2
0
RDS(ON) =
IOUT2
0
50
100
150 200
250
300
350
400
450
500
550
Rt (KΩ)
For:
VIN(LDO) = 2.5V
VOUT2 = 1.6V
IOUT2 = 2A
Figure 14 - Switching Frequency vs. Rt.
Results to: RDS(ON)(MAX) = 0.45Ω
Note that since the MOSFET RDS(ON) increases with tem-
perature, this number must be divided by ~1.5 in order
to find the RDS(ON)(MAX) at room temperature. The IRLR2703
has a maximum of 0.065Ω RDS(ON) at room temperature,
which meets our requirements.
Rev. 1.0
09/17/03
www.irf.com
13
IRU3073
TYPICAL APPLICATION
2.5V
Vcc
VcL
C16
1uF
Q3
IRLR2703
C13
Drv2
Fb2
L1
150uF
C2A,B,C=47uF
+5V
1uH
R2
C19
1uF
D3
BAT54
C1
47uF
1.6V
@ 2A
1K
R14
C14
150uF
U1
IRU3073
VcH
1K
C11
1uF
C3
0.1uF
Q1
IRF7832
HDrv
VP1
C10
D2
0.1uF
BAT54
V
REF
L2
3.3uH
C2
33pF
R4
5.1K
OCSet
LDrv
2.5V
@ 8A
R7
C7
2200pF
Comp
Q2
IRF7832
C12
1uF
24K
C9B C9C
330uF 330uF
Rt
SS/SD
R9
2.15K
C6
0.1uF
Fb1
Gnd
PGnd
R10
1K
Figure 15 - Typical application of IRU3073 for single 5V.
Rev. 1.0
09/17/03
www.irf.com
14
IRU3073
TYPICAL APPLICATION
3.3V
VcH
Vcc
VcL
12V
C11
1uF
Q3
C13
Drv2
IRLR2703
150uF
L1
C2A,B,C=47uF
R2
1K
R14
C16
1uF
+5V
1uH
1.6V
@ 1A
Fb2
C1
C14
47uF
U1
IRU3073
150uF
C19
1uF
1K
Q1
IRF7832
HDrv
VP1
D2
BAT54
C10
0.1uF
VREF
L2
3.3uH
C2
33pF
R4
5.1K
OCSet
LDrv
2.5V
@ 8A
R7
C7
2200pF
Comp
C12
1uF
Q2
IRF7832
24K
C9B C9C
330uF
330uF
Rt
SS/SD
R9
2.15K
C6
0.1uF
Fb1
R10
1K
Gnd
PGnd
Figure 16 - Typical application of IRU3073.
Rev. 1.0
09/17/03
www.irf.com
15
IRU3073
DEMO-BOARD APPLICATION
2.5V
Vcc
VcH
VcL
12V
+5V
C11
1uF
Q3
IRLR2703
C13
Drv2
L1
150uF
1uH
R2
C16
1uF
C1
47uF
1.6V
@ 2A
Fb2
C2C
47uF 47uF
C2A
47uF
C2B
1K
C14
C15
1uF
R14
U1
IRU3073
150uF
C19
1uF
1K
Q1
IRF7832
HDrv
VP1
D2
BAT54
C10
0.1uF
VREF
L2
3.3uH
C2
33pF
R4
5.1K
OCSet
LDrv
2.5V
@ 8A
R7
C7
2200pF
Comp
C12
1uF
Q2
IRF7832
24K
C9B C9C
330uF
330uF
Rt
SS/SD
R9
2.15K
C6
0.1uF
Fb1
R10
1K
Gnd
PGnd
Figure 17 - Typical application of IRU3073.
Rev. 1.0
09/17/03
www.irf.com
16
IRU3073
DEMO-BOARD APPLICATION
PARTS LIST
Ref Desig Description
Value
30V, 4mΩ
Qty
2
Part#
IRF7832
Manuf
Web site (www.)
Q1,Q2
Q3
U1
MOSFET
MOSFET
Controller
Schottky Diode
Inductor
IR
IR
IR
IR
irf.com
30V, 45mΩ
1
1
1
IRLR2703
IRU3073CQ
BAT54
D2
L1
1µH, 5.6A
3.3µH, 17A
47µF, 16V
1
1
4
DO3316P-102
DO5022P-332HC
16TPB47M
Coilcraft
Coilcraft
Sanyo
coilcraft.com
sanyo.com
L2
Inductor
C1,C2A,B,C Cap, Poscap
C2
C6,C10
C7
Cap, Ceramic
Cap, Ceramic
Cap, Ceramic
Cap, Ceramic
33pF, NPO, 5%
0.1µF, Y5V, 25V
2200pF, X7R, 50V
470pF, X7R, 50V
330µF, 40mΩ
1µF, Y5V, 16V
1
2
1
ECU-V1H330JCV
ECJ-2VF1E104
ECU-V1H222KBV Panasonic
Panasonic maco.panasonic.co.jp
Panasonic
C8
1
2
7
ECJ-2VC1H471J
6TPB330M
ECJ-2VF1C1O5Z
Panasonic
Sanyo sanyo.com
Panasonic maco.panasonic.co.jp
C9B,C9C Cap, Poscap
C11,12,15, Cap, Ceramic
16,19,20,21
C13,C14
R1
Cap, Poscap
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
150µF, 6.3V
10Ω
2
1
3
1
1
1
1
1
6TPB150M
Sanyo
Any
Any
Any
Any
Any
Any
Any
sanyo.com
R2,10,14
R4
R6
1K, 1%
5.1K, 1%
100K
R7
R8
R9
24K, 1%
4.7Ω, 1%
2.15K, 1%
Rev. 1.0
09/17/03
www.irf.com
17
IRU3073
APPLICATION EXPERIMENTAL WAVEFORMS
Figure 18 - Normal condition at no load.
Ch1: HDrv
Figure 19 - Gate signals when SS pin pulls low.
Ch1: HDrv
Ch2: LDrv
Ch2: LDrv
Ch4: Inductor Current
Figure 20 - Soft-Start.
Ch1: VIN (5V)
Ch2: Bias Voltage (12V)
Ch3: VOUT1 (PWM)
Ch4: VOUT2 (LDO)
Rev. 1.0
09/17/03
www.irf.com
18
IRU3073
APPLICATION EXPERIMENTAL WAVEFORMS
Figure 21 - Output Shorted at start-up.
Figure 22 - Load Transient Response (PWM Section).
Ch1: VOUT
Ch4: IOUT
Ch1: VOUT1
Ch4: IOUT1 (0-8A)
Figure 23 - Load Transient Response (LDO Section).
Ch2: VOUT2
Ch4: IOUT2 (0-2A)
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.0
09/17/03
www.irf.com
19
IRU3073
(Q) QSOP Package, Narrow Body
16-Pin
H
A
M
B
D E
DETAIL-A
L
C
PIN NO. 1
DETAIL-A
J
0.36±0.13 x 458
G1
K
F
G
16-PIN
MIN
SYMBOL
MAX
A
B
4.80
0.635 BSC
4.98
C
D
E
0.20
3.81
5.79
1.35
0.10
1.37
0.30
3.99
6.20
1.75
0.25
1.50
F
G
G1
H
J
98 BSC
0.19
08
0.25
88
K
L
0.40
1.27
78±38
M
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 1.0
09/17/03
www.irf.com
20
IRU3073
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
TAPE & REEL
DESIG
DESCRIPTION
COUNT
PER REEL
Orientation
Q
QSOP Plastic, Narrow Body
16
2500
Fig A
1
1
1
Feed Direction
Figure A
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.0
09/17/03
www.irf.com
21
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