OPTIGA TPM SLB 9672 FW15 [INFINEON]
OPTIGA™ TPM SLB 9672 FW15.xx是面向未来的新一代OPTIGA™ TPM系列中的最新产品之一。;
| 型号： | OPTIGA TPM SLB 9672 FW15 |
| 厂家： | 
Infineon |
| 描述： | OPTIGA™ TPM SLB 9672 FW15.xx是面向未来的新一代OPTIGA™ TPM系列中的最新产品之一。 |
| 文件： | 总21页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPTIGA™ TPM
SLB 9672 TPM2.0
Data Sheet
Devices
•
•
SLB 9672VU2.0 FW15.xx
SLB 9672XU2.0 FW15.xx
Key features
•
•
Compliant to TPM Main Specification, Family "2.0", Level 00, Revision 01.59
Certifications:
–
CC, Version 3.1 Rev.5, level EAL4+, AVA_VAN.4 (moderate) according to TCG PC Client TPM Protection
Profile
–
FIPS 140-2 level 2 (physical security level 3) (targeted)
•
•
•
SPI interface
Meeting Intel TXT and Microsoft Windows certification criteria for successful platform qualification
Random Number Generator (RNG) implemented according to NIST SP800-90A using entropy source
according to NIST SP800-90B
•
Full personalization with 3 Endorsement Keys (EK) and 3 EK certificates (RSA 2048, ECC NIST P256, ECC NIST
P384)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Standard (-20..+85°C) and Enhanced temperature range (-40..+85°C)
PG-UQFN-32-1,-2 package
Optimized for battery operated devices: low standby power consumption (typ. 120 µA)
24 PCRs (SHA-1, SHA-256 or SHA384)
51 kByte NV memory
Unlimited amount of NV counters (only depending on NV memory utilization)
Up to 3 loaded sessions (TPM_PT_HR_LOADED_MIN)
Up to 64 active sessions (TPM_PT_ACTIVE_SESSIONS_MAX)
Up to 3 loaded transient Objects (TPM_PT_HR_TRANSIENT_MIN)
Up to 7 loaded persistent Objects (TPM_PT_HR_PERSISTENT_MIN)
Pre-generation of up to 7 RSA key pairs
RSA key generation (1024, 2048, 3072 and 4096 bit)
ECC (NIST P256, BN P256, NIST P384)
SHA1, SHA256, SHA384
Data Sheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Revision 1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
About this document
Scope and purpose
This data sheet describes the OPTIGA™ TPM SLB 9672 TPM2.0 Trusted Platform Module together with its features,
functionality and programming interface.
Intended audience
This data sheet is primarily intended for system developers.
Data Sheet
2
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Table of contents
Table of contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Device types and ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Typical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
TPM properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
5.3
5.4
5.5
6
Package dimensions (UQFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Packing type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
Data Sheet
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OPTIGA™ TPM
SLB 9672 TPM2.0
List of figures
List of figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Pinout of the OPTIGA™ TPM SLB 9672 (PG-UQFN-32-1,-2 package, top view) . . . . . . . . . . . . . . . . . . . . 6
Typical schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package dimensions PG-UQFN-32-1,-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Tape & reel dimensions PG-UQFN-32-1,-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended footprint PG-UQFN-32-1,-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Sheet
4
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OPTIGA™ TPM
SLB 9672 TPM2.0
List of tables
List of tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Not connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Infineon TPM property values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC characteristics of SPI interface pins (SCLK, CS#, MISO, MOSI, RST#, PIRQ#) . . . . . . . . . . . . . . . . . 12
DC characteristics of GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC characteristics of SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Sheet
5
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Overview
1
Overview
The OPTIGA™ TPM SLB 9672 is a Trusted Platform Module. It is available in PG-UQFN-32-1,-2 package. It supports
an SPI interface with a transfer rate of up to 33 MHz (typical). The OPTIGA™ TPM SLB 9672 is a TPM based on TCG
family 2.0 specifications (see [1] and [2]).
This TPM product is targeted to be certified, using the Common Criteria for Information Technology Security
Evaluation (CC), Version 3.1 Rev.5, in the level EAL4+, AVA_VAN.4 (moderate), ALC_FLR.1 according to the
Protection Profile PC Client Specific TPM, TPM Library Specification Family "2.0" Level 0 Revision 1.38
(CERTIFICATE ANSSI-CC-PP-2020/01).
1.1
Power management
In the OPTIGA™ TPM SLB 9672, power management is handled internally; no explicit power-down or standby
mode is available. The device automatically enters a low-power state after each successful command/response
transaction. If a transaction is started on the SPI bus from the host platform, the device will wake immediately
and will return to the low-power mode after the transaction has been finished.
2
Device types and ordering information
The OPTIGA™ TPM SLB 9672 product family features devices using an UQFN package. Table 1 shows the different
versions.
Table 1
Device configuration
Device Name
Package
Remarks
SLB 9672VU2.0 FW15.xx
SLB 9672XU2.0 FW15.xx
PG-UQFN-32-1,-2
PG-UQFN-32-1,-2
Standard temperature range
Enhanced temperature range
3
Pin description
30
26
1
VDD
GND
MISO
GND
VDD
22
GPIO_00
GPIO_01
NCI
TPM
SLB 9672VU2.0
MOSI
CS#
NC
SCLK
PIRQ#
RST#
PG-UQFN-32-1,-2
7
18
GPIO_02
NCI/VDD
10
15
Figure 1
Pinout of the OPTIGA™ TPM SLB 9672 (PG-UQFN-32-1,-2 package, top view)
Data Sheet
6
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Pin description
Table 2
Buffer types
Buffer type
Description
TS
ST
OD
Tri-state pin
Schmitt-trigger pin
Open-drain pin
Table 3
I/O Signals
Pin number
Name
Pin
type
Buffer Function
type
PG-UQFN-32-1,-2
20
CS#
I
ST
Chip select
The SPI chip select signal (active low).
19
SCLK
I
ST
SPI clock
The SPI clock signal. Only SPI mode 0 is supported by the
device.
21
24
18
MOSI
MISO
PIRQ#
I
ST
TS
OD
Master out slave in (SPI data)
SPI data which is received from the master.
O
O
Master in slave out (SPI data)
SPI data which is sent to the SPI bus master.
Interrupt request
Interrupt request signal to the host. The pin has no internal
pull-up resistor. The interrupt is active low.
17
RST#
I
ST
Reset
External reset signal. Asserting this pin unconditionally
resets the device. The signal is active low and is typically
connected to the PCIRST# signal of the host.
This pin has a weak internal pull-up resistor.
3
4
7
GPIO_00 I/O
GPIO_01 I/O
GPIO_02 I/O
TS
TS
TS
General purpose IO
This pin may be left unconnected; it has an internal pull-up
resistor. It can be controlled via TPM NV GPIO functionality.
General purpose IO
This pin may be left unconnected; it has an internal pull-up
resistor. It can be controlled via TPM NV GPIO functionality.
General purpose IO
This pin may be left unconnected; it has an internal pull-up
resistor. It can be controlled via TPM NV GPIO functionality.
Data Sheet
7
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OPTIGA™ TPM
SLB 9672 TPM2.0
Pin description
Table 4
Power supply
Pin number
PG-UQFN-32-1,-2
1, 14, 22
Name
Pin
type
Buffer
type
Function
VDD
PWR
—
Power supply
All VDD pins must be connected externally and should be
bypassed to GND via 100 nF capacitors.
2, 9, 23, 32
GND
GND
—
Ground
All GND pins must be connected externally.
Table 5
Not connected
Name
Pin number
Pin
type
Buffer
type
Function
PG-UQFN-32-1,-2
6, 29, 30
NC
NU
—
—
—
No connect
All pins must not be connected externally (must be left
floating).
5, 10 - 13, 15,
25 - 28, 31
NCI
—
Not connected internally
All pins are not connected internally (can be connected
externally).
8
NCI/VDD
—
Not connected internally/VDD
This pin is not connected internally (can be connected
externally).
Note that pin 8 is defined as VDD in the TCG specification
[2]. To be compliant, VDD can be connected to this pin.
16
NCI/GND
—
—
Not connected internally/GND
This pin is not connected internally (can be connected
externally).
Note that pin 16 is defined as GND in the TCG specification
[2]. To be compliant, GND can be connected to this pins.
Data Sheet
8
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OPTIGA™ TPM
SLB 9672 TPM2.0
Pin description
3.1
Typical schematic
Figure 2 shows the typical schematic for the OPTIGA™ TPM SLB 9672. The power supply pins should be bypassed
to GND with capacitors located close to the device.
3.3V (1.8V)
* if system design does not
assure that CS# is always at
defined levels during power-
on, reset etc.
10k*
3.3V (1.8V)
SCLK
TPM_CS#
MISO
SCLK
VDD
CS#
1 µF
MISO
MOSI
MOSI
GND
2x 100 nF (place close to
device VDD/GND pins)
PIRQ#
PIRQ#
RST#
RESET#
GPIO_00
GPIO_01
GPIO_02
NC/NCI
SLB 9672
Schematic_SLB9672.vsd
Figure 2
Typical schematic
Data Sheet
9
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
TPM properties
4
TPM properties
Properties defined within the TPM can be read with the command TPM2_GetCapability. The values are vendor
dependent or determined by a platform-specific specification. The following properties are returned by the
Infineon
OPTIGA™ TPM SLB 9672
using
the
command
TPM2_GetCapability
(capability =
TPM_CAP_TPM_PROPERTIES):
Table 6
Infineon TPM property values
TPM_PT_MANUFACTURER
TPM_PT_VENDOR_STRING_1
TPM_PT_VENDOR_STRING_2
TPM_PT_VENDOR_STRING_3
TPM_PT_VENDOR_STRING_4
TPM_PT_FIRMWARE_VERSION_1
“IFX”
“SLB9”
“672”
NULL
NULL
Major and minor version (for instance, 0x000F0015
indicates V15.21)1)
TPM_PT_FIRMWARE_VERSION_2
Build number and Common Criteria certification state (for
instance, 0x00402E00 or 0x00402E02)1)
Byte 1: reserved for future use (0x00)
Byte 2 and 3: Build number (for instance, 0x402E)1)
Byte 4: Common Criteria certification state/mode:
0x00 = TPM operational mode/TPM is CC certified
0x02 = TPM operational mode/TPM is not certified
0x60 = Manually entered TPM firmware recovery mode
(triggered externally for testing purposes)
0x61 = TPM firmware recovery mode (triggered by code
integrity failure detection)
0x62 = TPM firmware update mode
TPM_PT_MODES
Bit 0 (FIPS_140_2) = 1
Bits 1..31 = 0
1) The build- and version numbers given here are examples and do not necessarily match the numbers of the device this
data sheet has been provided for.
Data Sheet
10
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2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Electrical characteristics
5
Electrical characteristics
This chapter lists the maximum and operating ranges for various electrical and timing parameters.
5.1
Absolute maximum ratings
Table 7
Absolute maximum ratings
Symbol
Parameter
Values
Min. Typ. Max.
Unit
Note or Test Condition
Supply Voltage
VDD
-0.3
-0.5
-20
-40
-40
–
–
–
–
–
–
–
4.1
4.1
85
V
–
Voltage on any pin
Ambient temperature
Ambient temperature
Storage temperature
Vmax
TA
V
–
°C
°C
°C
V
Standard temperature devices
Enhanced temperature devices
–
TA
85
TS
125
2000
ESD robustness HBM:
VESD,HBM
According to EIA/JESD22-A114-B
1.5 kΩ, 100 pF
ESD robustness
VESD,CDM
–
–
500
100
V
According to ESD Association
Standard STM5.3.1 - 1999
Latchup immunity
Ilatch
mA
According to EIA/JESD78
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible
damage to the integrated circuit.
5.2
Functional operating range
Table 8
Functional operating range
Symbol
Parameter
Values
Min. Typ. Max.
Unit
Note or Test Condition
Supply Voltage
VDD
3.0
1.65
-20
-40
–
3.3
1.8
–
3.6
1.95
85
85
10
10
–
V
–
V
–
Ambient temperature
Ambient temperature
Useful lifetime
TA
TA
°C
°C
y
Standard temperature devices
Enhanced temperature devices
–
–
Operating lifetime
Average TA over lifetime
–
–
y
–
55
°C
Data Sheet
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OPTIGA™ TPM
SLB 9672 TPM2.0
Electrical characteristics
5.3
DC characteristics
TA = 25°C, VDD = 3.3 V ± 0.3 V or VDD = 1.8 V ± 0.15 V unless otherwise noted.
Table 9
Current consumption
Symbol
Parameter
Values
Min. Typ. Max.
35
Unit
Note or Test Condition
Current Consumption in IVDD_Active
Active Mode
mA
µA
Current Consumption in IVDD_Sleep
Sleep Mode
120
130
Pins GPIO, RST# and PIRQ# = VDD
CS# inactive (= VDD), MOSI, MISO
and SCLK don't care
,
Current Consumption
during reset
IVDD_Reset
µA
Pin RST# active (= GND), GPIO,
PIRQ#, CS#, MOSI, MISO and SCLK
don't care
Note:
Note:
Current consumption does not include any currents flowing through resistive loads on output pins!
Device sleep mode will be entered after 50 milliseconds of inactivity after the last TPM command was
executed.
Table 10 DC characteristics of SPI interface pins (SCLK, CS#, MISO, MOSI, RST#, PIRQ#)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Input voltage high
VIH
0.7 VDD
VDD+0.5
V
VDD,typ = 3.3 V, only pins SCLK,
MISO, MOSI and CS#
0.7 VDD
0.7 VDD
-0.5
VDD+0.3
VDD+0.3
0.3 VDD
0.3 VDD
4
V
VDD,typ = 3.3 V, pin RST#
VDD,typ = 1.8 V
V
Input voltage low
VIL
V
VDD,typ = 3.3 V
-0.3
V
VDD,typ = 1.8 V
Input leakage current
ILEAK
-4
µA
mA
0 V < VIN < VDD
-4.5
Pins SCLK, CS#, MISO, MOSI
-0.5 V < VIN < VDD+0.5 V
VDD,typ = 3.3 V
-4.5
mA
µA
Pins SCLK, CS#, MISO, MOSI
-0.3 V < VIN < VDD+0.3 V
VDD,typ = 1.8 V
-2
2
Pin RST#
0 V < VIN < VDD
Output high voltage
Output low voltage
Pad input capacitance
VOH
VOL
CIN
0.9 VDD
V
IOH = -100 µA
IOL = 1.5 mA
0.1 VDD
10
V
pF
pF
Output load capacitance CLOAD
30
Data Sheet
12
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Electrical characteristics
Table 11 DC characteristics of GPIO pins
Parameter
Symbol
Values
Unit
Note or Test Condition
Min.
0.7 VDD
-0.5
Typ. Max.
Input voltage high
Input voltage low
VIH
VDD+0.3
V
Pins GPIO
VIL
0.3 VDD
2
V
Pins GPIO
Input leakage current
Output high voltage
Output low voltage
Pad input capacitance
ILEAK
VOH
VOL
CIN
-2
µA
V
0 V < VIN < VDD
IOH = -1 mA, pins GPIO
IOL = 1 mA, pins GPIO
Pins GPIO
VDD-0.3
0.3
10
V
pF
5.4
AC characteristics
TA = 25°C, VDD = 3.3V ± 0.3V or VDD = 1.8V ± 0.15V unless otherwise noted.
Table 12 Power supply
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Supply voltage rise time tVDDR
1.0
V/ns
Table 13 Device reset
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
80
Max.
Cold (Power-On) Reset
Warm Reset
tPOR
µs
µs
tWRST
2
tPOR
VDD
tWRST
tWRST
RST#
RST_Timing.vsdx
Figure 3
Reset timing
Table 14 AC characteristics of SPI interface
Parameter
Symbol
Values
Typ.
33
Unit Note or Test Condition
Min.
Max.
SCLK frequency
SCLK period
fCLK
tCLK
34.65
MHz
1/fCLK
5%
-
1/fCLK
1/fCLK
5%
+
µs
Rising edge to rising edge,
measured at VIN = 0.5 VDD
Data Sheet
13
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Electrical characteristics
Table 14 AC characteristics of SPI interface (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
SCLK low time
SCLK high time
tCLKL
tCLKH
tSLEW
0.45 tCLK
µs
µs
Falling edge to rising edge,
measured at VIN = 0.5 VDD
0.45 tCLK
0.216
0.4
Rising edge to falling edge,
measured at VIN = 0.5 VDD
SCLK slew rate
(rising/falling)
4
4
V/ns fCLK < 20 MHz, between 0.2 VDD and
0.6 VDD
V/ns fCLK ≥ 20 MHz, between 0.2 VDD and
0.6 VDD
CS# high time
CS# setup time
tCS
50
60
ns
ns
Rising edge to falling edge
DD,typ = 1.8 V and tSLEW < 1 V/ns,
rising edge to falling edge, TPM
protocol abort only
V
tCSS
5
7
ns
ns
CS# falling edge to SCLK rising
edge
VDD,typ = 1.8 V and tSLEW < 1 V/ns,
CS# falling edge to SCLK rising
edge
CS# hold time
tCSH
tSU
tH
5
2
3
0
0
0
ns
ns
ns
ns
SCLK falling edge to CS# rising
edge
MOSI setup time
MOSI hold time
MISO hold time
MISO valid delay time
MISO active time
Data setup time to SCLK rising
edge
Data hold time from SCLK rising
edge
tHO
tV
Output hold time from SCLK
falling edge
0.7 tCLKL ns
ns
Output valid delay from SCLK
falling edge
tDRV
Delay from chip select assertion to
driving of MISO
5.5
Timing
Some pads are disabled after deassertion of the reset signal for up to 500 µs.
The OPTIGA™ TPM SLB 9672 features security mechanisms which detect and count all resets.
Data Sheet
14
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Package dimensions (UQFN)
6
Package dimensions (UQFN)
All dimensions are given in millimeters (mm) unless otherwise noted. The packages are “green” and RoHS
compliant.
Figure 4
Package dimensions PG-UQFN-32-1,-2
6.1
Packing type
PG-UQFN-32-1,-2: Tape & Reel (reel diameter 330mm), 5000 pcs. per reel
8
PIN 1
INDEX MARKING
4
0.3
5.25
0.8
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 5
Tape & reel dimensions PG-UQFN-32-1,-2
Data Sheet
15
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Package dimensions (UQFN)
6.2
Recommended footprint
Figure 6 shows the recommended footprint for the package. The exposed pad of the package is internally
connected to GND. It shall be connected to GND externally as well.
Figure 6
Recommended footprint PG-UQFN-32-1,-2
6.3
Chip marking
Line 1: SLB9672
Line 2: VU20 yy or XU20 yy (see Table 1), the <yy> is an internal FW indication (only at manufacturing due to field
upgrade option)
Line 3: <Lot number> H <datecode>
Infineon
1234567
VU20 YY
Softwarecode
XXH
Lot Code
ChipMarking_UQFN.vsd
Figure 7
Chip marking
For details and recommendations regarding assembly of packages on PCBs, please refer to
http://www.infineon.com/cms/en/product/technology/packages/
Data Sheet
16
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
References
References
[1] —, “Trusted Platform Module Library (Part 1-4)”, Family 2.0, Level 00, Rev. 01.59, November 8, 2019, TCG
[2] —, “TCG PC Client Platform TPM Profile (PTP) Specification”, Family 2.0, Level 00, Rev. 01.05 v14,
September 4, 2020, TCG
[3] —, “Errata For TCG Trusted Platform Libary, Family 2.0, Level 00, Rev. 01.59, November 8, 2019”, Errata
Version 1.1, June 18, 2020, TCG
[4] —, “Errata for PC Client Platform TPM Profile for TPM 2.0 Version 1.05 Revision 14”, Errata Version 1.0,
September 04, 2020, TCG
[5] —, “Registry of reserved TPM 2.0 handles and localities”, Version 1.1, Rev. 1.00, February 6, 2019, TCG
[6] —, “TCG EK Credential Profile”, Version 2.3, Rev. 2, July 23, 2020, TCG
[7] —, "NIST Special Publication 800-193, Platform Firmware Resiliency Guidelines", May, 2018, NIST
Data Sheet
17
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Terminology
Terminology
ESW
HMAC
PCR
Embedded Software
Hashed Message Authentication Code
Platform Configuration Register
Public Endorsement Key
PUBEK
SPI
Serial Peripheral Interface (bus)
Trusted Computing Group
Trusted Platform Module
TCG Software Stack
TCG
TPM
TSS
Data Sheet
18
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Licenses and notices
Licenses and notices
The following license and notice statements are reproduced from [1].
Licenses and Notices
1. Copyright Licenses:
Trusted Computing Group (TCG) grants to the user of the source code in this specification (the "Source Code") a
worldwide, irrevocable, nonexclusive, royalty free, copyright license to reproduce, create derivative works,
distribute, display and perform the Source Code and derivative works thereof, and to grant others the rights
granted herein.The TCG grants to the user of the other parts of the specification (other than the Source Code) the
rights to reproduce, distribute, display, and perform the specification solely for the purpose of developing
products based on such documents.
2. Source Code Distribution Conditions:
Redistributions of Source Code must retain the above copyright licenses, this list of conditions and the following
disclaimers.
Redistributions in binary form must reproduce the above copyright licenses, this list of conditions and the
following disclaimers in the documentation and/or other materials provided with the distribution.
3. Disclaimers:
THE COPYRIGHT LICENSES SET FORTH ABOVE DO NOT REPRESENT ANY FORM OF LICENSE OR WAIVER, EXPRESS
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, WITH RESPECT TO PATENT RIGHTS HELD BY TCG MEMBERS (OR
OTHER THIRD PARTIES) THAT MAY BE NECESSARY TO IMPLEMENT THIS SPECIFICATION OR OTHERWISE. Contact
TCG Administration (admin@trustedcomputinggroup.org) for information on specification licensing rights
available through TCG membership agreements.
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO EXPRESS OR IMPLIED WARRANTIES WHATSOEVER,
INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ACCURACY,
COMPLETENESS, OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS, OR ANY WARRANTY OTHERWISE
ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
Without limitation, TCG and its members and licensors disclaim all liability, including liability for infringement of
any proprietary rights, relating to use of information in this specification and to the implementation of this
specification, and TCG disclaims all liability for cost of procurement of substitute goods or services, lost profits,
loss of use, loss of data or any incidental, consequential, direct, indirect, or special damages, whether under
contract, tort, warranty or otherwise, arising in any way out of use or reliance upon this specification or any
information herein.
Any marks and brands contained herein are the property of their respective owners.
Data Sheet
19
Revision1.1
2022-01-20
OPTIGA™ TPM
SLB 9672 TPM2.0
Revision history
Page or item
Subjects (major changes since previous revision)
Revision 1.1, 2022-01-20
Changed Figure 2 (added pull-up resistor).
Revision 1.0, 2022-01-12
Initial document version.
Data Sheet
20
Revision1.1
2022-01-20
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
The information given in this document shall in no For further information on technology, delivery terms
Edition 2022-01-20
Published by
Infineon Technologies AG
81726 Munich, Germany
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest
characteristics ("Beschaffenheitsgarantie").
Infineon Technologies Office (www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
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intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
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information given in this document with respect to
such application.
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All Rights Reserved.
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dangerous substances. For information on the types
in question please contact your nearest Infineon
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