Q67007-A9466_技术文档

TLE 6361 G

Multi-Voltage Processor Power Supply

Data Sheet

1

Overview

Features

1.1

• High efficiency regulator system

• Wide input voltage range, up to 60V

• Stand-by mode with low current consumption

• Suitable for standard 12V, 24V and 42V PowerNets

• Step down converter as pre-regulator:

5.5V / 1.5A

P-DSO-36-12

• Step down slope control for lowest EME

• Switching loss minimization

• Three high current linear post-regulators with

selectable output voltages:

5V / 800mA

3.3V or 2.6V / 500mA

5V or 3.3V / 350mA

• Six independent voltage trackers (followers):

5V / 17mA each

• Stand-by regulator with 1mA current capability

• Three independent undervoltage detection circuits

(e.g. reset, early warning) for each linear post-regulator

• Power on reset functionality

• Window watchdog triggered by SPI

• Tracker control and diagnosis by SPI

• All outputs protected against short-circuit

• Power-DSO-36 package

Type

Ordering Code Package

Q 67007-A9466 P-DSO-36-12

TLE 6361 G

SMD = Surface Mounted Device

Data Sheet, Rev. 1.31

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TLE 6361 G

1.2

Short functional description

The TLE 6361 G is a multi voltage power supply system especially designed for

automotive applications using a standard 12V or 24V battery as well as the new 42V

powernet. The device is intended to supply 32 bit micro-controller systems which require

different supply voltage rails such as 5V, 3.3V and 2.6V. The regulators for external

sensors are also provided.

The TLE 6361 G cascades a Buck converter block with a linear regulator and tracker

block on a single chip to achieve lowest power dissipation thus being able to power the

application even at very high ambient temperatures.

The step-down converter delivers a pre-regulated voltage of 5.5V with a minimum

current capability of 1.5A.

Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V,

or 2.6V of output voltages depending on the configuration of the device with current

capabilities of 800mA, 500mA and 350mA.

In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Their

outputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able to

drive a current of 17mA each. The trackers can be turned on and off individually by a 16

bit serial peripheral interface (SPI). Through this interface also the status information of

each tracker (i.e. short circuit) can be read out.

To monitor the output voltage levels of each of the linear regulators three independent

undervoltage detection circuits are available which can be used to implement the reset

or an early warning function. The supervision of the µC is managed by the SPI-triggered

window watchdog.

For energy saving reasons while the motor is turned off, the TLE 6361 G offers a stand-

by mode, where the quiescent current does not exceed 30µA typically. In this stand-by

mode just the stand-by regulator remains active.

The TLE 6361 G is based on Infineon Power technology SPT  which allows bipolar ,

CMOS and Power DMOS circuitry to be integrated on the same monolithic circuitry.

Data Sheet, Rev. 1.31

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TLE 6361 G

1.3

Pin configuration

P-DSO-36-12

GND

CLK

CS

GND

1

2

3

4

5

6

7

36

35

34

33

32

31

30

29

SLEW

WAKE

BOOST

DI

DO

IN

ERR

SW

IN

Q_STB

SW

Q_T1

Q_T2

Q_T3

8

28

27

Bootstrap

9

10

11

12

13

14

15

16

Q_LDO1

FB/L_IN

Q_LDO2

SEL

Q_T4

Q_T5

26

25

24

23

22

21

20

19

Q_T6

Q_LDO3

CCP

R3

R2

C+

C-

R1

17

18

GND

Figure 1 Pin Configuration (Top View),

bottom heatslug and GND corner pins are connected

Data Sheet, Rev. 1.31

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TLE 6361 G

1.4

Pin definitions and functions

Pin No. Symbol

Function

1,18,19, GND

36

Ground; to reduce thermal resistance place cooling areas on

PCB close to this pins. Those pins are connected internally to the

heatslug at the bottom.

2

3

CLK

CS

SPI Interface Clock input; clocks the shiftregister; CLK has an

internal active pull down and requires CMOS logic level

inputs;see also chapter SPI

SPI Interface chip select input; CS is an active low input; serial

communication is enabled by pulling the CS terminal low; CS

input should only be switched when CLK is low; CS has an

internal active pull up and requires CMOS logic level inputs ;see

also chapter SPI

4

5

DI

SPI Interface Date input; receives serial data from the control

device; serial data transmitted to DI is a 16 bit control word with

the Least Significant Bit (LSB) being transferred first; the input

has an active pull down and requires CMOS logic level inputs; DI

will accept data on the falling edge of CLK-signal; see also

chapter SPI

SPI Interface Data output; this tristate output transfers

diagnosis data to the controlling device; the output will remain 3-

stated unless the device is selected by a low on Chip-Select CS;

see also the chapter SPI

DO

6

7

8

ERR

Error output; push-pull output. Monitors failures in parallel to the

SPI diagnosis word, reset via SPI. ERR is a latched output.

Q_STB

Q_T1

Standby Regulator Output; the output is active even when the

buck regulator and all other circuitry is in off mode

Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by

SPI command. Keep open, if not needed.

9

Q_T2

Q_T3

Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by

SPI command. Keep open, if not needed.

Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by

SPI command. Keep open, if not needed.

10

Data Sheet, Rev. 1.31

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TLE 6361 G

1.4

Pin definitions and functions (cont’d)

Function

Pin No. Symbol

11

12

13

14

15

16

17

Q_T4

Q_T5

Q_T6

Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by

SPI command. Keep open, if not needed.

Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by

SPI command. Keep open, if not needed.

Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by

SPI command. Keep open, if not needed.

Q_LDO3 Voltage Regulator Output 3; 5V or 3.3V output; ouput voltage

is selected by pin SEL (see also 3.4.2); For stability a ceramic

capacitor of 470nF to GND is sufficient.

R3

R2

R1

Reset output 3, undervoltage detection for output Q_LDO3;

open collector output; an external pullup resistor of 10kΩ is

required

Reset output 2, undervoltage detection for output Q_LDO2;

open collector output; an external pullup resistor of 10kΩ is

required

Reset output 1, undervoltage detection for output Q_LDO1 and

watchdog failure reset; open collector output ; an external pullup

resistor of 10kΩ is required

20

21

22

23

24

C-

Charge pump capacitor connection; Add the fly-capacitor of

100nF between C+ and C-

C+

Charge pump capacitor connection; Add the fly-capacitor of

100nF between C+ and C-

CCP

SEL

Charge Pump Storage Capacitor Output; Add the storage

capacitor of 220nF between pin CCP and GND.

Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3

(see also 2.2.2)

Q_LDO2 Voltage Regulator Output 2; 3.3V or 2.6V output; output

voltage is selected by pin SEL (see also 3.4.2); For stability a

ceramic capacitor of 470nF to GND is sufficient.

25, 26

FB/L_IN

Feedback and Linear Regulator Input; input connection for

the Buck converter output

Data Sheet, Rev. 1.31

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TLE 6361 G

1.4

Pin definitions and functions (cont’d)

Function

Pin No. Symbol

27

Q_LDO1 Voltage Regulator Output 1; 5V output; acts as the reference

for the voltage trackers.The SPI and window watchdog logic is

supplied from this voltage. For stability a ceramic capacitor of

470nF to GND is sufficient.

28

Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW

and pin Bootstrap, the capcitance value should be not lower

than 2% of the Buck converter output capacitance

29, 31

SW

Switch Output; connect both pins externally through short lines

directly to the cathode of the catch diode and the Buck circuit

inductance.

30, 32

33

IN

Supply Voltage Input; connect both pins externally through

short lines to the input filter/the input capacitors.

BOOST

Boost Input; for switching loss minimization connect a diode

(cathode directly to boost pin) in series with a 100nF ceramic

capacitor to the IN pin and from the anode of the diode to the

buck converter output a 22Ω resistor. Recommended for 42V

applications, in 12/24V applications connect boost directly to IN

34

35

WAKE

SLEW

Wake Up Input; a positive voltage applied to this pin turns on

the device

Slew control Input; a resistor to GND defines the current slope

in the buck switch for reduced EME

Data Sheet, Rev. 1.31

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TLE 6361 G

1.5

Basic block diagram

TLE 6361

Standby

Regulator

2.5V

Q_STB

Boost

SW

2*

IN

2*

BUCK

REGULATOR

Slew

Bootstrap

Driver

PWM

Internal

Error-

Amplifier

Reference

OSZ

feedback

FB/L_IN

2*

C+

C-

Charge

Pump

CCP

Protection

Power

Down

Logic

Wake

R1

SEL

Q_LDO1

Linear

Reg. 1

µ-controller /

memory

Reset

Logic

R2

R3

Q_LDO2

Q_LDO3

Linear

Reg. 2

supply

Linear

Reg. 3

ref

Q_T1

Q_T2

Q_T3

Q_T4

Q_T5

Q_T6

Tracker

5V

Window

Watchdog

ref

Tracker

5V

ref

CLK

CS

Tracker

5V

Sensor

supplies

(off board

supplies)

ref

Tracker

5V

SPI

16 bit

ref

DI

Tracker

5V

ref

DO

ERR

Tracker

5V

GND

4*

Figure 2 Block Diagram

Data Sheet, Rev. 1.31

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TLE 6361 G

2

Detailed circuit description

In the following major buck regulator blocks, the linear voltage regulators and trackers,

the undervoltage reset function, the watchdog and the SPI are described in more detail.

For applications information e.g. choice of external components, please refer to

section .

2.1

Buck Regulator

The diagram below shows the internal implemented circuit of the Buck converter, i. e. the

internal DMOS devices, the regulation loop and the other major blocks.

IN

5V

14V

Int. voltage

regulator

Int. charge

pump

150µA

to

8 to 10V

current sense

amplifier

FB/L_IN

C+

C-

CCP

Gate driver

Main switch ON/OFF

Main

DMOS

IN

under-

voltage

lockout

SW

BOOT-

STRAP

Slope switch

charge signal

BOOST

SW

switching frequency 330kHz

Divider

Slope

DMOS

Slope switch

discharge signal

Oscillator

1.4MHz

Slope

compensation

Gate off signal

from overtemp or

sleep command

Trigger for

gate on

Lowpass

Voltage

feedback

amplifier

Zero cross

detection

PWM logic

Slope logic

Delay unit

Current

comparator

Trigger for

gate off

Vref=6V

Current

sense

from

+

current sensing

amplifier

Slope

control

SLEW

external components

pins

Figure 3 Detailed Buck regulator diagram

The 1.5A Buck regulator consists of two internal DMOS power stages including a current

mode regulation scheme to avoid external compensation components plus additional

blocks for low EME and reduced switching loss. Figure 3 indicates also the principle how

Data Sheet, Rev. 1.31

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TLE 6361 G

the gate driver supply is managed by the combination of internal charge pump, external

charge pump and bootstrap capacitor.

2.1.1

Current mode control scheme

The regulation loop is located at the left lower corner in the schematic, there you find the

voltage feedback amplifier which gives the actual information of the actual output voltage

level and the current sense amplifier for the load current information to form finally the

regulation signal. To avoid subharmonic oscillations at duty cycles higher than 50% the

slope compensation block is necessary.

The control signal formed out of those three blocks is finally the input of the PWM

regulator for the DMOS gate turn off command, which means this signal determines the

duty cycle. The gate turn on signal is set by the oscillator periodically every 3µs which

leads to a Buck converter switching frequency around 330kHz.

With decreasing input voltage the device changes to the so called pulse skipping mode

which means basically that some of the oscillator gate turn off signals are ignored. When

the input voltage is still reduced the DMOS is turned on statically (100% duty cycle) and

its gate is supplied by the internal charge pump. Below typical 4.5V at the feedback pin

the device is turned off.During normal switching operation the gate driver is supplied by

the bootstrap capacitor.

2.1.2

Start-up procedure

To guarantee a device startup even under full load condition at the linear regulator

outputs a special start up procedure is implemented. At first the bootstrap capacitor is

charged by the internal charge pump. Afterwards the outpuput capacitor is charged

where the driver supply in that case is maintained only by the bootstrap capacitor. Once

the output capacitor of the buck converter is charged the external charge pump is

activated being able to supply the linear regulators and finally the linear regulators are

released to supply the loads.

2.1.3

Reduction of electromagnetic emission

In figure 3 it is recognized that two internal DMOS switches are used, a main switch and

an auxiliary switch. The second implemented switch is used to adjust the current slope

of the switching current. The slope adjustment is done by a controlled charge and

discharge of the gate of this DMOS. By choosing the external slew resistor appropriate

the current transition time can be adjusted between 20ns and 100ns.

2.1.4

Reducing the switching losses

The second purpose of the slope DMOS is to minimise the switching losses. Once being

in freewheeling mode of the buck regulator the output voltage level is sufficient to force

the load current to flow, the input voltage level is not needed in the first moment. By a

feedback network consisting of a resistor and a diode to the boost pin (connection see

Data Sheet, Rev. 1.31

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TLE 6361 G

section ) the output voltage level is present at the drain of the switch. As soon as the

voltage at the SW pin passes zero volts the handover to the main switch occurs and the

traditional switching behaviour of the Buck switch can be observed.

2.2

Linear Voltage Regulators

The Linear regulators offer voltage rails of 5V, 3.3V and 2.6V which can be determined

by a hardware connection (see table at 2.2.2) for proper power up procedure. Being

supplied by the output of the Buck pre-regulator the power loss within the three linear

regulators is minimized.

All voltage regulators are short circuit protected which means that each regulator

provides a maximum current according to its current limit when shorted. Together with

the external charge pump the NPN pass elements of the regulators allow low dropout

voltage operation. By using this structure the linear regulators work stable even with a

minimum of 470nF ceramic capacitors at their output.

Q_LDO1 has 5V nominal output voltage, Q_LDO2 has a hardware programmable

output voltage of 3.3V or 2.6V and Q_LDO3 is programmable to 5V or 3.3V (see 2.2.2).

All three regulators are on all the time, if one regulator is not needed a base load resistor

in parallel to the output capacitance for controlled power down is recommended.

2.2.1

Startup Sequence Linear Regulators

When acting as 32 bit µC supply the so-called power sequencing (the dependency of the

different voltage reails to each other) is important. Within the TLE 6361 G the following

Startup-Sequence is defined (see also figure 4):

V

_{Q_LDO2}≤ V_{Q_LDO1;}

and

_{Q_LDO2}≤ V_{Q_LDO1}with V_{Q_LDO1}=5V, V_{Q_LDO2}= 2.6V/3.3V and V_{Q_LDO3}= 5V

V_{Q_LDO3}≤ V_{Q_LDO1}with V_{Q_LDO1}=5V, V_{Q_LDO2}= 2.6V and V_{Q_LDO3}= 3.3V

V

The power sequencing refers to the regulator itself, externally voltages applied at

Q_LDO2 and Q_LDO3 are not pulled down actively by the device if Q_LDO1 is lower

than those outputs.

That means for the power down sequencing if different output capacitors and different

loads at the three outputs of the linear regulators are used the voltages at Q_LDO2 and

Q_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid this

behaviour three Schottky diodes have to be connected between the three outputs of the

linear regulators in that way that the cathodes of the diodes are always connected to the

higher nominal rail.

Data Sheet, Rev. 1.31

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TLE 6361 G

Power Sequencing

V_{FB/L_IN}

V_{LDO_EN}

t

V_{Q_LDO1}

5V

V_Rth5

3.3V

2.6V

V_{Q_LDO2}(2.6V Mode)

0.7V

5V LDO

2.6V

V_Rth2.6

0.7V

t

V_{Q_LDO3}(3.3V Mode)

5V LDO

+/- 50mV

5V LDO

3.3V

V_Rth3.3

+/- 50mV

t

Figure 4 Power-up and -down sequencing of the regulators

2.2.2

Q_LDO2 and Q_LDO3 output voltage selection*

To determine the output voltage levels of the three linear regulators, the selection pin

(SEL, pin 23) has to be connected according to the matrix given in the table below.

Definition of Output voltage Q_LDO2 and Q_LDO3

Select Pin SEL Q_LDO2

Q_LDO3

connected to

output voltage output voltage

GND

3.3 V

2.6 V

5 V

Q_LDO1

Q_LDO2

3.3 V

5 V

* for different output voltages please refer to the multi voltage supply TLE6368

Data Sheet, Rev. 1.31

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TLE 6361 G

2.3

Voltage Trackers

For off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA output

current capability each are available. The output voltages match Q_LDO1 within

+5 / -15mV. They can be individually turned on and off by the appropriate SPI command

word sent by the microcontroller. A ceramic capacitor with the value of 1µF at the output

of each tracker is sufficient for stable operation without oscillation.

The tracker outputs can be connected in parallel to obtain a higher output current

capability, no matter if only two or up to all six trackers are tied together. For uniformly

distributed current density in each tracker internal balance resistors at each output are

foreseen internally. By connecting twice three trackers in parallel two sensors with more

than 50mA each can be supplied, all six in parallel give more than 100mA.

The tracker outputs can withstand short circuits to GND or battery in a range from -5 to

+60V. A short circuit to GND at is detected and indicated individually for each tracker in

the SPI status word. Also an open load condition might be recognised and indicated as

a failure condition in the SPI status word. A minimum load current of 2mA is required to

avoid open load failure indication. In case of connecting several trackers to a common

branch balancing currents can prevent proper operation of the failure indication.

2.4

Standby Regulator

The standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA output

current which is on all the time. It is intended to supply the microcontroller in stop mode

and requires then only a minimum of quiescent current (<30µA) to extend the battery

lifetime.

2.5

Charge Pump

The 1.6 MHz charge pump with the two external capacitors will serve to supply the base

of the NPN linear regulators Q_LDO1 and Q_LDO3 as well as the gate of the Buck

DMOS transistor in 100% duty cycle operation at low battery condition. The charge pump

voltage in the range of 8 to 10V can be measured at pin 22 (CCP) but is not intended to

be used as a supply for additional circuitry.

2.6

Power On Reset

A power on reset is available for each linear voltage regulator output. The reset output

lines R1, R2 and R3 are active (low) during start up and turn inactive with a reset delay

time after Q_LDO1, Q_LDO2 and Q_LDO3 have reached their reset threshold. The

reset outputs are open collector, three pull up resistors of 10kΩ each have to be

connected to the I/O rail (e.g. Q_LDO1) of the µC. All three reset outputs can be linked

in parallel to obtain a wired-OR.

The reset delay time is 64 ms by default and can be set to lower values as 8 ms, 16 ms

or 32 ms by SPI command. At each power up of the device when the output voltage at

Data Sheet, Rev. 1.31

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TLE 6361 G

Q_LDO1 has decreased below 3.3V (max.) the default settings are valid, means the

64ms delay time. If the voltage on Q_LDO1 during sleep or power off mode was kept

above 3.3V the delay time set by the last SPI command is valid.

V_{FB/L_IN}

< t_rr

t

V_{Q_LDOx}

V_{RTH,Q_LDOx}

t_rr

t

t_RES

V_Rx

t_RES

thermal

under

over

load

shutdown

voltage

Figure 5 Undervoltage reset timing

2.7 RAM good flag

A RAM good flag will be set within the SPI status word when the Q_LDO1 voltage drops

below 2.3V. A second one will be set if Q_LDO2 drops below typical 1.4V. Both RAM

good flags can be read after power up to determine if a cold or warm start needs to be

processed. Both RAM good flags will be reset after each SPI cycle.

2.8

ERR Pin

An hardware error pin indicates any fault conditions on the chip. It should be connected

to an interrupt input of the microcontroller. A low signal indicates an error condition. The

microcontroller can read the root cause of the error by reading the SPI register.

2.9

Window Watchdog

The on board window watchdog for supervision of the µC works in combination with the

SPI. The window watchdog logic is triggered when CS is low and Bit WD-Trig in the SPI

command word is set to “1”. The watchdog trigger is recognized with the low to high

transition of the CS signal. To allow reading the SPI at any time without getting a reset

due to misinterpretation the WD-Trig bit has to be set to “0” to avoid false trigger

conditions. To disable the window watchdog the WD-OFF bits need to be set to “010”.

Data Sheet, Rev. 1.31

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TLE 6361 G

t_SR= t_OW/2

t_WDR= t_RES

t_CW=t_CW

t_OW=t_CW

(not the same scale)

closed window

open window

reset delay time without trigger

definition

reset start delay time after window

watchdog timeout

reset duration time after window

watchdog time-out

t_ECW

t

_EOW= end of open window

Example with:

t_CW=128ms

f_OSC=f_OSCmaxt _{EOW, w.c.}= ( t_CW+t_OW)(1-∆)

∆=25% (oscillator deviation)

worst cases

f_OSC=f_OSCmint _{ECW, w.c.}= t_CW(1+∆)

t_{ECW, w.c.}= 128(1.25) = 160ms

t_{EOW, w.c}= (128+128)(0.75) = 192ms

t_owmin

= 32ms

t _OWmin

Minimum open window time: t _OWmin= t_OW- ∆ * ( t_OW+ 2* t_CW

)

Figure 6 Window watchdog timing definition

Figure 6 shows some guidelines for designing the watchdog trigger timing taking the

oscillator deviation of different devices into account. Of importance is the maximum

(w.c.) of the closed window and the minimum of the open window in which the trigger has

to occur.

The length of the OW and CW can be modified by SPI command. If a change of the

window length is desired during the Watchdog function is operating please send the SPI

command with the new timing with a ’Watchdog trigger Bit’ D15=1.In this case the next

CW will directly start with the new length.

A minimum time gap of > 1/48 of the actual OW/CW time between a ’Watchdog disable’

and ’Watchdog enable’ SPI-command should be maintained. This allows the internal

Watchdog counters to be resetted. Thus after the enable command the Watchdog will

start properly with a full CW of the adjusted length.

Data Sheet, Rev. 1.31

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TLE 6361 G

Perfect triggering after Power on Reset

V_{Q_LDO1}

V_Rth1

1V

t

t_RES

R1

t_CW

t_SR

Watchdog

window

CW

OW

CW

OW

CW

OW

CS

with WD-

trig=1

ERR

Incorrect triggering

Watchdog

window

CW

OW

t

CS

with WD-

trig=1

1)

2)

1) Pretrigger

2) Missing trigger

Legend:

OW = Open window

CW = Closed window

Figure 7 Window watchdog timing

Figure 7 gives some timing information about the window watchdog. Looking at the

upper signals the perfect triggering of the watchdog is shown. When the 5V linear

regulator Q_LDO1 reaches its reset threshold, the reset delay time has to run off before

Data Sheet, Rev. 1.31

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TLE 6361 G

the closed window (CW) starts. Then three valid watchdog triggers are shown, no effect

on the reset line and/or error pin is observed. With the missing watchdog trigger signal

the error signal turns low immediately where the reset is asserted after another delay of

half the closed window time.

Also shown in the figure are two typical failure modes, one pretrigger and one missing

signal. In both cases the error signal will go low immediately the failure is detected with

the reset following after the half closed window time.

2.10

Overtemperature Protection

At a chip temperature of more than 130° an error and temperature flag is set and can be

read through the SPI. The device is switched off if the device reaches the

overtemperature threshold of 170°C. The overtemperature shutdown has a hysteresis to

avoid thermal pumping.

2.11

Power Down Mode

The TLE 6361 G is started by a static high signal at the wake input or a high pulse with

a minimum of 50µs duration at the Wake input (pin 34). In order to avoid instabilities of

the device voltages applied to the Wake pin (pin 34) have to have a certain slope, i.e.

1V/3µs. Voltages in the range between the turn on and turn off thresholds for a few 100µs

must be avoided!

By SPI command (“Sleep”-bit, D8, equals zero) all voltage regulators including the

switching regulator except the standby regulator can be turned off completely only if the

wake input is low. In the case the Wake input is permanently connected to battery the

device cannot be turned off by SPI command, it will always turn on again.

For stable “on” operation of the device the “Sleep”-bit, D8 has to be set to high at each

SPI cycle!

When powering the device again after power down the status of the SPI controlled

devices (e.g. trackers, watchdog etc.) depends on the output voltage on Q_LDO1. Did

the voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section)

is set otherwise the last SPI command defines the status.

2.12

Serial Peripheral Interface

A standard 16bit SPI is available for control and diagnostics. It is capable to operate in a

daisy chain. It can be written or read by a 16 bit SPI interface as well as by an 8 bit SPI

interface.

The 16-bit control word (write bit assignment, see figure 8) is read in via the data input DI,

synchronous to the clock input CLK supplied by the µC. The diagnosis word appears in

the same way synchronously at the data output DO (read bit assignment, see figure 9),

so with the first bit shifted on the DI line the first bit appears on the DO line.

Data Sheet, Rev. 1.31

16

2004-10-12

TLE 6361 G

The transmission cycle begins when the TLE 6361 G is selected by the “not chip select”

input CS (H to L). After the CS input returns from L to H, the word that has been read in

at the DI line becomes the new control word. The DO output switches to tristate status at

this point, thereby releasing the DO bus circuit for other uses. For details of the SPI

timing please refer to figures 10 to 13.

The SPI will be reset to default values given in the following table “write bit meaning” if

the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V).

The reset will be active as long as the power on reset is present so during the reset delay

time at power up no SPI commands are acceptable.

The register content of the SPI - including watchdog timings and reset delay timings - is

maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not

decrease below 3.3V).

2.12.1 Write mode

The following tables show the bit assignment to the different control functions, how to

change settings with the right bit combination and also the default status at power up.

2.12.2 Write mode bit assignment

BIT

DO

D1

D2

D3

D4

D5

D6

D7

D8

sleep

1

D9

D10

reset 1

0

D11

reset 2

0

D12

WD 1

0

D13

WD 2

0

D14

D 15

WD-Trig

0

WD_OF

F1

NOT

T1-

T2-

T6-

T4-

T5-

T6-

WD_OF

F2

WD_OF

F3

Name

assigned control

control

Default

1

X

0

1

Figure 8 Write Bit assignment

Write Bit meaning

Function

Bit

Combination Default

Not assigned

D1

X

0

Tracker 1 to 6 - control:

turn on/off the individual trackers

D2

D3

D4

D5

D6

D7

0: OFF

1: ON

Power down:

D8

0: SLEEP

1

send device to sleep

1: NORMAL

Data Sheet, Rev. 1.31

17

2004-10-12

TLE 6361 G

Write Bit meaning

Function

Bit

Combination Default

Reset timing:

Reset delay time t_RESvalid at warm start

D10D11

00: 64ms

10: 32ms

01: 16ms

11: 8ms

00

Window watchdog timing:

Open window time t_OWand

closed window time t_CWvalid at warm start

D12D13

00: 128ms

10: 64ms

01: 32ms

11: 16ms

00

Window watchdog function:

Enable /disable window watchdog

D0D9D14 010: OFF

1xx: ON

111

x0x: ON

xx1: ON

Window watchdog trigger:

Enable / disable window watchdog trigger

D15

0: not triggered 1

1: triggered

2.12.3 Read mode

Below the status information word and the bit assignments for diagnosis are shown.

2.12.3.1 Read mode bit assignment

BIT

DO

ERROR

0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

WD

D11

D12

D13

D14

D 15

temp_

warn

T1-

T2-

T3-

T4-

T5-

T6-

RAM

WD

DC/DC

status

Name

R-Error1 R-Error2 R-Error3

status

Good 1 Good 2 Window

Error

Default

0

1

Figure 9 Read Bit assignment

Error bit D0:

The error bit indicates fail function and turns high if the temperature prewarning, the

watchdog error is active, further if one RAM good indicates a cold start or if a voltage

tracker does not settle within 1ms when it is turned on.

In addition to the error indication by software the ERR pin atcs as a hardware error flag.

Data Sheet, Rev. 1.31

18

2004-10-12

TLE 6361 G

Read Bit meaning

Function

Type

Bit

Combination

Default

Error indication,

explanation see below this

table

Latched

D0

0: normal operation 0

1: fail function

Overtemperature warning Not latched D1

0: normal operation 0

1: prewarning

Status of Tracker Output

Q_T[1:6],only if output is

ON

Not latched D2

1: settled output

voltage

0:Tracker turned

off or

shorted output.

Also open load

may possibly be

indicated as 0.¹⁾

0

D3

D4

D5

D6

D7

Indication of cold start/

warm start, Q_LDO1

Latched

D8

D9

0: cold start

1: warm start

0

Indication of cold start/

warm start, Q_LDO2

0: cold start

1: warm start

Indication for open or

closed window

Not latched D10

Not latched D11

Not latched D12

Not latched D13

0: open window

1: closed window

Reset condition at output

Q_LDO1

0: normal operation 0

1: Reset R1

Reset condition at output

Q_LDO2

0: normal operation 0

1: Reset R2

Reset condition at output

Q_LDO3

0: normal operation 0

1: Reset R3

Watchdog Error

Latched

D14

0: normal operation 0

1: WD error

DC/DC converter status

Not latched D15

0: off

1: on

1

1)

Min. load current to avoid ’0’ signal caused by open load is 2mA.

Data Sheet, Rev. 1.31

19

2004-10-12

TLE 6361 G

2.12.4 SPI Timings

CS High to Low & rising edge of CLK: DO is enabled.

Status information is transferred to Output Shift Register

CS

CLK

DI

CS Low to High: Data from Register

are transferred to e.g. Trackers

time

0

1

2

3

13 14 15

0

1

Data In (N)

Data In (N+1)

D1

+

D0

+

D13 D14 D15

D0

D1 D2 D3

DI: Data will be accepted on the falling edge of CLK-Signal

Data Out (N)

Data Out (N-1)

D13 D14 D15

D1

D0 D1 D2 D3

D0

DO

DO: State will change on the rising edge of CLK-Signal

e.g.

Tracker-

Setting (N)

Setting (N-1)

control

e.g.

Tracker-

Status (N)

Status (N-1)

status

Figure 10 SPI Data Transfer Timing

Data Sheet, Rev. 1.31

20

2004-10-12

TLE 6361 G

Figure 11 SPI-Input Timing

t_rIN

t_fIN<10ns

0.7 V_{Q_LDO1}

50%

0.2 V_{Q_LDO1}

CLK

t_rDO

90%

10%

(low to high)

DO

t_VADO

t_fDO

90%

10%

(high to low)

DO

Figure 12 DO Valid Data Delay Time and Valid Time

Data Sheet, Rev. 1.31

21

2004-10-12

TLE 6361 G

t_fIN

t_rIN<10ns

0.7 V_{Q_LDO1}

50%

0.2 V_{Q_LDO1}

CS

DO

10k

Ω

Pullup

50%

to V_{Q_LDO1}

t_ENDO

t_DISDO

10k

Ω

Pulldown

to GND

Figure 13 DO Enable and Disable Time

Data Sheet, Rev. 1.31

22

2004-10-12

TLE 6361 G

3

Characteristics

3.1

Absolute Maximum Ratings

Item Parameter Symbol Limit Values

Unit

Test Condition

Min.

Max.

3.1.1 Supply Voltage Input IN

Voltage

Current

V_VS

I_VS

-0.5

–

60

–

V

–

3.1.2 Buck-Switch Output SW

Voltage

Current

V_SW

I_SW

-2

–

V_S+0.5

V

–

3.1.3 Feedback and Linear Voltage Regulator Input

Voltage

Current

V_{FB/L_IN}

I_{FB/L_IN}

-0.5

8

V

–

3.1.4 Bootstrap Connector Bootstrap

Voltage

V_BootstrapV_SW-

V_SW+

10V

V

0.5V

Voltage

Current

V_Bootstrap-0.5

70

–

V

–

I_Bootstrap

–

Internally Limited

3.1.5 Boost Input

Voltage

V_Boost

I_Boost

-0.5

–

60

–

V

–

Current

Internally Limited

3.1.6 Slope Control Input Slew

Voltage

Current

V_Slew

I_Slew

-0.5

–

6

–

V

–

Internally Limited

3.1.7 Charge Pump Capacitor Connector C-

Voltage

V_CL

-0.5

V_{FB/L_IN}

+0.5

V

Current

I_CL

-150

+150

mA

Data Sheet, Rev. 1.31

23

2004-10-12

TLE 6361 G

3.1.8 Charge Pump Capacitor Connector C+

Voltage

Current

V_CH

I_CH

-0.5

13

V

-150

+150

mA

3.1.9 Charge Pump Storage Capacitor CCP

Voltage

Current

V_CCP

I_CCP

-0.5

12

–

V

-150

mA

3.1.10 Standby Voltage Regulator output Q_STB

Voltage

Current

V_{Q_Stb}

I_{Q_Stb}

-0.5

6

–

V

–

Internally limited

3.1.11 Voltage Regulator output voltage Q_LDO1

Voltage

Current

V_{Q_LDO1}

I_{Q_LDO1}

-0.5

6

–

V

–

Internally limited

3.1.12 Voltage Regulator output voltage Q_LDO2

Voltage

Current

V_{Q_LDO2}

I_{Q_LDO2}

-0.5

6

–

V

–

Internally limited

3.1.13 Voltage Regulator output voltage Q_LDO3

Voltage

Current

V_{Q_LDO3}

I_{Q_LDO3}

-0.5

6

–

V

–

Internally limited

3.1.14 Voltage Tracker output voltage Q_T1

Voltage

Current

V_{Q_T1}

I_{Q_T1}

-5

60

–

V

–

Internally limited

mA

3.1.15 Voltage Tracker output voltage Q_T2

Voltage

Current

V_{Q_T2}

I_{Q_T2}

-5

60

–

V

–

Internally limited

mA

3.1.16 Voltage Tracker output voltage Q_T3

Voltage

Current

V_{Q_T3}

I_{Q_T3}

-5

60

–

V

–

Internally limited

mA

3.1.17 Voltage Tracker output voltage Q_T4

Voltage

Current

V_{Q_T4}

I_{Q_T4}

-5

60

–

V

–

Internally limited

mA

Data Sheet, Rev. 1.31

24

2004-10-12

TLE 6361 G

3.1.18 Voltage Tracker output voltage Q_T5

Voltage

Current

V_{Q_T5}

I_{Q_T5}

-5

60

–

V

–

Internally limited

mA

3.1.19 Voltage Tracker output voltage Q_T6

Voltage

Current

V_{Q_T6}

I_{Q_T6}

-5

60

–

V

–

Internally limited

mA

3.1.20 Select Input SEL

Voltage

Current

V_SEL

I_SEL

-0.5

6

–

V

–

Internally limited

3.1.21 Wake Up Input Wake

Voltage

Current

V_Wake

I_Wake

-0.5

60

–

V

–

3.1.22 Reset Output R1

Voltage

Current

V_R1

I_R1

-0.5

6

V

–

3.1.23 Reset Output R2

Voltage

Current

V_R2

I_R2

-0.5

6

V

–

3.1.24 Reset Output R3

Voltage

Current

V_R3

I_R3

-0.5

6

–

V

–

3.1.25 SPI Data Input DI

Voltage

Current

V_DI

I_DI

-0.5

6

–

V

–

3.1.26 SPI Data Output DO

Voltage

Current

V_DO

I_DO

-0.5

6

–

V

–

Internally limited

3.1.27 SPI Clock Input CLK

Voltage

Current

V_CLK

I_CLK

-0.5

6

–

V

–

Data Sheet, Rev. 1.31

25

2004-10-12

TLE 6361 G

3.1.28 SPI Chip Select Not Input CS

Voltage

Current

V_CS

I_CS

-0.5

6

–

V

–

3.1.29 Error Output Pin

Voltage

Current

V_Error

I_Error

-0.5

6

V

–

Internally limited

3.1.30 Thermal Resistance

Junction-

ambient

R_thja

R_thjc

37

29

2

¹⁾PCB heat sink area

300mm²

K/W

Junction-

ambient

¹⁾PCB heat sink area

600mm²

Junction-

case

–

3.1.31 Temperature

Junction

temperature

T_j

-40

150

175

°C

Junction

T_jt

lifetime=TBD

temperature

transient

Storage

T_stg

-50

150

°C

temperature

3.1.32 ESD - Protection (Human Body Model; 1.5kΩ; C=100pF)

Electrostatic V_ESD

discharge

-1

1

kV

All pins

voltage

1) Package mounted on FR4 47x50x1.5mm³; 70µ Cu, zero airflow

Note: Maximum ratings are absolute ratings; exceeding any one of these values may

cause irreversible damage to the integrated circuit.

Data Sheet, Rev. 1.31

26

2004-10-12

TLE 6361 G

3.2

Functional Range

-40°C < T_j< 150 °C

Item Parameter

Symbol

Limit Values

Unit

Condition

min.

5.5

max.

Supply

Voltage

V_IN

V

To achieve V_IN,minan

initial startup with

V_IN>8V is required;

Supply

V_IN

60

V

Voltage

Ripple at

FB/L_IN

V_{FB/L_IN}

0

150

mV_PP

ripple

Note: Within the functional range the IC can be operated . The electrical characteristics,

however, are not guaranteed over this full functional range

Data Sheet, Rev. 1.31

27

2004-10-12

TLE 6361 G

3.3

Recommended Operation Range

-40°C < T_j< 150 °C

Item Parameter

Symbol

Limit Values

typ. max.

100

Unit

Condition

min.

1)

Buck

Inductor

L_B

18

µH

µF

Buck

Capacitor

C_B

10

ESR <0.15 Ω,

ceramic

capacitor (X7R)

recommended¹⁾

Bootstrap

Capacitor

C_BTP

2

0

% of C_B

kΩ

SLEW

R_SLEW

20

resistor

Linear

C_{Q_LDO1-3}470

nF

ceramic

regulator

capacitors

capacitor (X7R)

Tracker

bypass

capacitors

C_{Q_T1-6}

1

µF

ns

ceramic

capacitor (X7R)

SPI rise and t_r,f

200

fall timings,

CS, DI, CLK

1)

C_{B, min}needs a Buck inductance L_B=47µH to avoid instabilities

Data Sheet, Rev. 1.31

28

2004-10-12

TLE 6361 G

3.4

Electrical Characteristics

The electrical characteristics involve the spread of values guaranteed within the

specified supply voltage and ambient temperature range. Typical values represent the

median values at room temperature, which are related to production processes.

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

Buck regulator

3.4.1 Switching

frequency

f_SW

280

370

20

425

kHz

ns

3.4.2 Current

transition

t_{r_I_SW}

R_SL=0Ω ¹⁾

R_SL=20kΩ ¹⁾

R_SL=0Ω ¹⁾

time, min.,

rising edge

3.4.3 Current

transition

t_{r_I_SW}

t_{f_I_SW}

100

20

ns

time, max.,

rising edge

3.4.4 Current

transition

time, min.,

falling edge

3.4.5 Current

transition

100

R_SL=20kΩ ¹⁾

time, max.,

falling edge

1)

3.4.6 Voltage rise / t_{f_V_SW}

fall time

25

ns

3.4.7 Static on

resistance

R_ON

160

280

mΩ

T_j=25°C

in static operation

3.4.8 Static on

resistance

R_ON

400

T_j=150°C

in static operation

3.4.9 Current limit I_MAX

1.5

5.4

3.2

6.3

A

V

V_{FB/L_IN}=5.4V

3.4.10 Output

voltage

V_OUT

I_OUT=0.1A

V_IN=13.5 V

3.4.11 Output

voltage

V_OUT

5.4

6.05

V

I_OUT=1.5A

V_IN=13.5 V

Data Sheet, Rev. 1.31

29

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

3.4.12 Bootstrap

charging

I_BTSTR

80

160

220

17

µA

current at

start-up

3.4.13 Bootstrap

voltage

V_BTSTR

10

5

V

V_{FB/L_IN}=6.5V,

Buck converter

off

(internal

charge

pump)

3.4.14 Bootstrap

undervoltage

lockout, Buck

turn on

V_BTSTR,

9

turn on

threshold

3.4.15 Bootstrap

undervoltage

lockout,

V_BTSTR,

2.5

V

-

turn on

V_BTSTR,

hysteresis

turn off

3.4.16 Charge

pump

V_CCP

7.9

11.0

I_{Q_LDO1}= 800mA,

V_{FB/L_IN}=6.0V,

voltage

C_FLY=100nF,

C_CCP=220nF

3.4.17 Max. Duty

Cycle

duty_max

duty_min

95

%

Switching

operation

3.4.18 Min. Duty

Cycle

0

Static-off

operation

Voltage Regulator Q_LDO1

3.4.19 Output

voltage

V_Q1

4.9

5.1

V

100mA < I_{Q_LDO1}

< 800mA

3.4.20 Output

voltage

V_Q1

5.0

40

V

I_{Q_LDO1}= 800mA

3.4.21 Load

∆V_{Q_LDO1}

mV

100mA< I_{Q_LDO1}

<800mA;

Regulation

V_{FB/L_IN}=5,5V

3.4.22 Current limit I_{Q_LDO1limit}800

Data Sheet, Rev. 1.31

1050

30

1400

mA

V_{Q_LDO1}=4V

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

3.4.23 Ripple

rejection

PSRR1

26

40

dB

nF

f=330kHz; ¹⁾

3.4.24 Output

Capacitor

C_{Q_LDO1}470

Ceramic type,

value for stability

Voltage Regulator Q_LDO2

3.4.25 Output

voltage 3.3V

V_{Q_LDO2}

3.14

3.46

V

50mA < I_{Q_LDO2}

400mA;

<

3.3V mode

3.4.26 Output

voltage 3.3V

3.4.27 Output

voltage 2.6V

V_{Q_LDO2}

3.32

V

I_{Q_LDO2}=400mA;

3.3V mode

2.500

2.750

50mA < I_{Q_LDO2}

400mA;

<

2.6V mode

3.4.28 Output

voltage 2.6V

3.4.29 Load

Regulation

V_{Q_LDO2}

2.62

50

V

I_{Q_LDO2}=400mA;

2.6V mode

∆V_{Q_LDO2}

mV

50mA< I_{Q_LDO3}

<400mA;

V_{FB/L_IN}=5.5V

3.3V mode

3.4.30 Load

Regulation

∆V_{Q_LDO2}

50

mV

50mA< I_{Q_LDO2}

<400mA;

V_{FB/L_IN}=5.5V

2.6V mode

3.4.31 Current limit I_{Q_LDO2limit}500

3.4.32 Current limit I_{Q_LDO2limit}500

650

40

850

mA

dB

V_{Q_LDO2}= 2.8V;

3.3V mode

V_{Q_LDO2}= 2V;

2.6V mode

f=330kHz; ¹⁾

3.4.33 Ripple

rejection

3.4.34 Output

Capacitor

Voltage Regulator Q_LDO3

PSRR2

26

C_{Q_LDO2}470

nF

Ceramic type,

value for stability

Data Sheet, Rev. 1.31

31

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

3.4.35 Output

voltage 5V

V_{Q_LDO3}

4.8

5.2

V

20mA < I_{Q_LDO3}

300mA;

<

5V mode

3.4.36 Output

voltage 5V

V_{Q_LDO3}

5.0

V

I_{Q_LDO3}=300mA;

5V mode

3.4.37 Output

voltage 3.3V

3.14

3.46

20mA < I_{Q_LDO3}

300mA;

<

3.3V mode

3.4.38 Output

voltage 3.3V

V_{Q_LDO3}

3.32

100

V

I_{Q_LDO3}=300mA;

3.3V mode

3.4.39 Load

Regulation

∆V_{Q_LDO3}

mV

20mA< I_{Q_LDO3}

<300mA;

V_{FB/L_IN}=5,5V

5V mode

3.4.40 Load

Regulation

∆V_{Q_LDO3}

50

mV

20mA< I_{Q_LDO3}

<300mA;

V_{FB/L_IN}=5,5V

3.3V mode

3.4.41 Current limit I_{Q_LDO3}

350

26

500

40

600

mA

dB

V_{Q_LDO3}=4V;

5V mode

limit

3.4.42 Current limit I_{Q_LDO3}

limit

V_{Q_LDO3}=2.8V;

3.3V mode

f=330kHz; ¹⁾

3.4.43 Ripple

rejection

3.4.44 Output

Capacitor

Voltage Tracker Q_T1

3.4.45 Output ∆V_{Q_T1}

PSRR3

C_{Q_LDO3}470

nF

Ceramic type,

value for stability

-15

5

mV

V_{Q_T1}-V_{Q_LDO1}

;

voltage

tracking

accuracy

1mA < I_{Q_T1}

17mA

<

3.4.46 Output

voltage

∆V_{Q_T1}

-10

32

V_{Q_T1}-V_{Q_LDO1}

_{Q_T1}= 17mA

;

I

tracking

accuracy

Data Sheet, Rev. 1.31

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values

Unit

Test Conditions

min.

typ.

max.

3.4.47 Overvoltage V_{OVQ_T1}

threshold

V_{Q_T1,}

mV

I_{Q_T1}= 0mA; ¹⁾

nom

1)

3.4.48 Undervoltage V_{UVQ_T1}

threshold

V_{Q_T1}-

15mV

3.4.49 Current limit I_{Q_T1 limit}17

30

mA

dB

V_{Q_T1}=4V

f=330kHz; ¹⁾

3.4.50 Ripple

rejection

PSRR

26

3.4.51 Tracker load C_{Q_T1}

capacitor

1

µF

Ceramic type,

minimum for

stability

Voltage Tracker Q_T2

3.4.52 Output

voltage

∆V_{Q_T2}

-15

5

mV

V_{Q_T2}-V_{Q_LDO1}

;

1mA < I_{Q_T2}

17mA

<

tracking

accuracy

3.4.53 Output

voltage

∆V_{Q_T2}

-10

V_{Q_T2}-V_{Q_LDO2}

I_{Q_T2}= 17mA

tracking

accuracy

3.4.54 Overvoltage V_{OVQ_T2}

threshold

V_{Q_T2,}

mV

I_{Q_T2}= 0mA;¹⁾

nom

1)

3.4.55 Undervoltage V_{UVQ_T2}

threshold

V_{Q_T2}-

15mV

3.4.56 Current limit I_{Q_T2 limit}17

30

mA

dB

V_{Q_T2}=4V

f=330kHz; ¹⁾

3.4.57 Ripple

rejection

PSRR

26

3.4.58 Tracker load C_{Q_T2}

capacitor

1

µF

Ceramic type,

minimum for

stability

Voltage Tracker Q_T3

Data Sheet, Rev. 1.31

33

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

3.4.59 Output

voltage

∆V_{Q_T3}

-15

5

mV

V_{Q_T3}-V_{Q_LDO1}

;

1mA < I_{Q_T3}

17mA

<

tracking

accuracy

3.4.60 Output

voltage

∆V_{Q_T3}

-10

mV

V_{Q_T3}-V_{Q_LDO3}

I_{Q_T3}= 17mA

;

tracking

accuracy

3.4.61 Overvoltage V_{OVQ_T3}

threshold

V_{Q_T3,}

mV

I_{Q_T3}= 0mA; ¹⁾

nom

1)

3.4.62 Undervoltage V_{UVQ_T3}

threshold

V_{Q_T3}-

15mV

3.4.63 Current limit I_{Q_T3 limit}17

30

mA

dB

V_{Q_T3}=4V

f=330kHz; ¹⁾

3.4.64 Ripple

rejection

PSRR

26

3.4.65 Tracker load C_{Q_T3}

capacitor

1

µF

Ceramic type,

minimum for

stability

Voltage Tracker Q_T4

3.4.66 Output

voltage

∆V_{Q_T4}

-15

5

mV

V_{Q_T4}-V_{Q_LDO1};

1mA < I_{Q_T4}

17mA

<

tracking

accuracy

3.4.67 Output

voltage

∆V_{Q_T4}

-10

V_{Q_T4}-V_{Q_LDO4}

;

I

_{Q_T4}= 17mA

tracking

accuracy

3.4.68 Overvoltage V_{OVQ_T4}

threshold

V_{Q_T4,}

mV

I_{Q_T4}= 0mA; ¹⁾

nom

1)

3.4.69 Undervoltage V_{UVQ_T4}

threshold

V_{Q_T4}-

15mV

3.4.70 Current limit I_{Q_T4 limit}17

3.4.71 Ripple PSSR 26

rejection

30

mA

dB

V_{Q_T4}=4V

f=330kHz; ¹⁾

Data Sheet, Rev. 1.31

34

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values

Unit

Test Conditions

min.

typ.

max.

3.4.72 Tracker load C_{Q_T4}

capacitor

1

µF

Ceramic type,

minimum for

stability

Voltage Tracker Q_T5

3.4.73 Output

voltage

∆V_{Q_T5}

-15

5

mV

V_{Q_T5}-V_{Q_LDO1}

;

1mA < I_{Q_T5}

17mA

<

tracking

accuracy

3.4.74 Output

voltage

∆V_{Q_T5}

-10

V_{Q_T5}-V_{Q_LDO5}

_{Q_T5}= 17mA

I

tracking

accuracy

3.4.75 Overvoltage V_{OVQ_T5}

threshold

V_{Q_T5,}

mV

I_{Q_T5}= 0mA; ¹⁾

nom

1)

3.4.76 Undervoltage V_{UVQ_T5}

threshold

V_{Q_T5}-

15mV

3.4.77 Current limit I_{Q_T5 limit}17

30

mA

dB

V_{Q_T5}=4V

f=330kHz; ¹⁾

3.4.78 Ripple

rejection

PSRR

26

3.4.79 Tracker load C_{Q_T5}

capacitor

1

µF

Ceramic type,

minimum for

stability

Voltage Tracker Q_T6

3.4.80 Output

voltage

∆V_{Q_T6}

-15

5

mV

V_{Q_T6}-V_{Q_LDO1};

1mA < I_{Q_T6}

17mA

<

tracking

accuracy

3.4.81 Output

voltage

∆V_{Q_T6}

-10

V_{Q_T6}-V_{Q_LDO6}

_{Q_T6}= 17mA

;

I

tracking

accuracy

3.4.82 Overvoltage V_{OVQ_T6}

threshold

V_{Q_T6,}

I_{Q_T6}= 0mA; ¹⁾

nom

Data Sheet, Rev. 1.31

35

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values

Unit

Test Conditions

min.

typ.

max.

1)

3.4.83 Undervoltage V_{UVQ_T6}

threshold

V_{Q_T6}

15mV

-

mV

3.4.84 Current limit I_{Q_T6 limit}17

30

mA

dB

V_{Q_T6}=4V

f=330kHz; ¹⁾

3.4.85 Ripple

rejection

PSRR

26

3.4.86 Tracker load C_{Q_T6}

capacitor

1

µF

Ceramic type,

minimum for

stability

Standby Regulator

3.4.87 Output

voltage

V_{Q_STB}

2.2

2.4

3

2.6

6

V

0µA

<I_{Q_STB}<500µA

3.4.88 Current limit I_{Q_STB limit}

1

mA

nF

V_{Q_STB}=2V

3.4.89 Standby

load

C_{Q_STB}

100

Ceramic type,

minimum for

stability

capacitor

Off-Mode

3.4.90 Supply

current from

battery

I_q,off

10

30

2.8

µA

V

V_IN=13.5V,

V_wake=0V,

I

_{Q_STB}=0µA

3.4.91 Supply

current from

battery

I_q,off

10

V_IN=42V,

V_wake=0V

I

_{Q_STB}=0µA

3.4.92 Turn on

Wake-up

V_{wake th, on}

2.4

2.35

V_wakeincreasing

V_wakedecreasing

V_wake=5V

threshold

3.4.93 Turn off

Wake-up

V_{wake th, off}1.8

V

threshold

3.4.94 Wake-up

input current

I_wake

t_wake,min

50

10

150

50

µA

µs

3.4.95 Wake up

input on time

4

V_wake

>

1)

V_{wake th, on max}

;

Reset R1

Data Sheet, Rev. 1.31

36

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

3.4.96 Reset

threshold

Q_LDO1

V_RTH

4.5

4.65

4.8

V

V_{Q_LDO1}

decreasing

Q_LDO1, de

3.4.97 Reset

threshold

Q_LDO1

V_RTH

4.55

4.70

4.9

V

V_{Q_LDO1}

increasing

Q_LDO1, in

3.4.98 Reset output V_{R1 L}

low voltage

0.4

0.3

1

V

I_R1=1.6mA;

V_{Q_LDO1}=5V

3.4.99 Reset output V_{R1 L}

low voltage

V

I_R1=0.3mA;

V_{Q_LDO1}=1V

3.4.100 Reset High

leakage

I_{R1 H}

µA

current

Reset R2

3.4.101 Reset

threshold

Q_LDO2

V_RTH

2.6

2.3

2.8

40

3.0

2.5

V

3.3V mode;

V_{Q_LDO2}

decreasing

Q_LDO2, de

3.4.102 Reset

threshold

hysteresis

Q_LDO2

V_RTH

mV

3.3V mode

-

Q_LDO2, in

V_RTH

Q_LDO2, de

V_RTH

3.4.103 Reset

threshold

Q_LDO2

2.4

40

V

2.6V mode;

V_{Q_LDO2}

decreasing

Q_LDO2, de

3.4.104 Reset

threshold

hysteresis

Q_LDO2

V_RTH

mV

2.6V mode

Q_LDO2, in

V_RTH

Q_LDO2, de

3.4.105 Reset output V_{R2 L}

low voltage

0.4

0.3

1

V

I_R2=1.6mA;

V_{Q_LDO2}=2.5V

3.4.106 Reset output V_{R2 L}

low voltage

V

I_R2=0.3mA;

V_{Q_LDO2}=1V

3.4.107 Reset High

leakage

I_{R2 H}

µA

current

Data Sheet, Rev. 1.31

37

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

Reset R3

3.4.108 Reset

threshold

Q_LDO3

V_RTH

2.7

2.85

3.0

V

3.3V mode;

V_{Q_LDO3}

decreasing

Q_LDO3, de

3.4.109 Reset

threshold

hysteresis

Q_LDO3

V_RTH

40

mV

3.3V mode

-

Q_LDO3, in

V_RTH

Q_LDO3, de

V_RTH

3.4.110 Reset

threshold

Q_LDO3

4.0

4.2

40

4.5

V

5V mode;

V_{Q_LDO3}

decreasing

Q_LDO3, de

3.4.111 Reset

threshold

hysteresis

Q_LDO3

V_RTH

mV

5V mode

Q_LDO3, in

V_RTH

Q_LDO3, de

3.4.112 Reset output V_{R3 L}

low voltage

0.4

0.3

1

V

I_R3=1.6mA;

V_{Q_LDO3}=3.3V

3.4.113 Reset output V_{R3 L}

low voltage

V

I_R3=0.3mA;

V_{Q_LDO3}=1V

3.4.114 Reset High

leakage

I_{R3 H}

µA

current

1)

3.4.115 Reset

reaction time

t_rr

1

2

10

µs

1

Valid for R1, R2

and R3

3.4.116 Reset Delay t_NORM,RES0.75

Norm factor

1

1.25

3.4.117 Reset Delay t_RES

time

0.75

t_RES(SPI)Valid for R1, R2

and R3; t_{RES (SPI)}

is defined by the

SPI word (see

section 2.12)

RAM Good

3.4.118 V_Q1threshold V_{Th Q1}

2.3

2.8

38

3.3

V

Data Sheet, Rev. 1.31

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter Symbol Limit Values

Unit

Test Conditions

min.

1.2

typ.

1.4

max.

3.4.119 V_Q2threshold V_{Th Q2}

3.4.120 V_Q2threshold V_{Th Q2}

Window Watchdog

1.7

V

3.3V mode

2.6V mode; ¹⁾

1.2

3.4.121 Closed

window time

tolerance

t_{CW_tol}

0.75

1

1.25

Multiply with

watchdog

window time set

by SPI to obtain

the limits (2.12)

3.4.122 Open

t_{OW_tol}

1

Multiply with

window time

tolerance

watchdog

window time set

by SPI to obtain

the limits (2.12)

3.4.123 Watchdog

reset low

t_WRL

t_RES

time

3.4.124 Watchdog

reset delay

time

t_SR

t_CW/2

Error Output ERR

3.4.125 H-output

V_ERR,H

V_{Q_LDO1}V_{Q_LDO1}

–

V

I_{ERR, H}= 1 mA

voltage level

– 2.0

–

– 0.7

0.3

3.4.126 L-output

V_ERR,L

0.5

I_{ERR, L}= – 1.6 mA

voltage level

SPI

3.4.127 SPI clock

frequency

f_CLK

0

2.5

MHz

Production test

up to 1MHz;

2.5MHz ¹⁾

SPI Input DI

Data Sheet, Rev. 1.31

39

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

–

3.4.128 H-input

voltage

V_IH

–

40

70

% of

V_{Q_LDO1}

threshold

–

3.4.129 L-input

voltage

V_IL

20

36

–

% of

V_{Q_LDO1}

threshold

1)

3.4.130 Hysteresis of V_IHY

50

5

200

25

10

–

500

100

15

mV

µA

pF

ns

input voltage

3.4.131 Pull down

I_I

V_DI= 0.2 *

V_{Q_LDO1}

current

3.4.132 Input

C_I

–

0 V < V_{Q_LDO1}<

5.25 V

1)

capacitance

3.4.133 Input signal t_r

–

200

rise time

1)

–

3.4.134 Input signal t_f

–

ns

fall time

SPI Clock Input CLK

3.4.135 H-input

V_IH

–

40

36

70

–

% of

V_{Q_LDO1}

voltage

threshold

–

3.4.136 L-input

voltage

V_IL

20

% of

V_{Q_LDO1}

threshold

1)

3.4.137 Hysteresis of V_IHY

50

5

200

25

10

–

500

100

15

mV

µA

pF

ns

input voltage

3.4.138 Pull down

I_I

V_CLK= 0.2 *

V_{Q_LDO1}

current

3.4.139 Input

C_I

–

0 V < V_{Q_LDO1}<

5.25 V

1)

capacitance

3.4.140 Input signal t_r

–

200

rise time

1)

3.4.141 Input signal t_f

–

ns

fall time

SPI Chip Select Input CS

Data Sheet, Rev. 1.31

40

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

–

3.4.142 H-input

voltage

V_IH

–

39

70

–

% of

V_{Q_LDO1}

threshold

–

3.4.143 L-input

voltage

V_IL

20

35

% of

V_{Q_LDO1}

threshold

1)

3.4.144 Hysteresis of V_IHY

50

200

500

– 5

mV

input voltage

3.4.145 Pull up

I_{I, CS}

– 100

– 25

µA

V_CS= 0.2 *

V_{Q_LDO1}

current at pin

CS

3.4.146 Input

C_I

–

10

–

15

pF

ns

0 V < V_{Q_LDO1}<

5.25 V

1)

capacitance

3.4.147 Input signal t_r

200

rise time

1)

3.4.148 Input signal t_f

–

fall time

Logic Output DO

3.4.149 H-output

voltage level

3.4.150 L-output

voltage level

V_DOH

V_{Q_LDO1}V_{Q_LDO1}

–

V

I_DOH= 1 mA

– 1.0

–

– 0.8

0.2

V_DOL

0.4

10

V

I_DOL= – 1.6 mA

3.4.151 Tri-state

leakage

I_{DO_TRI}

– 10

–

µA

V_CS= V_{Q_LDO1};

0 V < V_DO

V_{Q_LDO1}

<

current

3.4.152 Tri-state

C_DO

–

10

15

pF

ns

V_CS= V_{Q_LDO1}

input

0 V < V_{Q_LDO1}

5.25 V

<

capacitance

Data Input Timing

1)

3.4.153 Clock period t_pCLK

1000

–

Data Sheet, Rev. 1.31

41

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

1)

3.4.154 Clock high

t_CLKH

t_CLKL

t_bef

500

–

ns

time

1)

3.4.155 Clock low

time

500

–

3.4.156 Clock low

before CS

low

1)

3.4.157 CS setup

time

t_lead

t_lag

500

–

ns

3.4.158 CLK setup

time

3.4.159 Clock low

after CS high

t_beh

1)

3.4.160 DI setup time t_DISU

3.4.161 DI hold time t_DIHO

250

–

ns

Data Output Timing

C_L= 100 pF

low impedance

3.4.162 DO rise time t_rDO

3.4.163 DO fall time t_fDO

–

50

–

100

250

ns

3.4.164 DO enable

time

t_ENDO

high impedance

3.4.165 DO disable

time

t_DISDO

–

250

ns

V_DO< 10%

V_DO> 90%

C_L= 100 pF

3.4.166 DO valid time t_VADO

100

General

2)

3.4.167 Temperature T_J,Flag

warning flag

140

170

°C

3.4.168 Over

Temperature

T_J,Shutdown150

200

shutdown

Data Sheet, Rev. 1.31

42

2004-10-12

TLE 6361 G

-40 < T_j<150 °C; V_IN=13.5V unless otherwise specified

Item Parameter

Symbol

Limit Values

Unit

Test Conditions

min.

typ.

max.

3.4.169 Over-

Temperature

shutdown

∆T_{sd_hys}

30

K

Hysteresis

3.4.170 DeltaTW to

TSD

T_J,Shutdown

- T_J,Flag

20

K

1)

Specified by design, not subject to production test

2)

Simulated at wafer test only, not absolutely measured

4

Typical performance charcteristics

Buck converter switching frequency

vs. junction temperature

420

f_SW

kHz

400

380

360

340

320

300

280

-50

-20

10

40

70

100 130 160

T_j

°C

Data Sheet, Rev. 1.31

43

2004-10-12

TLE 6361 G

Buck converter output voltage at 1.5A load Buck converter current limit

vs. junction temperature

6.0

4.0

V_{FB/L_IN}

I_MAX

V

A

5.9

3.5

5.8

5.7

5.6

5.5

5.4

5.3

3.0

2.5

2.0

1.5

1.0

0.5

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Buck converter DMOS on-resistance

vs. junction temperature

Start-up bootstrap charging current

vs. junction temperature

280

400

I_BTSTR

R_ON

µA

mΩ

240

350

300

250

200

150

100

50

200

160

120

80

40

0

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Data Sheet, Rev. 1.31

44

2004-10-12

TLE 6361 G

Bootstrap UV lockout, turn on threshold

vs. junction temperature

Q_LDO1 output voltage at 800mA load

vs. junction temperature

V_BTSTR,

turn on

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

5.20

V_{Q_LDO1}

V

5.15

5.10

5.05

5.00

4.95

4.90

4.85

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Device wake up thresholds

vs. junction temperature

Reset1 threshold at drecreasing V_LDO1

vs. junction temperature

2.8

V_RTH

4.80

V_{wake th}

Q_LDO1, de

V

2.7

4.75

2.6

2.5

4.70

4.65

4.60

4.55

4.50

4.45

V_{wake th, on}

2.4

2.3

V_{wake th, off}

2.2

2.1

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Data Sheet, Rev. 1.31

45

2004-10-12

TLE 6361 G

Q_LDO1 current limit

Q_LDO2 current limit (2.6V mode)

vs. junction temperature

1400

850

I_{Q_LDO1}

I_{Q_LDO2}

V

1300

800

1200

1100

1000

900

750

700

650

600

550

500

800

700

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Q_LDO2 output voltage at 400mA load

(2.6V mode) vs. junction temperature

Q_LDO3 output voltage at 300mA load

(3.3V mode) vs. junction temperature

2.80

3.50

V_{Q_LDO2}

V_{Q_LDO3}

V

2.75

3.45

2.70

2.65

2.60

2.55

2.50

2.45

3.40

3.35

3.30

3.25

3.20

3.15

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Data Sheet, Rev. 1.31

46

2004-10-12

TLE 6361 G

Reset2 threshold at decreasing V_LDO2

(2.6V mode) vs. junction temperature

Reset3 threshold at decreasing V_LDO3

(3.3V mode) vs. junction temperature

V_RTH

2.60

3.00

Q_LDO2, de

Q_LDO3, de

V

2.55

2.95

2.50

2.45

2.40

2.35

2.30

2.25

2.90

2.85

2.80

2.75

2.70

2.65

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Q_LDO3 current limit (3.3V mode)

vs. junction temperature

Tracker current limit

vs. junction temperature

32

600

I_{Q_Tx}

I_{Q_LDO3}

mA

30

V

550

28

26

24

22

20

18

500

450

400

350

300

250

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Data Sheet, Rev. 1.31

47

2004-10-12

TLE 6361 G

Tracker accuracy with respect to V_LDO1 Q_STB current limit

vs. junction temperature

4

4.0

dV_{Q_Tx}

I_{Q_STB}

mV

2

mA

3.5

0

-2

3.0

2.5

2.0

1.5

1.0

0.5

-4

-6

-8

-10

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Q_STB output voltage at 500µA load

vs. junction temperature

Device current consumption in off mode

vs. junction temperature

2.8

35

V_{Q_STB}

I_{q, off}

V

µA

30

2.7

2.6

2.5

2.4

2.3

2.2

2.1

25

20

15

10

5

0

-50

-20

10

40

70

100 130 160

-50

-20

10

40

70

100 130 160

T_j

°C

Data Sheet, Rev. 1.31

48

2004-10-12

TLE 6361 G

5

Application Information

Application Diagram

5.1

R_Boost

22 Ω

TLE 6361

DBOOST

Standby

Q_STB

Regulator

2.5 V

C_STB

100 nF

C_BOOST

L_I

BOOST

Buck

100 nF

L_B

Up to

47 µH

SW 2*

Output

2* IN

47 µH

C

Battery

C_BTSTR

C_I3

+

DB

>^B10 µF

Buck

C_I1

100 nF

+

C_I2

47 µF

680 nF

3 A,

Regulator

10 to

ceramic or

60 V

100 nF

SLEW

BOOTSTRAP

> 20 µF

low ESR

tantalum

Driver

PWM

R_Slew

0 to

20 kΩ

Error-

Amplifier

Internal

Reference

Feedback

OSZ

To

FB/L_IN 2*

IGN

C+

C_FLY

Protection

10 kΩ

100 nF

C-

Charge

Pump

Q_LDO1

Power

Down

Logic

CCP

WAKE

C_CCP

220 nF

10 kΩ

SEL

R1

R2

R3

Q_LDO1

Lin. Reg.

5 V

C_LDO1,1

C_LDO1,2

+

470 nF

4.7 µF

To

Reset

Logic

Q_LDO2

Q_LDO3

Lin. Reg.

3.3/2.6 V

µ-Controller/

µC

C_LDO2,1

C_LDO2,2

Memory

Supply

470 nF

4.7 µF

Lin. Reg.

5/3.3 V

C_LDO3,1

470 nF

C_LDO3,2

4.7 µF

+

Ref

Q_T1

Q_T2

Q_T3

Q_T4

Q_T5

Q_T6

Tracker

5 V

Window

C_T1

Watchdog

1 µF

Tracker

5 V

C_T2

1 µF

10 kΩ

CLK

CS

DI

Tracker

5 V

C_T3

1 µF

Sensor

10 kΩ

1 kΩ

Supplies

(off board

supplies)

Tracker

5 V

C_T4

SPI

1 µF

16 Bit

To

Tracker

5 V

µC

C_T5

1 µF

DO

Tracker

5 V

C_T6

1 µF

ERR

GND

4*

AEA03380_6361ZR.VSD

Figure 14 Application Diagram

Data Sheet, Rev. 1.31

49

2004-10-12

TLE 6361 G

5.2

Buck converter circuit

A typical choice of external components for the buck converter is given in figure 14. For

basic operation of the buck converter the input capacitor C_I2, the bootstrap capacitor

C_BTP, the catch diode D_B, the induuctance L_B, the output capacitor C_Band the charge

pump capacitors C_FLYand C_CCPare necessary.

The additional components shown on top of the circuit lower the electromagnetic

emission (L_I, C_I1, C_I3, R_Slew) and the switching losses (R_Boost, C_Boost, D_Boost). For 12V

battery systems the switching loss minimization feature might not be used. In that case

the Boost pin (33) is connected directly to the IN pins (32, 30) and the components

R

_Boost, C_Boostand D_Boostare left away

5.2.1 Buck inductance (L_B) selection:

The inductance value determines together with the input voltage, the output voltage and

the switching frequency the current ripple which occurs during normal operation of the

step down converter. This current ripple is important for the all over ripple at the output

of the switching converter.

As a rule of thumb this current ripple ∆I is chosen between 10% and 50% of the load

current.

(V_I– V_OUT) V_OUT

L = --------------------------------------------------

f_SWV_I∆I

For optimum operation of the control loop of the Buck converter the inductance value

should be in the range indicated in section 3.3, recommended operation range.

When picking finally the inductance of a certain supplier (Epcos, Coilcraft etc.) the

saturation current has to be considered. With a maximum current limit of the Buck

converter of 3.2A an inductance with a minimum saturation current of 3.2A has to be

chosen.

Data Sheet, Rev. 1.31

50

2004-10-12

TLE 6361 G

5.2.2

Buck output capacitor (C_B) selection:

The choice of the output capacitor effects straight to the minimum achievable ripple

which is seen at the output of the buck converter. In continuous conduction mode the

ripple of the output voltage equals:

1









V_Ripple= ∆I

R

_ESRCB+ ----------------------------

8 f_SWC_B

From the formula it is recognized that the ESR has a big influence in the total ripple at

the output, so ceramic types or low ESR tantalum capacitors are recommended for the

application.

One other important thing to note are the requirements for the resonant frequency of the

output LC-combination. The choice of the components L and C have to meet also the

specified range given in section 3.3 otherwise instabilities of the regulation loop might

occur.

5.2.3

Input capacitor (C_I2) selection:

At high load currents, where the current through the inductance flows continuously, the

input capacitor is exposed to a square wave current with its duty cycle V_OUT/V_I. To

prevent a high ripple to the battery line a capacitor with low ESR should be used. The

maximum RMS current which the capacitor has to withstand is calculated to:

²



V_OUT

I_RMS= I_LOAD-------------- 1 +

V_IN

1

3

∆I

2 I_LOAD



-- -----------------------



5.2.4

Freewheeling diode / catch diode (D_B)

For lowest power loss in the freewheeling path Schottky diodes are recommended. With

those types the reverse recovery charge is negligible and a fast handover from

freewheeling to forward conduction mode is possible. Depending on the application (12V

battery systems) 40V types could be also used instead of the 60V diodes.

A fast recovery diode with recovery times in the range of 30ns can be also used if smaller

junction capacitance values (smaller spikes) are desired, the slew resistor should be set

in this case between 10 and 20kΩ.

Data Sheet, Rev. 1.31

51

2004-10-12

TLE 6361 G

5.2.5

Bootstrap capacitor (C_BTP)

The voltage at the Bootstrap capacitor does not exceed 15V, a ceramic type with a

minimum of 2% of the buck output capacitance and voltage class 16V would be

sufficient.

5.2.6

External charge pump capacitors (C_FLY, C_CCP)

Out of the feedback voltage the charge pump generates a voltage between 8 and 10V.

The fly capacitor connected between C+ and C- is charged with the feedback voltage

level and discharged to achieve the (almost) double voltage level at CCP. C_FLYis chosen

to 100nF and C_CCPto 220nF, both ceramic types.

The connection of CCP to a voltage source of e.g. 7V (take care of the maximum

ratings!) via a diode improves the start-up behavior at very low battery voltage. The diode

with the cathode on CCP has to be used in order to avoid any influence of the voltage

source to the device’s operation and vice versa.

5.2.7

Input filter components for reduced EME (C_I1, C_I2, C_I3, L_I, R_Slew)

At the input of Buck converters a square wave current is observed causing

electromagnetical interference on the battery line. The emission to the battery line

consists on one hand of components of the switching frequency (fundamental wave) and

its harmonics and on the other hand of the high frequency components derived from the

current slope. For proper attenuation of those interferers a π-type input filter structure is

recommended which is built up with inductive (L_I) and capacitive components (C_I1, C_I2,

C_I3). The inductance can be chosen up to the value of the Buck converter inductance,

higher values might not be necessary, C_I1and C_I3should be ceramic types and for C_I2an

input capacitance with very low ESR should be chosen and placed as close to the input

of the Buck converter as possible.

Inexpensive input filters show due to their parasitrics a notch filter characteristic, which

means basically that the lowpass filter acts from a certain frequency as a highpass filter

and means further that the high frequency components are not attenuated properly. For

that reason the TLE 6361 G offers the possibility of current slope adjustment. The current

transistion time can be set by the external slew resistor to times between 20ns and 80ns

by varying the resistor value bewteen 0Ω (fastest transition) and 20kΩ (slowest

transistion).

5.2.8

Feedback circuit for minimum switching loss (R_Boost, C_Boost, D_Boost)

To decrease the switching losses to a mininum the external components R_Boost, C_Boost

and D_Boostare needed. The current through the feedback resistor R_Boostis about a few

mA where the Diode D_Boostand the capacitor C_Boostrun a part of the load current.

If this feature is not needed the three components are not needed and the Boost pin (33)

can be connected directly to the IN pins(32, 30).

Data Sheet, Rev. 1.31

52

2004-10-12

TLE 6361 G

5.3

Reverse polarity protection

The Buck converter is due to the parasitic source drain diode of the DMOS not reverse

polarity protected. Therefore, as an example, the reverse polarity diode is shown in the

application circuit, in general the reverse polarity protection can be done in different

ways.

5.4

Linear voltage regulators (C_{LDO1, 2, 3})

As indicated before the linear regulators show stable operation with a minimum of 470nF

ceramic capacitors. To avoid a high ripple at the output due to load steps this output cap

might have to be increased to some few µF capacitors.

5.5

Linear voltage trackers (C_T1,2,3,4,5,6)

The voltage trackers require at their outputs 1µF ceramic capacitors each to avoid some

oscillation at the output. If needed the tracker outputs can be connected in parallel, in

that the output capacitor increases linear according to the number of parallel outputs.

5.6

Reset outputs (R1,2,3)

The undervoltage/watchdog reset outputs are open drain structures and require external

pull up resistors in the range of 10kΩ to the µC I/O voltage rail.

Data Sheet, Rev. 1.31

53

2004-10-12

TLE 6361 G

5.7

Components recommendation - overview

Device Type

Supplier

EPCOS

Coilcraft

TDK

Remark

L_I

B82479 series

10-1000µH; 4.3-0.56A

1-1000µH; 6.8-0.3A

10-1000µH; 8.0-0.8A

1-1000µH; 20.0-1.0A

10-1000µH; 8.0-0.8A

33µH, 3.2A

B82464-A4 series

DO3340P series

DO5022P series

DS5022P series

SLF1275T-330M3R2

Ceramic

C_I1

various

EPCOS

Coilcraft

various

Motorola

various

EPCOS

100nF, 60V

C_I2

Low ESR tantalum

Ceramic

47µF, 60V

C_I3

10nF to 100nF, 60V

D_Boost

L_B

S3B

B82479 series

B82464-A4 series

DO3340P series

DO5022P series

DS5022P series

Ceramic

10-1000µH; 4.3-0.56A

1-1000µH; 6.8-0.3A

10-1000µH; 8.0-0.8A

1-1000µH; 20.0-1.0A

10-1000µH; 8.0-0.8A

100nF, 10V

C_BTP

D_B

MBRD360

Schottky, 60V, 3A

Schottky, 40V, 3A

MBRD340

SS34

C_B

B45197-A2226

Low ESR Tantalum, 22µF, 10V,

C-case

2 * LMK316BJ475ML

C3216X7R1C106M

TPSC476K010R350

Taiyo Yuden

TDK

Ceramic X7R, 4.7µF, 10V

Ceramic X7R, 10µF, 16V

AVX

Low ESR Tantalum, 47µF, 10V,

C-case

C_LDOx

C_Tx

Ceramic

various

470nF, 10V

1µF, 60V

Data Sheet, Rev. 1.31

54

2004-10-12

TLE 6361 G

5.8

Layout recommendation

The most sensitive points for Buck converters - when considering the layout - are the

nodes at the input and the output of the Buck switch, the DMOS transistor.

For proper operation the external catch diode and Buck inductance have to be

connected as close as possible to the SW pins (29, 31). Best suitable for the connection

of the cathode of the Schottky diode and one terminal of the inductance would be a small

plain located next to the SW pins.

The GND connection of the catch diode must be also as short as possible. In general the

GND level should be implemented as surface area over the whole PCB as second layer,

if necessary as third layer.

The pin FB/L_IN is sensitive to noise. With an appropriate layout the Buck output

capacitor helps to avoid noise coupling to this pin. Also filtering of steep edges at the

supply voltage pin e.g. as shown in the application diagram is mandatory. C_I2may either

be a low ESR Tantalum capacitor or a ceramic capacitor. A minimum capacitance of

10µF is recommended for C_I2.

To obtain the optimum filter capability of the input π-filter it has to be located also as

close as possible to the IN pins, at least the ceramic capacitor C_I3should be next to those

pins.

Data Sheet, Rev. 1.31

55

2004-10-12

TLE 6361 G

Package Outlines

P-DSO-36-12

SMD = Surface Mounted Device

Dimensions in mm

1)

±0.15

11

B

2.8

±0.1

1.1

±0.1

15.74

6.3

(Heatslug)

Heatslug

0.65

0.1 C

(Mold)

±0.15

0.95

36x

0.25 A B C

0.25 ^+0.13

M

±0.3

14.2

0.25 B

Bottom View

36

19

36

Index Marking

Heatslug

1

18

1

10

13.7 _-0.2

(Metal)

1 x 45˚

1)

±0.1

15.9

A

(Mold)

¹⁾Does not include plastic or metal protrusion of 0.15 max. per side

see also: http://www.infineon.com -> Products -> Packages

Data Sheet, Rev. 1.31

56

2004-10-12

TLE 6361 G

Published by Infineon Technologies AG ,

Bereichs Kommunikation, St.-Martin-Strasse 53

D-81541 München

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted char-

acteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Infineon Technologiesis an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest In-

fineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address

list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the fail-

ure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life sup-

port devices or systems are intended to be implanted in the human body, or to support and/or maintain and sus-

tain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons

may be endangered.

Data Sheet, Rev. 1.31

57

2004-10-12


型号：	Q67007-A9466
厂家：	Infineon
描述：	Multi-Voltage Processor Power Supply 多电压处理器供电
文件：	总57页 (文件大小：698K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Q67007-A9466 [INFINEON]

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