Q67100-Q1152 [INFINEON]
2M x 8 - Bit Dynamic RAM 2k Refresh; 2M ×8 - 位动态RAM 2K刷新![Q67100-Q1152](http://pdffile.icpdf.com/pdf1/p00089/img/icpdf/Q67100_467699_icpdf.jpg)
型号: | Q67100-Q1152 |
厂家: | ![]() |
描述: | 2M x 8 - Bit Dynamic RAM 2k Refresh |
文件: | 总25页 (文件大小:259K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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2M x 8 - Bit Dynamic RAM
2k Refresh
HYB3117805BSJ -50/-60/-70
(Hyper Page Mode- EDO)
Advanced Information
• 2 097 152 words by 8-bit organization
• 0 to 70 °C operating temperature
• Performance:
-50
50
13
25
84
20
-60
60
15
30
-70
t
t
t
t
t
RAS access time
70
20
35
ns
ns
ns
RAC
CAC
AA
CAS access time
Access time from address
Read/Write cycle time
104 124 ns
25 30 ns
RC
Hyper page mode (EDO)
cycle time
HPC
• Single + 3.3 V (± 0.3 V) supply
• Low power dissipation
max. 432 mW active (-50 version)
max. 396 mW active (-60 version)
max. 360 mW active (-70 version)
7.2 mW standby (LV-TTL)
3.6 mW standby (CMOS)
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh and test mode
• Hyper page mode (EDO) capability
• All inputs, outputs and clocks fully TTL-compatible
• 2048 refresh cycles / 32 ms (2k-Refresh)
• Plastic Package:
P-SOJ-28-3 400 mil
Semiconductor Group
1
1.96
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
The HYB 3117805BSJ is a 16 MBit dynamic RAM organized as 2 097 152 words by 8-bits. The HYB
3117805BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 3117805BSJ to be packaged in a standard
SOJ 28
plastic package with 400 mil width. These packages provide high system bit densities and are
compatible with commonly used automatic testing and insertion equipment. System-oriented
features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic
device families such as Schottky TTL.
Ordering Information
Type
Ordering Code Package
Descriptions
HYB 3117805BJ-50
HYB 3117805BJ-60
HYB 3117805BJ-70
Q67100-Q1151 P-SOJ-28-3 400 mil
Q67100-Q1152 P-SOJ-28-3 400 mil
P-SOJ-28-3 400 mil
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
Pin Names
A0-A10
A0-A9
RAS
OE
Row Address Inputs
Column Address Inputs
Row Address Strobe
Output Enable
I/O1-I/O8
CAS
WE
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply (+ 3.3 V)
Ground (0 V)
VCC
VSS
N.C.
not connected
Semiconductor Group
2
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
P-SOJ-28-3
400 mil
O
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
VCC
I/O1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
I/O2
I/O3
I/O4
5
6
WE
RAS
N.C.
A10
A0
7
A9
A8
A7
8
9
10
11
12
13
14
A1
A6
A5
A2
A3
VCC
A4
VSS
Pin Configuration
Semiconductor Group
3
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
I/O8
I/O1 I/O2
WE
&
.
CAS
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
8
8
Column
Address
Buffer(10)
10
Column
Decoder
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
8
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (11)
1024
x8
11
A10
Row
Address
Buffers(11)
Row
Decoder
Memory Array
2048x1024x8
11
11
2048
No. 1 Clock
Generator
RAS
Block Diagram
Semiconductor Group
4
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage...................................................................................................-1.0V to 4.6 V
Power dissipation..................................................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Vcc+0.5
0.8
1)
1)
1)
1)
Input high voltage
VIH
VIL
2.0
– 0.5
2.4
–
V
Input low voltage
V
TTL Output high voltage (IOUT = – 2 mA)
TTL Output low voltage (IOUT = 2 mA)
CMOS Output high voltage (IOUT = –100 uA)
CMOS Output low voltage (IOUT = 100 uA)
VOH
VOL
VOH
VOL
II(L)
–
V
0.4
V
VCC-0.2 –
V
–
0.2
V
1)
1)
Input leakage current
(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V)
– 10
10
µA
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V)
IO(L)
ICC1
– 10
10
µA
Average VCC supply current:
-50 ns version
2) 3) 4)
2) 3) 4)
2) 3) 4)
–
–
–
120
110
100
mA
mA
mA
-60 ns version
-70 ns version
(RAS, CAS, address cycling, tRC = tRC min.)
Standby VCC supply current (RAS = CAS = VIH) ICC2
Average VCC supply current, during RAS-only ICC3
–
2
mA
–
2) 4)
2) 4)
2) 4)
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
–
–
–
120
110
100
mA
mA
mA
(RAS cycling: CAS = VIH, tRC = tRC min.)
Semiconductor Group
5
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Average VCC supply current, during hyper page ICC4
2) 3) 4)
2) 3) 4)
2) 3) 4)
mode EDO):
-50 ns version
-60 ns version
-70 ns version
–
–
–
70
55
45
mA
mA
mA
(RAS = VIL, CAS, address cycling, tPC = tPC min.)
1)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
–
1
mA
Average VCC supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
ICC6
2) 4)
2) 4)
2) 4)
–
–
–
120
110
100
mA
mA
mA
-70 ns version
(RAS, CAS cycling, tRC = tRC min.)
ICC7
_
1
mA
Average Self Refresh Current
(CBR cylce with tRAS>TRASSmin., CAS held low,
WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Capacitance
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10)
Input capacitance (RAS, CAS, WE, OE)
I/O capacitance (I/O1-I/O8)
CI1
CI2
CIO
–
–
–
5
7
7
pF
pF
pF
Semiconductor Group
6
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
5)6)
16E
AC Characteristics
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
common parameters
Random read or write cycle time tRC
84
30
50
8
–
104
40
60
10
0
–
124
50
70
12
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RAS precharge time
RAS pulse width
tRP
–
–
–
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
10k
10k
–
10k
10k
–
10k
10k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
0
8
–
10
0
–
10
0
–
0
–
–
–
8
–
10
14
12
15
50
5
–
12
14
12
17
60
5
–
12
10
13
40
5
37
25
45
30
–
53
35
–
CAS hold time
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
–
1
50
32
1
50
32
1
50
32
ns
7
tREF
–
–
–
ms
Read Cycle
Access time from RAS
Access time from CAS
tRAC
tCAC
–
50
13
25
13
–
–
60
15
30
15
–
–
70
17
35
17
–
ns 8, 9
ns 8, 9
ns 8,10
ns
–
–
–
Access time from column address tAA
–
–
–
OE access time
tOEA
–
–
–
Column address to RAS lead time tRAL
25
0
30
0
35
0
ns
Read command setup time
Read command hold time
tRCS
tRCH
tRRH
–
–
–
ns
0
–
0
–
0
–
ns 11
ns 11
Read command hold time
referenced to RAS
0
–
0
–
0
–
CAS to output in low-Z
tCLZ
tOFF
tOEZ
0
0
0
–
0
0
0
–
0
0
0
–
ns
8
Output buffer turn-off delay
Output turn-off delay from OE
13
13
15
15
17
17
ns 12
ns 12
Semiconductor Group
7
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
5)6)
16E
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
Data to CAS low delay
Data to OE low delay
CAS high to data delay
OE high to data delay
tDZC
tDZO
tCDD
tODD
0
–
–
–
–
0
–
–
–
–
0
–
–
–
–
ns 13
ns 13
ns 14
ns 14
0
0
0
10
10
13
13
15
15
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
tWCH
tWP
8
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
8
ns
tWCS
0
ns 15
ns
Write command to RAS lead time tRWL
Write command to CAS lead time tCWL
13
13
0
15
15
0
17
17
0
ns
Data setup time
Data hold time
tDS
tDH
ns 16
ns 16
8
10
12
Read-modify-Write Cycle
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
113
64
–
–
–
–
–
138
77
–
–
–
–
–
162
89
–
–
–
–
–
ns
ns 15
ns 15
ns 15
ns
27
32
36
Column address to WE delay time tAWD
39
47
54
OE command hold time
tOEH
10
13
15
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle
time
tHPC
tCP
20
–
25
–
30
–
ns
ns
CAS precharge time
8
–
10
–
–
10
–
–
Access time from CAS precharge tCPA
–
27
–
32
–
37
–
ns
ns
7
Output data hold time
tCOH
5
5
5
RAS pulse width in EDO mode
CAS precharge to RAS Delay
tRAS
50
27
200k 60
32
200k 70
37
200k ns
ns
tRHPC
–
–
–
Semiconductor Group
8
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
5)6)
16E
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-
write cycle time
tPRWC
58
–
68
–
77
–
ns
ns
CAS precharge to WE
tCPWD
41
–
49
–
56
–
CAS-before-RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
10
10
10
10
10
10
Write hold time referenced to RAS tWRH
CAS-before-RAS Counter Test Cycle
CAS precharge time
tCPT
35
–
40
–
40
–
ns
Self Refresh Cycle
RAS pulse width
RAS precharge
CAS hold time
tRASS
tRPS
tCHS
100k _
100k _
100k _
ns 17
ns 17
ns 17
95
_
_
110
-50
_
_
130
-50
_
_
-50
Test Mode
Write command setup time
Write command hold time
CAS hold time
tWTS
tWTH
tCHRT
10
10
30
–
–
–
10
10
30
–
–
–
10
10
30
–
–
–
ns
ns
ns
Semiconductor Group
9
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of t is measured from tristate.
, t
, t ,t
, t
. t
RAC CAC AA CPA OEA CAC
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC
.
10) Operation within the tRAD (max. limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
)
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.)
,
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh
Semiconductor Group
10
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRSH
tCAS
tRCD
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
V
IH
Column
Row
Row
V
IL
tRCH
tRAH
tRCS
tRRH
V
IH
V
IL
tAA
tOEA
V
IH
OE
V
IL
tCDD
tDZC
tODD
tDZO
V
IH
I/O
(Inputs)
V
tCAC
tCLZ
IL
tOFF
tOEZ
V
OH
I/O
(Outputs)
Hi Z
Valid Data Out
Hi Z
V
OL
tRAC
WL1
“H” or “L”
Read Cycle
Semiconductor Group
11
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
V
IL
tCWL
tRAH
tWCS
V
tWP
IH
V
IL
tWCH
tRWL
V
IH
OE
V
IL
tDH
tDS
V
IH
I/O
(Inputs)
Valid Data In
V
IL
V
OH
I/O
(Outputs)
Hi Z
V
OL
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
12
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
V
IL
tCWL
tRWL
tWP
tRAH
V
IH
V
IL
tOEH
V
IH
OE
V
tODD
tDS
tOEZ
IL
tDH
tDZO
tDZC
V
IH
I/O
(Inputs)
Valid Data
V
IL
tCLZ
tOEA
V
OH
Hi-Z
I/O
(Outputs)
Hi-Z
V
OL
WL3
“H” or “L”
Write Cycle (OE Controlled Write)
Semiconductor Group
13
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
V
IL
tRSH
tCAS
tRCD
tCRP
V
IH
V
CAS
IL
tRAH
tCAH
tASR
tASC
tASR
V
IH
Address
Row
Column
Row
V
IL
tCWL
tRWL
tWP
tAWD
tRAD
tCWD
tRWD
V
IH
WE
OE
V
IL
tAA
tRCS
tOEH
tOEA
V
IH
V
IL
tDS
tDH
tDZO
tDZC
V
IH
Valid
Data in
I/O
(Inputs)
V
IL
tCLZ
tCAC
tODD
tOEZ
V
OH
I/O
(Outputs)
Data
Out
V
OL
tRAC
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
14
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRP
tRAS
V
tRCD
tRHCP
IH
RAS
V
IL
tRSH
tCAS
tCRP
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAL
tCAH
t
tASC
RAH tASC
tASC
tCAH
tCAH
tASR
V
IH
Address
Column 2
Column N
Row
Column 1
V
IL
tRAD
tRRH
tRCH
tRCS
V
IH
WE
OE
V
tCAC
CAC
t
IL
AA
t
AA
t
OFF
t
tOES
tOEA
CPA
t
tCPA
V
OH
V
OL
tRAC
tAA
tCAC
OEZ
t
tCOH
tCOH
tCLZ
V
I/O
IH
Data Out
1
Data Out
Data Out
N
(Output)
2
V
IL
WL5
“H” or “L”
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
15
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRP
tRAS
V
tRCD
tRHCP
IH
RAS
V
IL
tCRP
tRSH
tCAS
tHPC
tCAS
tCRP
tCAS
tCP
V
IH
CAS
V
IL
tCSH
tRAH
tRAL
tCAH
tASC
tASC
tCAH
tASC
tCAH
tASR
V
IH
Row
Addr
Address
Column 1
Column 2
Column N
V
IL
tRAD
tRWL
tCWL
tCWL
tCWL
tWCH
tWP
tWCS
tWCS
tWCS
tWCH
tWP
tWCH
tWP
V
IH
WE
V
IL
V
OH
OE
V
OL
tDS
tDH
tDS
tDH
tDH
tDS
V
IH
Data In 1
Data In 2
Data In N
I/O (Input)
V
IL
“H” or “L”
WL8
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
16
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
R
SA
t
PR
t
P
RC
t
H
L
L
EO
WR
t
WC
t
t
PW
HD
t
t
H
SR
L
t
DS
D
t
S
AR
t
DO
t
AC
D
t
D
W
WC
D
t
A
WA
P
C
EO
t
t
Z
t
AC
PCA
LC
ACH
t
t
t
t
A
t
C
C
H
L
SA
ZD
EO
t
t
t
WC
t
HD
PW
t
t
C
W
SD
t
S
D
ASP
RP
R
Z
AC
t
t
DO
t
D
t
EO
D
t
W
D
t
A
WA
PCW
t
H
t
Z
A
EO
t
AC
LC
PC
t
t
t
A
t
C
L
DZC
SA
t
t
PC
t
WC
t
EOH
t
PW
t
HD
t
SD
t
D
OEZ
t
DO
D
t
S
AC
WC
D
t
t
A
D
WA
EO
H
t
C
WR
Z
t
t
SCH
AC
t
AC
LC
t
A
t
t
t
C
O
SA
t
ZD
t
S
D
ARC
ZDC
CR
t
t
t
CR
t
ARD
H
t
AR
t
SAR
t
WL17
Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle
Semiconductor Group
17
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCRP
tRPC
V
IH
CAS
V
IL
tRAH
tASR
tASR
V
IH
Address
Row
Row
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H” or “L”
WL9
RAS-Only Refresh Cycle
Semiconductor Group
18
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRC
tRP
tRP
tRAS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCSR
tCRP
tRPC
tCHR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
tOEZ
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
ODD
t
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
19
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
V
IH
RAS
V
IL
tRSH
tRCD
tCRP
tCHR
V
IH
CAS
V
tRAD
IL
tWRP
tASC
tASR
tRAH
tWRH
tCAH
tASR
V
IH
Column
Address
Row
Row
V
IL
tRRH
tRCS
V
IH
WE
OE
V
IL
tAA
tOEA
V
IH
V
IL
tDZC
tDZO
tCDD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
OH
I/O
(Outputs)
Valid Data Out
HI-Z
V
OL
WL11
“H” or “L”
Hidden Refresh Cycle (Read) Cycle
Semiconductor Group
20
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRC
tRC
tRP
tRP
tRAS
V
tRAS
IH
RAS
V
IL
tRCD
tRSH
tCHR
tCRP
V
IH
CAS
tRAD
V
IL
tRAH
tASR
tASC
tCAH
tASR
V
IH
Address
Row
Column
Row
V
IL
tWCS
tWRP tWRH
tWCH
tWP
V
IH
WE
V
IL
tDS
tDH
V
IH
I/O
(Input)
Valid Data
V
IL
V
OH
I/O
(Output)
HI-Z
V
OL
“H” or “L”
WL12
Hidden Refresh Early Write Cycle
Semiconductor Group
21
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRP
tRASS
tRPS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCRP
tCHS
tCSR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
ODD
t
tOEZ
V
OH
I/O
HI-Z
(Outputs)
V
OL
tOFF
WL13
“H” or “L”
Self Refresh
Semiconductor Group
22
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRAS
t
RP
Read Cycle:
RAS
V
IH
IL
V
tRSH
tCAS
tCP
tCHR
tCSR
CAS
V
IH
V
tRAL
IL
tASR
tASC tCAH
Column
tAA
V
IH
IL
Address
WE
Row
V
tWRP
tRRH
tRCH
V
IH
IL
tCAC
V
tWRH
tOEA
tRCS
V
IH
IL
OE
V
tCDD
tDZC
V
tODD
I/O
IH
IL
(Inputs)
V
tDZO
tOFF
tCLZ
tOEZ
Out
V
I/O
(Outputs)
OH
OL
Data
V
tWCS
tWRP
tRWL
tCWL
tWCH
Write Cycle:
WE
V
IH
IL
V
tWRH
V
V
IH
IL
OE
tDS
tDH
I/O
(Inputs)
V
IH
IL
Data In
V
I/O
(Outputs)
V
IH
HI-Z
V
IL
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
23
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
tRC
tRP
tRAS
tRP
V
IH
RAS
CAS
V
tRPC
IL
tCSR
tCP
tCHR
tCRP
tRPC
V
IH
V
IL
tRAH
tASR
V
IH
Address
WE
Row
V
IL
tWTS
tWTH
V
IH
V
IL
V
IH
OE
V
IL
tODD
V
I/O
(Inputs)
IH
HI-Z
V
IL
tCDD
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
WL15
Test Mode Entry
Semiconductor Group
24
HYB3117805BSJ-50/-60/-70
2M x 8-EDO DRAM
Plastic Package P-SOJ-28-3 (400mil)
(Small Outline J-lead, SMD)
Package Outline
Semiconductor Group
25
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