Q67100-Q1323 [INFINEON]
16 MBit Synchronous DRAM; 16兆位同步DRAM
| 型号： | Q67100-Q1323 |
| 厂家： | 
Infineon |
| 描述： | 16 MBit Synchronous DRAM |
| 文件： | 总22页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 MBit Synchronous DRAM
(second generation)
HYB 39S16400/800/160AT-8/-10
Advanced Information
• High Performance:
• Multiple Burst Read with Single Write
Operation
CAS latency = 3
-8
125
8
-10 Units
100 MHz
• Automatic and Controlled Precharge
Command
fCK
tCK3
tAC3
10
8
ns
ns
• Data Mask for Read/Write control (× 4, × 8)
• Dual Data Mask for byte control (× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles/64 ms
7
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Random Column Address every CLK
(1-N Rule)
• Dual Banks controlled by A11 (Bank Select)
• Programmable CAS Latency: 1, 2, 3
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface versions
• Programmable Wrap Sequence: Sequential
or Interleave
• Plastic Packages:
P-TSOPII-44-1 400 mil width (× 4, × 8)
P-TSOPII-50-1 400 mil width (× 16)
• Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential type
1, 2, 4, 8 for Interleave type
The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM’s based on the die revisions “B”
and “C” and organized as 2 banks × 2 MBit × 4, 2 banks × 1 MBit × 8 and 2 banks × 512 kBit × 16
respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V ± 0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Ordering Information
Type
Ordering Code Package
Description
LVTTL-Version
HYB 39S16400AT-8 Q67100-Q1333 P-TSOPII-44-1 (400 mil) 125 MHz 2B × 2 M × 4 SDRAM
PC66 2-2-2
HYB 39S16400AT-10 Q67100-Q1323 P-TSOPII-44-1 (400 mil) 100 MHz 2B × 2 M × 4 SDRAM
PC66 2-2-2
HYB 39S16800AT-8 Q67100-Q1335 P-TSOPII-44-1 (400 mil) 125 MHz 2B × 1 M × 8 SDRAM
PC66 2-2-2
HYB 39S16800AT-10 Q67100-Q1327 P-TSOPII-44-1 (400 mil) 100 MHz 2B × 1 M × 8 SDRAM
PC66 2-2-2
HYB 39S16160AT-8 Q67100-Q1337 P-TSOPII-50-1 (400 mil) 125 MHz 2B × 512 k × 16 SDRAM
HYB 39S16160AT-10 Q67100-Q1331 P-TSOPII-50-1 (400 mil) 100 MHz 2B × 512 k × 16 SDRAM
Pin Names
CLK
CKE
Clock Input
DQ
Data Input/Output
Data Mask
Clock Enable
DQM, LDQM,
UDQM
CS
Chip Select
VDD
VSS
Power (+ 3.3 V)
Ground
RAS
Row Address Strobe
Column Address Strobe
Write Enable
CAS
VDDQ
VSSQ
NC
Power for DQ’s (+ 3.3 V)
Ground for DQ’s
Not connected
WE
A0 - A10
A11 (BS)
Address Inputs
Bank Select
Semiconductor Group
2
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
VDD
VSS
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DQ0
VSSQ
2
DQ7
VSSQ
3
DQ1
VDDQ
4
DQ6
VDDQ
5
DQ2
VSSQ
6
DQ5
VSSQ
7
DQ3
VDDQ
8
DQ4
VDDQ
9
N.C.
N.C.
WE
CAS
RAS
CS
10
11
12
13
14
15
16
17
18
19
20
21
22
N.C.
N.C.
DQM
CLK
CKE
N.C.
A9
A11
A10
A0
A8
A7
A1
A6
A2
A5
A3
VDD
A4
VSS
SPP03402
Pin Configuration
Semiconductor Group
3
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description
Pin
Type
Signal Polarity Function
Pulse Positive The system clock input. All of the SDRAM inputs are
CLK
Input
Edge
sampled on the rising edge of the clock.
CKE
CS
Input
Input
Level Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode or the Self Refresh mode.
Pulse Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS and WE define the command to be executed by
the SDRAM.
A0 - A10 Input
Level
–
During a Bank Activate command cycle, A0 - A10 defines
the row address (RA0 - RA10) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0 - A9 defines
the column address (CA0 - CAn) when sampled at the
rising clock edge. CAn depends from the SDRAM
organisation.
4M × 4 SDRAM CAn = CA9
2M × 8 SDRAM CAn = CA8
1M × 16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke
autoprecharge operation at the end of the burst read or
write cycle. If A10 is high, autoprecharge is selected and
A11 defines the bank to be precharged (low = bank A,
high = bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in
conjunction with A11 to control which bank(s) to
precharge. If A10 is high, both bank A and bank B will be
precharged regardless of the state of A11. If A10 is low,
then A11 is used to define which bank to precharge.
A11 (BS) Input
Level
Level
–
–
Selects which bank is to be active. A11 low selects bank A
and A11 high selects bank B.
DQx
Input
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
Output
Semiconductor Group
4
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description (cont’d)
Pin
Type
Signal Polarity Function
DQM
LDQM
UDQM
Input
Pulse Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
VDD
VSS
Supply –
–
–
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply –
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Semiconductor Group
5
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
CKE
CKE Buffer
Self
Refresh Clock
2048 x 1024
Row Decoder
Memory Bank A
2048
1024
Bank A
Row/Column
Select
Row
Address
Counter
4
Sense Amplifiers
CLK
CLK Buffer
Column Decoder
and DQ Gate
11
3
Predecode A
8
A0
A1
Sequential
Control
Bank A
A2
12
12
A3
Data Latches
A4
DQ0
A5
8
A6
DQ1
A7
11
3
Mode Register
A8
DQ2
A9
A10
A11 (BS)
DQ3
8
Sequential
Control
Bank B
CS
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
Data Latches
8
11
RAS
CAS
WE
Predecode B
Column Decoder
and DQ Gate
Bank B
Row/Column
Select
Sense Amplifiers
1024
Memory Bank B
2048 x 1024
DQM
Row Decoder
2048
SPB02835
Block Diagram for HYB 39S16400T (2 banks × 4 M × 4 SDRAM)
Semiconductor Group
6
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
CKE
CKE Buffer
Self
Refresh Clock
2048 x 512
Memory Bank A
2048
Row Decoder
8
512
Bank A
Row/Column
Select
Row
Address
Counter
8
Sense Amplifiers
8
8
CLK
CLK Buffer
Column Decoder
and DQ Gate
11
3
Predecode A
8
A0
A1
A2
Sequential
Control
Bank A
12
12
A3
Data Latches
8
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A5
A6
A7
11
3
Mode Register
A8
A9
A10
A11 (BS)
8
Sequential
Control
Bank B
8
8
CS
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
Data Latches
8
11
RAS
CAS
WE
Predecode B
Column Decoder
and DQ Gate
Bank B
Row/Column
Select
Sense Amplifiers
8
512
Memory Bank B
2048 x 512
DQM
Row Decoder
2048
SPB02836
Block Diagram for HYB 39S16800T (2 banks × 1 M × 8 SDRAM)
Semiconductor Group
7
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
CKE
CKE Buffer
Self
2048 x 256
Refresh Clock
Row Decoder
16
Memory Bank A
2048
16
256
Bank A
Row/Column
Select
Row
Address
Counter
Sense Amplifiers
16
16
CLK
CLK Buffer
Column Decoder
and DQ Gate
11
3
Predecode A
8
A0
DQ0
A1
DQ1
A2
Sequential
Control
Bank A
12
12
DQ2
A3
Data Latches
8
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
11
3
Mode Register
A8
DQ8
A9
DQ9
A10
A11 (BS)
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
8
Sequential
Control
Bank B
16
16
CS
CS Buffer
RAS Buffer
CAS Buffer
WE Buffer
DQM Buffer
DQM Buffer
Data Latches
8
11
RAS
CAS
WE
Predecode B
Column Decoder
and DQ Gate
Bank B
Row/Column
Select
Sense Amplifiers
16
256
Memory Bank B
2048 x 256
UDQM
LDQM
Row Decoder
2048
SPB02837
Block Diagram for HYB 39S16160T (2 banks × 512 k × 16 SDRAM)
Semiconductor Group
8
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the most important operation commands.
Operation
CS
H
L
RAS
X
CAS
X
WE
X
H
H
L
(L/U)DQM
Standby, Ignore RAS, CAS, WE and Address
Row Address Strobe and Activating a Bank
Column Address Strobe and Read Command
Column Address Strobe and Write Command
Precharge Command
X
X
X
X
X
X
X
X
L
L
H
L
L
H
H
L
L
L
L
H
H
L
L
Burst Stop Command
L
H
L
L
Self Refresh Entry
L
H
L
Mode Register Set Command
Write Enable/Output Enable
Write Inhibit/Output Disable
No Operation (NOP)
L
L
L
X
X
L
X
X
X
X
H
X
X
H
X
H
H
Mode Register
For application flexibility, a CAS latency, a burst length, and a burst sequence can be programmed
in the SDRAM mode register. The mode set operation must be done before any activate command
after the initial power up. Any content of the mode register can be altered by reexecuting the mode
set command. Both banks must be in precharged state and CKE must be high at least one clock
before the mode set operation. After the mode register is set, a Standby or NOP command is
required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set
operation. Address input data at this timing defines parameters to be set as shown in the following
table.
Semiconductor Group
9
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
BS
A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus (Ax)
Operation Mode
CAS Latency
Burst Length
Mode Register (Mx)
Operation Mode
Burst Type
M11 M10 M9 M8 M7
Mode
M3
Type
0
0
0
0
0
Normal
0
1
Sequential
Interleave
Multiple Burst
with Single
Write
X
X
1
0
0
Burst Length
Length
Interleave
1
CAS Latency
M2 M1 M0
M6 M5 M4
Latency
Reserve
1
Sequential
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
2
2
4
4
3
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Full Page *)
Reserve
Reserve
Reserve
Reserve
*) optional
Sequential Burst Addressing
Interleave Burst Addressing
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
SPD03138
Address Input for Mode Set (Mode Register Operation)
Semiconductor Group
10
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Read and Write Access Mode
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and
CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define
either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organisation and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches sense amplifiers. The maximum tRAS or the refresh
interval time limits the number of random column accesses. A new burst access can be done even
before the previous burst ends. The interrupt operation at every clock cycles is supported. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two banks are activated sequentially, interleaved bank read or write operations are possible.
With the programmed burst length, alternate access and precharge operations on two banks can
realize fast serial data access modes among many different pages. Once two banks are activated,
column to column interleave operation can be done between two different pages.
Refresh Mode
SDRAM has two refresh modes, a CAS-before-RAS (CBR) automatic refresh and a self refresh. All
of banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses and no bank information is required for both refresh
modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and
WE are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
The chip has an on-chip timer and the self refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one tRC delay is required prior to any access command.
Semiconductor Group
11
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
DQM Function
DQM has two functions for data I/O read write operations. During reads, when it turns to high at a
clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Suspend Mode
During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).
Power Down
In order to reduce standby power consumption, a power down mode is available. Bringing CKE low
enters the power down mode and all of receiver circuits are gated. All banks must be precharged
before entering this mode. One clock delay is required for mode entry and exit. The Power Down
mode does not perform any refresh operation.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the precharge operation one clock after the Read
Command is registered for CAS latencies of 1 and 2, and two clocks for CAS latencies of 3. If
CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated.
The SDRAM automatically enters the precharge operation one clock delay form the last data-in for
CAS latencies of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as tDPL
.
Precharge Command
If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes
require a time tDPL from the last burst data to apply the precharge command.
Semiconductor Group
12
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Bank Selection by Address Bits
A10
Low
Low
High
A11
Bank A only
Bank B only
Both A and B
Low
High
Don’t Care
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Power Up Procedure
All VDD and VDDQ must reach the specified voltage no later than any of input signal voltages. An
initial pause of 200 µs is required after power on. All banks have to be precharged and a minimum
of 2 auto-refresh cycles are required prior to the mode register set operation.
Semiconductor Group
13
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70 °C
Storage temperature range..................................................................................... – 55 to + 150 °C
Input/output voltage .......................................................................... – 0.5 to min (VCC + 0.5, 4.6) V
Power supply voltage VDD / VDDQ ............................................................................. – 1.0 to + 4.6 V
Power Dissipation....................................................................................................................... 1 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operation and Characteristics for LV-TTL Versions
TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
max.
Unit Notes
min.
2.0
1, 2
Input high voltage
VIH
VIL
V
CC + 0.3
V
1, 2
Input low voltage
– 0.3
2.4
0.8
–
V
Output high voltage (IOUT = – 2.0 mA)
Output low voltage (IOUT = 2.0 mA)
VOH
VOL
II(L)
V
–
0.4
10
V
Input leakage current, any input
– 10
µA
(0 V < VIN < VDDQ, all other inputs = 0 V)
Output leakage current
IO(L)
– 10
10
µA
(DQ is disabled, 0 V < VOUT < VCC)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol max. Values Unit
Input capacitance (A0 to A11)
CI1
4
4
5
8
pF
pF
pF
pF
Input capacitance (RAS, CAS, WE, CS, CLK, CKE, DQM)
CI2
Output capacitance (DQ)
CIO
CREF
VREF
Semiconductor Group
14
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Operating Currents
TA = 0 to 70 oC, VCC = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol Test Condition
CAS
Latency
-8
-10 Unit Note
max. max.
80 65
115 90
6, 7
Operating current ICC1
Burst Length = 4
1
2
3
mA
mA
t
t
RC ≥ tRC(MIN.)
CK ≥ tCK(MIN.), IO = 0 mA
125 100 mA
2 bank interleave operation
Precharge
ICC2P
CKE ≤ VIL(MAX.), tCK ≥ tCK(MIN.)
–
3
3
mA
mA
Standby current in
Power Down
Mode
ICC2PS CKE ≤ VIL(MAX.), tCK = infinite –
2
2
Precharge
ICC2N
CKE ≥ VIH(MIN.)
CK ≥ tCK(MIN.) input signals
changed once in 3 cycles
,
–
20
20
mA CS = High
Standby current in
Non-power down
Mode
t
ICC2NS CKE ≥ VIH(MIN.),tCK = infinite, –
10
10
mA
input signals are stable
Active Standby
current in Power
Down Mode
ICC3P
ICC3PS CKE ≤ VIL(MAX.)
CK = infinite, input signals
CKE ≤ VIL(MAX)., tCK ≥ tCK(MIN.)
–
–
3
2
3
2
mA
mA
,
t
are stable
Active Standby
current in Non-
power Down
Mode
ICC3N
CKE ≥ VIH(MIN.)
,
–
–
25
15
25
15
mA CS = High
6
t
CK ≥ tCK(MIN.), changed once
in 3 cycles
ICC3NS CKE ≥ VIH(MIN.)
,
mA
t
CK = infinite, input signals
are stable
6, 7
Burst Operating
current
ICC4
Burst Length = full page
1
2
3
50
80
120 95
40
65
mA
t
t
RC = infinite
CK ≥ tCK(MIN.), IO = 0 mA
2 banks activated
6, 7
Auto (CBR)
Refresh current
ICC5
t
RC ≥ tRC(MIN.)
1
2
3
75
95
115 90
60
75
mA
mA
mA
6, 7
Self Refresh
ICC6
CKE ≤ 0.2 V
–
2
2
mA
Semiconductor Group
15
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
8, 9
AC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-10
min. max. min. max.
Unit Note
-8
Clock and Clock Enable
Clock Cycle time
tCK
tCK
tAC
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
8
12
24
–
–
–
10
15
30
–
–
–
ns
ns
ns
System frequency
Clock Access time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
–
–
125
83
41
–
–
–
100
66
33
MHz
MHz
MHz
10
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
–
–
7
8
21
–
–
–
8
9
27
ns
ns
ns
Clock High Pulse width
Clock Low Pulse width
tCH
tCL
tT
3
3
1
–
3.5
3.5
1
–
ns
ns
ns
–
–
Transition time (rise and fall)
30
30
Setup and Hold Times
Command Setup time
Address Setup time
11
tCS
2.5
2.5
2.5
2.5
2.5
8
–
–
–
–
–
–
–
–
–
–
3
3
3
3
3
8
1
1
1
1
–
–
–
–
–
–
–
–
–
–
ns
11
tAS
ns
11
Data In Setup time
tDS
ns
11
CKE Setup time
tCKS
tCKSP
tCKSR
tCH
ns
11
CKE Set-up time (Power down mode)
CKE Set-up time (Self Refresh Exit)
Command Hold time
Address Hold time
ns
ns
11
1
ns
11
tAH
1
ns
11
Data In Hold time
tDH
1
ns
11
CKE Hold time
tCKH
1
ns
Semiconductor Group
16
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
AC Characteristics (cont’d) 8, 9
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-10
min. max. min. max.
Unit Note
-8
Common Parameters
Row to Column Delay time
Row Active time
tRCD
tRAS
tRP
24
36
24
60
16
1
–
30
120k 45
30
120k 75
–
ns
120k ns
ns
120k ns
Precharge time
–
–
Row Cycle time
tRC
Bank to Bank delay time
CAS to CAS delay time (same bank)
tRRD
tCCD
–
–
20
1
–
–
ns
CLK
Refresh Cycle
13
12
Self Refresh Exit time
Refresh period (4096 cycles)
tSREX
tREF
2 CLK + tRC
ns
–
64
–
64
ms
Read Cycle
Data Out Hold time
tOH
tLZ
3
0
–
–
3
0
–
–
ns
ns
Data Out to Low Impedance time
14
Data Out to High Impedance time
tHZ
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
–
–
5
7
19
–
–
–
6
8
25
ns
ns
ns
DQM Data Out Disable Latency
tDQZ
2
–
2
–
CLK
Write Cycle
Last Data-Input to Precharge
(Write Recovery Latency)
CL = 1, 2 tDPL
CL = 3
1
2
–
–
1
2
–
–
CLK
CLK
DQM Write Mask Latency
tDQW
0
–
0
–
CLK
Semiconductor Group
17
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Notes
1. All voltages are referenced to VSS.
2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to
– 2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50 % points with amplitude
measured peak to DC reference.
3. Under all conditions VDDQ must be less than or equal to VDD.
4. The value of VREF may be selected by the user to provide optimum noise margin in the system.
VREF has to be in the range between 0.43 × VDDQ and 0.47 × VDDQ and is expected to track
variations in VDDQ
5. VIH may overshoot to VDD, VDDQ + 1.2 V for pulse width < 5 ns and VIL may undershoot to VSS,
SSQ – 1.2 V for pulse width < 5 ns.
.
V
6. The specified values are valid when addresses are changed no more than three times during
tRC(MIN.) and when No Operation commands are registered on every rising clock edge during
tRC(MIN.)
.
7. The specified values are valid when data inputs (DQ’s) are stable during tRC(MIN.)
.
8. An initial pause of 200 µs is required after power-up, then a Precharge All Banks command
must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set
Operation can begin.
9. AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced
to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC
measurements assume tT = 1 ns with the AC output load circuit shown in figure below.
10. If clock rising time is longer than 1 ns, (tT/2 – 0.5) ns has to be added to this parameter.
11. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
12. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
13. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
14. Referenced to the time which the output achieves the open circuit condition, not to output
voltage levels.
Semiconductor Group
18
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
tCH
2.4 V
0.4 V
CLOCK
tT
tCL
tHOLD
tSETUP
INPUT
1.4 V
tAC
tAC
tLZ
tOH
OUTPUT
1.4 V
tHZ
SPT03404
Semiconductor Group
19
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Clock Frequency and Latency
Parameter
Symbol
Speed Sort
Unit
-8
125 83
-10
Clock frequency
Clock Cycle time
CAS latency
max. tCK
100 66
MHz
ns
min. tCK
min. tAA
min. tRCD
min. tRL
min. tRAS
max. tRAS
min. tRP
min. tRC
8
3
3
6
5
12
2
10
3
15
2
CLK
CLK
CLK
CLK
Row to Column delay
RAS latency
2
3
2
4
6
4
Row Active time
3
5
3
120 120 120 120 µs
Row Precharge time
Row Cycle time
3
8
2
5
2
1
0
0
2
1
2
5
1
3
2
1
0
0
2
1
3
8
2
5
2
1
0
0
2
1
2
5
1
3
2
1
0
0
2
1
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Last Data-In to Precharge (Write Recovery) min. tDPL
Last Data-In to Active/Refresh
Bank to Bank delay time
CAS to CAS delay time
Write latency
min.
tDPL + tRP
min. tRRD
min. tCCD
fixed tWL
fixed tDQW
fixed tDQZ
fixed tCSL
DQM Write Mask latency
DQM Data Disable latency
Clock Suspend latency
Semiconductor Group
20
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Package Outlines
Plastic Package P-TSOPII-44
(400 mil, 0.8 mm lead pitch)
Thin Small Outline Package, SMD
15˚±5˚
15˚±5˚
2)
10.16±0.13
0.8
0.5±0.1
11.76±0.2
0.1 44x
21x 0.8 = 16.8
3)
M
0.2
44x
+0.1
0.35
-0.05
44
23
22
1
2.5 max
1)
18.41 ±0.13
GPX05941
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max per side
2) Does not include plastic protrusion of 0.25 max per side
3) Does not include dambar protrusion of 0.13 max per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
21
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Plastic Package P-TSOPII-50
(400 mil, 0.8 mm lead pitch)
Thin Small Outline Package, SMD
.06
10.16±
0.13
0
0.03
+
-
0.15
0.8
0.5±
0.1
11.76±
0.2
0.4+- 0.05
0.1
M
0.2
50x
0.1
50
26
1
25
1)
20.95±
0.13
GPX05956
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
22
1998-10-01
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