SP000938784_技术文档

IFX1763 V50

Wide Input Range Low Noise 500mA 5V LDO

IFX1763XEJV50

IFX1763LDV50

Data Sheet

Rev. 1.11, 2015-01-30

Standard Power

Wide Input Range Low Noise 500mA 5V LDO

IFX1763XEJV50

IFX1763LDV50

1

Overview

Features

•

Low Noise down to 42 µV_RMS(BW = 10 Hz to 100 kHz)

500mA Current Capability

Low Quiescent Current: 30 µA

Wide Input Voltage Range up to 20 V

Internal circuitry working down to 1.8 V

2.5% Output Voltage Accuracy (over full temperature and load range)

Low Dropout Voltage: 350 mV

Very low Shutdown Current: < 1 µA

No Protection Diodes Needed

PG-DSO-8 Exposed Pad

Fixed Output Voltage: 5.0 V

Stable with ≥ 3.3 µF Output Capacitor

Stable with Aluminium, Tantalum or Ceramic Capacitors

Reverse Battery Protection

No Reverse Current

Overcurrent and Overtemperature Protected

PG-DSO-8 Exposed Pad and TSON-10 Exposed Pad Packages

Green Product (RoHS compliant)

PG-TSON-10

Applications

•

Microcontroller Supply

Battery-Powered Systems

Noise Sensitive Instruments

Radar Applications

Image Sensors

The IFX1763 V50 is not qualified and manufactured according to the requirements of Infineon Technologies with

regards to automotive and/or transportation applications. For automotive applications please refer to the Infineon

TLx (TLE, TLS, TLF.....) voltage regulator products.

Type

Package

Marking

1763EV50

176LV50

IFX1763XEJV50

IFX1763LDV50

PG-DSO-8 Exposed Pad

PG-TSON-10

Data Sheet

2

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Overview

The IFX1763 V50 is a micropower, low noise, low dropout 5 V voltage regulator. The device is capable of

supplying an output current of 500 mA with a dropout voltage of 350 mV. Designed for use in battery-powered

systems, the low quiescent current of 30 µA makes it an ideal choice.

One feature of the IFX1763 V50 is its low output noise: by adding an external 0.01 µF bypass capacitor output

noise values down to 42 µV_RMSover a 10 Hz to 100 kHz bandwidth can be reached. The IFX1763 V50 voltage

regulator is stable with output capacitors as small as 3.3 µF. Small ceramic capacitors can be used without the

series resistance required by many other regulators. Its internal protection circuitry includes reverse battery

protection, current limiting and reverse current protection. The IFX1763 V50 is available in a PG-DSO-8 Exposed

Pad and as well as in a TSON10 exposed pad package.

Data Sheet

3

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Block Diagram

2

Block Diagram

Note:Pin numbers in the block diagram refer to the DSO-8 EP package type.

Saturation

IFX1763

Control

IN

8

5

1

OUT

Over Current

Protection

Temperature

Protection

EN

Bias

Voltage

reference

4

BYP

Error

Amplifier

2

SENSE

6

GND

Figure 1

Block Diagram IFX1763 V50

Data Sheet

4

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

1

2

8

7

OUT

IN

SENSE

NC

3

4

6

5

NC

GND

EN

9

BYP

IFX1763XEJ V50

Figure 2

Pin Configuration of IFX1763XEJV50 in PG-DSO-8 Exposed Pad

OUT

1

2

3

4

5

10

9

IN

NC

8

NC

EN

SENSE

BYP

7

11

6

GND

IFX1763LD V50

Figure 3

Pin Configuration of IFX1763LDV50 in PG-TSON10

Data Sheet

5

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Pin Configuration

3.2

Pin Definitions and Functions

Symbol

Function

1 (DSO-8 EP)

1,2 (TSON-10)

OUT

Output. Supplies power to the load. For this pin a minimum output capacitor of

3.3 µF is required to prevent oscillations. Larger output capacitors may be

required for applications with large transient loads in order to limit peak voltage

transients or when the regulator is applied in conjunction with a bypass capacitor.

For more details please refer to the section “Application Information” on

Page 19.

2 (DSO-8 EP)

4 (TSON-10)

SENSE

Output Sense. The SENSE pin is the input to the error amplifier. This allows to

achieve an optimized regulation performance in case of small voltage drops R_p

that occur between regulator and load. In applications where such drops are

relevant they can be eliminated by connecting the SENSE pin directly at the load.

In standard configurations the SENSE pin can be connected directly to the OUT

pin. For further details please refer to the section “Kelvin Sense Connection”

on Page 19.

3, 7 (DSO-8 EP) NC

3, 8 (TSON-10)

No Connect. The NC Pins have no connection to any internal circuitry. Connect

either to GND or leave open.

4 (DSO-8)

5 (TSON-10)

BYP

Bypass. The BYP pin is used to bypass the reference of the IFX1763 V50 to

achieve low noise performance. The BYP-pin is clamped internally to ±0.6 V (i.e.

one V_BE). A small capacitor from the output to the BYP pin will bypass the

reference to lower the output voltage noise¹⁾. If not used this pin must be left

unconnected.

5 (DSO-8 EP)

7 (TSON-10)

EN

Enable. With the EN pin the IFX1763 V50 can be put into a low power shutdown

state. The output will be off when the EN is pulled low. The EN pin can be driven

by 5V logic or open-collector logic with pull-up resistor. The pull-up resistor is

required to supply the pull-up current of the open-collector gate²⁾and the EN pin

current³⁾. Please note that if the EN pin is not used it must be connected to V_IN. It

must not be left floating.

6 (DSO-8 EP)

6,(TSON-10)

GND

IN

Ground.

8 (DSO-8 EP)

Input. Via the input pin IN the power is supplied to the device. A capacitor at the

input pin is required if the device is more than 6 inches away from the main input

filter capacitor or if bigger inductance is present at the IN pin⁴⁾. The IFX1763 V50

is designed to withstand reverse voltages on the Input pin with respect to GND

and Output. In the case of reverse input (e.g. due to a wrongly attached battery)

the device will act as if there is a diode in series with its input. In this way there will

be no reverse current flowing into the regulator and no reverse voltage will appear

at the load. Hence, the device will protect both - the device itself and the load.

9, 10 (TSON-10)

9 (DSO-8 EP)

11 (TSON-10)

Tab

Exposed Pad. To ensure proper thermal performance, solder Pin 11 (exposed

pad) of TSON10 to the PCB ground and tie directly to Pin 6. In the case of DSO-

8 EP as well solder Pin 9 (exposed pad) to the PCB ground and tie directly to Pin

6.

1) A maximum value of 10 nF can be used for reducing output voltage noise over the bandwidth from 10 Hz to 100 kHz.

2) Normally several microamperes.

3) Typical value is 1 µA.

4) In general the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-

powered circuits. Depending on actual conditions an input capacitor in the range of 1 to 10 µF is sufficient.

Data Sheet

6

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise

specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

-20

Max.

Input Voltage

Voltage

V_IN

–

20

V

–

P_4.1.1

Output Voltage

Voltage

V_OUT

-20

–

20

V

–

P_4.1.2

P_4.1.3

Input to Output Differential

Voltage

V_IN- V_OUT-20

Sense Pin

Voltage

V_SENSE

V_BYP

V_EN

-20

-0.6

-20

–

20

0.6

20

V

–

P_4.1.4

P_4.1.5

P_4.1.6

BYP Pin

Voltage

Enable Pin

Voltage

–

Temperatures

Junction Temperature

Storage Temperature

ESD Susceptibility

All Pins

T_j

-40

-55

–

150

°C

–

P_4.1.7

P_4.1.8

T_stg

V_ESD

-2

-1

–

2

1

kV

HBM²⁾

CDM³⁾

P_4.1.9

All Pins

P_4.1.10

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not

designed for continuous repetitive operation.

Data Sheet

7

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

Parameter

Symbol

Values

Unit Note /

Test Condition

Number

Min.

5.5

Typ.

Max.

20

Input Voltage Range

V_IN

T_j

–

V

–

P_4.2.1

P_4.2.2

Operating Junction Temperature

-40

125

°C

–

Note:Within the functional or operating range, the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the Electrical Characteristics table.

4.3

Thermal Resistance

Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 3

Thermal Resistance¹⁾

Symbol

Parameter

Values

Typ.

Unit

Note /

Test Condition

Number

Min.

Max.

IFX1763X EJ (PG-DSO-8 Exposed Pad)

Junction to Case

R_thJC

R_thJA

–

7.0

39

–

K/W

–

P_4.3.1

P_4.3.2

P_4.3.3

2)

Junction to Ambient

–

155

66

Footprint only³⁾

300 mm²heatsink P_4.3.4

area on PCB³⁾

Junction to Ambient

R_thJA

–

52

–

K/W

600 mm²heatsink P_4.3.5

area on PCB³⁾

IFX1763 LD (PG-TSON10)

Junction to Case

R_thJC

R_thJA

–

6.4

53

–

K/W

–

P_4.3.6

P_4.3.7

P_4.3.8

2)

Junction to Ambient

183

69

Footprint only³⁾

300 mm²heatsink P_4.3.9

area on PCB³⁾

Junction to Ambient

R_thJA

–

57

–

K/W

600 mm²heatsink P_4.3.10

area on PCB³⁾

1) Not subject to production test, specified by design.

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 x 70µm Cu).

Data Sheet

8

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Electrical Characteristics

5

Electrical Characteristics

5.1

Electrical Characteristics Table

Table 4

Electrical Characteristics

-40 °C < T_j< 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless

otherwise specified.

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Number

Min.

Max.

2.3

Minimum Operating Voltage¹⁾

Minimum Operating Voltage

Output Voltage²⁾

V_IN,min

V_OUT

–

1.8

V

I

_OUT= 500 mA

P_5.1.1

P_5.1.2

Output Voltage

4.875 5.00

5.125

1 mA < I_OUT< 500 mA;

6 V < V_IN< 20 V

Line Regulation

∆V_OUT

–

1

25

mV

ꢀV_IN= 5.5 V to 20 V;

P_5.1.3

I

_OUT= 1 mA

Load Regulation

∆V_OUT

–

16

–

32

57

mV

T_J= 25°C; V_IN= 6.0 V;

∆I_OUT= 1 to 500 mA

P_5.1.4

P_5.1.5

Load Regulation

V_IN= 6.0V;

∆I_OUT= 1 to 500 mA

Dropout Voltage³⁾

Dropout Voltage

V_DR

–

110

–

140

190

200

250

230

300

380

480

mV

I

_OUT= 10 mA;

V_IN= V_OUT,nom; T_J= 25°C

_OUT= 10 mA;

V_IN= V_OUT,nom

_OUT= 50 mA;

V_IN= V_OUT,nom; T_J= 25°C

_OUT= 50 mA;

V_IN= V_OUT,nom

_OUT= 100 mA;

V_IN= V_OUT,nom; T_J= 25°C

_OUT= 100 mA;

V_IN= V_OUT,nom

_OUT= 500 mA;

V_IN= V_OUT,nom; T_J= 25°C

_OUT= 500 mA;

V_IN= V_OUT,nom

P_5.1.6

P_5.1.7

P_5.1.8

P_5.1.9

P_5.1.10

P_5.1.11

P_5.1.12

P_5.1.13

Dropout Voltage

I

170

–

I

200

–

I

350

–

I

GND Pin Current⁴⁾

GND Pin Current

I_GND

–

30

50

60

µA

V_IN= V_OUT,nom;

_OUT= 0 mA

V_IN= V_OUT,nom;

_OUT= 1 mA

P_5.1.14

P_5.1.15

I

GND Pin Current

Data Sheet

100

I

9

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Electrical Characteristics

Table 4

Electrical Characteristics (cont’d)

-40 °C < T_j< 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless

otherwise specified.

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Number

Min.

Max.

GND Pin Current

I_GND

–

300

850

µA

V_IN= V_OUT,nom;

P_5.1.16

P_5.1.17

P_5.1.18

P_5.1.19

P_5.1.20

I

_OUT= 50 mA

V_IN= V_OUT,nom;

_OUT= 100 mA

V_IN= V_OUT,nom;

_OUT= 250 mA

V_IN= V_OUT,nom;

_OUT= 500 mA; T_J≥ 25°C

V_IN= V_OUT,nom;

_OUT= 500 mA; T_J< 25°C

–

0.7

3

2.2

8

mA

I

11

22

31

I

Quiescent Current in Shutdown

Quiescent Current in Off-Mode I_q

(EN-pin low)

–

0.1

1

µA

V_IN= 6 V; V_EN= 0 V;

T_J= 25°C

P_5.1.21

Enable

Enable Threshold High

Enable Threshold Low

EN Pin Current⁵⁾

V_th,EN

–

0.8

0.65

0.01

1

2.0

–

V

_OUT= Off to On

P_5.1.22

P_5.1.23

P_5.1.24

P_5.1.25

V_tl,EN

I_EN

0.25

–

V

_OUT= On to Off

–

µA

_EN= 0 V; T_J= 25°C

_EN= 20 V; T_J= 25°C

EN Pin Current⁵⁾

I_EN

–

Output Voltage Noise⁶⁾

Output Voltage Noise

e_no

–

55

–

µV_RMS

C

_OUT= 10 µF ceramic;

_BYP= 10 nF;

P_5.1.26

I

_OUT= 500 mA;

(BW = 10 Hz to100 kHz)

_OUT= 10µF ceramic

+250mΩ resistorinseries;

_BYP= 10 nF;

_OUT= 500 mA;

(BW = 10 Hz to100 kHz)

Output Voltage Noise

e_no

44

µV_RMSC

P_5.1.27

C

I

Output Voltage Noise

e_no

–

42

–

µV_RMS

C

_OUT= 22 µF ceramic;

_BYP= 10 nF;

P_5.1.28

P_5.1.29

I

_OUT= 500 mA;

(BW = 10 Hz to100 kHz)

_OUT= 22 µF ceramic

+250mΩ resistorinseries;

_BYP= 10 nF;

_OUT= 500 mA;

(BW = 10 Hz to100 kHz)

e_no

µV_RMSC

C

I

Power Supply Ripple Rejection⁶⁾

Power Supply Ripple Rejection PSRR

50

65

–

dB

V_IN- V_OUT= 1.5 V (avg); P_5.1.30

_RIPPLE= 0.5 Vpp;

f_r= 120 Hz;

_OUT= 500mA

V

I

Data Sheet

10

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Electrical Characteristics

Table 4

Electrical Characteristics (cont’d)

-40 °C < T_j< 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless

otherwise specified.

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Number

Min.

Max.

Output Current Limitation

Output Current Limit

I_OUT,limit520

–

mA

V_IN= 7 V; V_OUT= 0 V

P_5.1.31

P_5.1.32

Output Current Limit

V_IN= V_OUT,nom+ 1 V

∆V_OUT= -0.1 V

Input Reverse Leakage Current

Input Reverse Leakage

Reverse Output Current⁷⁾

Reverse Output Current

I_leak,rev

–

1

mA

µA

V_IN= -20 V; V_OUT= 0 V

P_5.1.33

P_5.1.34

I_Reverse

10

20

V_OUT= V_OUT,nom;

V_IN< V_OUT,nom

T_J= 25°C

;

Output Capacitor⁶⁾

Output Capacitance

ESR

C_OUT

ESR

3.3

–

3

µF

C_BYP= 0 nF

P_5.1.35

P_5.1.36

8)

–

Ω

–

1) This parameter defines the minimum input voltage for which the device is powered up and provides the maximum nominal

output current of 500 mA. Under this minimum input voltage condition the IFX1763 V50 starts to be in tracking mode and

the output voltage will typically be in the range of around 1 V while providing the 500 mA.

2) The operation conditions are limited by the maximum junction temperature. The regulated output voltage specification will

only apply for conditions where the limit of the maximum junction temperature is fulfilled. It will therefore not apply for all

possible combinations of input voltage and output current. When operating at maximum input voltage, the output current

must be limited for thermal reasons. The same holds true when operating at maximum output current where the input

voltage range must be limited for thermal reasons.

3) The dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output

current. In dropout, the output voltage will be equal to V_IN- V_DR

.

4) GND-pin current is tested with V_IN= V_OUT,nomand a current source load. This means that this parameter is tested while being

in dropout condition and thus reflects a worst case condition. The GND-pin current will in most cases decrease slightly at

higher input voltages - please also refer to the corresponding typical performance graphs.

5) The EN pin current flows into EN pin.

6) Not subject to production test, specified by design.

7) Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current

flows into the OUT pin and out of the GND pin.

8) C_BYP= 0 nF, C_OUT≥ 3.3 µF; please note that for cases where a bypass capacitor at BYP is used - depending on the actual

applied capacitance of C_OUTand C_BYP- a minimum requirement for ESR may apply. For further details please also refer to

the corresponding typical performance graph.

Note:The listed characteristics are ensured over the operating range of the integrated circuit. Typical

characteristics specified mean values expected over the production spread. If not otherwise specified,

typical characteristics apply at T_A= 25°C and the given supply voltage.

Data Sheet

11

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Typical Performance Characteristics

6

Typical Performance Characteristics

Dropout Voltage V_DRversus

Output Current I_OUT

Guaranteed Dropout Voltage V_DRversus

Output Current I_OUT

500

450

400

350

300

250

200

150

100

50

Δ = Guaranteed Limits

450

400

350

300

250

200

150

100

50

T_j= −40 °C

T_j= 25 °C

T_j= 125 °C

T_j≤ 25 °C

T_j≤ 125 °C

0

100

200

300

400

500

0

100

200

300

400

500

I_OUT[A]

Dropout Voltage V_DRversus

Junction Temperature T_J

Quiescent Current versus

Junction Temperature T_J

500

50

45

40

35

30

25

20

15

10

5

I_OUT= 10 mA

450

I_OUT= 50 mA

I_OUT= 100 mA

400

I_OUT= 500 mA

350

300

250

200

150

100

50

V_IN= 6 V

I_OUT= 0 mA .

V_EN= V

IN

0

−50

0

50

T_j[°C]

100

−50

0

50

T_j[°C]

100

Data Sheet

12

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Typical Performance Characteristics

Output Voltage V_OUTversus

Junction Temperature T_J

Quiescent Current I_qversus

Input Voltage V_IN

800

700

600

500

400

300

200

100

0

5.08

5.06

5.04

5.02

5

4.98

4.96

4.94

V_OUT,nom= 5.0 V

I_OUT,nom= 0 mA

V_EN= V

IN

T_j= 25 °C

4.92

I_OUT= 1 mA

4.9

−50

0

50

T_j[°C]

100

0

2

4

6

8

10

V_IN[V]

GND Current I_GNDversus

Input Voltage V_IN

GND Current I_GNDversus

Input Voltage V_IN

1600

16

R_Load= 5.0 kΩ / I_OUT= 1 mA*

R_Load= 100 Ω / I_OUT= 50 mA*

R_Load= 50.0 Ω / I_OUT= 100 mA*

R_Load= 16.7 Ω / I_OUT= 300 mA*

R_Load= 10.0 Ω / I_OUT= 500 mA *.

1400

1200

1000

800

600

400

200

0

14

12

10

8

[* for V_OUT= 5.0 V]

T_j= 25°C

[* for V_OUT= 5.0 V]

T_j= 25°C

6

4

2

0

2

4

6

8

10

0

2

4

6

8

10

V_IN[V]

Data Sheet

13

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Typical Performance Characteristics

GND Current I_GNDversus

Output Current I_OUT

EN Pin Threshold (On-to-Off) versus

Junction Temperature T_J

1.2

1

12

1 mA

500 mA

V_IN= 6 V

T_j= 25 ° C

10

8

0.8

0.6

0.4

0.2

0

6

4

2

0

−50

0

50

T_j[°C]

100

0

100

200

I_OUT[mA]

300

400

500

EN Pin Threshold (Off-to-On) versus

Junction Temperature T_J

EN Pin Current I_ENversus

EN Pin Voltage V_EN

1.2

1

1.4

1.2

1

T_j= 25 °C

V_IN= 20 V

1 mA

500 mA

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

−50

0

50

T_j[°C]

100

0

5

10

V_EN[V]

15

20

Data Sheet

14

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Typical Performance Characteristics

EN Pin Current versus

Current Limit versus

Junction Temperature T_J

Input Voltage V_IN

1.6

1.4

1.2

1

V_OUT= 0 V

V_EN= 20 V

T = 25 ° C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

j

0.8

0.6

0.4

0.2

0

−50

0

50

T_j[°C]

100

0

1

2

3

4

5

6

7

V_IN[V]

Current Limit versus

Reverse Output Current versus

Junction Temperature T_J

Output Voltage V_OUT

1.2

1

90

V_OUT.nom= 5.0 V (V50)

V_IN= 7 V

V_OUT= 0 V

80

70

V_IN= 0 V

T_j= 25 °C

0.8

0.6

0.4

0.2

0

60

50

40

30

20

10

0

−50

0

50

T_j[°C]

100

0

2

4

6

8

10

V_OUT[V]

Data Sheet

15

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Typical Performance Characteristics

Reverse Output Current versus

Minimum Input Voltage¹⁾versus

Junction Temperature T_J

22

2.5

V_OUT.nom= 5.0 V (V50)

20

18

2

1.5

1

V_IN= 0 V

16

14

12

10

8

6

0.5

0

4

I_OUT= 100 mA

I_OUT= 500 mA

2

0

−50

0

50

T_j[°C]

100

−50

0

50

T_j[°C]

100

Load Regulation versus

Junction Temperature T_J

0

V_IN= 6.0 V; V_OUT.nom= 5.0 V

−5

−10

−15

−20

−25

−30

ΔI_Load= 1 mA to 500 mA

−50

0

50

T_j[°C]

100

1) V_IN,min is referred here as the minimum input voltage for which the requested current is provided and V_OUTreaches 1 V.

Data Sheet

16

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Typical Performance Characteristics

ESR Stability versus

ESR(C_OUT) with C_BYP= 10 nF versus

Output Current I_OUT(for C_OUT= 3.3µF)

Output Capacitance C_OUT

3

2.5

2

10¹

C_Byp= 10 nF

measurement limit

ESR_maxC_Byp= 0 nF

10⁰

stable region above blue line

ESR_minC_Byp= 0 nF

ESR_maxC_Byp= 10 nF

ESR_minC_Byp= 10 nF

1.5

1

C_OUT= 3.3 µF

(0.06 Ω is measurement limit)

0.5

0

10⁻¹

0

100

200

300

400

500

2

3

4

5

6

7

I_OUT[mA]

C_OUT[µF]

Input Ripple Rejection PSRR versus

Frequency f

Input Ripple Rejection PSRR versus

Junction Temperature T_J

68

66

64

62

60

58

100

V_IN= V_OUTnom+ 1.5 V

V_ripple= 0.5 V_pp

C_OUT= 10 µF

90

80

70

60

50

40

30

20

10

0

56

V_IN= V_OUTnom+ 1.5 V

V_ripple= 0.5 V_pp

54

52

50

f_ripple= 120 Hz

C_OUT= 10 µF

I_OUT=500mA C_BYP=0 nF

I_OUT=500mA C_BYP=10nF

I_OUT=50mA C_BYP=0 nF

I_OUT=50mA C_BYP=10nF

I_OUT=500mA C_BYP=0 nF

I_OUT=500mA C_BYP=10nF

50

T_j[°C]

−50

0

100

10

100

1k

10k

100k

f [Hz]

Data Sheet

17

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Typical Performance Characteristics

Output Noise Spectral Density versus

Frequency (C_OUT= 10µF, I_OUT= 50mA¹⁾)

Output Noise Spectral Density versus

Frequency (C_OUT= 22µF, I_OUT= 50mA¹⁾)

10¹

C_OUT= 10 µF

_OUT= 50 mA

C_OUT= 22 µF

_OUT= 50 mA

I

10⁰

10⁻¹

C_Byp= 0 nF; ESR(C_OUT)=0

C_Byp= 10 nF; ESR(C_OUT)=0

C_Byp= 10 nF; ESR(C_OUT)=250mΩ

C_Byp= 0 nF; ESR(C_OUT)=0

C_Byp= 10 nF; ESR(C_OUT)=0

C_Byp= 10 nF; ESR(C_OUT)=250mΩ

10⁻²

10¹

10⁻²

10¹

10²

10³

f [Hz]

10⁴

10⁵

10²

10³

f [Hz]

10⁴

10⁵

Transient Response C_BYP= 0nF

Transient Response C_BYP= 10nF

0,2

0,4

C_OUT= 10 µF

0,15

C_OUT= 10 µF

0,3

C

_BYP= 10 nF

C_BYP

V_IN

=

0 nF

6V

V_IN

=

6V

0,1

0,05

0

0,2

0,1

0

-0,05

-0,1

-0,15

-0,2

-0,1

-0,2

-0,3

-0,4

0

20

40

60

80

100

Time / [μs]

120

140

160

180

200

0

100

200

300

400

500

Time (μs)

600

700

800

900

1000

600

500

400

300

200

100

0

600

500

400

300

200

100

0

I_OUT: 100 to 500mA

0

20

40

60

80

100

Time / [μs]

120

140

160

180

200

0

100

200

300

400

500

Time (μs)

600

700

800

900

1000

1) Load condition 50mA is representing a worst case condition with regard to output voltage noise performance.

Data Sheet

18

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Application Information

7

Application Information

Note:The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device.

IFX1763

V_IN

V_OUT

IN

OUT

C_IN

SENSE

R_Load

C_OUT

C_BYP

1µF

10nF

10µF

EN

BYP

GND

Figure 4

Typical Application Circuit IFX1763 V50

Note:This is a very simplified example of an application circuit. The function must be verified in the real

application¹⁾²⁾

.

The IFX1763 V50 is a 500 mA low dropout regulator with very low quiescent current and Enable-functionality. The

device is capable of supplying 500 mA at a dropout voltage of 350 mV. Output voltage noise numbers down to

42 µV_RMScan be achieved over a 10 Hz to 100 kHz bandwidth with the addition of a 10 nF reference bypass

capacitor. The usage of a reference bypass capacitor will additionally improve transient response of the regulator,

lowering the settling time for transient load conditions. The device has a low operating quiescent current of typical

30 µA that drops to less than 1 µA in shutdown (EN-pin pulled to low level). The device also incorporates several

protection features which makes it ideal for battery-powered systems. It is protected against both reverse input

and reverse output voltages. In battery backup applications where the output can be held up by a backup battery

when the input is pulled to ground the device behaves like it has a diode in series with its output and prevents

reverse current flow.

7.1

Kelvin Sense Connection

The SENSE pin of the IFX1763 V50 is the input to the error amplifier. An optimum regulation will be obtained at

the point where the SENSE pin is connected to the OUT pin of the regulator. In critical applications however small

voltage drops can be caused by the resistance R_pof the PC-traces and thus may lower the resulting voltage at the

load. This effect may be eliminated by connecting the SENSE pin to the output as close as possible at the load

1) Please note that in case a non-negligible inductance at IN pin is present, e.g. due to long cables, traces, parasitics, etc, a

bigger input capacitor C_INmay be required to filter its influence. As a rule of thumb if the IN pin is more than six inches away

from the main input filter capacitor an input capacitor value of C_IN= 10 µF is recommended.

2) For specific needs a small optional resistor may be placed in series to very low ESR output capacitors C_OUTfor enhanced

noise performance (for details please see “Bypass Capacitance and Low Noise Performance” on Page 20).

Data Sheet

19

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Application Information

(see Figure 5). Please note that the voltage drop across the external PC trace will add up to the dropout voltage

of the regulator.

IFX1763

R_P

IN

OUT

V_IN

C_IN

SENSE

R_Load

C_OUT

EN

BYP

GND

R_P

Figure 5

Kelvin Sense Connection

7.2

Bypass Capacitance and Low Noise Performance

The IFX1763 V50 regulator may be used in combination with a bypass capacitor connecting the OUT pin to the

BYP pin in order to minimize output voltage noise¹⁾.This capacitor will bypass the reference of the regulator,

providing a low frequency noise pole. The noise pole provided by such a bypass capacitor will lower the output

voltage noise in the considered bandwidth. For a given output voltage actual numbers of the output voltage noise

will - next to the bypass capacitor itself - be dependent on the capacitance of the applied output capacitor and its

ESR: In case of applying the IFX1763 V50 with a bypass capacitor of 10 nF in combination with a (low ESR)

ceramic C_OUTof 10 µF will result in output voltage noise numbers of typical 55 µV_RMS. This Output Noise level can

be reduced to typical 44 µV_RMSunder the same conditions by adding a small resistance of ~250 mΩ in series to

the 10 µF ceramic output capacitor acting as additional ESR. A reduction of the output voltage noise can also be

achieved by increasing capacitance of the output capacitor. For C_OUT= 22 µF (ceramic low ESR) the output

voltage noise will be typical 42 µV_RMS. For output capacitor values of 22 µF or bigger adding resistance in series

to C_OUTdoes not further lower output noise numbers significantly anymore. For further details please also see

“Output Voltage Noise6)” on Page 10,, of the Electrical Characteristics. Please note that next to reducing the

output voltage noise level the usage of a bypass capacitor has the additional benefit of improving transient

response which will be also explained in the next chapter. However one needs to take into consideration that on

the other hand the regulator start-up time is proportional to the size of the bypass capacitor and slows down to

values around 15 ms when using a 10 nF bypass capacitor in combination with a 10 µF C_OUToutput capacitor.

7.3

Output Capacitance Requirements and Transient Response

The IFX1763 V50 is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor

is an essential parameter with regard to stability, most notably with small capacitors. A minimum output capacitor

of 3.3 µF with an ESR of 3 Ω or less is recommended to prevent oscillations. Like in general for LDO’s the output

transient response of the IFX1763 V50 will be a function of the output capacitance. Larger values of output

capacitance decrease peak deviations and thus improve transient response for larger load current changes.

1) a good quality low leakage capacitor is recommended.

Data Sheet

20

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Application Information

Bypass capacitors, used to decouple individual components powered by the IFX1763 V50 will increase the

effective output capacitor value. Please note that with the usage of larger bypass capacitors for low noise

operation either larger values of output capacitors are needed or a minimum ESR requirement of C_OUTmay have

to be considered (see also Figure “ESR(COUT) with CBYP = 10 nF versus Output Capacitance COUT” on

Page 17 as example). In conjunction with the usage of a 10 nF bypass capacitor an output capacitor C_OUT

≥

6.8 µF is recommended. The benefit of a bypass capacitor to the transient response performance is impressive

and illustrated as one example in Figure 6 where the transient response of the IFX1763 V50 to one and the same

load step from 100 mA to 500 mA is shown with and without a 10 nF bypass capacitor: for the given configuration

of C_OUT= 10 µF with no bypass capacitor the load step will settle in the range of less than 200 µs while for

C_OUT= 10 µF in conjunction with a 10 nF bypass capacitor the same load step will settle in the range of 20 µs. Due

to the shorter reaction time of the regulator by adding the bypass capacitor not only the settling time improves but

also output voltage deviations due to load steps are sharply reduced.

0,4

C_BYP = 0nF

C_BYP = 10nF

C_OUT= 10 µF

_BYP= 0 vs 10nF

V_IN= 6 V

0,3

0,2

0,1

0

C

-0,1

-0,2

-0,3

-0,4

0

100

200

300

400

500

Time (μs)

600

700

800

900

1000

Figure 6

Influence of C_BYP: example of transient response to one and the same load step with and

without C_BYPof 10 nF (I_OUT100 mA to 500 mA)

7.4

Protection Features

The IFX1763 V50 regulators incorporate several protection features which make them ideal for usage in battery-

powered circuits. In addition to normal protection features associated with monolithic regulators like current limiting

and thermal limiting the device is protected against reverse input voltage, reverse output voltage and reverse

voltages from output to input.

Current limit protection and thermal overload protection are intended to protect the device against current overload

conditions at the output of the device. For normal operation the junction temperature must not exceed 125°C.

The input of the device will withstand reverse voltages of 20 V. Current flowing into the device will be limited to

less than 1 mA (typically less than 100 µA) and no negative voltage will appear at the output. The device will

protect both itself and the load. This provides protection against batteries being plugged backwards.

The output of the IFX1763 V50 can be pulled below ground without damaging the device. If the input is left open-

circuit or grounded, the output can be pulled below ground by 20 V. Under such conditions the OUT pin by itself

will act like an open circuit with practically no current flowing out of the pin¹⁾. In more application relevant cases

where the output pin OUT is connected to the SENSE pin there will be a small current of typically less than 100 µA

present from this origin. If the input is powered by a voltage source the output will source the short-circuit current

of the device and will protect itself by thermal limiting. In this case grounding the EN pin will turn off the device and

stop the output from sourcing the short-circuit current.

In circuits where a backup battery is required, several different input/output conditions can occur. The output

voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left

open-circuit. Current flow back into the output will follow the curve as shown in Figure 7 below.

1) typically < 1 µA for the mentioned conditions, V_OUTbeing pulled below ground with other pins either grounded or open.

Data Sheet

21

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Application Information

When the IN pin of the IFX1763 V50 is forced below the OUT pin, or the OUT pin is pulled above the IN pin, the

input current will typically drop to less than 2 µA. This can happen if the input of the device is connected to a

discharged battery and the output is held up by either a backup battery or a second regulator circuit. The state of

the EN pin will have no effect on the reverse output current when the output is pulled above the input.

90

V_OUT.nom= 5.0 V (V50)

80

70

V_IN= 0 V

T_j= 25 °C

60

50

40

30

20

10

0

2

4

6

8

10

V_OUT[V]

Figure 7

Reverse Output Current

Data Sheet

22

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Package Outlines

8

Package Outlines

0.35 x 45˚

1)

±0.1

3.9

0.1 C D 2x

+0.06

9

0.1

0.08

Seating Plane

C

0.64_±0.25

±0.2

0.2

1.27

0.2

2)

M

±0.09

0.41

D 8x

6

M

C A-B D 8x

D

Bottom View

±0.2

3

A

1

4

8

5

1

4

8

5

B

0.1 C A-B 2x

1)

±0.1

4.9

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width

3) JEDEC reference MS-012 variation BA

PG-DSO-8-27-PO V01

Figure 8

PG-DSO-8 Exposed Pad package outlines

±0.1

2.58

±0.1

0.1

±0.1

3.3

0.36

0.53

0.05

Z

Pin 1 Marking

±0.1

0.5

Pin 1 Marking

±0.1

0.25

PG-TSON-10-2-PO V02

Z (4:1)

0.07 MIN.

Figure 9

PG-TSON-10 Package Outlines

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with

government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e

Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

23

Rev. 1.11, 2015-01-30

IFX1763XEJV50

IFX1763LDV50

Revision History

9

Revision History

Revision

Date

Changes

1.11

2015-01-30

•

Editorial changes - figure title of TSON-10 package figure in Product Overview

corrected.

1.1

1.0

2014-10-30

2014-05-16

Updated Data Sheet including additional package type PG-TSON-10:

•

PG-TSON-10 package variants added: Product Overview, Pin Configuration

Thermal Resistance, Wording, etc added / updated accordingly.

Editorial changes throughout the document.

•

Data Sheet - Initial Release

Data Sheet

24

Rev. 1.11, 2015-01-30

Edition 2015-01-30

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

The Infineon Technologies component described in this Data Sheet may be used in life-support devices or systems

and/or automotive, aviation and aerospace applications or systems only with the express written approval of

Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-

support automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device

or system. Life support devices or systems are intended to be implanted in the human body or to support and/or

maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user

or other persons may be endangered.


型号：	SP000938784
厂家：	Infineon
描述：	Fixed Positive LDO Regulator, 输出元件调节器
文件：	总25页 (文件大小：2395K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP000938784 [INFINEON]

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