SP001344584 [INFINEON]
RISC Microcontroller,;型号: | SP001344584 |
厂家: | Infineon |
描述: | RISC Microcontroller, 时钟 微控制器 外围集成电路 |
文件: | 总68页 (文件大小:1301K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
XMC1100 AB-Step
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Data Sheet
V1.8 2016-09
Microcontrollers
Edition 2016-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
XMC1100 AB-Step
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Data Sheet
V1.8 2016-09
Microcontrollers
XMC1100 AB-Step
XMC1000 Family
XMC1100 Data Sheet
Revision History: V1.8 2016-09
Previous Version: V1.7 2016-08
Page 28, In Absolute Maximum Ratings renamed parameter VCM to VINP2, as the
Page 30
limitation is related to most P2 pins, also if no ACMP is available.
Clarified limit to pins P2.[1,2,6:9,11] in Overload specification.
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited.
Cortex®, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace
Buffer™ are trademarks of ARM, Limited.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Data Sheet
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1
1.2
1.3
1.4
2
2.1
2.2
2.2.1
2.2.2
2.2.3
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 22
3
3.1
Electrical Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power-Up and Supply Monitoring Characteristics . . . . . . . . . . . . . . . . 48
On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . 52
SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 54
Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 59
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.6.1
3.3.6.2
3.3.6.3
4
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1
4.1.1
4.2
5
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Data Sheet
5
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
About this Document
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC1100 series devices.
The document describes the characteristics of a superset of the XMC1100 series
devices. For simplicity, the various device types are referred to by the collective term
XMC1100 throughout this document.
XMC1000 Family User Documentation
The set of user documentation includes:
•
Reference Manual
– decribes the functionality of the superset of devices.
Data Sheets
•
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
•
Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions
of those documents.
Data Sheet
6
V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
Summary of Features
1
Summary of Features
The XMC1100 devices are members of the XMC1000 Family of microcontrollers based
on the ARM Cortex-M0 processor core. The XMC1100 series devices are designed for
general purpose applications.
SWD
Cortex-M0
Analog system
Debug
system
CPU
SPD
EVR
2 x DCO
NVIC
Temperature sensor
ANACTRL SFRs
AHB to APB
Bridge
PRNG
PAU
AHB-Lite Bus
Flash SFRs
64k + 0.5k1)
Flash
PORTS
CCU40
16k
SRAM
WDT
USIC0
SCU
RTC
8k ROM
VADC
ERU0
Memories
1) 0.5kbytes of sector 0 (readable only).
Figure 1
System Block Diagram
CPU Subsystem
CPU Core
– High-performance 32-bit ARM Cortex-M0 CPU
•
– Most 16-bit Thumb and subset of 32-bit Thumb2 instruction set
– Single cycle 32-bit hardware multiplier
Data Sheet
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V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
Summary of Features
– System timer (SysTick) for Operating System support
– Ultra low power consumption
•
•
Nested Vectored Interrupt Controller (NVIC)
Event Request Unit (ERU) for processing of external and internal service requests
On-Chip Memories
•
•
•
8 kbytes on-chip ROM
16 kbytes on-chip high-speed SRAM
up to 64 kbytes on-chip Flash program and data memory
On-Chip Peripherals
•
Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI,
quad-SPI, IIC, IIS and LIN interfaces
•
A/D Converters
– up to 12 analog input pins and channels
– 12-bit analog to digital converter
•
•
•
•
•
•
Capture/Compare Units 4 (CCU4) for use as general purpose timers
Window Watchdog Timer (WDT) for safety sensitive applications
Real Time Clock module with alarm support (RTC)
System Control Unit (SCU) for system configuration and control
Pseudo random number generator (PRNG) for fast random data generation
Temperature Sensor (TSE)
Input/Output Lines With Individual Bit Controllability
•
•
•
Tri-stated in input mode
Push/pull or open drain output mode
Configurable pad hysteresis
Debug System
•
Access through the standard ARM serial wire debug (SWD) or the single pin debug
(SPD) interface
•
•
A breakpoint unit (BPU) supporting up to 4 hardware breakpoints
A watchpoint unit (DWT) supporting up to 2 watchpoints
1.1
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:
•
•
<DDD> the derivatives function set
<Z> the package variant
– T: TSSOP
Data Sheet
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V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
Summary of Features
– Q: VQFN
•
•
<PPP> package pin count
<T> the temperature range:
– F: -40°C to 85°C
– X: -40°C to 105°C
•
<FFFF> the Flash memory size.
For ordering codes for the XMC1100 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC1100 series, some descriptions
may not apply to a specific product. Please see Table 1.
For simplicity the term XMC1100 is used for all derivatives throughout this document.
1.2
Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1
Synopsis of XMC1100 Device Types
Package
Derivative
Flash
SRAM
Kbytes
Kbytes
XMC1100-T016F0008
XMC1100-T016F0016
XMC1100-T016F0032
XMC1100-T016F0064
XMC1100-T016X0016
XMC1100-T016X0032
XMC1100-T016X0064
XMC1100-T038F0016
XMC1100-T038F0032
XMC1100-T038F0064
XMC1100-T038X0064
XMC1100-Q024F0008
XMC1100-Q024F0016
XMC1100-Q024F0032
XMC1100-Q024F0064
XMC1100-Q040F0016
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-40-13
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
32
64
16
32
64
16
32
64
64
8
16
32
64
16
Data Sheet
9
V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
Summary of Features
Table 1
Synopsis of XMC1100 Device Types (cont’d)
Derivative
Package
Flash
SRAM
Kbytes
Kbytes
XMC1100-Q040F0032
XMC1100-Q040F0064
PG-VQFN-40-13
PG-VQFN-40-13
32
16
16
64
1.3
Device Type Features
The following table lists the available features per device type.
Table 2
Features of XMC1100 Device Types1)
ADC channel
Derivative
XMC1100-T016
XMC1100-T038
XMC1100-Q024
XMC1100-Q040
6
12
8
12
1) Features that are not included in this table are available in all the derivatives
Table 3
ADC Channels
VADC0 G0
Package
VADC0 G1
PG-TSSOP-16
PG-TSSOP-38
PG-VQFN-24
PG-VQFN-40
CH0..CH5
CH0..CH7
CH0..CH7
CH0..CH7
-
CH1, CH5 .. CH7
-
CH1, CH5 .. CH7
1.4
Chip Identification Number
The Chip Identification Number allows software to identify the marking. It is a 8 words
value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at
address location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word and
most significant word of the Chip Identification Number are the value of registers
DBGROMID and IDCHIP, respectively.
Data Sheet
10
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Summary of Features
Table 4
XMC1100 Chip Identification Number
Derivative
Value
Marking
XMC1100-T016F0008
XMC1100-T016F0016
XMC1100-T016F0032
XMC1100-T016F0064
XMC1100-T016X0016
XMC1100-T016X0032
XMC1100-T016X0064
XMC1100-T038F0016
XMC1100-T038F0032
XMC1100-T038F0064
XMC1100-T038X0064
XMC1100-Q024F0008
XMC1100-Q024F0016
XMC1100-Q024F0032
XMC1100-Q024F0064
XMC1100-Q040F0016
00011032 01CF00FF 00001F37 00000000
00000C00 00001000 00003000 201ED083H
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
00011032 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
00011032 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
00011032 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
00011033 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
00011033 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
00011033 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
00011012 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
00011012 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
00011012 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
00011013 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
00011062 01CF00FF 00001F37 00000000
00000C00 00001000 00003000 201ED083H
00011062 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
00011062 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
00011062 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
00011042 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
Data Sheet
11
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Summary of Features
Table 4
XMC1100 Chip Identification Number (cont’d)
Derivative
Value
Marking
XMC1100-Q040F0032
00011042 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
AB
AB
XMC1100-Q040F0064
00011042 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
Data Sheet
12
V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
General Device Information
2
General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1
Logic Symbols
VDDP
VSSP
(2)
(2)
VDDP
VSSP
(1)
(1)
Port 0
16 bit
Port 0
8 bit
Port 1
6 bit
XMC1100
TSSOP-16
XMC1100
TSSOP-38
Port 2
3 bit
Port 2
4 bit
Port 2
3 bit
Port 2
8 bit
Figure 2
XMC1100 Logic Symbol for TSSOP-38 and TSSOP-16
Data Sheet
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V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
General Device Information
VDDP
VSSP
(1)
VDD VSS VDDP VSSP
(1) (1) (2) (1)
(1)
Port 0
10 bit
Port 0
16 bit
Port 1
4 bit
Port 1
7 bit
XMC1100
VQFN-24
XMC1100
VQFN-40
Port 2
4 bit
Port 2
4 bit
Port 2
4 bit
Port 2
8 bit
Figure 3
XMC1100 Logic Symbol for VQFN-24 and VQFN-40
Data Sheet
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V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
General Device Information
2.2
Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
P2.4
P2.5
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P2.3
Top View
2
P2.2
P2.6
3
P2.1
P2.7
4
P2.0
P2.8
5
P0.15
P0.14
P0.13
P2.9
6
P2.10
P2.11
SSP/VSS
7
8
P0.12
P0.11
P0.10
V
9
VDDP/VDD
10
11
12
13
14
15
16
17
18
19
P1.5
P1.4
P1.3
P0.9
P0.8
VDDP
P1.2
P1.1
P1.0
VSSP
P0.7
P0.6
P0.5
P0.4
P0.3
P0.0
P0.1
P0.2
Figure 4
XMC1100 PG-TSSOP-38 Pin Configuration (top view)
Data Sheet
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V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
General Device Information
P2.7/P2.8
P2.9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P2.6
Top View
P2.0
P0.15
P0.14
P0.9
P0.8
P0.7
P0.6
P2.10
P2.11
V
SSP/VSS
VDDP/VDD
P0.0
P0.5
Figure 5
XMC1100 PG-TSSOP-16 Pin Configuration (top view)
18 17 16 15 14 13
P0.8
P0.9
12
11
10
9
P1.2
P1.3
19
20
21
V
P0.12
P0.13
DDP/V DD
SSP /V SS
22
V
P0.14
P0.15
8
23
24
P2.11
P2.10
7
1
2
3
4
5
6
Figure 6
XMC1100 PG-VQFN-24 Pin Configuration (top view)
Data Sheet
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V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
General Device Information
30 29 28 27 26 25 24 23 22 21
VSSP
VDDP
P1.2
P1.3
P1.4
P1.5
31
32
33
20
19
18
17
16
15
14
P0.8
P0.9
34
35
36
P1.6
VDDP
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
37
38
39
40
VDD
VSS
13
12
11
P2.11
P2.10
1
2
3
4
5
6
7
8
9
10
Figure 7
XMC1100 PG-VQFN-40 Pin Configuration (top view)
Data Sheet
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V1.8, 2016-09
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XMC1100 AB-Step
XMC1000 Family
General Device Information
2.2.1
Package Pin Summary
The following general building block is used to describe each pin:
Table 5
Function
Px.y
Package Pin Mapping Description
Package A
Package B
...
Pad Type
N
N
Pad Class
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type:
•
•
•
•
•
STD_INOUT (standard bi-directional pads)
STD_INOUT/AN (standard bi-directional pads with analog input)
High Current (high current bi-directional pads)
STD_IN/AN (standard input pads with analog input)
Power (power supply)
Details about the pad properties are defined in the Electrical Parameters.
Table 6
Package Pin Mapping
Function VQFN TSSOP VQFN TSSOP Pad Type
Notes
40
23
24
25
26
27
28
29
30
33
34
35
36
37
38
17
18
19
20
21
22
23
24
27
28
29
30
31
24
15
-
16
7
-
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
STD_INOUT
-
-
-
-
-
-
16
17
18
19
20
-
8
9
10
11
12
-
-
-
21
-
Data Sheet
18
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping (cont’d)
Function VQFN TSSOP VQFN TSSOP Pad Type
Notes
40
38
39
40
22
21
20
19
18
17
16
1
38
32
33
34
16
15
14
13
12
11
-
24
22
23
24
14
13
12
11
-
16
-
P0.13
P0.14
P0.15
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.0
STD_INOUT
13
14
-
STD_INOUT
STD_INOUT
High Current
High Current
High Current
High Current
High Current
High Current
STD_INOUT
-
-
-
-
-
-
-
-
35
1
15
STD_INOUT/
AN
P2.1
2
36
2
-
STD_INOUT/
AN
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
3
37
38
1
3
-
-
STD_IN/AN
STD_IN/AN
STD_IN/AN
STD_IN/AN
STD_IN/AN
STD_IN/AN
STD_IN/AN
STD_IN/AN
4
-
5
-
-
6
2
-
-
7
3
4
5
5
6
7
16
1
1
2
3
8
4
9
5
10
11
6
7
STD_INOUT/
AN
P2.11
VSS
12
13
14
8
8
4
5
6
STD_INOUT/
AN
9
9
Power
Supply GND, ADC
reference GND
VDD
10
10
Power
Supply VDD, ADC
reference voltage/
ORC reference
voltage
Data Sheet
19
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping (cont’d)
Function VQFN TSSOP VQFN TSSOP Pad Type
Notes
40
38
24
16
VDDP
15
10
10
6
Power
When VDD is
supplied, VDDP has
to be supplied with the
same voltage.
VSSP
VDDP
VSSP
31
32
25
26
-
-
-
-
-
-
Power
Power
Power
I/O port ground
I/O port supply
Exp.
Pad
Exp.
Pad
Exposed Die Pad
The exposed die pad
isconnectedinternally
to VSSP. For proper
operation, it is
mandatory to connect
the exposed pad to
the board ground. For
thermal aspects,
please refer to the
Package and
Reliability chapter.
2.2.2
Port I/O Function Description
The following general building block is used to describe the I/O functions of each PORT
pin:
Table 7
Port I/O Function Description
Outputs
Function
Inputs
ALT1
ALTn
Input
Input
P0.0
Pn.y
MODA.OUT
MODC.INA
MODA.INA
MODA.OUT
MODC.INB
Data Sheet
20
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Pn.y
XMC1000
Control Logic
PAD
VDDP
Input 0
...
MODA.INA
Input n
HWI0
MODA
MODB
Pn.y
HWI1
SW
ALT1
MODB.OUT
...
ALTn
HWO0
HWO1
GND
Figure 8
Simplified Port Structure
Pn.y is the port pin name, defining the control and data bits/registers associated with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port
pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective
module, with the pin characteristics controlled by the port registers (within the limits of
the connected pad).
The port pin input can be connected to multiple peripherals. Most peripherals have an
input multiplexer to select between different possible input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
Please refer to the Port I/O Functions table for the complete Port I/O function mapping.
Data Sheet
21
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
2.2.3
Hardware Controlled I/O Function Description
The following general building block is used to describe the hardware I/O and pull control
functions of each PORT pin:
Table 8
Hardware Controlled I/O Function Description
Function
Outputs
HWO0
Inputs
Pull Control
HW0_PD
HWI0
HW0_PU
P0.0
Pn.y
MODB.OUT
MODB.INA
MODC.OUT
MODC.OUT
By Pn_HWSEL, it is possible to select between different hardware “masters”
(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).
Hardware control overrules settings in the respective port pin registers. Additional
hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the
peripherals can be used to control the pull devices of the pin.
Please refer to the Hardware Controlled I/O Functions table for the complete hardware
I/O and pull control function mapping.
Data Sheet
22
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
Table 9
Port I/O Functions
Function
Outputs
Inputs
Input
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
Input
Input
Input
Input
Input
Input
P0.0
P0.1
P0.2
P0.3
P0.4
ERU0.
PDOUT0
ERU0.
GOUT0
CCU40.OUT
0
USIC0_CH0. USIC0_CH1. CCU40.IN0C
USIC0_CH0. USIC0_CH1.
SELO0
SELO0
DX2A
DX2A
ERU0.
PDOUT1
ERU0.
GOUT1
CCU40.OUT
1
SCU.
VDROP
CCU40.IN1C
CCU40.IN2C
CCU40.IN3C
ERU0.
PDOUT2
ERU0.
GOUT2
CCU40.OUT
2
VADC0.
EMUX02
ERU0.
PDOUT3
ERU0.
GOUT3
CCU40.OUT
3
VADC0.
EMUX01
CCU40.OUT
1
VADC0.
EMUX00
WWDT.
SERVICE_O
UT
P0.5
CCU40.OUT
0
P0.6
CCU40.OUT
0
USIC0_CH1. USIC0_CH1. CCU40.IN0B
MCLKOUT DOUT0
USIC0_CH1.
DX0C
P0.7
CCU40.OUT
1
USIC0_CH0. USIC0_CH1. CCU40.IN1B
USIC0_CH0. USIC0_CH1. USIC0_CH1.
DX1C DX0D DX1C
SCLKOUT
DOUT0
P0.8
CCU40.OUT
2
USIC0_CH0. USIC0_CH1. CCU40.IN2B
SCLKOUT SCLKOUT
USIC0_CH0. USIC0_CH1.
DX1B DX1B
P0.9
CCU40.OUT
3
USIC0_CH0. USIC0_CH1. CCU40.IN3B
SELO0 SELO0
USIC0_CH0. USIC0_CH1.
DX2B DX2B
P0.10
P0.11
P0.12
P0.13
USIC0_CH0. USIC0_CH1.
SELO1 SELO1
USIC0_CH0. USIC0_CH1.
DX2C DX2C
USIC0_CH0.
MCLKOUT
USIC0_CH0. USIC0_CH1.
USIC0_CH0. USIC0_CH1.
DX2D DX2D
SELO2
SELO2
USIC0_CH0.
SELO3
CCU40.IN0A CCU40.IN1A CCU40.IN2A CCU40.IN3A USIC0_CH0.
DX2E
WWDT.
SERVICE_O
UT
USIC0_CH0.
SELO4
USIC0_CH0.
DX2F
P0.14
P0.15
P1.0
USIC0_CH0. USIC0_CH0.
DOUT0 SCLKOUT
USIC0_CH0. USIC0_CH0.
DX0A
DX1A
USIC0_CH0. USIC0_CH1.
USIC0_CH0.
DX0B
DOUT0
MCLKOUT
CCU40.OUT
0
USIC0_CH0.
DOUT0
USIC0_CH0.
DX0C
Table 9
Port I/O Functions
Function
Outputs
Inputs
Input
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
Input
Input
Input
Input
Input
Input
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
VADC0.
EMUX00
CCU40.OUT
1
USIC0_CH0. USIC0_CH1.
USIC0_CH0. USIC0_CH0. USIC0_CH1.
DOUT0
SELO0
DX0D
DX1D
DX2E
VADC0.
EMUX01
CCU40.OUT
2
USIC0_CH1.
DOUT0
USIC0_CH1.
DX0B
VADC0.
EMUX02
CCU40.OUT
3
USIC0_CH1. USIC0_CH1.
SCLKOUT DOUT0
USIC0_CH1. USIC0_CH1.
DX0A DX1A
VADC0.
EMUX10
USIC0_CH1.
SCLKOUT
USIC0_CH0. USIC0_CH1.
SELO0 SELO1
USIC0_CH0. USIC0_CH1.
DX5E
DX5E
VADC0.
EMUX11
USIC0_CH0.
DOUT0
USIC0_CH0. USIC0_CH1.
SELO1 SELO2
USIC0_CH1.
DX5F
VADC0.
EMUX12
USIC0_CH1.
DOUT0
USIC0_CH0.
SCLKOUT
USIC0_CH0. USIC0_CH1.
SELO2 SELO3
USIC0_CH0.
DX5F
ERU0.
PDOUT3
CCU40.OUT ERU0.
0 GOUT3
USIC0_CH0. USIC0_CH0.
DOUT0 SCLKOUT
VADC0.
G0CH5
ERU0.0B0
ERU0.1B0
ERU0.0B1
ERU0.1B1
ERU0.0A1
ERU0.1A1
ERU0.2A1
ERU0.3A1
ERU0.3B1
ERU0.3B0
ERU0.2B0
ERU0.2B1
USIC0_CH0. USIC0_CH0. USIC0_CH1.
DX0E DX1E DX2F
ERU0.
PDOUT2
CCU40.OUT ERU0.
GOUT2
USIC0_CH0. USIC0_CH1.
VADC0.
G0CH6
USIC0_CH0. USIC0_CH1. USIC0_CH1.
DX0F DX3A DX4A
1
DOUT0
SCLKOUT
VADC0.
G0CH7
USIC0_CH0. USIC0_CH0. USIC0_CH1.
DX3A DX4A DX5A
VADC0.
G1CH5
USIC0_CH0. USIC0_CH1. USIC0_CH1.
DX5B DX3C DX4C
VADC0.
G1CH6
USIC0_CH0. USIC0_CH0. USIC0_CH1.
DX3B DX4B DX5B
VADC0.
G1CH7
USIC0_CH0. USIC0_CH1. USIC0_CH1.
DX5D DX3E DX4E
VADC0.
G0CH0
USIC0_CH0. USIC0_CH0. USIC0_CH1.
DX3E DX4E DX5D
VADC0.
G1CH1
USIC0_CH0. USIC0_CH1. USIC0_CH1.
DX5C DX3D DX4D
VADC0.
G0CH1
USIC0_CH0. USIC0_CH0. USIC0_CH1.
DX3D DX4D DX5C
VADC0.
G0CH2
USIC0_CH0. USIC0_CH1. USIC0_CH1.
DX5A DX3B DX4B
ERU0.
PDOUT1
CCU40.OUT ERU0.
2 GOUT1
USIC0_CH1.
DOUT0
VADC0.
G0CH3
USIC0_CH0. USIC0_CH0. USIC0_CH1.
DX3C DX4C DX0F
ERU0.
PDOUT0
CCU40.OUT ERU0.
3 GOUT0
USIC0_CH1. USIC0_CH1.
SCLKOUT DOUT0
VADC0.
G0CH4
USIC0_CH1. USIC0_CH1.
DX0E DX1E
Table 10
Hardware Controlled I/O Functions
Function
Outputs
HWO1
Inputs
Pull Control
HW1_PD
HWO0
HWI0
HWI1
HW0_PD
HW0_PU
HW1_PU
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.0
P2.1
P2.2
P2.3
P2.4
USIC0_CH0. DOUT0
USIC0_CH0. DOUT1
USIC0_CH0. DOUT2
USIC0_CH0. DOUT3
USIC0_CH0. HWIN0
USIC0_CH0. HWIN1
USIC0_CH0. HWIN2
USIC0_CH0. HWIN3
CCU40.OUT3
CCU40.OUT3
Table 10
Hardware Controlled I/O Functions
Function
Outputs
HWO1
Inputs
HWI1
Pull Control
HW1_PD
HWO0
HWI0
HW0_PD
HW0_PU
HW1_PU
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
CCU40.OUT3
CCU40.OUT3
CCU40.OUT2
CCU40.OUT2
CCU40.OUT3
CCU40.OUT3
CCU40.OUT2
CCU40.OUT2
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3
Electrical Parameter
This section provides the electrical parameter which are implementation-specific for the
XMC1100.
3.1
General Parameters
3.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XMC1100
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
•
CC
Such parameters indicate Controller Characteristics, which are distinctive feature of
the XMC1100 and must be regarded for a system design.
SR
•
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC1100 is designed in.
Data Sheet
27
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.1.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 11
Absolute Maximum Rating Parameters
Symbol Values
Parameter
Unit Note /
Test Cond
Min Typ. Max.
.
ition
Junction temperature
Storage temperature
TJ
SR -40
SR -40
–
–
–
115
125
6
°C
°C
V
–
–
–
TST
Voltage on power supply pin VDDP SR -0.3
with respect to VSSP
Voltage on digital pins with
respect to VSSP
VIN
SR -0.5
–
–
–
–
–
V
DDP + 0.5
V
whichever
is lower
1)
or max. 6
Voltage on P2 pins with
VINP2 SR -0.3
VDDP + 0.3
V
–
2)
respect to VSSP
Voltage on analog input pins VAIN
with respect to VSSP
-0.5
VDDP + 0.5
V
whichever
is lower
VAREF SR
or max. 6
10
Input current on any pin
during overload condition
IIN
SR -10
mA
mA
–
Absolute maximum sum of all ΣIIN SR -50
inputcurrentsduring overload
condition
+50
–
1) Excluding port pins P2.[1,2,6,7,8,9,11].
2) Applicable to port pins P2.[1,2,6,7,8,9,11].
Data Sheet
28
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.1.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 12 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
•
•
full operation life-time is not exceeded
Operating Conditions are met for
– pad supply levels (VDDP
)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
conditions, then the parameters of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery.
Table 12
Overload Parameters
Symbol
Parameter
Values
Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin IOV SR -5
during overload condition
–
5
mA
mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR
–
–
25
Figure 9 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Data Sheet
29
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
VDDP
VDDP
Pn.y
IOVx
GND
ESD
GND
Pad
Figure 9
Input Overload Current via ESD structures
Table 13 and Table 14 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as defined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 13
PN-Junction Characterisitics for positive Overload
OV = 5 mA
Pad Type
I
Standard, High-current,
AN/DIG_IN
VIN = VDDP + 0.5 V
VAIN = VDDP + 0.5 V
VAREF = VDDP + 0.5 V
P2.[1,2,6:9,11]
VINP2 = VDDP + 0.3 V
Table 14
PN-Junction Characterisitics for negative Overload
OV = 5 mA
Pad Type
I
Standard, High-current,
AN/DIG_IN
VIN = VSS - 0.5 V
VAIN = VSS - 0.5 V
VAREF = VSS - 0.5 V
P2.[1,2,6:9,11]
VINP2 = VSS - 0.3 V
Data Sheet
30
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.1.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC1100. All parameters specified in the following tables
refer to these operating conditions, unless noted otherwise.
Table 15
Operating Conditions Parameters
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
SR -40
-40
Digital supply voltage1) VDDP SR 1.8
Typ.
Max.
85
Ambient Temperature TA
−
−
−
−
−
°C
°C
V
Temp. Range F
Temp. Range X
105
5.5
MCLK Frequency
PCLK Frequency
fMCLK CC
fPCLK CC
−
−
33.2
66.4
MHz CPU clock
MHz Peripherals
clock
Short circuit current of ISC
digital outputs
SR -5
−
−
5
mA
Absolute sum of short ΣISC_D SR
circuit currents of the
device
−
25
mA
1) See also the Supply Monitoring thresholds, Chapter 3.3.2.
Data Sheet
31
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.2
DC Parameters
3.2.1
Input/Output Characteristics
Table 16 provides the characteristics of the input/output pins of the XMC1100.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Unless otherwise stated, input DC and AC characteristics, including peripheral
timings, assume that the input pads operate with the standard hysteresis.
Table 16
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
Max.
Output low voltage on
port pins
(with standard pads)
VOLP CC
–
1.0
V
V
V
I
I
OL = 11 mA (5 V)
OL = 7 mA (3.3 V)
–
–
0.4
1.0
I
I
OL = 5 mA (5 V)
OL = 3.5 mA (3.3 V)
Output low voltage on
high current pads
VOLP1 CC
I
I
OL = 50 mA (5 V)
OL = 25 mA (3.3 V)
–
–
0.32
0.4
–
V
V
V
I
I
OL = 10 mA (5 V)
OL = 5 mA (3.3 V)
Output high voltage on VOHP CC VDDP
-
-
-
-
-
I
I
OH = -10 mA (5 V)
OH = -7 mA (3.3 V)
port pins
(with standard pads)
1.0
VDDP
0.4
–
–
–
–
V
V
V
V
I
I
OH = -4.5 mA (5 V)
OH = -2.5 mA (3.3 V)
Output high voltage on VOHP1 CC VDDP
I
I
I
OH = -6 mA (5 V)
OH = -8 mA (3.3 V)
OH = -4 mA (3.3 V)
high current pads
0.32
VDDP
1.0
VDDP
0.4
Input low voltage on port VILPS SR
pins
–
0.19 × V
VDDP
CMOS Mode
(5 V, 3.3 V & 2.2 V)
(Standard Hysteresis)
Input high voltage on
port pins
VIHPS SR 0.7 ×
–
V
CMOS Mode
(5 V, 3.3 V & 2.2 V)
VDDP
(Standard Hysteresis)
Data Sheet
32
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 16
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
Max.
Input low voltage on port VILPL SR
pins
–
0.08 × V
VDDP
CMOS Mode
(5 V, 3.3 V & 2.2 V)10)
(Large Hysteresis)
Input high voltage on
port pins
VIHPL SR 0.85 ×
–
V
CMOS Mode
VDDP
(5 V, 3.3 V & 2.2 V)10)
(Large Hysteresis)
Rise time on High
Current Pad1)
tHCPR CC
–
–
–
9
ns
ns
ns
50 pF @ 5 V2)
50 pF @ 3.3 V3)
50 pF @ 1.8 V4)
12
25
Fall time on High
Current Pad1)
tHCPF CC
–
–
–
9
ns
ns
ns
50 pF @ 5 V2)
50 pF @ 3.3 V3)
50 pF @ 1.8 V4)
12
25
Rise time on Standard tR
CC
CC
–
–
–
12
15
31
ns
ns
ns
50 pF @ 5 V5)
50 pF @ 3.3 V6)
50 pF @ 1.8 V7)
Pad1)
Fall time on Standard
Pad1)
tF
–
–
–
12
15
31
ns
ns
ns
50 pF @ 5 V5)
50 pF @ 3.3 V6)
50 pF @ 1.8 V7)
Input Hysteresis8)
HYS CC 0.08 ×
–
–
–
V
V
V
CMOS Mode (5 V),
Standard Hysteresis
VDDP
0.03 ×
VDDP
CMOS Mode (3.3 V),
Standard Hysteresis
0.02 ×
VDDP
CMOS Mode (2.2 V),
Standard Hysteresis
0.5 ×
VDDP VDDP
0.75 × V
0.75 × V
CMOS Mode(5 V),
Large Hysteresis
0.4 ×
VDDP VDDP
CMOS Mode(3.3 V),
Large Hysteresis
0.2 ×
VDDP VDDP
0.65 × V
CMOS Mode(2.2 V),
Large Hysteresis
Data Sheet
33
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 16
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
Max.
Pin capacitance (digital CIO
CC
–
10
pF
inputs/outputs)
Pull-up resistor on port RPUP CC 20
pins
50
50
1
kohm VIN = VSSP
kohm VIN = VDDP
Pull-down resistor on
port pins
Input leakage current9) IOZP
RPDP CC 20
CC -1
SR
SR -10
μA
V
0 < VIN < VDDP,
TA ≤ 105 °C
10)
Voltage on any pin
during VDDP power off
VPO
IMP
–
0.3
11
Maximum current per
pin (excluding P1, VDDP
and VSS)
mA
–
Maximum current per
high currrent pins
IMP1A SR -10
50
mA
mA
–
10)
Maximum current into
IMVDD1 SR
–
–
–
–
130
V
DDP (TSSOP28/16,
VQFN24)
10)
10)
10)
Maximum current into
IMVDD2 SR
260
130
260
mA
mA
mA
V
DDP (TSSOP38,
VQFN40)
Maximum current out of IMVSS1 SR
SS (TSSOP28/16,
V
VQFN24)
Maximum current out of IMVSS2 SR
V
SS (TSSOP38,
VQFN40)
1) Rise/Fall time parameters are taken with 10% - 90% of supply.
2) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.150 ns/pF at 5 V supply voltage.
3) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.
4) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.
5) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.225 ns/pF at 5 V supply voltage.
6) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.
7) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.
Data Sheet
34
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
8) Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot
be guaranteed that it suppresses switching due to external system noise.
9) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
10) However, for applications with strict low power-down current requirements, it is mandatory that no active
voltage source is supplied at any GPIO pin when VDDP is powered off.
Data Sheet
35
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.2.2
Analog to Digital Converters (ADC)
Table 17 shows the Analog to Digital Converter (ADC) characteristics.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 17
ADC Characteristics (Operating Conditions apply)1)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min. Typ. Max.
Supply voltage range
(internal reference)
V
DD_int SR
2.0
–
3.0
V
SHSCFG.AREF =
11B
CALCTR.CALGN
STC = 0CH
3.0
–
–
–
–
5.5
5.5
V
V
V
V
V
SHSCFG.AREF =
10B
Supply voltage range
(external reference)
V
V
V
V
DD_ext SR 3.0
SHSCFG.AREF =
00B
Analog input voltage
range
AIN SR
VSSP
- 0.05
VDDP
+ 0.05
Auxiliary analog
reference ground
REFGND SR VSSP
1.0
G0CH0
- 0.05
Internal reference
voltage (full scale
value)
REFINT CC
5
Switched capacitance
of an analog input
C
AINS CC
–
–
–
–
–
–
1.2
1.2
4.5
4.5
–
2
pF
pF
pF
pF
pF
pF
GNCTRxz.GAINy
= 00B (unity gain)
2
GNCTRxz.GAINy
= 01B (gain g1)
6
GNCTRxz.GAINy
= 10B (gain g2)
6
GNCTRxz.GAINy
= 11B (gain g3)
Total capacitance ofan CAINT CC
analog input
10
10
Total capacitance of
the reference input
CAREFT CC
–
Data Sheet
36
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 17
ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min. Typ. Max.
Gain settings
GIN CC
1
–
–
–
–
GNCTRxz.GAINy
= 00B (unity gain)
3
6
GNCTRxz.GAINy
= 01B (gain g1)
GNCTRxz.GAINy
= 10B (gain g2)
12
GNCTRxz.GAINy
= 11B (gain g3)
Sample Time
t
t
sample CC
4
–
–
–
–
–
–
–
–
1 /
fADC
V
V
V
DD = 5.0 V
DD = 3.3 V
DD = 2.0 V
4
1 /
fADC
30
1 /
fADC
Sigma delta loop hold
time
SD_hold CC 20
μs
Residual charge
stored in an active
sigma delta loop
remains available
2)
Conversion time
in fast compare mode
t
t
f
CF CC
9
1 /
fADC
2)
Conversion time
in 12-bit mode
C12 CC
20
1 /
fADC
Maximum sample rate
in 12-bit mode 3)
C12 CC
–
–
–
–
fADC
43.5
/
/
–
–
1 sample
pending
fADC
63.5
2 samples
pending
2)
Conversion time
in 10-bit mode
t
f
C10 CC
C10 CC
18
16
1 /
fADC
Maximum sample rate
in 10-bit mode 3)
–
–
–
–
fADC
41.5
/
/
–
–
1 sample
pending
fADC
59.5
2 samples
pending
2)
Conversion time
in 8-bit mode
t
C8 CC
1 /
fADC
Data Sheet
37
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 17
ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min. Typ. Max.
Maximum sample rate
in 8-bit mode 3)
f
C8 CC
–
–
–
–
fADC
38.5
/
–
–
1 sample
pending
–
fADC
54.5
/
2 samples
pending
RMS noise 4)
ENRMS CC
1.5
–
LSB DC input,
12
VDD = 5.0 V,
VAIN = 2.5 V,
25°C
DNL error
INL error
EADNL CC
EAINL CC
EAGAIN CC
–
–
–
–
±2.0
±4.0
±0.5
±3.6
–
–
–
–
LSB
12
LSB
12
Gain error with
external reference
%
SHSCFG.AREF =
00B (calibrated)
Gain error with internal EAGAIN CC
%
SHSCFG.AREF =
1XB (calibrated),
-40°C - 105°C
reference 5)
–
–
±2.0
±8.0
–
–
%
SHSCFG.AREF =
1XB (calibrated),
0°C - 85°C
Offset error
EAOFF CC
mV
Calibrated,
V
DD = 5.0 V
1) The parameters are defined for ADC clock frequency fSH = 32MHz.
2) No pending samples assumed, excluding sampling time and calibration.
3) Includes synchronization and calibration (average of gain and offset calibration).
4) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(AMAXeff / NRMS).
With AMAXeff = 2N / 2, SNR[dB] = 20 × log ( 2048 / NRMS) [N = 12].
NRMS = 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB.
5) Includes error from the reference voltage.
Data Sheet
38
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
CH7
VAIN
.
.
SAR
Converter
:
CH0
VREF
VREFGND
VREFINT
VAREF
VSS
VDD
Internal
Reference
VDDint
VDDext
/
CHNR
REFSEL
AREF
MC_VADC_AREFPATHS
Figure 10
ADC Voltage Supply
Data Sheet
39
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.2.3
Temperature Sensor Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 18
Temperature Sensor Characteristics
Parameter
Symbol
Values
Unit Note /
Test Condition
Min. Typ. Max.
Measurement time
tM CC
−
−
−
–
–
–
–
−
10
115
6
ms
°C
°C
°C
°C
°C
μs
Temperature sensor range TSR SR
Sensor Accuracy1)
-40
T
TSAL CC -6
TJ > 20°C
-10
-18
-31
10
18
31
15
0°C ≤ TJ ≤ 20°C
-25°C ≤ TJ < 0°C
-40°C ≤ TJ < -25°C
Start-up time after enabling tTSSTE SR −
1) The temperature sensor accuracy is independent of the supply voltage.
Data Sheet
40
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.2.4
Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lower than those given in the following tables,
and depend on the customer's system operating conditions (e.g. thermal connection or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19
Power Supply Parameters; VDDP = 5V
Parameter
Symbol
Values
Unit
Note /
Min Typ.1) Max.
.
Test Condition
Active mode current
Peripherals enabled
fMCLK / fPCLK in MHz2)
I
I
I
I
DDPAE CC −
8.4
7.3
6.1
5.1
3.7
4.7
4.1
3.3
2.6
1.5
6.3
5.4
4.6
3.8
3.0
5.9
5.4
4.8
4.3
3.7
11.0
−
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
−
−
−
−
−
−
−
Active mode current
Peripherals disabled
fMCLK / fPCLK in MHz3)
DDPAD CC −
−
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
−
−
−
−
−
−
−
−
Active mode current
DDPAR CC −
−
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
Code execution from RAM
Flash is powered down
fMCLK / fPCLK in MHz
−
−
−
−
−
−
−
−
Sleep mode current
DDPSE CC −
−
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
Peripherals clock enabled
−
fMCLK / fPCLK in MHz4)
−
−
−
Data Sheet
41
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 19
Power Supply Parameters; VDDP = 5V
Parameter
Symbol
Values
Unit
Note /
Min Typ.1) Max.
.
Test Condition
Sleep mode current
Peripherals clock disabled
Flash active
I
I
I
DDPSD CC −
DDPSR CC −
DDPDS CC −
1.8
1.7
1.6
1.5
1.4
1.2
1.1
1.0
0.8
0.7
0.24
6
−
−
−
−
−
−
−
−
−
−
−
−
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
cycles
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
fMCLK / fPCLK in MHz5)
Sleep mode current
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
Peripherals clock disabled
Flash powered down
fMCLK / fPCLK in MHz6)
Deep Sleep mode current7)
Wake-up time from Sleep to tSSA CC
−
Active mode8)
Wake-up time from Deep
Sleep to Active mode9)
t
DSA CC
−
280
−
μsec
1) The typical values are measured at TA = + 25 °C and VDDP = 5 V.
2) CPU and all peripherals clock enabled, Flash is in active mode.
3) CPU enabled, all peripherals clock disabled, Flash is in active mode.
4) CPU in sleep, all peripherals clock enabled and Flash is in active mode.
5) CPU in sleep, Flash is in active mode.
6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up.
7) CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.
8) CPU in sleep, Flash is in active mode during sleep mode.
9) CPU in sleep, Flash is in powered down mode during deep sleep mode.
Data Sheet
42
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Figure 11 shows typical graphs for active mode supply current for VDDP = 5V, VDDP
=
3.3V, VDDP = 1.8V across different clock frequencies.
9
8
7
6
IDDPAE 5V/3.3V
5
I (mA)
4
IDDPAE 1.8V
3
2
IDDPAD
5V/3.3V/1.8V
1
0
1/1
8/16 16/32 24/48 32/64
MCLK / PCLK (MHz)
Condition:
1. TA = +25° C
Figure 11
Active mode, a) peripherals clocks enabled, b) peripherals clocks
disabled: Supply current IDDPA over supply voltage VDDP for different
clock frequencies
Data Sheet
43
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Figure 12 shows typical graphs for sleep mode current for VDDP = 5V, VDDP = 3.3V, VDDP
= 1.8V across different clock frequencies.
1.4
1.2
1
0.8
I (m A)
0.6
0.4
0.2
0
IDDPS R
5V/3.3V/1.8V
1/1
8/16 16/32 24/48 32/64
M CLK / PCLK (M Hz)
Condition:
1. TA = +25° C
Figure 12
Sleep mode, peripherals clocks disabled, Flash powered down:
Supply current IDDPSR over supply voltage VDDP for different clock
frequencies
Data Sheet
44
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 20 provides the active current consumption of some modules operating at 5 V
power supply at 25° C. The typical values shown are used as a reference guide on the
current consumption when these modules are enabled.
Table 20
Typical Active Current Consumption
Active Current
Consumption
Symbol
Limit
Values
Unit
Test Condition
Typ.
Baseload current ICPUDDC
5.04
mA
Modules including Core, SCU,
PORT, memories, ANATOP1)
VADC and SHS
USIC0
IADCDDC
3.4
mA
mA
mA
mA
mA
Set CGATCLR0.VADC to 12)
Set CGATCLR0.USIC0 to 13)
Set CGATCLR0.CCU40 to 14)
Set CGATCLR0.WDT to 15)
Set CGATCLR0.RTC to 16)
IUSIC0DDC 0.87
ICCU40DDC 0.94
CCU40
WDT
IWDTDDC
IRTCDDC
0.03
0.01
RTC
1) Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loop
in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.
2) Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode
3) Active current is measured with: module enabled, alternating messages sent to PC at 57.6kbaud every 200ms
4) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching
from 1500Hz and 1000Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle
5) Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB =
0x00008000; WDT serviced every 1s
6) Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled
Data Sheet
45
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.2.5
Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 21
Flash Memory Parameters
Symbol
Parameter
Values
Min. Typ. Max.
Unit
Note /
Test Condition
Erase Time per
page / sector
t
ERASE CC
6.8
7.1 7.6
ms
Program time per block tPSER CC
102
−
152 204
μs
μs
ns
Wake-Up time
t
WU CC
ta CC
RET CC
32.2
50
−
−
−
−
Read time per word
Data Retention Time
−
t
10
years Max. 100 erase /
program cycles
Flash Wait States 1)
N
WSFLASH CC
0
0
1
0
0
1
2
1
fMCLK = 8 MHz
fMCLK = 16 MHz
fMCLK = 32 MHz
1
1.3
0
Fixed Flash Wait
States configured in bit
NVM_NVMCONF.WS
NFWSFLASH SR 0
NVM_CONFIG1
.FIXWS = 1B,
fMCLK ≤ 16 MHz
1
1
1
NVM_CONFIG1
.FIXWS = 1B,
16 MHz < fMCLK
≤ 32 MHz
Erase Cycles
N
ECYC CC
−
−
−
−
5*104 cycles Sum of page and
sector erase
cycles
Total Erase Cycles
NTECYC CC
2*106 cycles
1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical
values are calculated from the execution of the Dhrystone benchmark program.
Data Sheet
46
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.3
AC Parameters
3.3.1
Testing Waveforms
VDDP
90%
90%
10%
10%
VSS
tR
tF
Figure 13
Rise/Fall Time Parameters
VDDP
VDDP / 2
VDDP / 2
Test Points
VSS
Figure 14
Testing Waveform, Output Delay
VLOAD + 0.1V
VOH - 0.1V
Timing
Reference
Points
VLOAD - 0.1V
VOL + 0.1V
Figure 15
Testing Waveform, Output High Impedance
Data Sheet
47
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.3.2
Power-Up and Supply Monitoring Characteristics
Table 22 provides the characteristics of the supply monitoring in XMC1100.
The guard band between the lowest valid operating voltage and the brownout reset
threshold provides a margin for noise immunity and hysteresis. The electrical
parameters may be violated while VDDP is outside its operating range.
The brownout detection triggers a reset within the defined range. The prewarning
detection can be used to trigger an early warning and issue corrective and/or fail-safe
actions in case of a critical supply voltage drop.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 22
Power-Up and Supply Monitoring Parameters (Operating Conditions
apply)1)
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Condition
Min.
RAMPUP SR VDDP
V
V
DDP ramp-up time
DDP slew rate
t
/
−
−
−
107
0.1
10
μs
SVDDPrise
S
VDDPOP SR
0
V/μs Slope during
normal operation
SVDDP10 SR
0
0
V/μs Slope during fast
transient within +/-
10% of VDDP
S
VDDPrise SR
−
−
10
V/μs Slope during
power-on or
restart after
brownout event
SVDDPfall2) SR 0
0.25 V/μs Slope during
supply falling out
of the +/-10%
limits3)
V
DDP prewarning
V
DDPPW CC 2.1
2.85
4.2
2.25 2.4
V
V
V
ANAVDEL.VDEL_
SELECT = 00B
voltage
3
3.15
4.6
ANAVDEL.VDEL_
SELECT = 01B
4.4
ANAVDEL.VDEL_
SELECT = 10B
Data Sheet
48
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 22
Power-Up and Supply Monitoring Parameters (Operating Conditions
apply)1) (cont’d)
Parameter
Symbol
Values
Typ. Max.
1.62 1.75
Unit Note /
Test Condition
Min.
DDPBO CC 1.55
V
DDP brownout reset
V
V
V
calibrated, before
user code starts
running
voltage
V
DDP voltage to
DDPPA CC
−
−
1.0
−
V
ensure defined pad
states
Start-up time from
power-on reset
t
t
SSW SR
320
–
μs
Time to the first
user code
instruction in all
start-up modes4)
BMI program time
BMI SR
−
8.25
–
ms
Time taken from a
user-triggered
system reset after
BMI installation is
is requested
1) Not all parameters are 100% tested, but are verified by design/characterisation.
2) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated for
this parameter.
3) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to
the chip. A larger capacitor value has to be chosen if the power source sink a current.
4) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 32 MHz
and the clocks to peripheral as specified in register CGATSTAT0 are gated.
5.0V
VDDPPW
}
VDDP
VDDPBO
Figure 16
Supply Threshold Parameters
Data Sheet
49
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.3.3
On-Chip Oscillator Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 23 provides the characteristics of the 64 MHz clock output from the digital
controlled oscillator, DCO1 in XMC1100.
Table 23
64 MHz DCO1 Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
Min. Typ. Max.
Nominal frequency fNOM CC
–
64
–
MHz under nominal
conditions1) after
trimming
Accuracy2)
ΔfLT CC -1.7
–
3.4
4.0
%
with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)
-3.9
–
%
with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
2) The accuracy of the DCO1 oscillator can be further improved through alternative methods, refer to XMC1000
Oscillator Handling Application Note.
Data Sheet
50
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Figure 17 shows the typical curves for the accuracy of DCO1, with and without
calibration based on temperature sensor, respectively.
4.00
3.00
2.00
Without calibration based
on temperature sensor
1.00
With calibration based on
temperature sensor
0.00
-1.00
-2.00
-3.00
-4.00
-50 -40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100 110 120
°
Temperature [ C]
Figure 17
Typical DCO1 accuracy over temperature
Table 24 provides the characteristics of the 32 kHz clock output from digital controlled
oscillators, DCO2 in XMC1100.
Table 24
32 kHz DCO2 Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
Min. Typ. Max.
Nominal frequency
Accuracy
fNOM CC –
32.75 –
kHz under nominal
conditions1) after trimming
ΔfLT CC -1.7
–
–
3.4
%
%
with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)
-3.9
4.0
with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
Data Sheet
51
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.3.4
Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 25
SWD Interface Timing Parameters(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
50
Typ. Max.
SWDCLK high time
SWDCLK low time
t1 SR
t2 SR
t3 SR
–
–
–
500000 ns
500000 ns
–
–
–
50
SWDIO input setup
10
–
ns
to SWDCLK rising edge
SWDIO input hold
t4 SR
10
–
–
ns
–
after SWDCLK rising edge
SWDIO output valid time t5 CC
after SWDCLK rising edge
–
–
4
–
–
–
68
62
–
ns
ns
ns
CL = 50 pF
CL = 30 pF
SWDIO output hold time t6 CC
from SWDCLK rising edge
t1
t2
SWDCLK
t6
SWDIO
(Output)
t5
t3
t4
SWDIO
(Input )
Figure 18
SWD Timing
Data Sheet
52
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.3.5
SPD Timing Requirements
The optimum SPD decision time between 0B and 1B is 0.75 µs. With this value the
system has maximum robustness against frequency deviations of the sampling clock on
tool and on device side. However it is not always possible to exactly match this value
with the given constraints for the sample clock. For instance for a oversampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
Table 26
Optimum Number of Sample Clocks for SPD
Sample Effective Remark
Sample Sampling Sample
Freq.
Factor
Clocks 0B Clocks 1B Decision
Time1)
8 MHz
4
1 to 5
6 to 12
0.69 µs
The other closest option
(0.81 µs) for the effective
decision time is less robust.
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks)
For a balanced distribution of the timing robustness of SPD between tool and device, the
timing requirements for the tool are:
•
•
Frequency deviation of the sample clock is +/- 5%
Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
Data Sheet
53
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.3.6
Peripheral Timings
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 27
USIC SSC Master Mode Timing
Symbol Values
Typ. Max.
Parameter
Unit Note /
Test Condition
Min.
CLK CC 62.5
SCLKOUT master clock
period
t
−
−
ns
ns
Slave select output SELO t1 CC 80
active to first SCLKOUT
transmit edge
−
−
Slave select output SELO t2 CC
inactive after last
0
−
−
ns
SCLKOUT receive edge
Data output DOUT[3:0]
valid time
t3 CC -10
t4 SR 80
−
−
10
ns
ns
Receive data input
−
DX0/DX[5:3] setup time to
SCLKOUT receive edge
Data input DX0/DX[5:3]
hold time from SCLKOUT
receive edge
t5 SR
0
−
−
ns
Data Sheet
54
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 28
USIC SSC Slave Mode Timing
Parameter
Symbol
Min.
Values
Unit Note /
Test Condition
Typ. Max.
DX1 slave clock period
tCLK SR 125
t10 SR 10
−
−
−
−
ns
ns
Select input DX2 setup to
first clock input DX1 transmit
edge1)
Select input DX2 hold after t11 SR 10
last clock input DX1 receive
edge1)
−
−
−
−
−
ns
ns
ns
ns
Receive data input
t12 SR 10
−
DX0/DX[5:3] setup time to
shift clock receive edge1)
Data input DX0/DX[5:3] hold t13 SR 10
time from clock input DX1
receive edge1)
−
Data output DOUT[3:0] valid t14 CC -
80
time
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
55
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Master Mode Timing
t1
t2
Select Output
SELOx
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
Last Receive
Edge
First Transmit
Edge
Transmit
Edge
t3
t3
Data Output
DOUT[3:0]
t4
t4
t5
t5
Data Input
DX0/DX[5:3]
Data
valid
Data
valid
Slave Mode Timing
t10
t11
Select Input
DX2
Inactive
Active
Inactive
Clock Input
DX1
Receive
Edge
Last Receive
Edge
First Transmit
Edge
Transmit
Edge
t12
t12
t13
t13
Data Input
DX0/DX[5:3]
Data
valid
Data
valid
t14
t14
Data Output
DOUT[3:0]
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched.
Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signa.l
USIC_SSC_TMGX.VSD
Figure 19
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
Data Sheet
56
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
3.3.6.2 Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 29
USIC IIC Standard Mode Timing1)
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
Typ.
Max.
Fall time of both SDA and t1
-
-
300
ns
ns
µs
ns
µs
µs
µs
µs
µs
µs
SCL
CC/SR
Rise time of both SDA and t2
-
-
-
-
-
-
-
-
-
-
1000
SCL
CC/SR
Data hold time
t3
0
-
-
-
-
-
-
-
-
CC/SR
Data set-up time
t4
250
4.7
4.0
4.0
4.7
4.0
4.7
CC/SR
LOW period of SCL clock t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
CC/SR
Hold time for (repeated)
START condition
Set-up time for repeated t8
START condition
CC/SR
Set-up time for STOP
condition
t9
CC/SR
Bus free time between a t10
STOP and START
CC/SR
condition
Capacitive load for each
bus line
Cb SR
-
-
400
pF
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Data Sheet
57
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Table 30
USIC IIC Fast Mode Timing1)
Parameter
Symbol
Min.
Values
Typ.
-
Unit Note /
Test Condition
Max.
Fall time of both SDA and t1
20 +
300
ns
SCL CC/SR 0.1*Cb
2)
Rise time of both SDA and t2
20 +
-
-
-
-
-
-
-
-
-
300
ns
µs
ns
µs
µs
µs
µs
µs
µs
SCL
CC/SR 0.1*Cb
Data hold time
t3
0
-
-
-
-
-
-
-
-
CC/SR
Data set-up time
t4
100
1.3
0.6
0.6
0.6
0.6
1.3
CC/SR
LOW period of SCL clock t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
CC/SR
Hold time for (repeated)
START condition
Set-up time for repeated t8
START condition
CC/SR
Set-up time for STOP
condition
t9
CC/SR
Bus free time between a t10
STOP and START
CC/SR
condition
Capacitive load for each
bus line
Cb SR
-
-
400
pF
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
2) Cb refers to the total capacitance of one bus line in pF.
Data Sheet
58
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
t1
t2
t4
70%
30%
SDA
SCL
t1
t3
t2
t6
9th
clock
t7
t5
t10
S
SDA
SCL
t8
t7
t9
9th
clock
Sr
P
S
Figure 20
USIC IIC Stand and Fast Mode Timing
3.3.6.3 Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 31
USIC IIS Master Transmitter Timing
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
Clock period
t1 CC
2/fMCLK
4/fMCLK
-
-
-
-
-
-
ns
ns
ns
VDDP ≥ 3 V
VDDP < 3 V
Clock HIGH
Clock Low
t2 CC
t3 CC
0.35 x
t1min
0.35 x
t1min
-
-
-
ns
Hold time
t4 CC
t5 CC
0
-
-
-
ns
Clock rise time
0.15 x ns
t1min
Data Sheet
59
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
t1
t2
t5
t4
t3
SCK
WA/
DOUT
Figure 21
USIC IIS Master Transmitter Timing
USIC IIS Slave Receiver Timing
Table 32
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
Clock period
Clock HIGH
t6 SR
t7 SR
4/fMCLK
-
-
-
-
ns
ns
0.35 x
t6min
Clock Low
Set-up time
Hold time
t8 SR
t9 SR
0.35 x
t6min
-
-
-
-
-
-
ns
ns
ns
0.2 x
t6min
t
10 SR
10
t6
t7
t8
t9
SCK
t10
WA/
DIN
Figure 22
USIC IIS Slave Receiver Timing
Data Sheet
60
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
4
Package and Reliability
The XMC1100 is a member of the XMC1000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the exposed die pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1
Package Parameters
Table 33 provides the thermal characteristics of the packages used in XMC1100.
Table 33
Thermal Characteristics of the Packages
Parameter
Symbol
Limit Values
Min. Max.
Unit
Package Types
Exposed Die Pad
Dimensions
Ex × Ey
CC
-
-
-
2.7 × 2.7 mm
3.7 × 3.7 mm
PG-VQFN-24-19
PG-VQFN-40-13
PG-TSSOP-16-81)
PG-TSSOP-38-91)
PG-VQFN-24-191)
PG-VQFN-40-131)
Thermal resistance
Junction-Ambient
RΘJA CC
104.6
70.3
46.0
38.4
K/W
K/W
K/W
K/W
-
-
-
1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSSP, independent of EMC and thermal requirements.
4.1.1
Thermal Considerations
When operating the XMC1100 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 115 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
Data Sheet
61
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
The internal power consumption is defined as
INT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
IOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
P
P
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
62
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
4.2
Package Outlines
Figure 23
PG-TSSOP-38-9
Data Sheet
63
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Figure 24
PG-TSSOP-16-8
Data Sheet
64
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Figure 25
PG-VQFN-24-19
Data Sheet
65
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Figure 26
PG-VQFN-40-13
All dimensions in mm.
Data Sheet
66
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Quality Declaration
5
Quality Declaration
Table 34 shows the characteristics of the quality parameters in the XMC1100.
Table 34
Quality Parameters
Symbol Limit Values
Parameter
Unit Notes
Min.
Max.
ESD susceptibility
according to Human Body SR
Model (HBM)
VHBM
-
2000
V
V
Conforming to
EIA/JESD22-
A114-B
ESD susceptibility
VCDM
-
500
Conforming to
according to Charged
Device Model (CDM) pins
SR
JESD22-C101-C
Moisture sensitivity level
MSL
CC
-
-
3
-
JEDEC
J-STD-020D
Soldering temperature
TSDR
SR
260
°C
Profile according
to JEDEC
J-STD-020D
Data Sheet
67
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号:
SP001422940
RF Power Field-Effect Transistor, 1-Element, Ultra High Frequency Band, Silicon, N-Channel, Metal-oxide Semiconductor FET, GREEN, CERAMIC, H-36248-2, 2 PIN
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