TDA5220 [INFINEON]
ASK/FSK Single Conversion Receiver; ASK / FSK单一转换接收器
| 型号： | TDA5220 |
| 厂家： | 
Infineon |
| 描述： | ASK/FSK Single Conversion Receiver |
| 文件： | 总44页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
ASK/FSK Single Conversion Receiver
TDA 5220 Version 0.1
Target Specification October 2001
confidential
preliminary
confidential
Revision History
Current Version: 0.1. as of 31.10.01
Please note that this is a target specification that is subject to change.
Previous Version: n.a.
Page
Page(s)
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
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Edition 10.01
Published by Infineon Technologies AG,
Balanstraße 73,
81541 München
© Infineon Technologies AG October 2001.
All Rights Reserved.
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1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
2.1
2.2
2.3
2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.3
3.4
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.6 FSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.7 Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
10
10
11
11
11
12
12
12
12
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
4.1
4.2
4.3
4.4
Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
6
4.5
4.6
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
8
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
10
4.7
Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
3
4
9
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 AC/DC Characteristics at TAMB = -40 to 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDA 5220
preliminary
Product Info
confidential
Product Info
Package
General Description The IC is a very low power consump-
tion single chip FSK/ASK Superhet-
erodyne Receiver (SHR) for the
frequency bands 810 to 870 MHz and
400 to 440 MHz. The IC offers a high
level of integration and needs only a
few external components. The device
contains a low noise amplifier (LNA), a
double balanced mixer, a fully inte-
grated VCO, a PLL synthesiser, a
crystal oscillator, a limiter with RSSI
generator, a PLL FSK demodulator, a
data filter, a data comparator (slicer)
and a peak detector. Additionally there
is a power down feature to save bat-
tery life.
Features ꢀ Low supply current (typ. at 868MHz ꢀ Selectable frequency ranges 810-
Is = 5.9mA in FSK mode,
Is = 5.2mA in ASK mode)
870 MHz and 400-440 MHz
ꢀ Limiter with RSSI generation,
ꢀ Supply voltage range 5V ±10%
operating at 10.7MHz
ꢀ Power down mode with very low
ꢀ Selectable reference frequency
supply current (50nA typ)
ꢀ 2nd order low pass data filter with
ꢀ FSK and ASK demodulation capa-
external capacitors
bility
ꢀ Data slicer with self-adjusting
ꢀ Fully integrated VCO and PLL
threshold
Synthesiser
ꢀ FSK sensitivity <-100dBm
ꢀ ASK sensitivity < –107dBm
Application ꢀ Keyless Entry Systems
ꢀ Alarm Systems
ꢀ Remote Control Systems
ꢀ Low Bitrate Communication
Systems
Ordering Information
Type
Ordering Code
Package
TDA 5220
P-TSSOP-28-1
samples available on tape and reel
Wireless Components
Product Info
Target Specification, October 2001
2
Product Description
Contents of this Chapter
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5220
preliminary
Product Description
confidential
2.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne
Receiver (SHR) for the frequency bands 810 to 870 MHz and 400 to 440 MHz.
The IC offers a high level of integration and needs only a few external compo-
nents. The device contains a low noise amplifier (LNA), a double balanced
mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter
with RSSI generator, a PLL FSK demodulator, a data filter, a data comparator
(slicer) and a peak detector. Additionally there is a power down feature to save
battery life.
2.2 Application
ꢀ Keyless Entry Systems
ꢀ Remote Control Systems
ꢀ Alarm Systems
ꢀ Low Bitrate Communication Systems
2.3 Features
ꢀ Low supply current (at 868MHz Is = 5.9 mA typ. FSK mode, 5.2mA typ. ASK
mode)
ꢀ Supply voltage range 5V ±10%
ꢀ Power down mode with very low supply current (50nA typ)
ꢀ FSK and ASK demodulation capability
ꢀ Fully integrated VCO and PLL Synthesiser
ꢀ RF input sensitivity ASK < –107dBm
ꢀ RF input sensitivity FSK < –100dBm
ꢀ Selectable frequency ranges 810-870 MHz and 400-440 MHz
ꢀ Selectable reference frequency
ꢀ Limiter with RSSI generation, operating at 10.7MHz
ꢀ 2nd order low pass data filter with external capacitors
ꢀ Data slicer with self-adjusting threshold
Wireless Components
2 - 2
Target Specification, October 2001
TDA 5220
preliminary
Product Description
confidential
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2 - 3
Target Specification, October 2001
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TDA 5220
preliminary
Functional Description
confidential
3.1 Pin Configuration
CRST1
VCC
LNI
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CRST2
PDW N
PDO
2
3
TAG C
AG ND
LNO
4
DATA
3VO UT
THRES
FFB
5
6
VCC
M I
7
TDA 5220
8
O PP
M IX
9
SLN
AG ND
FSEL
IFO
10
11
12
13
14
SLP
LIM X
LIM
DG ND
VDD
SSEL
M SEL
Pin_Configuration_5220.wmf
Figure 3-1
IC Pin Configuration
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3 - 2
Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
3.2 Pin Definition and Function
In the subsequent table the internal circuits connected to the pins of the device
are shown. ESD-protection circuits are omitted to ease reading.
.
Table 3-1 Pin Definition and Function
Pin No. Symbol
Equivalent I/O-Schematic
Function
1
CRST1
External Crystal Connector 1
4.15V
1
50uA
2
3
VCC
LNI
5V Supply
LNA Input
57uA
3
500uA
4k
1k
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Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
4
TAGC
AGC Time Constant Control
4.3V
3uA
4
1k
1.4uA
1.7V
5
6
AGND
LNO
Analogue Ground Return
LNA Output
5V
1k
6
7
8
VCC
MI
5V Supply
Mixer Input
1.7V
2k
2k
9
MIX
Complementary Mixer Input
8
9
400uA
10
AGND
Analogue Ground Return
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3 - 4
Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
11
FSEL
868/434 MHz Operating Fre-
quency Selector
750
1.2V
2k
11
12
IFO
10.7 MHz IF Mixer Output
300uA
2.2V
60
12
4.5k
13
14
DGND
VDD
Digital Ground Return
5V Supply (PLL Counter Cir-
cuitry)
15
MSEL
ASK/FSK Modulation Format
Selector
1.2V
40k
15
16
SSEL
Data-Slicer Reference-Level
Selector
1.2V
40k
16
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Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
17
18
LIM
Limiter Input
2.4V
15k
17
LIMX
Complementary Limiter Input
75uA
330
18
15k
19
SLP
Data Slicer Positive Input
15uA
100
3k
19
80µA
20
SLN
Data Slicer Negative Input
5uA
10k
20
21
OPP
OpAmp Noninverting Input
5uA
200
21
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3 - 6
Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
22
FFB
Data Filter Feedback Pin
5uA
100k
22
23
THRES
AGC Threshold Input
5uA
10k
23
24
3VOUT
3V Reference Output
24
20k
Ω
3.1V
25
DATA
Data Output
500
25
40k
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Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
26
PDO
Peak Detector Output
26
446k
27
PDWN
Power Down Input
27
220k
220k
28
CRST2
External Crystal Connector 2
4.15V
28
50uA
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3 - 8
Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
3.3 Functional Block Diagram
VCC
IF
Filter
MSEL
H=ASK
L=FSK
MI
FFB
LNO
MIX
9
IFO
12
LIM
LIMX
18
OPP
SLP
19
SLN
20
22
21
6
8
17
15
16
25
SSEL
DATA
Logic
CM
-
LNI
+
3
4
LNA
RF
CP
+
-
-
+
-
+
FSK
PLL Demod
FSK
ASK
+
LIMITER
DATA-
SLICER
OP
-
TAGC
TDA 5220
PEAK
DETECTOR
PDO
26
23 THRES
OTA
U REF
3VOUT
24
AGC
Reference
: 1
: 2
Φ
DET
CRYSTAL
OSC
VCO
: 64
VCC
14
13
Bandgap
Reference
Loop
Filter
DGND
11
28
27
1
2,7
5,10
VCC AGND
PDWN
FSEL
Crystal
Function_5220.wmf
Figure 3-2
Main Block Diagram
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
the LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and
MIX (Pins 8 and 9). The noise figure of the LNA is approximately 3dB and the
current consumption is 500µA. The gain can be reduced by approximately
18dB. The switching point of this AGC action can be determined externally by
applying a threshold voltage at the THRES pin (Pin 23). This voltage is com-
pared internally with the received signal (RSSI) level generated by the limiter
circuitry. In case that the RSSI level is higher than the threshold voltage the LNA
gain is reduced and vice versa. The threshold voltage can be generated by
attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a
temperature stable 3V output generated from the internal bandgap voltage and
the THRES pin as described in Section 4.1. The time constant of the AGC
action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and
should be chosen along with the appropriate threshold voltage according to the
Wireless Components
3 - 9
Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
intended operating case and interference scenario to be expected during oper-
ation. The optimum choice of AGC time constant and the threshold voltage is
described in Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 400-440MHz/810-870MHz to the intermediate frequency (IF) at
10.7MHz with a voltage gain of approximately 21dB by utilising either high- or
low-side injection of the local oscillator signal. In case the mixer is interfaced
only single-ended, the unused mixer input has to be tied to ground via a capac-
itor. The mixer is followed by a low pass filter with a corner frequency of 20MHz
in order to suppress RF signals to appear at the IF output (IFO pin). The IF out-
put is internally consisting of an emitter follower that has a source impedance
of approximately 330 Ω=to facilitate interfacing the pin directly to a standard
10.7MHz ceramic filter without additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including on-chip spiral inductors and varac-
tor diodes. It’s nominal centre frequency is 840MHz, the operating range guar-
anteed over the temperature range specified is 820 to 860MHz. Depending on
whether high- or low-side injection of the local oscillator is used the receive fre-
quency ranges are 810 to 840 and 840 to 870MHz or 400 to 420 and 420 to
440MHz (see also Section 4.4). No additional external components are neces-
sary.
The oscillator signal is fed both to the synthesiser divider chain and to the down-
converting mixer. In case of operation in the 400 to 440 MHz range, the signal
is divided by two before it is fed to the mixer. This is controlled by the selection
pin FSEL (Pin 11) as described in the following table. The overall division ratio
of the divider chain is 64. The loop filter is also realised fully on-chip.
Table 3-2 FSEL Pin Operating States
FSEL
RF Frequency
400-440 MHz
810-870 MHz
Open
Shorted to ground
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Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
3.4.4 Crystal Oscillator
The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is explained in Section 4.4.
3.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80 dB that has a bandpass-characteristic centred around
10.7 MHz. It has a typical input impedance of 330 Ω=to allow for easy interfacing
to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal
Strength Indicator (RSSI) generator which produces a DC voltage that is
directly proportional to the input signal level as can be seen in Figure 4-2. This
signal is used to demodulate ASK-modulated receive signals in the subsequent
baseband circuitry. The RSSI output is applied to the modulation format switch,
to the Peak Detector input and to the AGC circuitry.
In order to demodulate ASK signals the MSEL pin has to in its ’High’-state as
described in the next chapter.
3.4.6 FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contained fully on chip. The Limiter output differential signal is fed to the linear
phase detector as is the output of the 10.7 MHz center frequency VCO. The
demodulator gain is typically 180µV/kHz. The passive loop filter output that is
comprised fully on chip is fed to both the VCO and the modulation format switch
described in more detail below. This signal is representing the demodulated sig-
nal with high IF-frequencies applied to the demodulator demodulated to logic
ones and low IF-frequencies demodulated to logic zeroes. Please note that due
to this behaviour a sign inversion of the data occurs in case of high-side injec-
tion of the local oscillator at receive frequencies below 840 or 420MHz, respec-
tively. See also .
The modulation format switch is actually a switchable amplifier with an AC gain
of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table.
This gain was chosen to facilitate detection in the subsequent circuits. The DC
gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset
produced by the demodulator in case of large frequency offsets of the IF signal.
The resulting frequency characteristic and details on the principle of operation
of the switch are described in Section 4.6.
Table 3-3 MSEL Pin Operating States
MSEL
High
Low
Modulation Format
ASK
FSK
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Target Specification, October 2001
TDA 5220
preliminary
Functional Description
confidential
The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ= on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
3.4.8 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of up to 100kBaud. The maximum achievable
data rate also depends on the IF Filter bandwidth and the local oscillator toler-
ance values. Both inputs are accessible. The output delivers a digital data sig-
nal (CMOS-like levels) for subsequent circuits. A self-adjusting slicer-threshold
on pin 20 its generated by a RC-term. In ASK-mode alternatively a scaled value
of the voltage at the PDO-output (approx. 87%) can be used as the slicer-
threshold. The data slicer threshold generation alternatives are described in
more detail in Section 4.5.
3.4.9 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. A capacitor is necessary. The input is con-
nected to the output of the RSSI-output of the Limiter, the output is connected
to the PDO pin (Pin 26). This output can be used as an indicator for the received
signal strength to use in wake-up circuits and as a reference for the data slicer
in ASK mode. Note that the RSSI level is also output in case of FSK mode.
3.4.10 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 50nA.
Table 3-4 PDWN Pin Operating States
PDWN
Operating State
Powerdown Mode
Receiver On
Open or tied to ground
Tied to Vs
Wireless Components
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Target Specification, October 2001
4
Applications
Contents of this Chapter
4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . 4-2
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . 4-8
4.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
TDA 5220
preliminary
Applications
confidential
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is
shown.
R1
R2
U
th re s h old
23
Pins:
24
RSSI (0.8 - 2.8V)
20kΩ
OTA
VCC
+3.1V
I
LNA
load
Gain control
voltage
RSSI > Uthres hold: Iload=4.2µA
RSSI < Uthres hold: Iload= -1.5µA
4
Uc :< 2.6V : Gain high
Uc :> 2.6V : Gain low
UC
C
Uc max = VCC - 0.7V
Uc min = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimped-
ance amplifier that is used to compare the received signal strength signal
(RSSI) generated by the Limiter with an externally provided threshold voltage
Uthres. As shown in the following figure the threshold voltage can have any
value between approximately 0.8 and 2.8V to provide a switching point within
the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage
can be generated by attaching a voltage divider between the 3VOUT pin
(Pin 24) which provides a temperature stable 3V output generated from the
internal bandgap voltage and the THRES pin. If the RSSI level generated by the
Limiter is higher than Uthres, the OTA generates a positive current Iload. This
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a
negative current. These currents do not have the same values in order to
achieve a fast-attack and slow-release action of the AGC and are used to
charge an external capacitor which finally generates the LNA gain control volt-
age.
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3
2.5
2
RSSI Level
1.5
1
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating sce-
nario. The determination of the optimum point is described in the accompanying
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.
It should be noted that the output of the 3VOUT pin is capable of driving up to
50µA, but that the THRES pin input current is only in the region of 40nA. As the
current drawn out of the 3VOUT pin is directly related to the receiver power con-
sumption, the power divider resistors should have high impedance values. The
sum of R1 and R2 has to be 600kΩ in order to yield 3V at the 3VOUT pin. R1
can thus be chosen as 240kΩ, R2 as 360kΩ to yield an overall 3VOUT output
current of 5µA1 and a threshold voltage of 1.8V
Note: If the LNA gain shall be kept in either high or low gain mode this has to
be accomplished by tying the THRES pin to a fixed voltage. In order to achieve
high gain mode operation, a voltage higher than 2.8V shall be applied to the
THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain
mode operation a voltage lower than 0.7V shall be applied to the THRES, such
as a short to ground.
As stated above the capacitor connected to the TAGC pin is generating the gain
control voltage of the LNA due to the charging and discharging currents of the
OTA and thus is also responsible for the AGC time constant. As the charging
and discharging currents are not equal two different time constants will result.
The time constant corresponding to the charging process of the capacitor shall
be chosen according to the data rate. According to measurements performed
at Infineon the capacitor value should be greater than 47nF.
1. note the 20kΩ resistor in series with the 3.1V internal voltage source
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4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-
nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
C1
22
C2
21
Pins:
19
R
R
100k
100k
Filter_Design.wmf
Figure 4-3
(1)(2)
Data Filter Design
b
2Q b
R2Πf3dB
C2 = ---------------------------
4QRΠf3dB
C1 = ----------------------
with
b
a
(3)the quality factor of the poles
Q = ------
where
in case of a Bessel filter a = 1.3617, b = 0.618
and thus Q = 0.577
and in case of a Butterworth filter a = 1.414, b = 1
and thus Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kΩ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
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4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
quartz specifications given by the quartz manufacturer.
CS
Pin 28
Input
impedance
Crystal
Z1-28
TDA5220
Pin 1
Quartz_load.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
1
CS =
1
+ 2π f X L
Cl
with Cl the load capacitance (refer to the quartz crystal specification).
Example:
13.4 MHz: CL = 12 pFXL=1010 ΩCS = 5.9 pF
This value may be obtained in high accuracy by putting two capacitors in series
to the quartz, such as 22pF and 8.2pF for 13.4MHz.
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4.4 Quartz Frequency Calculation
As described in Section 3.4.3 the operating range of the on-chip VCO is 820 to
860 MHz with a nominal center frequency of 840MHz. This signal is divided by
2 before applied to the mixer in case of operation at 434 MHz. This local oscil-
lator signal can be used to downconvert the RF signals both with high- or low-
side injection at the mixer. The resulting receive frequency ranges then extend
between 810 and 870MHz or between 400 and 440MHz. Low-side injection of
the local oscillator has to be used for receive frequencies between 840 and
870MHz as well as high-side injection for receive frequencies below 840MHz.
Corresponding to that in the 400MHz region low-side injection is applicable for
receive frequencies above 420MHz, high-side injection below this frequency.
Therefore for operation both in the 868 and the 434 MHz ISM bands low-side
injection of the local oscillator has to be used. Then the local oscillator fre-
quency is calculated by subtracting the IF frequency (10.7 MHz) from the RF
frequency (434 or 868 MHz). Please note that no sign-inversion occurs in case
of reception and demodulation of FSK-modulated signals.
The overall division ratios in the PLL is 64 in case of operation at 868 MHz or
32 in case of operation at 434 MHz. The quartz frequency in case of low-side
injection may be calculated by using the following formula:
ƒQU = (ƒRF - 10.7) / r
with ƒRF receive frequency
ƒLO local oscillator (PLL) frequency (ƒRF - 10.7)
ƒQU quartz oscillator frequency
r
ratio of local oscillator (PLL) frequency and quartz frequency as
shown in the subsequent table
Table 4-1 Dependence of PLL Overall Division Ratio on FSEL
FSEL
open
GND
Ratio r = (fLO/fQU)
32
64
:
fQU
fQU
=
(
868.4MHz −10.7MHz
)
/ 64 = 13.40156MHz
=
(
434.2MHz −10.7MHz
)
/32 = 13.23437MHz
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4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated using an external R-C inte-
grator as shown in Figure 4-5. The cut-off frequency of the R-C integrator has
to be lower than the lowest frequency appearing in the data signal. In order to
keep distortion low, the minimum value for R is 20kΩ.
R
C
data out
Pins:
19
20
25
Uthreshold
CM
data
filter
data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use
the peak detector in connection with an internal resistive divider and one capac-
itor as shown in the following figure. The component values are depending on
the coding scheme and the protocol used.
C
data out
Pins:
26
25
peak detector
56k
390k
data slicer
CP
Uthreshold
data
filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
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4.6 ASK/FSK Switch Functional Description
The TDA5220 is containing an ASK/FSK switch which can be controlled via
Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that
are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of
the FSK amplifier in order to achieve an appropriate demodulation gain charac-
teristic. In order to compensate for the DC-offset generated especially in case
of the FSK PLL demodulator there is a feedback connection between the
threshold voltage of the bit slicer comparator (Pin 20) to the negative input of
the FSK switch amplifier.
In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87%
of the peak-detector output-voltage at Pin 26 (PDO) can be used as the slicer-
reference level. The selection between these modes is controlled by Pin 16
(SSEL). This is shown in the following figure.
MSEL
15
H=ASK
L=FSK
PEAK
DETECTOR
PDO
from RSSI Gen
(ASK signal)
26
R=56k
ASK/FSK Switch
C=100 nF
R=390k
Data Filter
Comp
R1=100k
R2=100k
-
-
+
FSK PLL Demodulator
+
CP
CM
ASK
FSK
v = 1
25
DATA Out
+
-
+
-
H=CP
L=CM
0.18 mV/kHz
R3=300k
typ. 2 V
1.5 V......2.5 V
R4=30k
22
21
19
20
16
ASK mode: v=1
FSK mode: v=11
FFB
C2
OOP
SLP
SLN
SSEL
R
C1
C
ask_fsk_datapath.WMF
Figure 4-7
ASK/FSK mode datapath
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4.6.1 FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown
above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is
determined by the external RC-combination. The upper cutoff frequency f3 is
determined by the data filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 180µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting
dynamic gain of this circuit is 2mV/kHz within the bandpass. The gain for the DC
content of FSK signal remains at 180µV/kHz. The cutoff frequencies of the
bandpass have to be chosen such that the spectrum of the data signal is influ-
enced in an acceptable amount.
In case that the user data is containing long sequences of logical zeroes the
effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset
voltage inherent at the negative input of the slicer comparator (Pin20) is used.
The comparator has no hysteresis built in.
This offset voltage is generated by the bias current of the negative input of the
comparator (i.e. 20nA) running over the external resistor R. This voltage raises
the voltage appearing at pin 20 (e.g. 1mV with R = 100kΩ). In order to obtain
benefit of this asymmetrical offset for the demodulation of long zeros the lower
of the two FSK frequencies should be chosen in the transmitter as the zero-
symbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v
v-3dB
20dB/dec
-40dB/dec
3dB
0dB
f
DC
f1
f2
f3
0.18mV/kHz
2mV/kHz
frequenzgang.WMF
Figure 4-8
Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
1
f1 =
R 330kΩ
2π
C
R + 330kΩ
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f2 = v f1 =11 f1
f3 = f3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2.
Example:
R = 100kΩ,=C = 47nF
This leads tof1 = 44Hz and f2 = 485Hz
4.6.2 ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charac-
tersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff
frequency is determined by the external capacitors C12 and C14 and the inter-
nal 100k resistors as described in Section 4.2
0dB
-3dB
-40dB/dec
f
f3dB
freq_ask.WMF
Figure 4-9
Frequency charcteristic in case of ASK mode
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TDA 5220
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4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network
as described in Section 4.5 it is necessary to use large values for the capacitor
C attached to the SLN pin (pin 20) in order to achieve long time constants. This
results also from the fact that the choice of the value for R connected between
the SLP and SLN pins (pins 19 and 20) is limited by the 330kΩ resistor appear-
ing in parallel to R as can be seen in Figure 4-7. Apart from this a resistor value
of 100kΩ leads to a voltage offset of 1mv at the comparator input as described
in Section 4.6.1. The resulting startup time constant τ1 can be calculated with:
τ1 = (R // 330kΩ) · C
In case R is chosen to be 100kΩ and C is chosen as 47nF this leads to
τ1 = (100kΩ // 330kΩ) · 47nF = 77kΩ · 47nF = 3.6ms
When the device is turned on this time constant dominates the time necessary
for the device to be able to demodulate data properly. In the powerdown mode
the capacitor is only discharged by leakage currents.
In order to reduce the turn-on time in the presence of large values of C a pre-
charge circuit was included in the TDA5220 as shown in the following figure.
C2
R1+R2=600k
R2
R1
C
R
U
thres hold
20
19
24
23
Iload
Uc
ASK/FSK Switch
Uc>Us Uc<Us
DataFilter
-
U2
+
0 / 240uA
OTA
Us
U2<2.4V : I=240uA
U2>2.4V: I=0
-
20k
+2.4V
+3.1V
precharge.WMF
Figure 4-10 Principle of the precharge circuit
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This circuit charges the capacitor C with an inrush current Iload of typically
220µA for a duration of T2 until the voltage Uc appearing on the capacitor is
equal to the voltage Us at the input of the data filter. This voltage is limited to
2.5V. As soon as these voltages are equal or the duration T2 is exceeded the
precharge circuit is disabled.
τ2 is the time constant of the charging process of C which can be calculated as
τ2 ≈=20kΩ · C2
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can
then be calculated according to the following formula:
æ
ç
ç
ç
ç
è
ö
1
T2 = τ 2 ln
≈ τ 2 1.6
2.4V
3V
1 −
The voltage transient during the charging of C2 is shown in the following figure:
U2
3V
2.4V
T2
2
e-fkt1.WMF
Figure 4-11 Voltage appearing on C2 during precharging process
The voltage appearing on the capacitor C connected to pin 20 is shown in the
following figure. It can be seen that due to the fact that it is charged by a con-
stant current source it exhibits a linear increase in voltage which is limited to
USmax = 2.5V which is also the approximate operating point of the data filter
input. The time constant appearing in this case can be denoted as T3, which
can be calculated with
USmax
C
2,5V
220µA
----------------
T3 = ----------------------- =
C
220µA
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Uc
Us
T3
e-Fkt2.WMF
Figure 4-12 Voltage transient on capacitor C attached to pin 20
As an example the choice of C2 = 22nF and C = 47nF yields
τ2 = 0.44ms
T2 = 0.71ms
T3 = 0.53ms
This means that in this case the inrush current could flow for a duration of
0.64ms but stops already after 0.49ms when the USmax limit has been reached.
T3 should always be chosen to be shorter than T2.
It has to be noted finally that during the turn-on duration T2 the overall device
power consumption is increased by the 220µA needed to charge C.
The precharge circuit may be disabled if C2 is not equipped. This yields a T2
close to zero. Note that the sum of R4 and R5 has to be 600kΩ in order to pro-
duce 3V at the THRES pin as this voltage is internally used also as the refer-
ence for the FSK demodulator.
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Target Specification, October 2001
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
TDA 5220
preliminary
Reference
confidential
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
=-40°C ... + 105°C
AMB
#
Parameter
Symbol
Limit Values
Unit
Remarks
min
-0.3
max
5.5
1
2
3
4
5
Supply Voltage
Vs
Tj
V
°C
Junction Temperature
Storage Temperature
Thermal Resistance
-40
-40
+150
+125
114
Ts
°C
RthJA
VESD
K/W
ESD integrity, all pins excl. Pins 1,3, 6, 28
ESD integrity Pins 1,3,6,28
+2
+1.5
kV
kV
HBM
according to
MIL STD
883D,
method
3015.7
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5.1.2 Operating Range
Within the operational range the IC operates as explained in the circuit descrip-
tion. The AC/DC characteristic limits are not guaranteed. Currents flowing into
the device are denoted as positive currents and v.v.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature T
= -40°C ... + 105°C
AMB
#
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
max
1
Supply Current
I
t.b.d.
t.b.d.
t.b.d.
t.b.d.
t.b.d.
t.b.d.
t.b.d.
t.b.d.
mA
mA
mA
mA
f
f
f
f
= 868MHz, FSK Mode
= 434MHz, FSK Mode
= 868MHz, ASK Mode
= 434MHz, ASK Mode
SF 868
RF
RF
RF
RF
I
SF 434
I
SA 868
I
SA 434
2
Receiver Input Level
ASK
FSK, frequ. dev. ± 50kHz
@ source impedance 50Ω,
BER 2E-3, average power
level, Manchester encoded
datarate 4kBit, 280kHz IF
Bandwidth
ꢀ
RFin
-106
-100
-13
-13
dBm
dBm
3
4
5
LNI Input Frequency
fRF
fMI
400/
810
440/
870
MHz
MHz
MI/MIX Input Frequency
400/
810
440/
870
3dB IF Frequency Range
ASK
FSK
fIF -3dB
5
10.4
23
11
MHz
ꢀ
ꢀꢀThis value is guaranteed by design.
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5.1.3 AC/DC Characteristics at TAMB = 25°C
AC/DC characteristics involve the spread of values guaranteed within the spec-
ified voltage and ambient temperature range. Typical characteristics are the
median of the production. Currents flowing into the device are denoted as pos-
itive currents and vice versa.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Supply
Supply Current
1
Supply current,
standby mode
IS PDWN
50
t.b.d.
t.b.d.
nA
Pin 27 (PDWN)
open or tied to 0 V
2
Supply current, device
operating in 868 MHz
range, FSK mode
I
t.b.d.
t.b.d.
t.b.d.
t.b.d.
5.9
mA
Pin 11 (FSEL) tied
to GND, Pin 15
(MSEL) tied to GND
SF 868
3
4
5
Supply current, device
operating in 434 MHz
range, FSK mode
I
5.7
5.2
5
t.b.d.
t.b.d.
t.b.d.
mA
mA
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) tied to GND
SF 434
Supply current, device
operating in 868 MHz
range, ASK mode
I
I
Pin 11 (FSEL) tied
to GND, Pin 15
(MSEL) open
SA 868
SA 434
Supply current, device
operating in 434 MHz
range, ASK mode
Pin 11 (FSEL)
open, Pin 15
(MSEL) open
LNA
Signal Input LNI (PIN 3), V
> 2.8V, high gain mode
THRES
1
Average Power Level
at BER = 2E-3
(Sensitivity) ASK
RFin
-110
dBm Manchester
encoded datarate
ꢀ
ꢀ
4kBit, 280kHz IF
Bandwidth
2
Average Power Level
at BER = 2E-3
RFin
-103
dBm Manchester enc.
datarate 4kBit,
(Sensitivity) FSK
280kHz IF Bandw.,
± 50kHz pk. dev.
ꢀ
ꢀ
3
4
Input impedance,
S
S
0.873 / -34.7 deg
0.738 / -73.5 deg
11 LNA
f
=434 MHz
RF
Input impedance,
=869 MHz
11 LNA
f
RF
ꢀ
ꢀ
5
6
Input level @ 1dB com-
pression
P1dB
IIP3
-15
-10
dBm
LNA
Input 3rd order intercept
LNA
LNA
dBm
dBm
matched input
matched input
point f =434 MHz
RF
Input 3rd order intercept
ꢀ
7
IIP3
-14
point f =869 MHz
RF
Wireless Components
5 - 4
Target Specification, October 2001
TDA 5220
preliminary
Reference
confidential
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
-73
ꢀ
8
LO signal feedthrough
at antenna port
LO
dBm
LNI
Signal Output LNO (PIN 6), V
> 2.8V, high gain mode
THRES
ꢀ
ꢀ
ꢀ
1
2
3
Gain f =434 MHz
RF
S
1.509 / 138.2 deg
21 LNA
Gain f =869 MHz
RF
S
1.419 / 101.7 deg
0.886 / -12.9 deg
21 LNA
22 LNA
Output impedance,
S
f
=434 MHz
RF
ꢀ
4
5
6
Output impedance,
=869 MHz
S
0.866 / -24.2 deg
22 LNA
f
RF
Voltage Gain Antenna
G
42
40
dB
dB
AntMI
AntMI
to IFO f =434 MHz
RF
Voltage Gain Antenna
G
to IFO f =869 MHz
RF
Signal Input LNI, V
= GND, low gain mode
THRES
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
2
3
4
5
Input impedance,
=434 MHz
S
0.873 / -34.7 deg
11 LNA
f
RF
Input impedance,
=869 MHz
S
0.738 / -73.5 deg
11 LNA
f
RF
Input level @ 1dB C. P
= 434 MHz
P1dB
P1dB
IIP3
-18
-6
dBm matched input
dBm matched input
dBm matched input
LNA
f
RF
Input level @ 1dB C. P
= 869 MHz
LNA
f
RF
Input 3rd order intercept
LNA
-10
point f =434 MHz
RF
Input 3rd order intercept
LNA
ꢀ
6
IIP3
-5
dBm matched input
point f =869 MHz
RF
Signal Output LNO, V
= GND, low gain mode
THRES
ꢀ
ꢀ
ꢀ
1
2
3
Gain f =434 MHz
S
S
S
0.183 / 140.6 deg
RF
21 LNA
21 LNA
22 LNA
Gain f =869 MHz
RF
0.179 / 109.1deg
0.897 / -13.6 deg
Output impedance,
f
=434 MHz
RF
ꢀ
4
5
6
Output impedance,
=869 MHz
S
0.868 / -26.3 deg
22 LNA
f
RF
Voltage Gain Antenna
G
22
19
dB
dB
AntMI
to MI f =434 MHz
RF
Voltage Gain Antenna
G
AntMI
to MI f =869 MHz
RF
Wireless Components
5 - 5
Target Specification, October 2001
TDA 5220
preliminary
Reference
confidential
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Signal 3VOUT (PIN 24)
1
2
Output voltage
Current out
V
2.9
-3
3.1
-5
3.3
-10
V
3VOUT Pin open
see Section 4.1
3VOUT
I
µA
3VOUT
Signal THRES (PIN 23)
1
2
3
4
Input Voltage range
LNA low gain mode
LNA high gain mode
Current in
V
0
0
V -1V
S
V
V
see Section 4.1
THRES
V
THRES
V
2.8
3
5
V
S
V
or shorted to Pin 24
THRES
ITHRES_in
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-3.6
1
-4.2
1.6
-5
µA
µA
RSSI > V
RSSI>V
THRES
2
Current in, LNA high
gain state
V
2.2
TAGC_in
THRES
MIXER
Signal Input MI/MIX (PINS 8/9)
ꢀ
ꢀ
ꢀ
1
2
3
Input impedance,
=434 MHz
S
S
0.942 / -14.4 deg
0.918 / -28.1 deg
-28
11 MIX
f
RF
Input impedance,
=869 MHz
11 MIX
f
RF
Input 3rd order intercept
MIX
MIX
IIP3
IIP3
dBm
dBm
point f =434 MHz
RF
Input 3rd order intercept
ꢀ
ꢀ
4
-26
point f =869 MHz
RF
Signal Output IFO (PIN 12)
1
2
Output impedance
Z
330
+19
Ω
IFO
Conversion Voltage
G
dB
MIX
Gain f =434 MHz
RF
3
Conversion Voltage
G
+18
dB
MIX
Gain f =869 MHz
RF
LIMITER
Signal Input LIM/LIMX (PINS 17/18)
ꢀ
1
2
3
4
Input Impedance
RSSI dynamic range
RSSI linearity
Z
264
60
330
396
Ω
dB
LIM
DR
LIN
f
80
RSSI
ꢀ
ꢀ
dB
±1
RSSI
Operating frequency
(3dB points)
5
10.7
23
MHz
LIM
Wireless Components
5 - 6
Target Specification, October 2001
TDA 5220
preliminary
Reference
confidential
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
DATA FILTER
ꢀ
1
2
Useable bandwidth
BW
100
1
kHz
V
BB FILT
RSSI Level at Data Fil-
ter Output SLP,
RSSI
0.3
1.8
LNA in high gain
mode
low
RF =-103dBm
IN
3
RSSI Level at Data Fil-
ter Output SLP,
RSSI
3
V
LNA in high gain
mode
high
RF =-30dBm
IN
Slicer, Signal Output DATA (PIN 25)
ꢀ
1
Maximum Datarate
DR
100
0.1
kBps NRZ, 20pF capaci-
tive loading
max
2
3
LOW output voltage
HIGH output voltage
V
V
0
V
V
SLIC_L
V -
S
V -1V
S
V -
S
SLIC_H
1.3V
-100
0.7V
-300
Slicer, Negative Input (PIN 20)
Precharge Current Out
1
I
-220
µA
see Section 4.7
PCH_SLN
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
2
Load current
I
-600
-950
446
-1300
t.b.d.
µA
load
R
Internal resistive load
t.b.d.
kΩ
CRYSTAL OSCILLATOR
Signals CRSTL1, CRSTL 2, (PINS 1/28)
1
Operating frequency
f
t.b.d.
14
MHz fundamental mode,
series resonance
CRSTL
ꢀ
2
Input Impedance
@ ~13MHz
Z
-600
+j1010
Ω
1-28
3
Serial Capacity
@ ~13MHz
C
=C1
5.9
pF
S13
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
2
3
ASK Mode
FSK Mode
V
1.4
0
4
V
V
or open
MSEL
V
I
0.2
MSEL
Input bias current
MSEL
t.b.d.
-11
t.b.d.
µA
MSEL tied to GND
MSEL
Wireless Components
5 - 7
Target Specification, October 2001
TDA 5220
preliminary
Reference
confidential
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
FSK DEMODULATOR
1
Demodulation Gain
G
85
180
225
µV/
FMDEM
kHz
2
Useable IF Bandwidth
BW
10.2
10.7
11.2
MHz
IFPLL
POWER DOWN MODE
Signal PDWN (PIN 27)
1
2
3
Powerdown Mode On
Powerdown Mode Off
PWDN
0
0.8
V
V
ON
PWDN
I
2.8
V
S
Off
Input bias current
PDWN
19
uA
Power On Mode
PDWN
4
Start-up Time until valid
signal is detected at IF
T
1
ms
SU
VCO MULTIPLEXER
Signal FSEL (PIN 11)
1
2
3
f
f
range 434 MHz
range 869 MHz
V
1.4
0
4
V
V
or open
RF
RF
FSEL
V
I
0.2
FSEL
Input bias current
FSEL
-160
-200
-240
µA
FSEL tied to GND
FSEL
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1
Slicer-Reference is
voltage at Pin 20 (SLN)
V
1.4
0
4
V
V
or open
SSEL
2
Slicer-Reference is
V
0.2
SSEL
approx. 87% of the volt-
age at Pin 26 (PDO)
3
Input bias current
SSEL
I
-3
-5
-7
µA
SSEL tied to GND
SSEL
ꢀꢀMeasured only in lab.
Wireless Components
5 - 8
Target Specification, October 2001
TDA 5220
preliminary
Reference
confidential
5.1.4 AC/DC Characteristics at TAMB = -40 to 105°C
Currents flowing into the device are denoted as positive currents and vice versa
Table 5-4 AC/DC Characteristics with T = -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
AMB
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Supply
Supply Current
1
Supply current,
standby mode
IS PDWN
50
t.b.d.
t.b.d.
nA
Pin 27 (PDWN)
open or tied to 0 V
2
Supply current, device
operating in 868 MHz
range, FSK mode
I
t.b.d.
t.b.d.
t.b.d.
t.b.d.
5.9
mA
Pin 11 (FSEL) tied
to GND, Pin 15
(MSEL) tied to GND
SF 868
3
4
5
Supply current, device
operating in 434 MHz
range, FSK mode
I
5.7
5.2
5
t.b.d.
t.b.d.
t.b.d.
mA
mA
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) tied to GND
SF 434
Supply current, device
operating in 868 MHz
range, ASK mode
I
Pin 11 (FSEL) tied
to GND, Pin 15
(MSEL) open
SA 868
Supply current, device
operating in 434 MHz
range, ASK mode
I
Pin 11 (FSEL)
open, Pin 15
(MSEL) open
SA 434
Signal 3VOUT (PIN 24)
1
2
Output voltage
Current out
V
2.9
-3
3.1
-5
3.3
-10
V
3VOUT Pin open
see Section 4.1
3VOUT
I
µA
3VOUT
Signal THRES (PIN 23)
1
2
3
4
Input Voltage range
LNA low gain mode
LNA high gain mode
Current in
V
0
0
3
V -1V
S
V
V
see Section 4.1
THRES
V
0.3
THRES
V
V
S
V
or shorted to Pin 24
THRES
ITHRES_in
5
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-1
-4.2
1.5
-8
5
µA
µA
RSSI > V
RSSI>V
THRES
2
Current in, LNA high
gain state
V
0.5
TAGC_in
THRES
MIXER
1
Conversion Voltage
G
+19
+18
dB
dB
MIX
Gain f =434 MHz
RF
2
Conversion Voltage
G
MIX
Gain f =869 MHz
RF
LIMITER
Signal Input LIM/LIMX (PINS 17/18)
RSSI dynamic range DR
1
60
80
dB
RSSI
Wireless Components
5 - 9
Target Specification, October 2001
TDA 5220
preliminary
Reference
confidential
Table 5-4 AC/DC Characteristics with T
= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
AMB
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
1
DATA FILTER
2
RSSI Level at Data Fil-
ter Output SLP,
RSSI
0.3
1.8
V
V
LNA in high gain
mode
low
RF =-103dBm
IN
3
RSSI Level at Data Fil-
ter Output SLP,
RSSI
3
LNA in high gain
mode
high
RF =-30dBm
IN
Slicer, Signal Output DATA (PIN 25)
ꢀ
1
Maximum Datarate
DR
100
0.1
kBps NRZ, 20pF capaci-
tive loading
max
2
3
LOW output voltage
HIGH output voltage
V
V
0
V
V
SLIC_L
V -
S
V -1V
S
V -
S
SLIC_H
1.5V
-100
0.5V
-300
Slicer, Negative Input (PIN 20)
Precharge Current Out
1
I
-220
µA
see Section 4.7
PCH_SLN
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
2
Load current
I
-400
-850
446
-1400
t.b.d.
µA
load
Internal resistive load
R
t.b.d.
kΩ
CRYSTAL OSCILLATOR
Signals CRSTL1, CRSTL 2, (PINS 1/28)
Operating frequency
1
f
t.b.d.
14
MHz fundamental mode,
series resonance
CRSTL
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
2
3
ASK Mode
FSK Mode
V
V
I
1.4
0
4
V
V
or open
MSEL
0.2
MSEL
Input bias current
MSEL
t.b.d.
-11
t.b.d.
µA
MSEL tied to GND
MSEL
FSK DEMODULATOR
1
Demodulation Gain
G
105
180
245
µV/
FMDEM
kHz
2
Useable IF Bandwidth
BW
10.2
10.7
11.2
MHz
IFPLL
POWER DOWN MODE
Signal PDWN (PIN 27)
1
2
Powerdown Mode On
Powerdown Mode Off
PWDN
0
0.8
V
V
ON
PWDN
2.8
V
S
Off
Wireless Components
5 - 10
Target Specification, October 2001
TDA 5220
preliminary
Reference
confidential
Table 5-4 AC/DC Characteristics with T
= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
AMB
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
1
3
Start-up Time until valid
signal is detected at IF
T
ms
SU
VCO MULTIPLEXER
Signal FSEL (PIN 11)
1
2
3
f
f
range 434 MHz
range 869 MHz
V
V
I
1.4
0
4
V
V
or open
RF
RF
FSEL
0.2
FSEL
Input bias current FSEL
-110
-200
-340
µA
FSEL tied to GND
FSEL
DATA-SLICER REFERENCE-LEVEL
Signal SSEL (PIN 16), ASK-Mode
1
Slicer-Reference is
voltage at Pin 20 (SLN)
V
1.4
0
4
V
V
or open
SSEL
2
Slicer-Reference is
V
0.2
SSEL
approx. 87% of the volt-
age at Pin 26 (PDO)
3
Input bias current
SSEL
I
t.b.d.
-11
t.b.d.
µA
SSEL tied to GND
SSEL
Wireless Components
5 - 11
Target Specification, October 2001
相关型号：
TDA5235
Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing
INFINEON
TDA5240
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