TLD5191ES_技术文档

TLD5191ES

Datasheet

™

LITIX Power H-Bridge DC-DC controller

Features

• Single inductor high power buck-boost controller

• Switching frequency range from 200 kHz to 700 kHz

• Maximum eﬀiciency in every condition (up to 96%)

• Constant current (LED) and constant voltage regulation

• EMC optimized device: spread spectrum always activated

• Overvoltage, shorted LED fault and overtemperature diagnostic output

• Enhanced dimming features: Analog and PWM dimming (from digital input or sourced by

embedded PWM engine)

• LED current accuracy ꢀ%

Potential applications

• Especially designed for driving high power LEDs in automotive applications

• Automotive exterior lighting: full LED headlamp assemblies (low beam, high beam, matrix beam,

pixel light)

• Voltage pre-regulator for rear lamp assemblies

• General purpose DC-DC for constant current or constant voltage applications

Product validation

Product validation according to AEC-Q100, Grade1. Qualified for automotive applications.

Description

The TLD5191ES is a synchronous MOSFET H-Bridge DC-DC controller with built-in protection features. This concept is beneficial

for driving high power LEDs with maximum system eﬀiciency and minimum number of external components. The TLD5191ES

oﬀers analog and digital (PWM) dimming and embedded PWM engine. The switching frequency is adjustable in the range of

200 kHz to 700 kHz. A built-in spread spectrum switching frequency modulation and the forced continuous current regulation

mode improve the overall EMC behavior. Furthermore the current mode regulation scheme provides a stable regulation loop

maintained by small external compensation components. The adjustable sof start feature limits the current peak as well as

voltage overshoot at start-up. The TLD5191ES is suitable for use in the automotive environment.

V_S

C_POW

V_IVCC

D_BS2

V_IVCC

D_BS1

VIN

BST1

BST2

C_IN

C_OUT1C_OUT2

R_FB

V_IVCC

M₄

M_ꢀ

M₁

M₂

C_BS1C_BS2

R_OV1

R_OV2

IVCC

HSGD1

SWN1

C_IVCC

R_INUVLO1

LSGD1

SWCS

EN/INUVLO

R_INUVLO2

R_FREQ

R_SWCS

TLD5191ES

FREQ

SGND

C_{SOFT START}

R_COMP

C_COMP

SOFT START

COMP

LSGD2

HSGD2

SWN2

VFB

Analog

SET

dimming

V_IVCC

R_PWM1

V_IVCC

FBH

PWMI

EF

R_PWM2

R_PUEF

FBL

M_PWM

To µC

PWMO

AGND

Datasheet

www.infineon.com

Please read the sections "Important notice" and "Warnings" at the end of this document

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

Description

Parameter

Symbol

V_POW

Values

Power stage input voltage range

Device input supply voltage range

4.5 V … 55 V

4.5 V … 40 V

V_VIN

55 V as LED driver boost mode

50 V as LED driver buck mode

50 V as voltage regulator

Maximum output voltage (depending on the application

conditions)

V_OUT(max)

Switching frequency range

f_SW

200 kHz … 700 kHz

Typical H-Bridge NMOS driver on-state resistance at T_J= 25°C

R_{DS(ON_PU)}

2.ꢀ Ω

(Gate pull-up)

Typical H-Bridge NMOS driver on-state resistance at T_J= 25°C

(Gate pull-down)

R_{DS(ON_PD)}

1.2 Ω

Protective functions

• Overload protection of external MOSFETs

• Shorted load, output overvoltage protection

• Input undervoltage protection

• Thermal shutdown of device with autorestart behavior

• Electrostatic discharge protection (ESD)

Diagnostic functions

Diagnostic information via error flag: device overtemperature shutdown, output short to GND, output overvoltage

Type

Package

Marking

TLD5191ES

PG-TSDSO-24

TLD5191ES

Datasheet

2

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

Table of contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1

2

2.1

2.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

ꢀ.1

ꢀ.2

ꢀ.ꢀ

4

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Diﬀerent power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ꢀ

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.1

4.2

4.ꢀ

5

5.1

5.2

5.ꢀ

Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Regulator diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Adjustable sofꢀstart ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Switching frequency setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Operation of 4 switches H-Bridge architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Boost mode (VIN < VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Buck mode (VIN > VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Buck-Boost mode (VIN ~ VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Programming output voltage (constant voltage regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2ꢀ

5.4

5.4.1

5.4.2

5.4.ꢀ

5.5

5.6

6

6.1

6.2

Digital dimming function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

7

7.1

7.2

Analog dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢀ1

8

8.1

8.2

Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ2

IVCC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢀ2

Datasheet

ꢀ

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

Table of contents

9

Protection and diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀꢀ

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀꢀ

Output overvoltage, short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀꢀ

Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ4

Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ4

Device temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ4

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢀ5

9.1

9.2

9.2.1

9.2.2

9.ꢀ

9.4

10

Infineon FLAT SPECTRUM feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ7

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ7

Spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢀ7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢀ7

10.1

10.2

10.ꢀ

11

12

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ꢀ8

Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4ꢀ

Datasheet

4

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

1 Block diagram

1

Block diagram

IVCC

Internal

Supply

Power On

Reset

IVCC

VIN

LDO

GATE

DRIVERS

BST1

Oscillator

HSGD1

SWN1

FREQ

BUCK

LOGIC

IVCC

Spread

Spectrum

Generator

LSGD1

LSGD2

Main PWM

Generator

Thermal Protection

Output Over Voltage

+ Short to GND detection

BOOST

LOGIC

Soft

Start

SOFT_START

BST2

VIN Voltage

Protection +

Enable

EN/INUVLO

HSGD2

SWN2

IVCC

Embedded

PWM engine

PWMO

SWCS

PWMI

EF

Switch Current

Error Amplifier

Error

Flag

SGND

VFB

Voltage

Feedback

FBH

FBL

Analog

Dimming

Feedback Error Amplifier

SET

AGND

COMP

Figure 1

Block diagram TLD5191ES

Datasheet

5

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

2 Pin configuration

2

Pin configuration

Pin assignment

2.1

1

2

24

2ꢀ

22

21

20

19

18

HSGD1

SWN1

BST1

IVCC

SOFT START

VIN

ꢀ

Exposed

Pad

LSGD1

4

EN/INUVLO

LSGD2

BST2

5

AGND

FREQ

6

SWN2

7

EF

PIN CONFIGURATION.VSDX

8

17

PWMO

PWMI

HSGD2

FBH

9

16

15

14

1ꢀ

10

11

12

FBL

SET

VFB

SGND

SWCS

COMP

Figure 2

Pin configuration PG-TSDSO-24

2.2

Pin definitions and functions

Table 1

Pin definitions and functions

Symbol

I/O¹⁾

Function

22

VIN

-

Power supply voltage

Supply for internal biasing

20

-

AGND

EP

-

Analog ground

Ground reference

Exposed pad

Connect to external heatspreading Cu area (e.g. inner GND layer of multilayer

PCB with thermal vias)

1

HSGD1

O

High-side gate driver output 1

Drives the top n-channel MOSFET with a voltage equal to V_IVCCsuperimposed

on the switch node voltage SWN1. Connect to gate of external switching

MOSFET

(table continues...)

Datasheet

6

Rev.1.00

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TLD5191ES

Datasheet

2 Pin configuration

Table 1

(continued) Pin definitions and functions

Symbol

I/O¹⁾

Function

8

HSGD2

O

High-side gate driver output 2

Drives the top n-channel MOSFET with a voltage equal to V_IVCCsuperimposed

on the switch node voltage SWN2. Connect to gate of external switching

MOSFET

4

5

LSGD1

LSGD2

O

Low-side gate driver output 1

Drives the low-side n-channel MOSFET between GND and V_IVCC.Connect to gate

of external switching MOSFET

Low-side gate driver output 2

Drives the low-side n-channel MOSFET between GND and V_IVCC.Connect to gate

of external switching MOSFET

2

SWN1

SWN2

IVCC

IO

O

Switch node 1

SWN1 pin swings from a diode voltage drop below ground up to V_IN

7

Switch node 2

SWN2 pin swings from ground up to a diode voltage drop above V_OUT

24

Internal LDO output

Used for internal biasing and gate driver supply. Bypass with external capacitor

close to the pin. Pin must not be lef open

21

EN/INUVLO

I, PD

Enable/Input undervoltage lockout

Used to put the device in a low current consumption mode, with additional

capability to fix an undervoltage threshold via external components. Pin must

not be lef open

19

16

FREQ

PWMI

I

Frequency select input

Connect external resistor to GND to set frequency

I, PD

PWM Control input

Used to control the digital dimming via external PWM signal or via the

embedded PWM engine

9

FBH

FBL

I

Output current feedback positive

Non inverting Input (+)

10

ꢀ

I

Output current feedback negative

Inverting Input (-)

BST1

IO

Bootstrap capacitor

Used for internal biasing and to drive the high-side switch HSGD1. Bypass to

SWN1 with external capacitor close to the pin. Pin must not be lef open

6

BST2

IO

I

Bootstrap capacitor

Used for internal biasing and to drive the high-side switch HSGD2. Bypass to

SWN2 with external capacitor close to the pin. Pin must not be lef open

12

SWCS

Current sense input

Inductor current measurement - Non-inverting input (+)

(table continues...)

Datasheet

7

Rev.1.00

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TLD5191ES

Datasheet

2 Pin configuration

Table 1

(continued) Pin definitions and functions

Symbol

I/O¹⁾

Function

11

SGND

I

Current sense / Power ground

Inductor current sense - Inverting Input (-). Power ground, connect to GND

1ꢀ

2ꢀ

14

15

COMP

O

I

Compensation network pin

Connect R and C network to pin for stability phase margin adjustment

SOFT_START

VFB

Softsars configuration pin

Connect a capacitor C_{SOFT_START}to GND to fix a sof start ramp default time

Output voltage feedback pin

Output voltage feedback to set output overvoltage protection function

SET

I

Analog current sense adjustment pin

A voltage V_SETbetween 0.2 V and 1.4 V will adjust the I_LEDor V_OUTin a linear

relation

17

18

PWMO

EF

O

PWM Digital dimming output

Drives n-channel MOSFET between GND and V_IVCCfor dimming purposes

Error flag output

An open drain output which is pulled to LOW when an output short to GND, an

output overvoltage or IC overtemperature occurs

1) O: Output, I: Input, PD: pull-down circuit integrated

Datasheet

8

Rev.1.00

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TLD5191ES

Datasheet

3 General product characteristics

3

General product characteristics

3.1

Absolute maximum ratings

Table 2

Absolute maximum ratings

T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Not subject to production test, specified by design

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

Max.

Supply voltages

VIN Supply Input

V_VIN

-0.ꢀ

–

60

V

–

PRQ-ꢀ2

PRQ-ꢀꢀ

IVCC Internal linear

voltage regulator output

voltage

V_IVCC

-0.ꢀ

–

6

Gate Driver Stages

LSGD1,2 Low-side

gatedriver voltage

V_LSGD1,2

-0.ꢀ

–

5.5

60

6

V

–

PRQ-ꢀ4

PRQ-ꢀ5

PRQ-ꢀ6

PRQ-ꢀ7

PRQ-ꢀ8

PRQ-ꢀ9

PRQ-40

PRQ-41

HSGD1,2 - SWN1,2 High- V_{HSGD1,2-SWN1,2}-0.ꢀ

side gate driver voltage

Diﬀerential signal

(not referred to GND)

SWN1, SWN2 Switching V_{SWN1, 2}

node voltage

-1

–

(BST1-SWN1), (BST2-

SWN2) Boostrap voltage

V_{BST1,2-SWN1,2}

V_{BST1, 2}

V_SWCS

-0.ꢀ

-0.5

Diﬀerential signal

(not referred to GND)

BST1, BST2 Boostrap

voltage related to GND

65

0.ꢀ

0.5

–

SWCS Switch current

sense input voltage

SGND Switch current

sense GND voltage

V_SGND

SWCS-SGND Switch

current sense diﬀerential

voltage

V_SWCS-SGND

Diﬀerential signal

(not referred to GND)

PWMO Output voltage

V_PWMO

-0.ꢀ

–

5.5

V

–

PRQ-46

High voltage pins

FBH, FBL Feedback error V_{FBH, FBL}

amplifier voltage

-0.ꢀ

-0.5

–

60

V

PRQ-42

PRQ-4ꢀ

FBH-FBL Feedback error V_FBH-FBL

amplifier diﬀerential

voltage

0.5

Diﬀerential signal

(not referred to GND)

EN/INUVLO Device

enable/input

undervoltage lockout

V_EN/INUVLO

-0.ꢀ

–

60

V

–

PRQ-44

(table continues...)

Datasheet

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Datasheet

3 General product characteristics

Table 2

(continued) Absolute maximum ratings

T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Not subject to production test, specified by design

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

Max.

Analog pins

PWMI Input voltage

VFB Input voltage

V_PWMI

V_VFB

V_EF

-0.ꢀ

–

5.5

V

–

PRQ-45

PRQ-47

PRQ-48

-0.ꢀ

–

5.5

EF Error flag output

voltage

SET Analog dimming

input voltage

V_SET

-0.ꢀ

–

5.5

ꢀ.6

V

–

PRQ-49

PRQ-205

PRQ-50

PRQ-51

COMP Compensation

input voltage

V_COMP

SOFT_START Sofstart

voltage

V_{SOFT_START}

V_FREQ

FREQ Voltage at

frequency selection pin

Temperatures

Junction Temperature

Storage Temperature

ESD susceptibility

T_J

-40

-55

–

150

°C

–

PRQ-52

PRQ-5ꢀ

T_stg

ESD resistivity of all pins V_ESD,HBM

-2

–

2

kV

V

HBM¹⁾

CDM²⁾

PRQ-54

PRQ-55

ESD Resistivity to GND

V_ESD,CDM

-750

750

1)

2)

ESD susceptibility, Human Body Model “HBM” according to AEC Q100-002

ESD susceptibility, Charged Device Model “CDM” according to AECQ100-011

Notes:

1.

Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum

rating conditions for extended periods may aﬀect device reliability.

2.

Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not

designed for continuous repetitive operation.

Datasheet

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TLD5191ES

Datasheet

3 General product characteristics

3.2

Functional range

Table 3

Parameter

Functional Range

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

4.5

Max.

40

1)

Device extended supply V_VIN

voltage range

V

PRQ-142

PRQ-57

PRQ-58

PRQ-59

Device nominal supply

voltage range

V_VIN

V_POW

T_J

8

–

ꢀ6

V

–

1)

Power stage voltage

range

4.5

–

55

V

Junction temperature

-40

–

150

°C

–

1)

Not subject to production test, specified by design.

Note:

Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

3.3

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to

www.jedec.org.

Table 4

Thermal Resistance

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

Max.

1) 2)

Junction to case

Junction to ambient

1)

R_thJC

R_thJA

–

7.78

–

K/W

PRQ-60

PRQ-61

ꢀ8.2

³⁾2s2p

Not subject to production test, specified by design

2)

Specified R_thJCvalue is simulated at natural convection on a cold plate setup (all pins and the exposed pad are

fixed to ambient temperature). T_A= 25°C; The IC is dissipating 1 W

3)

Specified R_thJAvalue is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-ꢀ) +

heatsink area at natural convection on FR4 board; The device was simulated on a 76.2 x 114.ꢀ x 1.5 mm board.

The 2s2p board has 2 outer copper layers (2 x 70 µm Cu) and 2 inner copper layers (2 x ꢀ5 µm Cu). A thermal

via (diameter = 0.ꢀ mm and 25 µm plating) array was applied under the exposed pad and connected the first

outer layer (top) to the first inner layer and second outer layer (bottom) of the JEDEC PCB. T_A= 25°C; The IC is

dissipating 1 W

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Datasheet

4 Power supply

4

Power supply

Description

4.1

The TLD5191ES is supplied by the VIN (main supply voltage) pin.

The VIN supply provides internal supply voltages for the analog and digital blocks.

IVCC supplies the low side driver stages and the PWMO driver.

This supply is used also to charge, through external Schottky diodes, the bootstrap capacitors which provide supply

voltages to the high-side driver stages.

The supply pins VIN and IVCC have undervoltage detections.

If the voltage on IVCC goes below V_{IVCC RTH,d}, driver stages are deactivated, thus stopping the switching activity.

_

The EN/INUVLO pin can be used as input undervoltage protection by placing a resistor divider from VIN to GND.

If the voltage on EN/INUVLO pin goes below V_EN/INUVLOth, IVCC voltage regulator is switched oﬀ, and switching activity

is stopped.

Figure ꢀ shows a basic concept drawing of the supply domains and interactions among pins VIN and IVCC.

V_S

VIN

R₁

VREG (5V)

IVCC

EN/INUVLO

Internal pre-regulated

voltage Supply

R₂

LS – Drivers &

PWMO driver

VREG digital

VREG analog

SGND

Bandgap

Reference

BSTx

HS - Drivers

SWNx

LOGIC

TLD5191ES

Figure 3

Power supply concept diagram

Usage of EN/INUVLO pin in diﬀerens applications

The pin EN/INUVLO is a double function pin and can be used to put the device into a low current consumption mode.

An undervoltage threshold should be fixed by placing an external resistor divider (A) in order to avoid low voltage

operating conditions. This pin can be driven by a µC-port as shown in (B) and (C) or directly connected to the input

voltage supply as shown in (D).

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Datasheet

4 Power supply

A

B

C

D

V_S

VIN

R₁

R₂

R₁

µC port

EN/INUVLO

TLD5191ES

R₂

µC port

Figure 4

Usage of EN/INUVLO pin in diﬀerens applications

4.2

Diﬀerens power states

TLD5191ES has the following power states:

•

SLEEP state

IDLE state

ACTIVE state

The transition between the power states is determined according to these variables:

•

VIN level

EN/INUVLO level

IVCC level

The state diagram including the possible transitions is shown in Figure 5

Power-up

EN/INUVLO = HIGH

EN/INUVLO = LOW

SLEEP

EN/INUVLO = LOW

IDLE

ACTIVE

VIN = LOW

or IVCC = LOW

VIN = HIGH

& IVCC = HIGH

Figure 5

Simplified state diagram

The Power-up condition is entered when the supply voltage V_VINexceeds its minimum supply voltage threshold

V_VIN(ON)

.

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Datasheet

4 Power supply

SLEEP

When the TLD5191ES is in the SLEEP state, all gate drivers and error flag are in OFF state, independently from the

supply voltages V_IN, IVCC. The current consumption is lower than I_VIN(SLEEP)

.

The transition from SLEEP to ACTIVE state requires a specified time: t_ACTIVE

.

IDLE

In IDLE state the internal voltage regulator is working. The output drivers are switched OFF.

Diagnosis functions are not available.

ACTIVE

In active state the device will start switching activity to provide power at the output only when PWMI = HIGH or PWMI

is in a valid range to enable the embedded PWM engine.

If the voltage between pins BST1,2 and SWN1,2 is higher than V_{BST1,2 - VSWN1,2_Uvth}, high side gate drivers are enabled,

otherwise they are disabled and no switching activity is permitted.

In active state the device current consumption via V_INis dependent on the external MOSFETs used and the switching

frequency f_SW

.

Digital dimming PWM activity is mirrored on the PWMO output pin unless a fault condition is detected (for details

see Chapter 6.1).

V_EN/INUVLO

t_ACTIVE

V_EN/INUVLOth

t

V_IVCC

V_{IVCC_RTH,d}

+V_{IVCCX_HYST}

t

V_PWMI

V_PWMO

t

Switching

activity

t

V_FBH-V_FBL

V_{(FBH-FBL)_100}

t

Softstart

PWM ON

Gate ON

PWM OFF

Gate OFF

Diag OFF

PWM ON

Gate ON

Diag ON

PWM OFF

Gate OFF

Diag OFF

PWM ON

Gate ON

Diag ON

PWM OFF

Gate OFF

Diag OFF

Power ON

Diagnosis ON

Figure 6

Timing diagram LED dimming and startup behavior example (V_VINstable in the functional

range and not during startup)

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TLD5191ES

Datasheet

4 Power supply

4.3

Electrical characteristics

Table 5

Electrical Characteristics

V_IN= 8V to ꢀ6V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

Max.

4.7

Input voltage startup

V_VIN(ON)

–

V

V_VINincreasing;

V_EN/INUVLO= HIGH;

I_IVCC= 0 mA

PRQ-64

Input undervoltage

switch OFF

V_VIN(OFF)

–

4.5

V

V_VINdecreasing;

V_EN/INUVLO= HIGH;

I_IVCC= 10 mA

PRQ-65

Device operating current I_VIN(ACTIVE)

–

5

–

7

mA

µA

¹⁾ACTIVE mode;

V_PWMI= 0 V

PRQ-66

PRQ-67

VIN Sleep mode supply

current

I_VIN(SLEEP)

1.5

V_EN/INUVLO= 0 V;

V_VIN= 1ꢀ.5 V;

V_IVCC= 0 V

Input undervoltage

falling threshold

V_EN/INUVLOth

1.6

–

1.75

90

1.9

–

V

–

PRQ-68

PRQ-69

PRQ-70

PRQ-71

PRQ-72

1)

EN/INUVLO rising

hysteresis

V_{EN/INUVLO(hyst)}

mV

µA

ms

EN/INUVLO input current I_{EN/INUVLO(LOW)}

LOW

0.45

0.89

2.2

–

1.ꢀ4

ꢀ.ꢀ

0.7

V_EN/INUVLO= 0.8 V;

EN/INUVLO input current I_{EN/INUVLO(HIGH)}1.1

HIGH

V_EN/INUVLO= 2 V;

1)

SLEEP mode to ACTIVE

time

t_ACTIVE

–

C

= 10 µF;

IVCC

V_VIN= 1ꢀ.5 V

1)

Not subject to production test, specified by design

Datasheet

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TLD5191ES

Datasheet

5 Regulator

5

Regulator

The TLD5191ES includes all of the functions necessary to provide constant current to the output as usually required

to drive LEDs. A constant voltage regulation can also be implemented (refer to Chapter 5.5).

It is designed to control 4 gate driver outputs in a H-Bridge topology by using only one inductor and 4 external

MOSFETs. This topology is able to operate in high power BOOST, BUCK-BOOST and BUCK mode applications with

maximum eﬀiciency.

The transition between the diﬀerent regulation modes is done automatically by the device itself, with respect to the

application boundary conditions.

The transition phase between modes is seamless.

5.1

Regulator diagram

An analog current control loop (with total gain = IFBx_gm) connected to the sensing pins FBL, FBH regulates the output

current.

The regulator function is implemented by a pulse width modulated (PWM) current mode controller. The error in the

output current loop is used to determine the appropriate duty cycle to get a constant output current.

An external compensation network (RCOMP, CCOMP) is used to adjust the control loop to various application

boundary conditions. The inductor current for the current mode loop is sensed by the RSWCS resistor. R_SWCSis used

also to limit the maximum external switches / inductor current.

If the voltage across R_SWCSexceeds its overcurrent threshold (V_{SWCS_buck}or V_{SWCS_boost}for buck or boost operation

respectively) the device reduces the duty cycle in order to bring the switches current below the imposed limit.

The current mode controller has a built-in slope compensation as well to prevent sub-harmonic oscillations.

The control loop logic block (LOGIC) provides a PWM signal to four internal gate drivers. The gate drivers (HSGD1,2

and LSGD1,2) are used to drive external MOSFETs in an H-Bridge setup.

Once V_{SOFT_START}exceeds V_{SofꢁStartꢁLOFF}or V_FBH-FBLexceeds V_{FBH_FBL_VALID}, TLD5191ES forces CCM regulation mode.

The control loop block diagram displayed in Figure 7 shows a typical constant current application. The voltage across

R_FBsets the output current.

R_FB

I_OUT

V_S

C_OUT

HSGD1

LSGD1

HSGD2

LSGD2

M₁

M₂

M₄

L_OUT

M_ꢀ

FBH

FBL

TLD5191ES

I_SWCS

SWCS

HSGD1

LSGD1

R_SWCS

SLOPE

COMPESANTION

LOGIC

HSGD2

LSGD2

SGND

SET

I_{soft_Start_PU}

SOFT

START

LOGIC

I_{soft_Start_PD}

SOFT

START

COMP

R_COMP

C_COMP

C_{SOFT START}

Figure 7

Regulator block diagram - TLD5191ES

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TLD5191ES

Datasheet

5 Regulator

5.2

Adjustable tofꢀtsars ramp

The sofꢀstart routine limits the current through the inductor and the external MOSFET switches during initialization

to minimize potential overshoots at the output.

The SOFT START pin is also used to implement a fault mask and wait-before-retry time, on rising and falling edge

respectively.

See Figure 8 and Chapter 9.2 for details.

The sof start routine is applied if PWMI is above V_PWMI,ONor PWMI is in a valid range to enable the embedded PWM

engine, if one of the following conditions is verified:

•

afer IDLE to ACTIVE power state transition

afer PWMI has been kept below V_{PWMI,DC_0}for more than t_PWMI,OFF

afer output short to GND detection

The sof start routine is active during the rising and falling edge of V_{SOFT_START}. The sof start timing is defined

by a capacitor placed on the SOFT_START pin and both the sof start pull-up and pull-down current sources

(I_{SofꢁStartꢁPU}, I_{SofꢁStartꢁPD}). Sof start rising edge time is approximately:

C_{Soft_Start}

(1)

t_{Soft_Start, r}

=

V_{Soft_Start_LOFF}

·

I_{Soft_Start_PU}

Note:

Minimum value of sof start capacitor has to be designed such that, during startup, the output voltage

exceeds the short to ground threshold (V_FBH> V_{FBH_S2G_inc}), before the sof start voltage reaches

V_{SOFT_START_LOFF}. Minimum temperature and minimum input voltage shall be considered as worst case

condition for the dimensioning.

The sof start routine limits the inrush current by clamping the COMP pin through a buﬀer like depicted in Figure 7.

Therefore this functionality is eﬀective only when sof start capacitor is suﬀiciently larger than the COMP capacitor

and its eﬀect is visible mainly in buck-boost or boost regulation mode.

If a short circuit on the output is detected the pull-down current source I_{SofꢁStartꢁPD}is activated. This current

discharges the V_{SOFT_START}until V_{SofꢁStartꢁRESET}is reached. Aferwards the pull-up current source I_{SofꢁStartꢁPU}turns

on again only if the PWMI signal is higher than V_{PWMI,DC_0}. If the fault condition hasn't been removed

before V_{SofꢁStartꢁLOFF}is reached, the pull-down current source is reactivated initiating a new cycle.

During sof start rise time switching activity is observed, during the fall time instead the switching activity is halted

like shown in Figure 8. This hiccup mode will continue until the fault is removed.

It is possible to latch the fault condition on the TLD5191ES by sourcing a current higher than I_{SofꢁStartꢁPD}through

an external pull-up resistor connected from IVCC to the SOFT START pin. In this condition the device will restart

regulating only if EN/INUVLO pin is toggled or if PWMI is toggled afer having kept it low for more than t_PWMI,OFF

.

During rising edge of sof start, the internal PWM is extended till one of the 2 following condition is reached:

•

Until V_{SOFT_START}exceeds V_{SofꢁStartꢁLOFF}

Until V_FBH-FBLexceeds V_{FBH_FBL_VALID}

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TLD5191ES

Datasheet

5 Regulator

t_{S2G_mask}

V_FBH

VFBH_S2G

PWMI

SWN

SHORT

DETECTION

ISOFT_START_PU

ISOFT_START_PD

I

SOFT_START

Vsoft_Start_reg

V_{SOFT_START}

Vsoft_Start_LOFF

Vsoft_Start_RESET

Application Normal

Normal

Operation

Vout shorted to GND

Operation

Status

Event

Vout short to GND applied

Event

Vout short to GND removed

Figure 8

Sof start timing diagram on a short to ground detected by the FBH pin

5.3

Switching frequency setup

The switching frequency can be set from 200 kHz to 700 kHz by an external resistor connected from the FREQ pin

to GND. Select the switching frequency with an external resistor according to the graph in Figure 9 or the following

approximated formulas.

−0 . 8

(2)

(ꢀ)

f_SWkHz = 5375 * R_FREQkΩ

R_FREQkΩ = 46023 * f_SWkHz

−1 . 25

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Datasheet

5 Regulator

Figure 9

Switching frequency f_SWversus frequency select resistor to GND R_FREQ

5.4

Operation of 4 switches H-Bridge architecture

Inductor L_OUTconnects in an H-Bridge configuration with 4 external n-channel MOSFETs (M₁, M₂, M_ꢀ& M₄)

•

Transistor M₁and M_ꢀprovides a path between V_INand ground through L_OUTin one direction (Driven by top and

bottom gate drivers HSGD1 and LSGD2)

Transistor M₂and M₄provides a path between V_OUTand ground through L_OUTin the other direction (Driven by top

and bottom gate drivers HSGD2 and LSGD1)

Nodes SWN1, SWN2, voltage across R_SWCSand load current are also monitored by the TLD5191ES

Table 6

4 switches H-Bridge architecture transistor status summary

BOOST mode

ON

BUCK-BOOST mode

BUCK mode

PWM

M1

M2

Mꢀ

M4

PWM

OFF

PWM

OFF

PWM

ON

V_OUT

V_S

M₁

M_ꢀ

HSGD1

HSGD2

L_OUT

SWN₁

SWN₂

LSGD1

LSGD2

M₂

M_ꢀ

R_SWCS

Figure 10

4 switches H-Bridge architecture overview

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Datasheet

5 Regulator

5.4.1

Boost mode (VIN < VOUT)

•

M₁is always ON, M₂is always OFF

Every cycle M_ꢀturns ON first and inductor current is sensed (peak current control)

M_ꢀstays ON until the upper reference threshold is reached across R_SWCS(Energizing)

M_ꢀturns OFF, M4 turns ON until the end of the cycle (Recirculation)

Switches M_ꢀand M₄alternate, behaving like a typical synchronous boost regulator

I_LOUT

V_OUT

V_S

M₁

M₄

Recirculation

ON

HSGD1

LSGD1

HSGD2

LSGD2

L_OUT

SWN₁

SWN₂

Energizing

OFF

M₂

M_ꢀ

t

M1+M3

M1+M4

M1+M3

M1+M4

M1+M3

M1+M4

R_SWCS

Figure 11

4 switches H-Bridge architecture in BOOST mode

Simplified comparison of 4 switches H-Bridge architecture to traditional asynchronous Boost approach

•

M₂is always OFF in this mode (open)

M₁is always ON in this mode (closed connection of inductor to V_IN)

M₄acts as a synchronous diode, with significantly lower conduction power losses (I²x R_DSONvs. 0.7 V x I)

Note:

Diode is source of losses and lower system eﬀiciency!

Figure 12

4 switches H-Bridge architecture in BOOST mode compared to standard async booster

5.4.2

Buck mode (VIN > VOUT)

•

M₄is always ON, M_ꢀis always OFF

Every cycle M₂turns ON and inductor current is sensed (valley current control)

M₂stays ON until the lower reference threshold is reached across R_SWCS(Recirculation)

M₂turns OFF, M₁turns ON until the end of the cycle (Energizing)

Switches M₁and M₂alternate, behaving like a typical synchronous BUCK Regulator

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Datasheet

5 Regulator

I_LOUT

V_OUT

V_S

M₁

M₄

HSGD1

ON

HSGD2

LSGD2

Energizing

L_OUT

SWN₁

SWN₂

Recirculation

LSGD1

OFF

M₂

M_ꢀ

t

M1+M4

M2+M4

M1+M4

M2+M4

M1+M4

M2+M4

R_SWCS

Figure 13

4 switches H-Bridge architecture in BUCK mode

Simplified comparison of 4 switches architecture to traditional asynchronous Buck approach

•

M_ꢀis always OFF in this mode (open)

M₄is always ON in this mode (closed connection inductor to V_OUT

M₂acts as a synchronous diode, with significantly lower conduction losses (I²x R_DSONvs. 0.7 V x I)

)

Figure 14

4 switches H-Bridge architecture in BUCK mode compared to standard async BUCK

5.4.3

Buck-Boost mode (VIN ~ VOUT)

•

When V_INis close to V_OUTthe controller is in Buck-Boost operation

All switches are switching in buck-boost operation. The direct energy transfer from the input to the output (M₁+M₄

= ON) is beneficial to reduce ripple current and improves the energy eﬀiciency of the buck-boost control scheme

•

The two buck boost waveforms and switching behaviors are displayed in Figure 15 below

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Datasheet

5 Regulator

I_LOUT

V_S≤ V_OUT

V_OUT

V_S

M₁

M₄

HSGD1

HSGD2

LSGD2

Energizing

L_OUT

SWN₁

SWN₂

Recirculation

Energizing

LSGD1

M₂

M_ꢀ

t

M1+Mꢀ M1+M4

M1+M4

R_SWCS

I_LOUT

V_S≥ V_OUT

t

M2+M4 M1+M4

M1+M4

Figure 15

4 switches H-Bridge architecture in BUCK_BOOST mode

5.5

Programming output voltage (constant voltage regulation)

For a voltage regulator, the output voltage can be set by selecting the values R_FB1and R_FB2according to the following

equation:

V_{FBH − FBL}

R_FB1

V_OUT

=

− I_FBL· R_FB2+ V_{FBH − FBL}

(4)

V_OUT

FBH

R_FB1

TLD5191ES

I_FBL

FBL

R_FB2

Figure 16

Programming output voltage (Constant voltage regulation)

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Datasheet

5 Regulator

5.6

Electrical characteristics

Table 7

Electrical characteristics

V_IN= 8 V to ꢀ6 V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

Max.

V(FBH-FBL) threshold @ V_{(FBH-FBL)_100}

145.5

150

154.5

mV

µA

V_SET= 2 V; V_FBH= 2 V to PRQ-7ꢀ

analog dimming 100%

60 V;

V(FBH-FBL) threshold @ V_{(FBH-FBL)_10}

analog dimming 10%

10

65

15

20

V_SET= 0.ꢀ2 V; V_FBH= 2 PRQ-74

V to 60 V

1)

FBH Bias current

FBL Bias current

I_FBH

110

155

V

= 7 V;

PRQ-75

FBL

V_{FBH -FBL}= 150 mV

1)

I_FBL

17

110

–

ꢀ0

4ꢀ

1ꢀ0

–

µA

mV

µS

%

V

= 7 V; V_FBH-FBL

=

PRQ-76

PRQ-198

PRQ-77

PRQ-80

PRQ-81

PRQ-82

FBL

150 mV

V(FBH-FBL) valid range

threshold

V_{FBH_FBL_VALID}

IFBx_gm

120

890

91

V_SET> 1.5 V

1)

OUT Current sense

amplifier gain

Maximum BOOST duty

cycle

D_{BOOST_MAX}

89

70

-60

9ꢀ

82

-40

f

= ꢀ00 kHz

sw

1)

Switch peak over current V_{SWCS_boost}

threshold - BOOST

76

mV

Switch peak over current V_{SWCS_buck}

threshold - BUCK

-50

Sof Start pull up current I_{SofꢁStartꢁPU}

22

26

ꢀ2

µA

V_SofꢁStart= 1 V

PRQ-8ꢀ

PRQ-84

Sof Start pull down

I_{SofꢁStartꢁPD}

2.2

2.6

ꢀ.2

current

Sof start latch-OFF

threshold

V_{SofꢁStartꢁLOFF}

1.65

1.75

1.85

V

–

PRQ-85

Sof start reset threshold V_{SofꢁStartꢁRESET}0.1

0.2

2

0.ꢀ

2.1

V

–

PRQ-86

PRQ-87

Sof start voltage during V_{SofꢁStartꢁreg}

1.9

¹⁾No Faults

regulation

Average switching

frequency

f_SW

280

ꢀ00

ꢀ20

kHz

T_J= 25°C;

PRQ-88

R_FREQ= ꢀ7.4 kΩ;

Average value (spread

spectrum modulator

always on)

Gate driver undervoltage V_BST1,2-

ꢀ.4

–

4

V

V_{BST1,2 - VSWN1,2}

decreasing;

PRQ-89

threshold

VSWN1,2_UVth

Diﬀerential signal

(not referred to GND)

(table continues...)

Datasheet

2ꢀ

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

5 Regulator

Table 7

(continued) Electrical characteristics

V_IN= 8 V to ꢀ6 V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

2.ꢀ

Unit

Note or condition

P-Number

Min.

1.4

Max.

ꢀ.7

HSGD1,2 NMOS driver

on-state resistance (Gate

Pull Up)

R_{DS(ON_PU)HS}

Ω

V_{BST1,2 - VSWN1,2}= 5 V; PRQ-90

I_source= 100 mA

HSGD1,2 NMOS driver

on-state resistance (Gate

Pull Down)

R_{DS(ON_PD)HS}

0.6

1.4

0.4

ꢀ80

1.2

2.ꢀ

1.2

–

2.2

ꢀ.7

2.5

–

Ω

V_{BST1,2 - VSWN1,2}= 5 V; PRQ-91

I_sink= 100 mA

LSGD1,2 NMOS driver on- R_{DS(ON_PU)LS}

state resistance (Gate

Pull Up)

Ω

V_IVCC= 5 V; I_source

=

PRQ-92

PRQ-9ꢀ

PRQ-161

100 mA

LSGD1,2 NMOS driver on- R_{DS(ON_PD)LS}

state resistance (Gate

Pull Down)

Ω

V_IVCC= 5 V; I_sink=

100 mA

1)

HSGD1,2 Gate driver

peak sourcing current

I_{HSGD1,2_SRC}

mA

V

=

HSGD1,2 - VSWN1,2

1 V to 4 V;

V_{BST1,2 - VSWN1,2}= 5 V

1)

HSGD1,2 Gate driver

peak sinking current

I_{HSGD1,2_SNK}

410

–

mA

V

- V_SWN1,2

=

PRQ-162

HSGD1,2

4 V to 1 V;

V_BST1,2- V_SWN1,2= 5 V

1)

LSGD1,2 Gate driver peak I_{LSGD1,2_SRC}

ꢀ70

550

–

mA

ns

V

= 1 V to 4 V; PRQ-16ꢀ

= 4 V to 1 V; PRQ-164

PRQ-98

LSGD1,2

sourcing current

V_IVCC= 5 V

1)

LSGD1,2 Gate driver peak I_{LSGD1,2_SNK}

sinking current

–

V

LSGD1,2

V_IVCC= 5 V

1)

LSGD1,2 OFF to HSGD1,2 t_{LSOFF-HSON_delay}15

ON delay

ꢀ0

60

40

75

1)

HSGD1,2 OFF to LSGD1,2 t_{HSOFF-LSON_delay}ꢀ5

ON delay

ns

PRQ-99

1)

Not subject to production test, specified by design

Datasheet

24

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

6 Digital dimming function

6

Digital dimming function

PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shif. PWM dimming achieves

brightness reduction by varying the duty cycle of a constant current in the LED string.

6.1

Description

PWM via direct interface

Pulse width modulated (PWM) signals can be applied to the PWMI pin. The gate drivers are enabled if the signal is on

high level and they are disabled if the the signal is at low level.

The applied PWM signal shall have a frequency above f_PWM,min.

PWMO pin replicates PWMI pin HIGH or LOW state, unless one of the following conditions occur:

•

Output overvoltage event

Output short to ground event

Thermal shutdown

µC

TLD5191ES

PWMI

Digital dimming

Figure 17

Digital dimming overview

PWM dimming in LOW states can be used to suspend the output current for long time intervals in a safe

manner. Indeed a sof start routine is applied once the channel is enabled if the PWM input signal has been kept

below V_{PWMI,DC_0}for at least t_PWMI,OFF.

f_PWMI> PWM_fmin

V_PWMI

V_PWMI,ON

V_PWMI,OFF

t

I_LED

Dim ON

Dim OFF

Dim ON

Dim OFF

V_PWMI< V_{PWMI,DC_0}for at least t_PWMI,OFF

V_PWMI

V_PWMI,ON

V_{PWMI,DC_0}

t

I_LED

Soft Start

Dim OFF

Figure 18

PWMI timings diagrams

Datasheet

25

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

6 Digital dimming function

PWM via embedded PWM engine

If an analog signal in between V_{PWMI,DC_0}and V_{PWMI,DC_100}is applied, embedded PWM is activated.

The embedded PWM engine has an 8 bit resolution with a fixed internal frequency of f_PWM

.

TLD5191ES

Main PWM

generator

IVCC

R_A

R_B

PWMI

PWMO

PWM dimming

generator

I_{PWMI_INT}

Figure 19

Block diagram of embedded PWM generator

Note:

A non linear embedded PWM engine is implemented to guarantee high accuracy for low values of duty

cycle. It helps the headlamp designers to achieve high LED brightness accuracy when dimming to low duty

cycle values. Moreover it helps to produce smooth fading curve, compensating the logarithmic change in the

perceived brightness.

PWMO pin replicates the frequency and duty cycle of the embedded PWM engine, unless one of the following

conditions occur:

•

Output overvoltage event

Output short to ground event

Thermal shutdown

The duty cycle produced by the embedded PWM engine is a function of the voltage applied on PWMI pin.

The duty cycle is quantized with diﬀerent LSB step values in the following V_PWMIranges:

•

0.142% for V_{PWMI,DC_0}≤ V_PWMI≤ 0.2ꢀ⋅V_IVCC

0.284% for 0.2ꢀ⋅V_IVCC< V_PWMI≤ 0.28⋅V_IVCC

0.569% for 0.28⋅V_IVCC< V_PWMI≤ V_{PWMI,DC_100}

and can be calculated by the following formulas:

V

− 0 . 18 · V

PWMI

IVCC

DC % = 63 ·

· 0 . 142 % for

V

≤ V

≤ 0 . 23 · V

(5)

(6)

(7)

PWMI, DC_0

PWMI

IVCC

0 . 05 · V

IVCC

V

− 0 . 23 · V

PWMI

IVCC

DC % = 8 . 95 % + 64 ·

· 0 . 284 % for 0 . 23 · V

· 0 . 569 % for 0 . 28 · V

< V

≤ 0 . 28 · V

≤ V

IVCC

PWMI

IVCC

0 . 05 · V

IVCC

V

− 0 . 28 · V

PWMI

DC % = 27 . 13 % + 128 ·

< V

PWMI

PWMI, DC_100

0 . 1 · V

IVCC

Datasheet

26

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

6 Digital dimming function

PWM

Duty Cycle

100%

27%

9%

V_{PWMI,DC_0}

V_{PWMI,DC_100}

V_PWMI

PWM

OFF

PWM ON

Variable DC

PWM ON

DC = 100%

Figure 20

Analog PWM DC curve

6.2

Electrical characteristics

Table 8

Electrical characteristics

V_IN= 8 V to ꢀ6 V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

Max.

PWMI Turn on threshold V_PWMI,ON

PWMI Turn oﬀ threshold V_PWMI,OFF

PWMI Oﬀ time threshold t_PWMI,OFF

–

2

–

V

–

PRQ-100

PRQ-101

PRQ-199

PRQ-202

0.8

–

V

–

1)

25

–

ms

Hz

1)

PWMI Minimum

frequency

f_PWM,min

75

PWM Engine minimum

voltage

V_{PWMI,DC_0}

0.176* 0.18*

–

V

–

PRQ-102

PRQ-10ꢀ

V_IVCC

PWM Engine maximum

voltage

V_{PWMI,DC_100}

–

0.ꢀ8*

0.ꢀ87*

V_IVCC

–

V_IVCC

PWM Engine DC

PWM_{DC_15%}

f_PWM

14.25

220

15

275

–

15.75

ꢀꢀ0

%

V_PWMI= 0.246*V_IVCC

PRQ-104

PRQ-105

PRQ-106

PWM Engine frequency

Hz

uA

–

1)

PWMI Internal pull down I_{PWMI_INT}

current

1.5

ꢀ.5

V

= 0.2*V_IVCC

PWMI

1)

PWMO Gate driver

sourcing current

I_{PWMO_SRC}

-40

-22

-10

mA

V_PWMO= 2.5 V; V_IVCCPRQ-109

= 5 V

(table continues...)

Datasheet

27

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

6 Digital dimming function

Table 8

(continued) Electrical characteristics

V_IN= 8 V to ꢀ6 V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

10

Max.

40

1)

PWMO Gate driver

sinking current

I_{PWMO_SNK}

t_R,PWMO

25

mA

ns

V

= 2.5 V; V_IVCC= PRQ-110

PWMO

5 V

1)

PWMO Gate driver rise

time

200

150

4.8

450

ꢀ75

5

700

600

5.2

C

= 2.2 nF;

PRQ-111

PRQ-112

PRQ-11ꢀ

gate

V_PWMO= 1 V to 4 V

1)

PWMO Gate driver fall

time

t_F,PWMO

ns

V

C

= 2.2 nF;

gate

V_PWMO= 4 V to 1 V

PWMO Gate driver supply V_PWMO

voltage

–

1)

Not subject to production test, specified by design

Datasheet

28

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

7 Analog dimming

7

Analog dimming

The analog dimming feature allows further control of the output current. This approach is used to:

•

Reduce the default current in a narrow range to adjust to diﬀerent binning classes of the used LEDs

Adjust the load current to enable the usage of one hardware for several LED types where diﬀerent current levels

are required

•

Reduce the current at high temperatures (protect LEDs from overtemperature)

Reduce the current at low input voltages (for example, cranking-pulse breakdown of the supply or power

derating)

7.1

Description

The analog dimming feature is adjusting the average load current level via the control of the feedback error amplifier

voltage (V_FBH-FBL).

The SET pin is used to adjust the mean output current/voltage. The V_SETrange where analog dimming is enabled is

from 200 mV to 1.5 V.

Diﬀerent application scenarios are described in Figure 22.

Using the SET pin to adjust the output current:

For the calculation of the output current IOUT the following equation is used:

V_{FBH − FBL}

I_OUT

=

(8)

R_FB

A decrease of the average output current can be achieved by controlling the voltage at the SET pin (V_SET) between 0.2

V and 1.4 V. The mathematical relation is given in the formula below:

V_SET− 200mV

R_FB· 8

I_OUT

=

(9)

If V_SETis 200 mV (typ.) the LED current is only determined by the internal oﬀset voltages of the comparators.

To assure the switching activity is stopped and I_OUT= 0, V_SEThas to be < 100 mV.

V_FBH-FBL

V_{(FBH-FBL)_100}

0mV

100mV

200mV

1.4V

1.5V

V_SET

Analog Dimming Enabled

Analog Dimming Disabled

Figure 21

Analog dimming overview

Datasheet

29

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

7 Analog dimming

Multi-purpose usage of the analog dimming feature

1.

2.

3.

A μC integrated digital analog converter (DAC) output or a stand alone DAC can be used to supply the SET pin of

the TLD5191ES.

The usage of an external resistor divider connected between IVCC, SET and GND can be chosen for systems

without μC on board. The concept allows control of the LED current by placing low power resistors.

Furthermore a temperature sensitive resistor (thermistor) to protect the LED loads from thermal destruction

can be connected.

4.

5.

If the analog dimming feature is not needed, the SET pin should be connected to the IVCC pin.

Instead of a DAC, the μC can provide a PWM signal and an external R-C filter to produce a constant voltage for

the analog dimming. The voltage level depends on the duty cycle which can be controlled by the μC sofware

afer reading the coding resistor placed on the LED module.

1

3

5

2

D/A output

SET

IVCC

R_A

R_B

µC

TLD5191ES

V_SET

SET

GND

AGND

V_SET

C_filter

4

IVCC

R_A

TLD5191ES

SET

R_B

AGND

V_SET

C_filter

PWM output

SET

µC

TLD5191ES

V_SET

C_filter

GND

AGND

Figure 22

Diﬀerens use cases for analog dimming pin SET

Datasheet

ꢀ0

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

7 Analog dimming

7.2

Electrical characteristics

Table 9

Electrical characteristics

V_IN= 8V to ꢀ6V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

Max.

1)

Source current on SET

I_{SET_source}

–

1

µA

V

= 0.2 V to 1.4 V PRQ-114

SET

1)

Not subject to production test, specified by design

Datasheet

ꢀ1

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

8 Linear regulator

8

Linear regulator

The TLD5191ES features an integrated voltage regulator for the supply of the internal gate driver stages.

8.1

IVCC description

Internal linear voltage regulator supplies the internal gate drivers with a typical voltage of 5 V and current up to I_LIM

.

An external output capacitor with low ESR is required on pin IVCC for stability and buﬀering transient load currents.

During normal operation the external MOSFET switches will draw transient currents from the linear regulator and its

output capacitor. Proper sizing of the output capacitor must be considered to supply suﬀicient peak current to the

gate of the external MOSFET switches. A minimum capacitance value is given in parameter C_IVCC

.

Integrated undervoltage protection for the external switching MOSFET

An integrated undervoltage reset threshold circuit monitors the linear regulator output voltage. If the voltage on IVCC

pin falls below V_{IVCC_RTH,d}the gate drivers are turned OFF.

The undervoltage reset threshold for the IVCC pin helps to protect the external switches from excessive power

dissipation by ensuring the gate drive voltage is suﬀicient to enhance the gate of the external logic level n-channel

MOSFETs.

8.2

Electrical characteristics

Table 10

Electrical characteristics

V_IN= 8V to ꢀ6V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

4.8

Max.

5.2

Output voltage

V_IVCC

5

V

V_VIN= 1ꢀ.5 V;

PRQ-1ꢀ4

0.1 mA ≤ I_IVCC≤ 50 mA

1)

Output current limitation I_LIM

70

–

90

110

ꢀ50

mA

mV

V

= 4 V

PRQ-1ꢀ5

PRQ-1ꢀ6

IVCC

Drop out voltage

V_DR

200

V_VIN= 5 V;

I_IVCC= 10 mA

1) 2)

IVCC buﬀer capacitor

C_IVCC

10

–

µF

V

PRQ-1ꢀ7

PRQ-1ꢀ8

3)

IVCC undervoltage reset V_{IVCC_RTH,d}

switch OFF threshold

ꢀ.7

ꢀ.9

4.1

V

decreasing

IVCC

IVCC undervoltage

hysterisis

V_{IVCC_HYST}

0.ꢀ1

0.ꢀ4

0.ꢀ7

V

V_IVCCincreasing;

PRQ-1ꢀ9

1)

2)

not subject to production test, specified by design

minimum value given is needed for regulator stability; application might need higher capacitance than the

minimum. Use capacitors with LOW ESR

selection of external switching MOSFET is crucial and the V_IVCC,RTH,dmin, as worst case the threshold voltage of

MOSFET must be considered

3)

Datasheet

ꢀ2

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

9 Protection and diagnostic functions

9

Protection and diagnostic functions

Description

9.1

The TLD5191ES has integrated circuits to diagnose and protect against overvoltage, short circuits of the load and

overtemperature faults.

In IDLE state only the overtemperature shut-down is reported according to specifications.

In Figure 2ꢀ a summary of the protection, diagnostic and monitor functions is displayed.

Protection and Diagnostic

EF

OR

Overvoltage

No output current

IVCC OFF

OR

Short at the Load

Device

Overtemperature

OR

Input

Undervoltage

TLD5191ES

Figure 23

Protection and diagnostic overview - TLD5191ES

9.2

Output overvoltage, short circuit protection

V_S

IVCC

C_IVCC

D₁

D₂

V_OUT

V_{VFBH_S2G}

BST1

BST2

R_FB

C_BS1

C_BS2

M₁

M₄

C_OUT

D_LED1

HSGD1

R_VFBH

V_{VFB_OVTH}

R_VFBL

SWN1

L_OUT

D_LEDn

M₂

M_ꢀ

LSGD1

SWCS

TLD5191ES

R_SWCS

SGND

LSGD2

SWN2

HSGD2

VFB

VFBH

VFBL

Figure 24

Protections pins - overview

Datasheet

ꢀꢀ

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

9 Protection and diagnostic functions

9.2.1

Short circuit protection

The device detects a short circuit at the output if this condition is verified:

•

The pin V_FBHfalls below the threshold voltage V_{VFBH_S2G_dec}for at least t_{S2G_mask}

.

During the rising edge of the sofꢀstart the short circuit detection is ignored until V_{SOFT_START_LOFF}

.

The TLD5191ES provides an open-drain status pin, EF, which pulls low when the short circuit is detected.

In case of short circuit detection, the SOFT START pin is used to implement a fault mask and wait-before-retry time,

on rising and falling edge respectively. See Figure 8 for more details.

Note:

If the short circuit condition disappears, the device will re-start with the sof start routine as described

in Chapter 5.2.

9.2.2

Overvoltage protection

TLD5191ES integrates an output overvoltage protection by monitoring the voltage on the VFB pin.

A voltage divider between VOUT, VFB pin and AGND is used to adjust the overvoltage protection threshold.

To fix the overvoltage protection threshold the following equation is used:

R_VFBH+ R_VFBL

V_{OUT_OV_protected}= V_{VFB_OVTH}

·

(10)

R_VFBL

An overvoltage event is detected when V_VFB> V_{VFB_OVTH}and the device reacts as described below:

•

Switching activity is disabled

Mosfet M₁, M_ꢀand M₄are kept OFF while mosfet M₂is kept ON to discharge the inductor current to the output

Once the voltage V_VFB< V_{VFB_OVTH}- V_{VFB_OVTH,HYS}the switching activity is resumed.

In case of overvoltage event at the output, the open-drain status pin EF will toggle to LOW. Afer the overvoltage event

disappeared the device will auto restart and the status pin EF will toggle to HIGH.

Note:

During the overvoltage event the inductor current is discharged to the output, thus an output voltage

increase may be observed based on the L_OUTand C_OUTdesign. The overvoltage threshold must be designed

to avoid to exceed the device maximum absolute ratings.

9.3

Device temperature monitoring

A temperature sensor is integrated on the chip. The temperature monitoring circuit compares the measured

temperature to the shutdown threshold.

If the internal temperature sensor reaches the shut-down temperature T_J,SD, the IVCC regulator is shut down and the

gate driver outputs are set to LOW.

The device exits from thermal shutdown condition with a sof start routine afer the temperature measured by the

integrated sensor decreases below T_J,SD- T_J,SD,hyst.

The TLD5191ES provides an open-drain status pin, EF, which pulls low when the shut-down temperature is reached.

Datasheet

ꢀ4

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

9 Protection and diagnostic functions

T_J

T_J,SD

ΔT

T_J,SD,hyst

t

xSGDx

LED

current

t

EF and IVCC

5 V

t

Device

OFF

Overtemp

Fault

Overtemp

Fault

Overtemp

Fault

Overtemp

Fault

Normal Operation

ON

Figure 25

Device overtemperature protection behavior

9.4

Electrical characteristics

Table 11

Electrical characteristics

V_IN= 8V to ꢀ6V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-Number

Min.

1.9

Max.

2.15

Short to GND exit

threshold

V_{FBH_S2G_inc}

V_{FBH_S2G_dec}

t_{S2G_mask}

T_J,SD

2

V

V_FBHincreasing

PRQ-127

PRQ-128

PRQ-20ꢀ

PRQ-129

PRQ-1ꢀ0

PRQ-1ꢀ1

PRQ-1ꢀ2

Short to GND entry

threshold

1.65

–

1.75

42

1.85

50

V

V_FBHdecreasing

1)

Short to GND masking

time

μs

°C

V

1)

Over temperature

shutdown

160

–

175

10

190

–

Over temperature

shutdown hysteresis

T_J,SD,hyst

VFB over voltage

feedback threshold

V_{VFB_OVTH}

V_{VFB_OVTH,HYS}

1.42

25

1.46

40

1.50

58

–

Output over voltage

feedback hysteresis

mV

Output Voltage

decreasing

(table continues...)

Datasheet

ꢀ5

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

9 Protection and diagnostic functions

Table 11

(continued) Electrical characteristics

V_IN= 8V to ꢀ6V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

2.1

Unit

Note or condition

P-Number

Min.

Max.

EF pin output impedance R_EF

–

kΩ

¹⁾Fault Condition

PRQ-1ꢀꢀ

I = 100 μA

1)

specified by design; not subject to production test

Note:

Integrated protection functions are designed to prevent IC destruction under fault conditions described in

the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions

are not designed for continuous repetitive operation.

Datasheet

ꢀ6

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

10 Infineon FLAT SPECTRUM feature

10

Infineon FLAT SPECTRUM feature

Description

10.1

The Infineon FLAT SPECTRUM feature has the target to minimize external additional filter circuits.

10.2

Spread spectrum

The spread spectrum modulation technique significantly improves the lower frequency range of the spectrum (f < ꢀ0

MHz).

By using the spread spectrum technique, it is possible to optimize the input filter only for the peak limits, and also

pass the average limits (average emission limits are -20 dB lower than the peak emission limits). By using spread

spectrum, the need for low ESR input capacitors is relaxed because the input capacitor series resistor is important for

the low frequency filter characteristic. This can be an economic benefit if there is a strong requirement for average

limits.

The TLD5191ES features a built in spread spectrum function always activated with modulation frequency f_FMand a

frequency deviation f_dev

.

f_SW

f_dev

t

1/f_FM

Figure 26

Spread spectrum overview

10.3

Electrical characteristics

Table 12

Electrical Characteristics

V_IN= 8V to ꢀ6V, T_J= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin; (unless

otherwise specified)

Parameter

Symbol

Values

Typ.

20

Unit

Note or condition

P-Number

Min.

Max.

1)

Frequency deviation

Frequency modulation

1)

f_dev

f_FM

–

%

PRQ-140

PRQ-141

12

kHz

specified by design; not subject to production test

Datasheet

ꢀ7

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

11 Application information

11

Application information

Note:

The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device.

V_S

C_POW

V_IVCC

D_BS2

V_IVCC

D_BS1

VIN

BST1

BST2

C_IN

C_OUT1C_OUT2

R_FB

V_IVCC

M₄

M_ꢀ

M₁

M₂

C_BS1C_BS2

R_OV1

R_OV2

IVCC

HSGD1

SWN1

C_IVCC

R_INUVLO1

LSGD1

SWCS

EN/INUVLO

R_INUVLO2

R_FREQ

R_SWCS

TLD5191ES

FREQ

SGND

C_{SOFT START}

R_COMP

C_COMP

SOFT START

COMP

LSGD2

HSGD2

SWN2

VFB

Analog

dimming

SET

V_IVCC

Digital

dimming

FBH

PWMI

R_PUEF

FBL

M_PWM

To µC

EF

PWMO

AGND

Figure 27

Application drawing - TLD5191ES as current regulator

Datasheet

ꢀ8

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

11 Application information

V_S

C_POW

V_IVCC

D_BS2

V_IVCC

D_BS1

VIN

BST1

BST2

C_IN

C_OUT1C_OUT2

R_FB

V_IVCC

M₄

M_ꢀ

M₁

C_BS1C_BS2

R_OV1

R_OV2

IVCC

HSGD1

SWN1

C_IVCC

R_INUVLO1

M₂

LSGD1

SWCS

EN/INUVLO

R_INUVLO2

R_FREQ

R_SWCS

TLD5191ES

FREQ

SGND

C_{SOFT START}

R_COMP

C_COMP

SOFT START

COMP

LSGD2

HSGD2

SWN2

VFB

Analog

SET

dimming

V_IVCC

R_PWM1

V_IVCC

FBH

PWMI

EF

R_PWM2

R_PUEF

FBL

M_PWM

To µC

PWMO

AGND

Figure 28

Application drawing - TLD5191ES as current regulator with PWM engine

V_S

C_POW

V_IVCC

D_BS2

V_IVCC

D_BS1

VIN

BST1

BST2

C_IN

C_OUT1C_OUT2

M_{PWM_P}

R_FB

V_IVCC

M₄

M_ꢀ

M₁

M₂

C_BS1C_BS2

R_OV1

R_OV2

IVCC

HSGD1

SWN1

C_IVCC

R_INUVLO1

LSGD1

SWCS

EN/INUVLO

R_INUVLO2

R_FREQ

R_SWCS

TLD5191ES

FREQ

SGND

M_{PWM_N}

C_{SOFT START}

R_COMP

C_COMP

SOFT START

COMP

LSGD2

HSGD2

SWN2

VFB

Analog

dimming

SET

V_IVCC

Digital

dimming

FBH

PWMI

R_PUEF

FBL

To µC

EF

PWMO

AGND

Figure 29

Application drawing - TLD5191ES as current regulator with dimming PMOS

Datasheet

ꢀ9

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

11 Application information

V_S

C_POW

V_IVCC

D_BS2

V_IVCC

D_BS1

VIN

BST1

BST2

C_IN

C_OUT1C_OUT2

V_IVCC

PWMI

IVCC

M₄

M_ꢀ

M₁

V_OUT

C_BS2

C_BS1

R_OV1

R_OV2

HSGD1

SWN1

C_IVCC

R_INUVLO1

M₂

LSGD1

SWCS

EN/INUVLO

R_INUVLO2

R_FREQ

C_{SOFT START}

R_COMP

R_SWCS

TLD5191ES

FREQ

SOFT

START

COMP

SGND

LSGD2

C_COMP

HSGD2

SWN2

VFB

Analog

dimming

SET

EF

V_IVCC

FBH

FBL

R_FB1

R_FB2

R_PUEF

To µC

R_FF

C_FF

PWMO

AGND

Figure 30

Application drawing - TLD5191ES voltage mode

Datasheet

40

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

12 Package dimensions

12

Package dimensions

Figure 31

PG-TSDSO-24 package outline

Figure 32

PG-TSDSO-24 package pads and stencil

Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly

products and to be compliant with government regulations the device is available as a green product. Green products

are RoHS-Compliant (i.e Pb free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website: https://www.infineon.com/packages

Datasheet

41

Rev.1.00

2022-02-18

TLD5191ES

Datasheet

Revision history

Document

version

Date of

Description of changes

release

Rev.1.00

2022-02-18

Datasheet release

Datasheet

42

Rev.1.00

2022-02-18

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

Edition 2022-02-18

Published by

Infineon Technologies AG

81726 Munich, Germany

IMPORTANT NOTICE

WARNINGS

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaﬀenheitsgarantie”).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer’s compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer’s products and any use of the product of

Infineon Technologies in customer’s applications.

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies oﬀice.

Except as otherwise explicitly approved by Infineon

Technologies in

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or

any consequences of the use thereof can reasonably

be expected to result in personal injury.

a written document signed by

©

2022 Infineon Technologies AG

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Document reference

IFX-qnq1639124674948

The data contained in this document is exclusively

intended for technically trained staﬀ. It is the

responsibility of customer’s technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to such

application.


型号：	TLD5191ES
厂家：	Infineon
描述：	TLD5191ES 是一款具有内置保护功能的同步 MOSFET H 桥 DC-DC 控制器。该设计有利于以最高的系统效率和最少的外部组件驱动高功率 LED。 TLD5191ES 具有模拟和数字 (PWM) 调光及嵌入式 PWM 发生器。开关频率可在 200 kHz 至 700 kHz 范围内调节。内置扩频开关频率调制和强制连续电流调节模式改善了整体 EMC 行为。此外，电流模式调节方案提供了一个由小型外部补偿元件维持的稳定调节环路。可调软启动功能可限制启动时的电流峰值和电压过冲。 TLD5191ES 适用于汽车环境以及工业和消费类应用（例如无线充电）。开关无线驱动控制器软启动
文件：	总43页 (文件大小：1324K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLD5191ES [INFINEON]

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