TLE4473GV53AUMA2_技术文档

Dual Low Drop Voltage Regulator

TLE 4473 GV53

TLE 4473 GV52

Features

• Output 1: 300 mA, 3.3 V (±3%) or 2.6 V (±3%)

• Output 2: 180 mA, 5 V (±2%)

• Low quiescent current consumption

• Disable function separately for both outputs

• Wide operation range: up to 42 V

• Very low dropout voltage

• 2 independent reset circuits

• Watchdog

• Output protected against short circuit

• Wide temperature range: -40 °C to 150 °C

• Overtemperature protection

• Overload protection

Functional Description

The TLE 4473 is a monolithic integrated voltage regulator with two very low-drop

outputs, Q1 for loads up to 300 mA and Q2 providing a maximum of 180 mA. An input

voltage in the range of 5.6 V ≤ V_I≤ 45 V is transformed to V_Q2= 5.0 V (±2%) and

V_Q1= 3.3 V ±3% (TLE 4473 GV53) or V_Q1= 2.6 V ±3% (TLE 4473 GV52). The device is

also available with dual 5 V output voltage, please refer to the TLE 4473 GV55 data

sheet. Two inhibit pins allow a flexible power management. Both outputs can

independently be enabled or disabled. Thus the current consumption of the application

can be reduced to a minimum. The quiescent current of the TLE 4473 with both outputs

disabled is < 1 µA. The TLE 4473 is designed to supply microprocessor systems and

sensors under the severe conditions of automotive applications and is therefore

equipped with additional protection functions against overload, short circuit and

overtemperature.

The device operates in the wide junction temperature range of -40 °C to 150 °C.

Type

Package

TLE 4473 GV53

TLE 4473 GV52

PG-DSO-12

Data Sheet

1

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

The low drop regulator features a reset with adjustable power on delay for each of the

outputs. In addition the output for the microcontroller supply comes up with a watchdog

in order to supervise a microcontroller.

TLE 4473 GV53 / TLE 4473 GV52

e. g. µC I/O

Q2

4

2

7

I

V_Bat

or Sensor

Supply

10

µF

Overtemperature

Shutdown

4.7 kΩ

Current and

Saturation

Control,

Bandgap

RO2

Reset

Overcurrent

Protection

Reference

Generator

?1

D2 10

9

INH2

Inhibit

µC

100 nF

Q1

5

µC Core

Supply

22 µF

or

10 µF

4.7 kΩ

Current and

Saturation

Control,

RO1

WI

3

1

Reset

µC

Generator

Reset

Overcurrent

Protection

Watchdog

(from µC)

8

INH1

Watchdog

Inhibit

Ignition

D1 11

100 nF

6, 12

GND

AEB03507.VSD

Figure 1

Block Diagram with Typical External Components

Data Sheet

2

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Reset and Watchdog Behaviour:

The reset output RO1 is in high-state if the voltage on the delay capacitor C_D1is greater

or equal V_DL1. The delay capacitor C_D1is charged with the current I_DC1for output voltages

greater than the reset threshold V_RT1. If the output voltage drops below V_RT1(“reset

condition”), the delay capacitor C_D1will be discharged rapidly. If V_D1reaches V_DL1, the

reset output RO1 is set to low.

At power-on, the charging process of C_D1starts from 0 V, which leads to the equation

C

_D1× V_DU1

I_DC1

t_{D, on}= ----------------------------

(1)

for the power-on reset delay time.

When the voltage at the delay capacitor has reached V_DU1and RO1 was set to high, the

watchdog circuit is enabled and discharges C_D1with the constant current I_DD1

.

If there is no rising edge observed at the watchdog input, C_D1will be discharged down to

V_DL1, where the reset output RO1 will be set to low and C_D1will be charged again with

the current I_DC1until V_D1reaches V_DU1and reset will be set high again.

If a watchdog pulse (rising edge at watchdog input WI) occurs during the discharge

period, C_D1is charged again and the reset output stays high. After V_D1has reached V_DU1

,

the periodical cycle starts again.

The watchdog timing is shown in Figure 2. The maximum duration between two

watchdog pulses corresponds to the minimum watchdog trigger time T_WI,tr. Higher

capacitances on pin D1 result in larger watchdog trigger time:

T_WI,tr

= 0.42 ms/nF × C_D1

(2)

max

If the output voltage Q2 decreases below V_RT2, the external capacitor C_D2is discharged.

When the voltage at this capacitor drops below V_DL2, a reset signal is generated at pin

11 (RO2), i.e. the reset output is set to low-level. If the output voltage rises above the

reset threshold, C_D2will be charged with the constant current I_DC2. After the power-on-

reset time, the voltage at the capacitor reaches V_DU2and the reset output will be set to

high again. The value of the power-on-reset time can be set within a wide range

depending of the capacitance of C_D2using Equation (1) analogous for Q2.

Data Sheet

3

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

V_W

Ι

t

V

Ι

V_Q

T_{WD, p}

V_D1

T_{WI, tr}

V_DU1

V_DL1

t_{WD, L}

V_WO

(V_DU1- V_DL1

)

(V_DU1

-

V_DL1) (Ι _DC1

Ι _DC1Ι _DD1

+

Ι _DD1

)

(V_DU1- V_DL1)

T_{WI, tr}

=

C_D1

;

T_{WD, p}

=

C_D1

;

t_{WD, L}

=

C_D1

Ι _DD1

x

Ι _DC1

AED03099_4473gv53

Figure 2

Watchdog Timing Schedule

Data Sheet

4

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

WI

RO2

RO1

Q2

1

2

3

4

5

6

12

11

10

9

GND

D1

D2

INH2

INH1

I

Q1

8

N.C.

7

AEP03318_4473gv53.VSD

Pin 6 and heat slug should be connected to GND

Figure 3

Table 1

Pin Configuration TLE 4473 GV53, TLE 4473 GV52 (top view)

Pin Definitions and Functions (TLE 4473 GV53, TLE 4473 GV52)

Pin No. Symbol Function

1

WI

Watchdog input; input for watchdog pulses, positive edge

triggered

2

3

4

RO2

RO1

Q2

Reset output for Q2; open collector output

Reset and watchdog output for Q1; open collector output

Output voltage 2 (5 V); block to GND with a capacitor C_Q2≥ 22 µF,

ESR < 5 Ω at 10 kHz or C_Q2≥ 10 µF, ESR < 4 Ω at 10 kHz

5

Q1

Output voltage 1 (3.3 V/2.6 V); block to GND with a capacitor

C_Q1≥ 10 µF, ESR < 5 Ω at 10 kHz

6

7

N.C.

I

Not connected; connect to GND

Input voltage; block to GND directly at the IC with a ceramic

capacitor.

8

INH1

INH2

D2

Inhibit input 1; low level at INH2 and INH1 disables Q2 and Q1

Inhibit input 2; low level disables Q2

9

10

11

Reset Delay 2; connect a capacitor to set reset delay for Q2

D1

Reset Delay 1; connect a capacitor to GND to set reset delay and

watchdog timing for Q1

12

GND

Ground

Heatsink N. C.

Not connected; connect to GND

Data Sheet

5

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Table 2

Absolute Maximum Ratings

-40 °C < T_j< 150 °C

Parameter

Symbol Limit Values Unit

Remarks

Min.

Max.

Input I

Voltage

V_I

I_I

-42

–

45

–

V

–

Current

mA

Internally limited

Stand-by Output Q2

Voltage

V_Q2

I_Q2

-0.3

–

18

–

V

–

Current

mA

Internally limited

Main Output Q1

Voltage

V_Q1

I_Q1

-0.3

–

18

–

V

–

Current

mA

Internally limited

Inhibit Input INH1

Voltage

V_INH1

I_INH1

-42

-2

45

2

V

–

Current

mA

Inhibit Input INH2

Voltage

V_INH2

I_INH2

-42

-2

45

2

V

–

Current

mA

Reset Output RO1

Voltage

V_RO1

I_RO1

-0.3

–

18

–

V

–

Current

mA

Internally limited

Reset Output RO2

Voltage

V_RO2

I_RO2

-0.3

–

18

–

V

–

Current

mA

Internally limited

Reset Delay D1

Voltage

V_D1

I_D1

-0.3

-5

7

5

V

–

Current

mA

Reset Delay D2

Voltage

V_D

I_D

-0.3

-5

7

5

V

–

Current

mA

Data Sheet

6

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Table 2

Absolute Maximum Ratings (cont’d)

-40 °C < T_j< 150 °C

Parameter

Symbol Limit Values Unit

Remarks

Min.

Max.

Watchdog Input WI

Voltage

V_RADJ

I_RADJ

-0.3

-5

7

5

V

–

Current

mA

Temperatures

Junction temperature

Storage temperature

ESD Protection

T_j

-40

-50

150

°C

–

T_stg

Electrostatic Discharge

Voltage

V_ESD

–2

2

kV

Human Body Model

Note: Maximum ratings are absolute ratings; exceeding any one of these values may

cause irreversible damage to the integrated circuit.

Data Sheet

7

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Table 3

Operating Range

Symbol Limit Values Unit

Parameter

Remarks

Min.

5.6

Max.

42

Input voltage

V_I

T_j

V

Q1 & Q2

4.5

42

V

only Q1 regulating

–

Junction temperature

-40

150

°C

Thermal Resistances PG-DSO-12

Junction pin

R_thj-pin

–

3

K/W

–

Junction ambient

R_thj-a

115

PCB Heat Sink

Area 0 mm^{2 1)}

Junction ambient

–

100

60

K/W

PCB Heat Sink

Area 100 mm^{2 1)}

PCB Heat Sink

Area 300 mm²

1)

48

PCB Heat Sink

Area 600 mm^{2 1)}

1) Package mounted on PCB 80 × 80 × 1.5 mm³; 35 µ Cu; 5 µ Sn; zero airflow.

Note: In the operating range the functions given in the circuit description are fulfilled.

Integrated protection functions are designed to prevent IC destruction under fault

conditions. Protection functions are not designed for repetitive operation.

Data Sheet

8

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Electrical Characteristics

V_I1=13.5 V; V_INH1=V_INH2= 5V; – 40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

min. typ. max.

REGULATOR 2:

Output Q2

Output voltage

V_Q2

I_Q2

4.90 5.0

200 300

5.10

600

V

1 mA < I_Q2< 180 mA;

6 V < V_I< 28 V

Output current

limitation

mA V_Q2= 4.5 V

Output drop voltage; V_DRQ2

_DRQ2= V_I2– V_Q2

–

300

mV I_Q2= 100 mA; ¹⁾

V

Load regulation

Line regulation

∆V_Q2,Lo

∆V_Q2,Li

–

15

5

50

20

mV 1 mA < I_Q2< 200 mA;

mV I_Q2= 1 mA;

6 V < V_I< 28 V

PSRR

Power supply ripple

rejection

–

65

–

dB

f_r= 100 Hz;

V_r= 1 V_pp

Current Consumption

Quiescent current;

stand-by

I_q= I_I– I_Q2

I_q

–

165

205

180

210

µA

TLE 4473 GV52;

I_Q2= 500 µA; T_j= 25 °C;

V_INH1< V_{INH1 OFF}(Q1 off)

TLE 4473 GV52;

I_Q2= 500 µA; T_j= 85 °C;

V_INH1< V_{INH1 OFF}(Q1 off)

TLE 4473 GV53;

I_Q2= 500 µA; T_j= 25 °C;

V_INH1< V_{INH1 OFF}(Q1 off)

TLE 4473 GV53;

I_Q2= 500 µA; T_j= 85 °C;

V_INH1< V_{INH1 OFF}(Q1 off)

–

235

µA

I_Q2= 500 µA;

V_INH1< V_{INH1 OFF}(Q1 off)

Data Sheet

9

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Electrical Characteristics (cont’d)

V_I1=13.5 V; V_INH1=V_INH2= 5V; – 40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

min. typ. max.

Current Consumption (cont’d)

Quiescent current;

stand-by

I_q

5

mA I_Q2= 100 mA;

V_INH1< V_{INH1 OFF}(Q1 off)

I_q= I_I– I_Q2

Quiescent current;

inhibited

I_q

–

1

µA

V_INH1=V_INH2= 0V;

T_J< 85°C

Inhibit Input INH2

Turn-on Voltage

Turn-off Voltage

H-input current

L-input current

V_{INH2 ON}

–

2.3

–

V

V_Q2on

V_Q2off

V_{INH2 OFF}0.8

–

V

I_{INH2 ON}

– 1

0.5

0.1

3

µA

V_INH2= 5 V

I_{INH2 OFF}

1

0 V < V_INH2< 0.8 V

Reset Timing D2

Charge current

I_DC2

5.0

1.6

9.0

1.8

13.0 µA

V_D2= 0.7 V

Upper timing

threshold

V_DU2

2.2

V

–

Lower timing

threshold

V_DL2

0.3

0.45 0.6

100

V

–

Saturation Voltage

Reset delay time

V_D2,SAT

T_RD2

mV V_Q2< V_RT2

12

–

20

28

10

ms

C_D2= 100 nF

Reset reaction time T_rr

µs

Data Sheet

10

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Electrical Characteristics (cont’d)

V_I1=13.5 V; V_INH1=V_INH2= 5V; – 40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

min. typ. max.

Reset Output RO2

Reset switching

threshold

V_RT2

4.5

–

4.65 4.8

1.4

V

–

Reset output current I_RO2

–

mA Collector current of RO1,

power good, reset still

delayed.

V_Q2=5V, V_D2=0V,V_RO2=0.3V

Reset output low

voltage

V_RO2L

–

0.15 0.3

V

V_Q2≥ 1 V, V_D2=0V,

_RO2= 0.5mA

I

Reset high voltage V_RO2H

4.5

–

R_RO2,ext=4.7kΩ

REGULATOR 1:

Output Q1

Output voltage

V_Q12

I_Q1

3.20 3.3

3.40

V

TLE 4473 GV53

1 mA < I_Q1< 300 mA;

4.5 V < V_I< 28 V

Output voltage

2.52 2.60 2.68

TLE 4473 GV52

1 mA < I_Q1< 300 mA;

4.5 V < V_I< 28 V

Output current

limitation

350 500

600

mA V_Q1= 3.0 V

(TLE 4473 GV53);

V_Q1= 2.3 V

(TLE 4473 GV52)

Load regulation

Line regulation

∆V_Q1,Lo

∆V_Q1,Li

–

5

50

20

mV 5 mA < I_Q1< 300 mA;

mV I_Q1= 5 mA;

6 V < V_I< 28 V

Power-Supply-

Ripple-Rejection

–

65

–

dB

f_r= 100 Hz;

V_r= 1V_pp

PSRR

Data Sheet

11

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Electrical Characteristics (cont’d)

V_I1=13.5 V; V_INH1=V_INH2= 5V; – 40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

min. typ. max.

Current Consumption

Quiescent current;

I_q= I_I– I_Q1– I_Q2

I_q

–

200

210

7

265

280

20

µA

TLE 4473 GV52;

I_Q1= 500 µA;

Q1 on; Q2 off; T_j< 85°C

TLE 4473 GV53;

I_Q1= 500 µA;

Q1 on; Q2 off; T_j< 85°C

mA I_Q1= 300 mA

I_Q2= 500 µA,

V_Q1& V_Q2on

250

500

µA

I_Q2= I_Q1= 500 µA;

V_Q1& V_Q2on

Inhibit Input INH1

Turn-on Voltage

Turn-off Voltage

H-input current

L-input current

V_{INH1 ON}

–

2.3

–

V

V_Q1on

V_{INH1 OFF}0.8

–

V

V_Q1off

I_{INH1 ON}

– 1

0.5

0.1

3

µA

V_INH1= 5 V

0 V < V_INH1< 0.8 V

I_{INH1 OFF}

1

Watchdog and Reset Timing D1

Charge current

I_DC1

I_DD1

V_DU1

3.0

1.1

0.7

7.0

1.5

1.1

11.0 µA

V_D1= 0.7 V

–

Discharge current

3.7

1.6

µA

Upper timing

threshold

V

Lower timing

threshold

V_DL1

0.2

0.35 0.6

12

V

–

Data Sheet

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Electrical Characteristics (cont’d)

V_I1=13.5 V; V_INH1=V_INH2= 5V; – 40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

min. typ. max.

Watchdog and Reset Timing D1 (cont’d)

Saturation Voltage

V_D1,SAT

100

40

mV V_Q1< V_RT2

Watchdog trigger

time

T_WI,tr

24

32

17

ms

C_D1= 100 nF

Reset delay time

T_RD1

11

–

23

ms

C_D1= 100 nF

Reset reaction time T_rr

5.0

µs

Reset Output RO1

Reset switching

threshold

V_RT1

2.97 3.08 3.18

2.34 2.42 2.50

V

TLE 4473 GV53

TLE 4473 GV52

Reset threshold

headroom

V_R1HEAD

100

80

–

mV TLE 4473 GV53

Reset threshold

headroom

–

mV TLE 4473 GV52

Reset output current I_RO1

1.4

mA Collector current of RO1,

power good, reset still

delayed.

V_Q1= 3.30 V

(TLE 4473 GV53),

V_Q1= 2.60 V

(TLE 4473 GV52);

V_Q2=5.0 V;

V_D1=0 V,V_RO1=0.3 V

Reset output low

voltage

V_RO1L

V_RO1H

–

0.1

0.3

–

V

V_Q1≥ 1 V, V_D1=0V,

_RO1=0.5mA

I

Reset output high

voltage

2.45 –

3.15 –

R_RO1,ext=4.7kΩ connected

to Q1;TLE 4473 GV52

Reset output high

voltage

–

R_RO1,ext=4.7kΩ connected

to Q1;TLE 4473 GV53

1) Drop voltage = V_I– V_Q(measured when the output voltage has dropped 100 mV from the nominal value

obtained at 13.5 V input)

Data Sheet

13

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Package Outlines

1)

±0.1

7.5

B

+0.075

-0.035

0.25

(0.2)

0.1

C

±0.15

0.7

±0.1

12x

7.8

(Heatslug)

±0.3

10.3

0.1

C

0.25 B

Seating Plane

Bottom View

1)

±0.1

6.4

A

7

12

7

1

6

1

6

Index Marking

0.4^+0.13

Heatslug

1

12x

0.25

±0.1

5.1

M

C A B

5 x 1 = 5

1) Does not include plastic or metal protrusion of 0.15 max. per side

PG-DSO-12-4, -5, -8, -11, -12, -16-PO V04

Figure 4

PG-DSO-12 (Plastic Dual Small Outline)

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products

and to be compliant with government regulations the device is available as a green

product. Green products are RoHS-compliant (i.e Pb-free finish on leads and suitable for

Pb-free soldering according to IPC/JEDEC J-STD-020).

Data Sheet

14

Rev. 1.1, 2008-09-19

TLE 4473 GV53

TLE 4473 GV52

Revision History

Version

Date

Changes

Rev. 1.1

2008-19-09 Initial version of RoHS-compliant derivate of TLE 4473 GV53

and TLE 4473 GV52

Page 1: AEC certified statement added

Page 1 and Page 14: RoHS compliance statement and

Green product feature added

Page 1 and Page 14: Package changed to RoHS compliant

version

Legal Disclaimer updated

Rev. 1.0

2004-07-14 Initial version

You can find all of our packages, sorts of packing and others in our

Infineon Internet Page “Products”: http://www.infineon.com/products.

Dimensions in mm

SMD = Surface Mounted Device

Data Sheet

15

Rev. 1.1, 2008-09-19

Edition 2008-09-19

Published by

Infineon Technologies AG

81726 München, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values

stated herein and/or any information regarding the application of the device, Infineon Technologies hereby

disclaims any and all warranties and liabilities of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.


型号：	TLE4473GV53AUMA2
厂家：	Infineon
描述：	Fixed Positive LDO Regulator, 2 Output, 3.3V1, 5V2, PDSO12, GREEN, PLASTIC, SOP-12 光电二极管输出元件调节器
文件：	总16页 (文件大小：291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLE4473GV53AUMA2 [INFINEON]

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