TLE6285GDUMA1_技术文档

Data Sheet, Rev. 2.0, April 2005

TLE 6285

LIN-Transceiver with Voltage Regulator

Automotive Power

N e v e r s t o p t h i n k i n g .

Edition 2005-04-18

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

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Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

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approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

LIN-Transceiver with Voltage Regulator

TLE 6285

Features

• Single-wire transceiver, suitable for LIN protocol

• Transmission rate up to 20 kBaud

• Compatible to LIN specification 1.3, 2.0

• Compatible to ISO 9141 functions

• Low current consumption in sleep mode

• Control output for voltage regulator

• LIN bus, short circuit proof to ground and battery

• Integrated 5V ±2%, low drop voltage regulator

• 150 mA output current capability

P-DSO-16-9, -11

• Adjustable reset threshold

• Overtemperature protection

• Wide temperature range

• Suitable for use in automotive electronics

Description

The TLE 6285 is a single-wire transceiver with a LDO. It is a chip by chip integrated

circuit in a P-DSO-16-11 package. It works as an interface between the protocol

controller and the physical bus. The TLE 6285 is especially suitable to drive the bus line

in LIN systems in automotive and industrial applications. Further it can be used in

standard ISO9141 systems.

In order to reduce the current consumption the TLE 6285 offers a sleep operation mode.

In this mode a voltage regulator can be controlled in order to minimize the current

consumption of the whole application. The on-chip voltage regulator (VR) is designed for

this application but it is also possible to use an external voltage regulator. A wake-up

caused by a message on the bus enables the voltage regulator and sets the RxD output

low until the device is switched to normal operation mode. To achieve proper operation

of the µC, the device supplies a reset signal. The reset delay time is selected application

specific by an external capacitor. The reset threshold is adjustable.

The TLE 6285 is designed to withstand the severe conditions of automotive applications.

Type

Ordering Code

Package

TLE 6285 G

Q67065-A7059

P-DSO-16-11

Data Sheet

3

Rev. 2.0, 2005-04-18

TLE 6285

T L E 6 2 8 5 G

(P -D S O -1 6 -1 1 )

G N D

R D

G N D

IN H I

R O

1

2

3

4

5

6

7

8

1 6

1 5

1 4

1 3

1 2

1 1

1 0

9

L e a d fra m e

C h ip :

V o lta g e

R _{T h}

R e g u la to r

V _{C C O}

IN H O

R x D

V _{B A T}

B u s

C h ip :

T x D

T ra n s c e iv e r

E N L IN

G N D

V _{C C I}

G N D

A E P 0 3 4 5 0 .V S D

Figure 1

Pin Configuration (top view)

Data Sheet

4

Rev. 2.0, 2005-04-18

TLE 6285

Table 1

Pin Definitions and Functions

Pin No. Symbol Function

1, 8, 9,

16

GND

INHI

RO

Ground; place to cooling tabs to improve thermal behavior

2

Inhibit Voltage Regulator Input; TTL compatible, HIGH active

(HIGH switches the VR on); connect to V_BATif not needed

3

Reset Output; open collector output connected to the output via

a resistor of 20 kΩ

4

5

6

7

V_CCO

INHO

RxD

5-V Output; connected to GND with 22 µF capacitor, ESR < 5Ω

Inhibit LIN Output; to control a voltage regulator

Receive Data Output; Integrated pull-up, LOW in dominate state

ENLIN

Enable LIN Input; integrated 30 kΩ pull-down, transceiver in

normal operation mode when HIGH

10

11

12

V_CCI

TxD

BUS

5-V Supply Input; V_CCinput to supply the LIN transceiver

Transmit Data Input; internal pull-up, LOW in dominant state

LIN BUS Output/Input; internal 30 kΩ pull-up to V_S, LOW in

dominant state

13

14

15

V_BAT

RTh

RD

Battery Supply Input; a reverse current protection diode is

required, block GND with 100 nF ceramic capacitor and 22 µF

capacitor

Reset Threshold; internal defined typical 4.6 V, adjustable down

to 3.5 V according to the voltage level on this pin; connect to GND

if not needed

Reset Delay; connected to ground via external delay capacitor

Data Sheet

5

Rev. 2.0, 2005-04-18

TLE 6285

Functional Block Diagram

13

5

V_Bat

INHO

10

V_CCI

7

Mode Control

ENLIN

30 kΩ

Output

Stage

Driver

30 k Ω

12

Bus

Temp.-

Protection

11

TxD

Receiver

6

RxD

GND

TLE 4299

4

13

V_Bat

V_CCO

R_SO

Band-Gap

Reference

Current & Saturation

Control

R_RO

2

Inhibit

INHI

Control

3

RO

Reference

Reset

14

Control

R_Th

15

RD

GND

AEB03449.VSD

Figure 2

Block Diagram

Data Sheet

6

Rev. 2.0, 2005-04-18

TLE 6285

S ta rt U p

P o w e r U p

N o rm a l M o d e

V _{C C}

O N

E N LIN

H igh

IN H O

H ig h

E N L IN

H ig h

S ta n d -B y

E N L IN

L o w

V _{C C}

O N

R x D

E N L IN IN H O

L ow H ig h

1)

3)

L o w

H ig h

E N L IN

H ig h

O N )

(

V _{C C I}

W ak e U p

t

> t_{W A K E}

S le e p M o d e

V _{C C}

E N LIN

L ow

IN H O

2 )

F lo a tin g O F F

1 ) A fte r w a k e -u p v ia bu s

2 ) O N w h e n IN H O n o t c o n n e cte d to IN H I

3 ) A fte r s tart u p

A E A 034 51.V S D

Figure 3

Operation Mode State Diagram

Operation Modes

In order to reduce the current consumption the TLE 6285 offers a sleep operation mode.

This mode is selected by switching the enable input ENLIN low (see Figure 3,

Operation Mode State Diagram). In the sleep mode a voltage regulator can be

controlled via the INHO output in order to minimize the current consumption of the whole

application. A wake-up caused by a message on the communication bus automatically

enables the voltage regulator by switching the INHO output high. In parallel the wake-up

is indicated by setting the RxD output low. When entering the normal mode this wake-up

flag is reset and the RxD output is released to transmit the bus data.

Data Sheet

7

Rev. 2.0, 2005-04-18

TLE 6285

In case the voltage regulator control input is not connected to INH output or the

microcontroller is active respectively, the TLE 6285 can be set in normal operation mode

without a wake-up via the communication bus.

LIN Transceiver

The LIN Transceiver has already a pull-up resistor of 30 kΩ as termination implemented.

There is also a diode in this path, to protect the circuit from feedback of voltages from

the bus line to the power supply. To configure the TLE 6285 as a master node, an

additional external termination resistor of 1 kΩ is required. To avoid reverse currents

from the bus line into the battery supply line in case of an unpowered node, it is also

recommended to place a diode in series to the external pull-up. For small systems (low

bus capacitance) the EMC performance of the system is supported by an additional

capacitor of at least 1 nF in the master node (see Figure 5, Application Example).

An capacitor of 10 µF at the supply voltage input V_Sbuffers the input voltage. In

combination with the required reverse polarity diode this prevents the device from

detecting power down conditions in case of negative transients on the supply line.

Input Capacitor

The input capacitor C_Iis necessary for compensation of line influences. Using a resistor

of approx. 1 Ω in series with C_I, the oscillating circuit consisting of input inductivity and

input capacitance can be damped. The output capacitor is necessary for the stability of

the regulating circuit. Stability is guaranteed at values ≥ 22 µF and an ESR of ≤ 5 Ω

within the operating temperature range. For small tolerances of the reset delay the

spread of the capacitance of the delay capacitor and its temperature coefficient should

be noted.

Voltage Regulator

The TLE 6285 incorporates a PNP based very low drop linear voltage regular. It

regulates the output voltage to V_CC= 5 V for an input voltage range of 6 V ≤ V_I≤ 35V.

The control circuit protects the device against potential caused by damages overcurrent

and overtemperature.

The internal control circuit achieves a 5 V output voltage with a tolerance of ±2% in the

temperature range of T_j= -40 to 125 °C.

The device includes a power on reset and an under voltage reset function with adjustable

reset delay time and adjustable reset switching threshold as well as a sense control/early

warning function. The device includes an inhibit function to disable it when the ECU is

not used for example while the motor is off.

The reset logic compares the output voltage V_CCto an internal threshold. If the output

voltage drops below this level, the external reset delay capacitor C_Dis discharged. When

V_Dis lower than V_LD, the reset output RO is switched Low. If the output voltage drop is

Data Sheet

8

Rev. 2.0, 2005-04-18

TLE 6285

very short, the V_LDlevel is not reached and no reset-signal is asserted. This feature

avoids resets at short negative spikes at the output voltage e.g. caused by load changes.

As soon as the output voltage is more positive than the reset threshold, the delay

capacitor is charged with constant current. When the voltage reaches V_UDthe reset

output RO is set High again.

The reset threshold is either the internal defined V_RTvoltage (typical 4.6 V) or can be

lowered by a voltage level at the RTh input down to 3.5 V. The reset delay time and the

reset reaction time are defined by the external capacitor C_D. The reset function is active

down to V_I= 1 V.

The device is capable to supply 150 mA. For protection at high input voltage above 25 V,

the output current is reduced (SOA protection).

Reset

The power on reset feature is necessary for a defined start of the microprocessor when

switching on the application. For the reset delay time after the output voltage of the

regulator is above the reset threshold, the reset signal is set High again. The reset delay

time is defined by the reset delay capacitor C_RDat pin RD (refer to Figure 4 and

Figure 5).

The undervoltage reset circuitry supervises the output voltage. In case V_Qdecreases

below the reset threshold the reset output is set LOW after the reset reaction time. The

reset LOW signal is generated down to an output voltage V_Qto 1 V. Both the reset

reaction time and the reset delay time is defined by the capacitor value.

The power on reset delay time is defined by the charging time of an external delay

capacitor C_D.

C_D= (t_d× I_D) / ∆V

(1)

Definitions:

• C_D= reset delay capacitor

• t_d= reset delay time

•

∆V = V_UD, typical 1.8 V for power up reset

•

∆V = V_UD- V_LD, typical 1.35 V for undervoltage reset

• I_D= charge current typical 6.5 µA

For a delay capacitor C_D= 100 nF the typical power on reset delay time is 28 ms.

The reset reaction time t_RRis the time it takes the voltage regulator to set reset output

LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs

for delay capacitor of 100 nF. For other values for C_Dthe reaction time can be estimated

using the following equation:

t_RR= 10 ns / nF × C_D

(2)

Data Sheet

9

Rev. 2.0, 2005-04-18

TLE 6285

The reset output is an open collector output with a pull-up resistor of typical 20 kΩ to Q.

An external pull-up can be added with a resistor value of at least 5.6 kΩ.

In addition the reset switching threshold can be adjusted by an external voltage divider.

The feature is useful for microprocessors which guarantee safe operation down to

voltages below the internally set reset threshold of 4.65 V typical.

If the internal used reset threshold of typical 4.65 V is used, the pin RTh has to be

connected to GND.

If a lower reset threshold is required by the system, a voltage divider defines the reset

threshold V_Rthbetween 3.5 V and 4.60 V:

V_Rth= V_{RADJ TH}× (R₁+ R₂) / R₂

(3)

V_{RADJ TH}is typical 1.36 V.

Data Sheet

10

Rev. 2.0, 2005-04-18

TLE 6285

Table 2

Absolute Maximum Ratings

Symbol Limit Values Unit

Parameter

Remarks

Min.

Max.

Voltages

Supply voltage

Battery supply voltage

Bus input voltage

V_CC

V_S

-0.3

-20

6

V

–

40

32

40

–

V_bus

V_I

–

-20

t < 1 s

Logic voltages at EN, TxD,

RxD

-0.3

V_CC

+ 0.3

0 V < V_CC< 5.5 V

Input voltages at INHO

V_INHO

-0.3

V_S

V

–

+ 0.3

Output current at INHO

Reset output voltage

Reset delay voltage

I_INHO

V_R

–

20

7

mA

V

–

-0.3

-40

-0.3

-10

-4

V_D

7

V

Output voltage on V_CCO

INHI input voltage

V_Q

7

V

V_INH

V_Th

I_Th

40

7

V

Reset Threshold voltage

Reset Threshold current

V

10

4

mA

kV

Electrostatic discharge

V_ESD

human body model

voltage at V_S, Bus

(100 pF via 1.5 kΩ)

Electrostatic discharge

voltage

V_ESD

-2

2

kV

human body model

(100 pF via 1.5 kΩ)

Temperatures

Junction temperature

T_j

-40

150

°C

–

Note: Maximum ratings are absolute ratings; exceeding any one of these values may

cause irreversible damage to the integrated circuit.

Data Sheet

11

Rev. 2.0, 2005-04-18

TLE 6285

Table 3

Operating Range

Symbol Limit Values Unit

Parameter

Remarks

Min.

4.5

6

Max.

5.5

Supply voltage

V_CC

V_S

T_j

V

–

Battery Supply Voltage

Junction temperature

35

V

-40

150

°C

Thermal Shutdown (junction temperature)

Thermal shutdown temp.

Thermal shutdown hyst.

Thermal Resistances

Junction ambient

T_jSD

150

–

170

10

190

–

°C

∆T

K

R_thj-a

–

80

K/W

PCB heat sink area

300mm²

Data Sheet

12

Rev. 2.0, 2005-04-18

TLE 6285

Table 4

Electrical Characteristics

V_CC= 5V; V_S= 13.5V; R_L= 500 Ω; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Sym-

bol

Limit Values

Unit Remarks

Min. Typ. Max.

Current Consumption

Current consumption at

I_Bat

I_CCI

I_Bat

I_CCI

–

1.1

1.9

0.4

20

3

mA recessive state;

V_Bat(LIN + Voltage

INHI = INHO = HIGH;

_TxD= V_CC

mA dominant state;

INHI = INHO = HIGH;

_TxD= V_CC

Regulator)

V

4

V

Current consumption at

0.7

0.8

40

10

mA recessive state;

LDO sleep;

V_CCI(LIN only)

V

_TxD= V_CC

mA dominant state;

LDO sleep;

V

_TxD= 0 V

Current consumption

sleep mode

(LIN + Voltage Regulator)

µA

sleep mode;

INHI = INHO = LOW;

(LIN only)

sleep mode;

INHI = INHO = LOW

Current consumption

LDO (Voltage Regulator,

LIN in sleep mode)

I_Bat

–

170 500

µA

I

_CCO= 10 mA;

_CCO= 50 mA;

0.7

2

mA

Enable Input (pin ENLIN)

HIGH level input voltage V_EN,on

–

2.8

0.7 × V

normal mode

threshold

V_CC

LOW level input voltage V_EN,off

0.3 × 2.2

–

V

low power mode

threshold

V_CC

EN input hysteresis

V_EN,hys300 600 900

mV

–

EN pull-down resistance R_EN

15

30

60

kΩ

Inhibit Output (pin INHO)

I_INH= - 15 mA

Inhibit R_onresistance

R_onINHO

65

120

Ω

Data Sheet

13

Rev. 2.0, 2005-04-18

TLE 6285

Table 4

Electrical Characteristics (cont’d)

V_CC= 5V; V_S= 13.5V; R_L= 500 Ω; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Sym-

bol

Limit Values

Unit Remarks

Min. Typ. Max.

Leakage current

I_INHO,lk-5.0

–

5.0

µA

sleep mode;

_INHO= 0 V

V

V_QOutput (pin V_CCO

)

Output voltage

V_Q

4.90 5.00 5.10

4.85 5.00 5.15

250 400 500

V

1 mA ≤ I_Q≤ 100 mA;

6 V ≤ V_I≤ 16 V

Output voltage

I_Q≤ 150 mA;

6 V ≤ V_I≤ 16 V

Current limit

I_Q

mA

V

–

Drop voltage

Load regulation

Line regulation

V_dr

–

0.22 0.5

I_Q= 100 mA¹⁾

∆V_Q

5

30

25

mV I_Q= 1 mA to 100 mA

10

mV V_I= 6 V to 28 V;

I_Q= 1 mA

Power Supply Ripple

rejection

PSRR

–

66

–

dB

²⁾f_r= 100 Hz;

V_r= 1 Vpp;

I_Q= 100 mA

Data Sheet

14

Rev. 2.0, 2005-04-18

TLE 6285

Table 4

Electrical Characteristics (cont’d)

V_CC= 5V; V_S= 13.5V; R_L= 500 Ω; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Sym-

bol

Limit Values

Unit Remarks

Min. Typ. Max.

Reset Generator (pins RO, RD)

Switching threshold

Reset pull-up

V_rt

4.50 4.60 4.80

V

–

R_RO

V_R

10

–

20

40

kΩ

V

Reset low voltage

0.17 0.40

³⁾V_Q< 4.5 V;

internal R_RO;

I_R= 1 mA

External reset pull-up

R_{RO ext}5.6

–

kΩ

Pull-up resistor pin

RO to pin V_CCO

Delay switching threshold V_DT

Switching threshold

Reset delay low voltage V_D

1.5

1.85 2.2

V

–

V_ST

0.35 0.50 0.60

–

0.1

V_Q< V_RT

V_D= 1 V

Charge current

I_ch

t_d

4.0

17

0.5

8.0

28

1.2

12.0 µA

Reset delay time

Reset reaction time

35

ms C_D= 100 nF

t_RR

3.0

µs

C_D= 100 nF

V_Q> 3.5 V

Reset adjust switching

threshold

V_{RADJ TH}1.26 1.36 1.44

V

Inhibit Input (pin INHI)

Inhibit OFF voltage range V_{INHI OFF}

–

0.8

–

V

V_Qoff

V_Qon

Inhibit ON voltage range V_{INHI ON}3.5

–

V

High input current

Low input current

I_{INHI ON}

–

3

8

µA

V

_INHI= 5 V

_INHI= 0 V

I_{INHI OFF}

0.5

2

Receiver Output RxD

HIGH level output current I_RD,H

LOW level output current I_RD,L

-1.2 -0.8 -0.5 mA V_RD= 0.8 × V_CC

0.5 0.8 1.2 mA V_RD= 0.2 × V_CC

Data Sheet

15

Rev. 2.0, 2005-04-18

TLE 6285

Table 4

Electrical Characteristics (cont’d)

V_CC= 5V; V_S= 13.5V; R_L= 500 Ω; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Sym-

bol

Limit Values

Unit Remarks

Min. Typ. Max.

Transmission Input TxD

HIGH level input voltage V_TD,H

–

2.9

0.7 × V

recessive state

threshold

V_CC

TxD input hysteresis

V_TD,hys300 700 900

mV

V

–

LOW level input voltage V_TD,L

0.3 × 2.1

–

dominant state

threshold

V_CC

TxD pull-up current

I_TD

-150 -110 -70

µA

V

_TxD< 0.3 V_CC

Bus Receiver

Receiver threshold

voltage, recessive to

dominant edge

V_bus,rd

0.44 0.48 –

× V_S× V_S

V

-8 V < V_bus< V_bus,dom

Receiver threshold

voltage, dominant to

recessive edge

V_bus,dr

–

0.52 0.60

× V_S× V_S

V

_bus,rec< V_bus< 20 V

Receiver hysteresis

V_bus,hys0.02 0.04 0.1 × mV

× V_S× V_SV_S

_bus,hys= V_bus,rec-

V_bus,dom

Receiver threshold center V_bus,cnt0.475 0.5 × 0.525

LIN2.0 table 3.1

voltage

× V_SV_S

× V_S

Input leakage current

I_bus,lek

-1

mA

V

V_bus= 0V, V_bat= 12V,

pull-up resistor as

specified in LIN2.0

Wake-up threshold

voltage

V_wake

0.40 0.55 0.60

× V_S× V_S× V_S

–

Bus Transmitter

Bus recessive output

voltage

V_bus,rec0.9 × –

V_S

2

V

_TxD= V_CC

V_S

Bus dominant output

voltage

V_bus,dom

0

–

V

_TxD= 0 V

7.3V<V_S<27V

_TxD= 0 V

6V<V_S<7.3V

0

–

1.2

150

V

Bus short circuit current I_bus,sc

40

85

mA

V

_bus,short= 13.5 V

Data Sheet

16

Rev. 2.0, 2005-04-18

TLE 6285

Table 4

Electrical Characteristics (cont’d)

V_CC= 5V; V_S= 13.5V; R_L= 500 Ω; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Sym-

bol

Limit Values

Unit Remarks

Min. Typ. Max.

Leakage current

I_bus,lk

-1

-

–

mA V_CC= 0 V, V_S= 0 V,

V

_bus= -8 V,

–

10

20

µA

kΩ

V_CC= 0 V,

V_S= 13.5V,

V

_bus= 20 V,

Bus pull-up resistance

R_bus

20

30

47

–

Data Sheet

17

Rev. 2.0, 2005-04-18

TLE 6285

Table 4

Electrical Characteristics (cont’d)

V_CC= 5V; V_S= 13.5V; R_L= 500 Ω; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Sym-

bol

Limit Values

Unit Remarks

Min. Typ. Max.

Dynamic Transceiver Characteristics

60% > V_bus> 40%

Falling edge slew rate

Rising edge slew rate

Slope symmetry

S_bus(L)

-3

-2.0 -1

V/µs

1 µs<(τ = R_BUS× C_BUS)<5µs⁴⁾

V_CC= 5 V;

V_S= 13.5 V

40% < V_bus< 60%

1 µs<(τ = R_BUS× C_BUS)<5µs⁴⁾

V_CC= 5 V;

S_bus(H)

1

1.5

3

V_S= 13.5 V

t_slopesym-5

–

1

5

4

µs

t_fslope- t_rslope

Propagation delay

TxD LOW to bus

t_d(L),T

t_d(H),T

t_d(L),R

–

V_CC= 5 V

V_CC= 5 V;

Propagation delay

TxD HIGH to bus

1

4

6

µs

Propagation delay

bus dominant to RxD

LOW

C

_RxD= 20 pF

Propagation delay

bus recessive to RxD

HIGH

t_d(H),R

–

1

6

µs

V_CC= 5 V;

_RxD= 20 pF

C

Receiver delay symmetry t_sym,R

-2

–

2

µs

t

_sym,R= t_d(L),R- t_d(H),R

_sym,T= t_d(L),T- t_d(H),T

Transmitter delay

symmetry

t_sym,T

0.396

duty cycle 1⁴⁾

TH_Rec(max) = 0.744 × V_S;

TH_Dom(max) = 0.581 × V_S;

V_S= 7.0 … 18 V;

Duty cycle D1

t_duty1

–

µs

t_bit= 50 µs;

D1 = t_{bus_rec(min)}/2 t_bit;

0.581

duty cycle 2⁴⁾

TH_Rec(max) = 0.422× V_S;

TH_Dom(max) = 0.264 × V_S

V_S= 7.6 … 18 V;

Duty cycle D2

t_duty2

–

µs

t_bit= 50 µs;

D2 = t_{bus_rec(max)}/2 t_bit;

Wake-up delay time

Data Sheet

t_wake

30

–

100 150

170

µs

T_j≤ 125 °C

T_j≤ 150 °C ²⁾

–

18

Rev. 2.0, 2005-04-18

TLE 6285

Table 4

Electrical Characteristics (cont’d)

V_CC= 5V; V_S= 13.5V; R_L= 500 Ω; V_EN> V_EN,ON; -40 °C < T_j< 125 °C; all voltages with

respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Sym-

bol

Limit Values

Unit Remarks

Min. Typ. Max.

Delay time for change

sleep/stand by mode -

normal mode

t_snorm

–

50

µs

–

Delay time for change

normal mode - sleep

mode

t_nsleep

–

50

1) Drop voltage = V_I- V_Q(measured when the output voltage has dropped 100 mV from the nominal value

obtained at 13.5 V input)

2) Not subject to production test, specified by design.

^{3) The reset output is low within the range}V_Q= 1 V to V_rt

4) Bus load conditions concerning LIN spec 2.0 C_bus, R_bus= 1 nF, 1 kΩ / 6.8 nF, 660 Ω / 10 nF, 500 Ω

Data Sheet

19

Rev. 2.0, 2005-04-18

TLE 6285

Diagrams

V

I

<

t_rr

t

V_Q

V_{Q, rt}

I_{D, ch}

d

V

t

=

V_D

C_D

V_DU

V_DRL

t_rd

t_rr

t

V_RO

t

Power-ON

Reset

Over-

temperature

Voltage Drop Under-

at Input voltage

Secondary

Spike

Load

Bounce

AET03066

Figure 4

Time Response

Data Sheet

20

Rev. 2.0, 2005-04-18

TLE 6285

Typical Performance Characteristics

Output Voltage V_Q(PIN V_CCO) versus

Input Voltage V_I(PIN V_BAT

)

Temperature T_j

AED01671

AED01808

5.2

12

V_Q

V

5.1

5.0

4.9

4.8

4.7

4.6

10

V_Ι= 13.5 V

8

6

R_L= 50

Ω

4

2

0

-40

0

40

80

120 C 160

0

2

4

6

8

V 10

T_j

V_Ι

Data Sheet

21

Rev. 2.0, 2005-04-18

TLE 6285

Charge Current I_chversus

Temperature T_j

Drop Voltage V_drversus

Output Current I_Q(PIN V_CCO

)

AED03108

AED02929

12

400

mV

µA

10

I_D

V_DR

125 ˚C

300

8

6

4

2

0

25 ˚C

250

V

= 13.5 V

I

V_D= 1 V

200

150

100

50

0

-40

0

40

80

120 ˚C 160

0

50

100

150 mA 200

T_j

I_Q

Switching Voltage V_dtand V_stversus

Temperature T_j

Reset Adjust Switching Threshold

_RADJTHversus Temperature T_j

V

AED01804

AED03109

3.2

1.5

V

V_D

V

V_RADJTH

2.8

1.4

1.3

1.2

1.1

1.0

0.9

V_Ι= 13.5 V

2.4

2.0

1.6

1.2

0.8

0.4

0

V_UD

V

LD

-40

0

40

80

120 C 160

-40

0

40

80

120 ˚C 160

T_j

Data Sheet

22

Rev. 2.0, 2005-04-18

TLE 6285

Sense Threshold V_si

Output Current Limit I_Q(PIN V_CCO

)

versus Temperature T_j

versus Input Voltage V_I(PIN V_BAT

)

AED02933

AED03110

350

mA

300

1.6

Ι _Q

V

V_Si

1.5

Sense Output High

Sense Output Low

250

200

150

100

50

1.4

1.3

1.2

1.1

1.0

T_j= 25 C

T_j= 125 C

0

-40

0

40

80

120 ˚C 160

0

10

20

30

40

V 50

T_j

V_Ι

Current Consumption I_qversus

Output Current I_Q

Current Consumption I_qversus

Output Current I_Q

AED02931

AED02932

1.0

mA

5

mA

I_q

0.8

0.6

0.4

0.2

0

4

3

2

1

0

10

20

30

40

mA 60

0

50

100

150 mA 200

I_Q

Data Sheet

23

Rev. 2.0, 2005-04-18

TLE 6285

Application

V

L I N B u s

B

a

t

M

a s t e r

N

o d e

T L E 6 2 8 5

G

2 2 µ F

+

1 3

3

7

V

R O

B

a

t

1 0 0

E N L I N

n F

6

µ P

R

x D

1

k

Ω

1 1

T x D

1 2

5

1 0

V

B u s

C

I

G

N D

1 n F

1 0 0

n F

1 0 0

n F

I N H O

5

V

4

V

C

O

2

R

I N H I

R D

1

1 5

1 4

+

R

2 2 µ F

t h

C

D

R

G

N

D

2

1 0 0 n F

1 , 8 , 9 , 1 6

E C U

1

S l a v e N o d e

T L E 6 2 8 5

G

1 3

3

7

V

R O

B

a

t

+

1 0 0

n F

2 2 µ F

E N L I N

6

µ P

R

x D

1 1

T x D

1 2

1 0

V

B u s

C

I

G

N D

1 0 0

n F

1 0 0

n F

2 2 0

5

I N H O

p F

5

V

4

V

C

O

2

R

I N H I

R D

1

1 5

1 4

+

R

2 2 µ F

t h

C

D

G

N

D

2

1 0 0 n F

1 , 8 , 9 , 1 6

E C U

X

A

E

A

0

3

4

8

. V

S

D

Figure 5

Application Example

Data Sheet

24

Rev. 2.0, 2005-04-18

TLE 6285

Package Outlines

±0.08

0.33

x 45˚

0.64

1)

4_-0.2

1.27

C

±0.25

0.1

+0.1

0.41

-0.06

M

0.2 A C 16x

±0.2

6

16

1

9

8

1)

10 _-0.2

A

Index Marking

¹⁾Does not include plastic or metal protrusion of 0.25 max. per side

GPS09453

Figure 6

P-DSO-16-11 (Plastic Dual Small Outline)

You can find all of our packages, sorts of packing and others in our

Infineon Internet Page “Products”: http://www.infineon.com/products.

Dimensions in mm

SMD = Surface Mounted Device

Data Sheet

25

Rev. 2.0, 2005-04-18


型号：	TLE6285GDUMA1
厂家：	Infineon
描述：	Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, BCDMOS, PDSO16, PLASTIC, SOP-16 驱动 CD 光电二极管接口集成电路驱动器
文件：	总25页 (文件大小：446K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLE6285GDUMA1 [INFINEON]

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