TLE9262BQX [INFINEON]
The device is designed for various CAN-LIN automot;型号: | TLE9262BQX |
厂家: | Infineon |
描述: | The device is designed for various CAN-LIN automot |
文件: | 总175页 (文件大小:4782K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
OPTIREG™ SBC TLE9262BQX
Mid-Range+ System Basis Chip Family
Features
•
Two integrated Low-Drop Voltage Regulators: Main regulator with
5 V up to 250 mA (3.3 V variant available) and auxiliary regulator
(5 V up to 100 mA) with off-board usage protection
•
•
Voltage regulator (5 V or 3.3 V selectable) with external PNP
transistor configurable for off-board usage or for load sharing
1 high-speed CAN transceiver supporting FD communication up to
5 Mbit/s according to ISO 11898-2:2016 & SAE J2284 (Partial
Networking option available)
•
•
•
•
LIN transceiver supporting LIN 2.2/ISO 17987-4/SAE J2602
4 high-side outputs 7 Ω typ., 2 HV GPIOs, 3 HV wake inputs
Integrated fail-safe and supervision functions, e.g. fail-safe, watchdog, interrupt- and reset outputs
16-bit SPI for configuration and diagnostics
Potential applications
•
•
•
•
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Body Control Modules (BMC), Passive keyless entry and start modules, Gateway applications
Heating, ventilation and air conditioning (HVAC)
Seat, roof, tailgate, trailer, door and other closure modules
Light control modules
Gear shifters and selectors
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
Body System IC with Integrated Voltage Regulators, Power Management Functions, HS-CAN Transceiver
supporting CAN FD and LIN Transceiver.
Featuring Multiple High-Side Switches and High-Voltage Wake Inputs.
Type
Package
Marking
TLE9262BQX
PG-VQFN-48
TLE9262BQX
Datasheet
www.infineon.com/sbc
Rev. 1.2
2022-05-04
1
OPTIREG™ SBC TLE9262BQX
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hints for Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hints for Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
4.2
4.3
4.4
5
5.1
System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Description of State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Configuration and SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SBC Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SBC Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SBC Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SBC Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration and Operation of Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Cyclic Sense in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Supervision Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.1
5.1.1.1
5.1.1.2
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.2
5.2.3
5.3
6
Voltage Regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1
6.2
6.3
7
7.1
7.2
Voltage Regulator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Datasheet
2
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
7.2.1
7.3
Short to Battery Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8
External Voltage Regulator 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External Voltage Regulator as Independent Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
External Voltage Regulator in Load Sharing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Calculation of RSHUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.1
8.2
8.2.1
8.2.2
8.3
8.4
8.5
8.6
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.3
High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Over- and Undervoltage Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Overcurrent Detection and Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
HSx Operation in Different SBC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PWM and Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10
10.1
10.2
High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
CAN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
10.3
11
11.1
11.1.1
11.2
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LIN Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LIN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LIN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LIN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LIN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Slope Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Flash Programming via LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.2.9
11.3
12
Wake and Voltage Monitoring Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Datasheet
3
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
12.1
12.2
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Alternate Measurement Function with WK1 and WK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.2.1
12.2.2
12.2.2.1
12.2.2.2
12.3
13
13.1
13.2
Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14
Fail Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
General Purpose I/O Functionality of FO2 and FO3 as Alternate Function . . . . . . . . . . . . . . . . . . . 101
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
14.1
14.1.1
14.2
15
15.1
Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Watchdog Setting Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Watchdog during SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Watchdog Start in SBC Stop Mode due to Bus Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
VS Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Undervoltage VS and VSHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Overvoltage VSHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
VCC1 Over-/ Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
VCC1 Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
VCC1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
VCC1 Short Circuit and VCC3 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
VCC2 Undervoltage and VCAN Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Individual Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SBC Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
15.1.1
15.1.2
15.2
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
15.3
15.4
15.5
15.6
15.6.1
15.6.2
15.7
15.8
15.9
15.9.1
15.9.2
15.9.3
15.10
16
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SPI Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI Status Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.1
16.2
16.3
16.4
16.5
16.5.1
16.6
16.6.1
Datasheet
4
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
16.6.2
16.7
Family and Product Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
17
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
17.1
17.2
17.3
18
19
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Datasheet
5
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Overview
1
Overview
Scalable System Basis Chip Family
•
•
•
•
•
•
•
Product family with various products for complete scalable application coverage
Dedicated Data Sheets are available for the different product variants
Complete compatibility (hardware and software) across the family
TLE9263 with 2 LIN transceivers, 3 voltage regulators
TLE9262 with 1 LIN transceiver, 3 voltage regulators
TLE9261 without LIN transceivers, 3 voltage regulators
Product variants for 5 V (TLE926xBQX) and 3.3 V (TLE926xBQXV33) output voltage for main voltage
regulator
•
CAN Partial Networking variants for 5 V (TLE926x-3BQX) and 3.3 V (TLE926x-3BQXV33) output voltage
Device Description
The TLE9262BQX is a monolithic integrated circuit in an exposed pad VQFN-48 (7 mm x 7 mm) power package
with Lead Tip Inspection (LTI) feature to support Automatic Optical Inspection (AOI).
The device is designed for various CAN-LIN automotive applications as main supply for the microcontroller
and as interface for a LIN and CAN bus network.
To support these applications, the System Basis Chip (SBC) provides the main functions, such as a 5 V low-
dropout voltage regulator (LDO) for e.g. a microcontroller supply, another 5 V low-dropout voltage regulator
with off-board protection for e.g. sensor supply, another 5 V/3.3V regulator to drive an external PNP
transistor, which can be used as an independent supply for off-board usage or in load sharing configuration
with the main regulator VCC1, a HS-CAN transceiver supporting CAN FD and LIN transceiver for data
transmission, high-side switches with embedded protective functions and a 16-bit Serial Peripheral Interface
(SPI) to control and monitor the device. Also implemented are a configurable timeout / window watchdog
circuit with a reset feature, three Fail Outputs and an undervoltage reset feature.
The device offers low-power modes in order to minimize current consumption on applications that are
connected permanently to the battery. A wake-up from the low-power mode is possible via a message on the
buses, via the bi-level sensitive monitoring/wake-up inputs as well as via cyclic wake.
The device is designed to withstand the severe conditions of automotive applications.
Datasheet
6
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Overview
Product Features
•
•
•
•
•
•
Very low quiescent current consumption in Stop- and Sleep Mode
Periodic Cyclic Wake in SBC Normal- and Stop Mode
Periodic Cyclic Sense in SBC Normal-, Stop- and Sleep Mode
Low-Drop Voltage Regulator 5 V, 250 mA
Low-Drop Voltage Regulator 5 V, 100 mA, protected features for off-board usage
Low-Drop Voltage Regulator, driving an external PNP transistor - 5 V in load sharing configuration or
5 V/3.3 V in stand-alone configuration, protected features for off-board usage. Current limitation by shunt
resistor (up to 350 mA with 470 mΩ external shunt resistor) in stand-alone configuration
•
High-Speed CAN Transceiver:
–
–
fully compliant to HS-CAN standard ISO 11898-2:2016
supporting CAN FD communication up to 5 Mbps
•
•
LIN Transceiver LIN 2.2/ISO 17987-4/SAE J2602 with configurable TXD timeout feature and LIN Flash Mode
Fully compliant to “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive
Applications” Revision 1.3, 2012-05-04
•
•
•
Four High-Side Outputs 7 Ω typ.
Dedicated supply pin for High-Side Outputs
Two General Purpose High-Voltage In- and Outputs (GPIOs) configurable as add. Fail Outputs, Wake Inputs,
Low-Side switches or High-Side switches
•
•
•
•
•
•
•
•
•
•
•
Three universal High-Voltage Wake Inputs for voltage level monitoring
Alternate High-Voltage Measurement Function, e.g. for battery voltage sensing
Configurable wake-up sources
Reset Output
Configurable timeout and window watchdog
Up to three Fail Outputs (depending on configuration)
Overtemperature and short circuit protection feature
Wide supply input voltage and temperature range
Software compatible to all SBC families TLE926x and TLE927x
Green Product (RoHS compliant) & AEC Qualified
PG-VQFN-48 leadless exposed-pad power package with Lead Tip Inspection (LTI) feature to support
Automatic Optical Inspection (AOI)
Datasheet
7
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Block Diagram
2
Block Diagram
VSHS
VS
VS
VS
VCC1
VCC3
HS1
HS2
High Side
HS3
HS4
FO1
FO2
VCC2
VCC2
FO3/TEST
Fail Safe
Alternative function
for FO2/3: GPIO1/2
SDI
SDO
SPI
SBC
STATE
CLK
CSN
MACHINE
INT
Interrupt
Control
Window Watchdog
RO
RESET
GENERATOR
WK1
WK
VCAN
Alternative
function for WK 1/2:
WAKE
REGISTER
Voltage measurement
WK2
TXDCAN
RXDCAN
WK
CAN cell
CANH
CANL
WK3
WK
VSHS
TXDLIN1
RXDLIN1
LIN cell
LIN 1
GND
Figure 1
Block Diagram
Datasheet
8
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
VCAN 37
GND 38
CANL 39
CANH 40
n.c. 41
24 WK3
23 WK2
22 WK1
21 FO1
20 GND
19 n.c.
TLE9262
LIN1 42
GND 43
N.U. 44
n.c. 45
18 VCC2
17 VCC1
16 n.c.
PG-VQFN-48
n.c. 46
15 VS
FO2 47
14 VS
FO3/TEST 48
13 VSHS
TLE9262.vsd
Figure 2
Pin Configuration
Datasheet
9
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Pin Configuration
3.2
Pin Definitions and Functions
Pin
1
Symbol
GND
Function
Ground
2
n.c.
not connected; internally not bonded.
VCC3REF; Collector connection for external PNP, reference input
VCC3B; Base connection for external PNP
VCC3SH; Emitter connection for external PNP, shunt connection
not connected; internally not bonded.
not connected; internally not bonded.
High Side Output 1; typ. 7Ω
3
VCC3REF
VCC3B
VCC3SH
n.c.
4
5
6
7
n.c.
8
HS1
9
HS2
High Side Output 2; typ. 7Ω
10
11
12
13
HS3
High Side Output 3; typ. 7Ω
HS4
High Side Output 4; typ. 7Ω
n.c
not connected; internally not bonded.
VSHS
Supply Voltage for High-Side Switches and LIN and GPIO 1/2 in HS
configuration; Connected to battery voltage with reverse protection diode and
filter against EMC; Connect to VS if separate supply is not needed
14
15
VS
VS
Supply Voltage for chip internal supply and voltage regulators; Connected to
Battery Voltage with external reverse protection Diode and Filter against EMC
Supply Voltage for chip internal supply and voltage regulators; Connected to
Battery Voltage with external reverse protection Diode and Filter against EMC
16
17
18
19
20
21
22
n.c.
not connected; internally not bonded.
Voltage Regulator Output 1
Voltage Regulator Output 2
not connected; internally not bonded.
Ground
VCC1
VCC2
n.c.
GND
FO1
WK1
Fail Output 1
Wake Input 1; Alternative function: HV-measurement function input pin
(only in combination with WK2, see Chapter 12.2.2)
23
WK2
Wake Input 2; Alternative function: HV-measurement function output pin
(only in combination with WK1, see Chapter 12.2.2)
24
25
26
27
28
29
30
WK3
N.U.
N.U.
CLK
SDI
Wake Input 3
Not Used; Used for internal testing purpose. Do not connect, leave open
Not Used; Used for internal testing purpose. Do not connect, leave open
SPI Clock Input
SPI Data Input; into SBC (=MOSI)
SDO
CSN
SPI Data Output; out of SBC (=MISO)
SPI Chip Select Not Input
Datasheet
10
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Pin Configuration
Pin
Symbol
Function
31
INT
Interrupt Output; used as wake-up flag for microcontroller in SBC Stop or
Normal Mode and for indicating failures. Active low.
During start-up used to set the SBC configuration. External pull-up sets config
1/3, no external pull-up sets config 2/4.
32
33
34
35
36
37
38
39
40
41
42
RO
Reset Output
TXDLIN1
RXDLIN1
TXDCAN
RXDCAN
VCAN
GND
Transmit LIN1
Receive LIN1
Transmit CAN
Receive CAN
Supply Input; for internal HS-CAN cell
Ground
CANL
CAN Low Bus Pin
CAN High Bus Pin
not connected; internally not bonded.
CANH
n.c.
LIN1
LIN1 Bus; Bus line for the LIN interface, according to LIN 2.2/ISO 17987-4 as well
as SAE J2602-2.
43
44
45
46
47
GND
N.U.
n.c.
Ground
Not Used; Used for internal testing purpose. Do not connect, leave open
not connected; internally not bonded.
not connected; internally not bonded.
n.c.
FO2
Fail Output 2 - Side Indicator; Side indicators 1.25Hz 50% duty cycle output;
Open drain. Active LOW.
Alternative Function: GPIO1; configurable pin as WK, or LS, or HS supplied by
VSHS (default is FO2, see also Chapter 14.1.1)
48
FO3/TEST
Fail Output 3 - Pulsed Light Output; Break/rear light 100Hz 20% duty cycle
output;
Open drain. Active LOW
TEST; Connect to GND to activate SBC Development Mode;
Integrated pull-up resistor. Connect to VS with pull-up resistor or leave open for
normal operation.
Alternative Function: GPIO2; configurable pin as WK, or LS, or HS supplied by
VSHS (default is FO3, see also Chapter 14.1.1)
Cooling GND
Tab
Cooling Tab - Exposed Die Pad; connect the exposed pad to GND. It is
recommended to connect the exposed pad to a heat sink.
Note:
All VS Pins must be connected to battery potential or insert a reverse polarity diodes where required;
all GND pins as well as the Cooling Tab must be connected to one common GND potential;
note that the tie bars at each package corner are connected to the cooling tab (see also Chapter 18)
Datasheet
11
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Pin Configuration
3.3
Hints for Unused Pins
It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that
they are disabled via SPI:
•
•
•
•
•
•
WK1/2/3: connect to GND and disable WK inputs via SPI
HSx: leave open
LINx, RXDLINx, TXDLINx, CANH/L, RXDCAN, TXDCAN: leave all pins open
RO / FOx: leave open
INT: leave open
TEST: connect to GND during power-up to activate SBC Development Mode;
connect to VS or leave open for normal user mode operation
•
•
•
•
•
VCC2: leave open and keep disabled
VCC3: See Chapter 8.5
VCAN: connect to VCC1
n.c.: not connected; internally not bonded; connect to GND
N.U.: Not Used; Used for internal testing purposes only. Do not connect, leave open, i.e. not connected to
any potential on the board. In case N.U. pins are connected on the board an open bridge has to be foreseen
to avoid external disturbances. The bridge can be shorted by a 0 Ω resistance if signal is needed.
3.4
Hints for Alternate Pin Functions
In case of alternate pin functions, selectable via SPI, it must be ensured that the correct configurations are also
selected via SPI, in case it is not done automatically. Please consult the respective chapter. In addition,
following topics shall be considered:
•
•
WK1..2: The pins can be either used as HV wake / voltage monitoring inputs or for a voltage measurement
function (via bit WK_MEAS). In the second case, the WK1..2 pins shall not be used / assigned for any wake
detection nor cyclic sense functionality, i.e. WK1 and WK2 must be disabled in the register WK_CTRL_2 and
the level information is to be ignored in the register WK_LVL_STAT.
FO2..3: The pins can also be configured as GPIOs in the GPIO_CTRL register. In this case, the pins shall not
be used for any fail output functionality. The default function after Power on Reset (POR) is FOx.
Datasheet
12
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Voltages
Supply Voltage (VS, VSHS)
Supply Voltage (VS, VSHS)
VSx, max
VSx, max
-0.3
-0.3
–
–
28
40
V
V
–
P_4.1.1
P_4.1.2
Load Dump,
max. 400 ms
Voltage Regulator 1
Voltage Regulator 2
VCC1, max
VCC2, max
-0.3
-0.3
–
–
5.5
28
V
V
VCC1 = 5.6V for
max. 10s
P_4.1.3
P_4.1.4
VCC2 = 40V for
Load Dump,
max. 400 ms;
Voltage Regulator 3
(VCC3REF)
VCC3REF,max -0.3
–
–
–
28
V
V
V
VCC3REF = 40V for P_4.1.5
Load Dump,
max. 400 ms;
Voltage Regulator 3 (VCC3B) VCC3B,max
-0.3
VS
+ 10
VCC3B = 40V for
Load Dump,
max. 400 ms;
P_4.1.25
P_4.1.26
Voltage Regulator 3
(VCC3SH)
VCC3SH,max
VS
VS
+ 0.30
–
- 0.30
Wake Inputs WK1..3
Fail Pin FO1
VWK, max
-0.3
-0.3
-0.3
–
–
–
40
40
V
V
V
–
–
–
P_4.1.6
P_4.1.7
P_4.1.23
VFO1, max
VFO2_3, max
Fail Pins FO2, FO3/TEST
VS
+ 0.3
LINx, CANH, CANL
VBUS, max
-27
–
–
40
40
V
V
–
–
P_4.1.8
Maximum Differential CAN VCAN_Diff, max -40
P_4.1.27
Bus Voltage
Logic Input Pins (CSN, CLK, VI, max
SDI, TXDLINx, TXDCAN)
-0.3
-0.3
–
–
VCC1
+ 0.3
V
V
–
–
P_4.1.9
Logic Output Pins (SDO, RO, VO, max
VCC1
P_4.1.10
INT, RXDLINx, RXDCAN)
+ 0.3
VCAN Input Voltage
High Side 1...4
VVCAN, max
VHS, max
-0.3
-0.3
–
–
5.5
V
V
–
–
P_4.1.11
P_4.1.12
VSHS
+ 0.3
Currents
2)
Wake input WK1
IWK1,max
0
–
500
µA
P_4.1.13
Datasheet
13
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
Table 1
Absolute Maximum Ratings1) (cont’d)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
2)
Wake input WK2
IWK2,max
-500
0
µA
P_4.1.14
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
ESD Resistivity
Tj
-40
-55
–
–
150
150
°C
°C
–
–
P_4.1.15
P_4.1.16
Tstg
VESD,11
-2
-2
-8
–
–
–
2
2
8
kV
kV
kV
HBM3)
HBM3)
HBM4)3)
P_4.1.17
P_4.1.18
P_4.1.19
ESD Resistivity to GND, HSx VESD,12
ESD Resistivity to GND,
CANH, CANL, LINx
VESD,13
ESD Resistivity to GND
VESD,21
VESD,22
-500
-750
–
–
500
750
V
V
CDM5)
CDM5)
P_4.1.20
P_4.1.21
ESD Resistivity Pin 1,
12,13,24,25,36,37,48 (corner
pins) to GND
1) Not subject to production test, specified by design
2) Applies only if WK1 and WK2 are configured as alternative HV-measurement function
3) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF)
4) For ESD “GUN” Resistivity 6KV (according to IEC61000-4-2 “gun test” (150pF, 330Ω)), will be shown in Application
Information and test report will be provided from IBEE
5) ESD susceptibility, Charged Device Model according to ANSI/ESDA/JEDEC JS-002
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Datasheet
14
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
1)
Supply Voltage
VS,func
VPOR
28
V
V
see
P_4.2.1
POR
Chapter 15.10
2)
LIN Bus Voltage
CAN Supply Voltage
SPI frequency
VS,LIN,func
VCAN,func
fSPI
6
–
–
–
18
5.25
4
V
V
P_4.2.2
P_4.2.3
P_4.2.4
4.75
–
–
MHz see
Chapter 16.7 for
fSPI,max
–
Junction Temperature
Tj
-40
–
150
°C
P_4.2.5
1) Including Power-On Reset, Over- and Undervoltage Protection
2) Parameter Specification according to LIN 2.2/ISO 17987-4
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Device Behavior Outside of Specified Functional Range:
•
28V < VS,func < 40V: Device will still be functional including the state machine; the specified electrical
characteristics might not be ensured anymore. The regulators VCC1/2/3 are working properly, however, a
thermal shutdown might occur due to high power dissipation. HSx switches might be turned OFF
depending on VSHS_OV configurations. The specified SPI communication speed is ensured; the absolute
maximum ratings are not violated, however the device is not intended for continuous operation of VS >28V.
The device operation at high junction temperatures for long periods might reduce the operating life time;
•
•
•
•
•
18V < VS,LIN <28V: The LIN transceiver is still functional. However, the communication might fail due to out-
of-LIN-spec operation;
V
SHS,UVD < VS,LIN < 6V: The LIN transceiver is still functional. However, the communication might fail due to
out-of-LIN-spec operation;
VCAN < 4.75V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_1 and the transmitter
will be disabled as long as the UV condition is present;
5.25V < VCAN < 5.50V: CAN transceiver still functional. However, the communication might fail due to out-of-
spec operation;
V
POR,f < VS < 5.5V: Device will still be functional; the specified electrical characteristics might not be ensured
anymore.
–
The voltage regulators will enter the low-drop operation mode
(applies for VCC3 only if bit VCC3_VS_ UV_OFF is set),
–
–
–
A VCC1_UV reset could be triggered depending on the Vrtx settings,
The LIN transmitter will be disabled if VSHS,UVD is reached,
HSx switch behavior will depend on the respective configuration:
- HS_UV_SD_EN = ‘0’ (default): HSx will be turned OFF for VSHS < VSHS_UV and will stay OFF;
- HS_UV_SD_EN = ‘1’: HSx stays on as long as possible. An unwanted overcurrent shut down may occur.
OC shut down bit set and the respective HSx switch will stay OFF;
Datasheet
15
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
–
–
FOx outputs will remain ON if they were enabled before VS > 5.5V,
The specified SPI communication speed is ensured.
4.3
Thermal Resistance
Table 3
Thermal Resistance1)
Symbol
Parameter
Values
Typ.
6
Unit Note or
Test Condition
Number
Min.
Max.
Junction to Soldering Point RthJSP
Junction to Ambient RthJA
–
–
–
K/W Exposed Pad
P_4.3.1
P_4.3.2
2)
–
33
K/W
1) Not subject to production test, specified by design.
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for 1.5W. Board: 76.2x114.3x1.5mm3 with
2 inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper
layer and 300mm2 cooling area on the bottom layer (70µm).
Datasheet
16
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
4.4
Current Consumption
Table 4
Current Consumption
Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
SBC Normal Mode
Normal Mode current
consumption
INormal
–
3.5
44
6.5
mA
µA
VS = 5.5 V to 28 V;
Tj = -40 °C to +150 °C;
VCC2, CAN, LIN, VCC3,
HSx = OFF
P_4.4.1
SBC Stop Mode
Stop Mode current
consumption
IStop_1,25
–
–
60
70
1)VCC2/3, HSx = OFF; P_4.4.2
CAN, LINx, WKx not
wake capable;
Watchdog = OFF;
no load on VCC1;
I_PEAK_TH = ‘0’
1)2)Tj = 85°C;
VCC2/3, HSx = OFF;
CAN, LINx, WKx not
wake capable;
Stop Mode current
consumption
IStop_1,85
50
µA
P_4.4.3
Watchdog = OFF;
no load on VCC1;
I_PEAK_TH = ‘0’
Stop Mode current
consumption
(high active peak threshold)
IStop_2,25
–
–
64
70
90
µA
µA
1)VCC2/3, HSx = OFF; P_4.4.35
CAN, LINx, WKx not
wake capable;
Watchdog = OFF;
no load on VCC1;
I_PEAK_TH = ‘1’
Stop Mode current
consumption
(high active peak threshold)
IStop_2,85
100
1)2)Tj = 85°C;
P_4.4.36
VCC2/3, HSx = OFF;
CAN, LINx, WKx not
wake capable;
Watchdog = OFF;
no load on VCC1;
I_PEAK_TH = ‘1’
SBC Sleep Mode
Sleep Mode current
consumption
ISleep,25
–
–
15
25
25
35
µA
µA
VCC2/3, HSx = OFF;
CAN, LINx, WKx not
wake capable
2)Tj = 85°C;
VCC2/3, HSx = OFF;
CAN, LINx, WKx not
wake capable
P_4.4.5
P_4.4.6
Sleep Mode current
consumption
ISleep,85
Datasheet
17
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
Table 4
Current Consumption (cont’d)
Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Feature Incremental Current Consumption
Max.
Current consumption for
CAN module, recessive state
ICAN,rec
–
–
–
2
3
mA
mA
mA
SBC Normal/Stop
Mode; CAN Normal
Mode; VCC1
connected to VCAN;
VTXDCAN = VCC1; no
RL on CAN
2)SBC Normal/Stop
Mode; CAN Normal
Mode; VCC1
connected to VCAN;
VTXDCAN = GND;
no RL on CAN
2)SBC Normal/Stop
Mode; CAN Receive
Only Mode; VCC1
connected to VCAN;
VTXDCAN = VCC1; no
RL on CAN
P_4.4.7
Current consumption for
CAN module, dominant
state
ICAN,dom
3
4.5
1.2
P_4.4.8
P_4.4.9
Current consumption for
CAN module, Receive Only
Mode
ICAN,RcvOnly
0.9
Current consumption per
LIN module, recessive state
ILIN,rec
–
–
0.1
1.0
1
mA
mA
SBC Normal/Stop
Mode; LIN Normal
Mode; VTXDLIN =
VCC1;
P_4.4.10
P_4.4.11
P_4.4.12
no RL on LIN
Current consumption per
LIN module, dominant state
ILIN,dom
1.5
2)SBC Normal/Stop
Mode; LIN Normal
Mode; VTXDLIN =
GND;
no RL on LIN
Current consumption per
LIN module, Receive Only
Mode
ILIN,RcvOnly
IWake,WKx,25
IWake,WKx,85
–
–
–
0.2
0.2
0.5
0.5
2
mA
µA
µA
2)SBC Normal/Stop
Mode; LIN Receive
OnlyMode; VTXDLIN =
VCC1; no RL on LIN
3)4)5) SBC Sleep Mode; P_4.4.13
WK1..3 wake capable
(all WKx enabled);
LIN, CAN = OFF
2)3)4)5)SBC Sleep
Mode; Tj = 85°C;
WK1..3 wake capable;
(all WKx enabled);
LIN, CAN = OFF
Current consumption for
WK1..3 wake capability
(all wake inputs)
Current consumption for
WK1..3 wake capability
(all wake inputs)
3
P_4.4.14
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
Table 4
Current Consumption (cont’d)
Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)
Parameter
Symbol
Values
Typ.
0.2
Unit Note or
Test Condition
Number
Min.
Max.
Current consumption per
LIN module wake capability
IWake,LIN,25
–
2
µA
3)SBC Sleep Mode;
LIN wake capable;
WK1..3, CAN = OFF
P_4.4.15
Current consumption per
LIN module wake capability
IWake,LIN,85
–
0.5
3
µA
2)3)SBC Sleep Mode;
Tj = 85°C;
LIN wake capable;
WK1..3, CAN = OFF
3)SBC Sleep Mode;
CAN wake capable;
WK1..3, LIN = OFF
2)3)SBC Sleep Mode; Tj P_4.4.18
= 85°C;
P_4.4.16
P_4.4.17
Current consumption for
CAN wake capability
IWake,CAN,25
–
–
4.5
5.5
6
7
µA
µA
Current consumption for
CAN wake capability
IWake,CAN,85
CAN wake capable;
WK1..3, LIN = OFF
VCC2 Normal Mode current INormal,VCC2
consumption
–
–
2.5
25
3.5
35
mA
µA
VS = 5.5 V to 28 V;
Tj = -40 °C to +150 °C;
VCC2 = ON (no load)
1)3)SBC Sleep Mode;
VCC2 = ON (no load);
LIN, CAN,
P_4.4.32
P_4.4.19
Current consumption for
VCC2 in SBC Sleep Mode
ISleep,VCC2,25
ISleep,VCC2,85
ISleep,VCC3,25
WK1..3 = OFF
Current consumption for
VCC2 in SBC Sleep Mode
–
–
30
40
40
60
µA
µA
1)2)3)SBC Sleep Mode; P_4.4.20
Tj = 85°C; VCC2 = ON
(no load); LIN, CAN,
WK1..3 = OFF
Current consumption for
VCC3 in SBC Sleep Mode in
stand-alone configuration
1)3)SBC Sleep Mode;
VCC3 = ON (no load,
stand-along config.);
LIN, CAN,
P_4.4.21
WK1..3 = OFF
Current consumption for
VCC3 in SBC Sleep Mode in
stand-alone configuration
ISleep,VCC3,85
–
–
50
70
µA
µA
1)2)3)SBC Sleep Mode; P_4.4.22
Tj = 85°C; VCC3 = ON
(no load, stand-along
config.); LIN, CAN,
WK1..3 = OFF
Current consumption for
HSx in SBC Stop Mode
IStop,HSx,25
550
675
3)6)SBC Stop Mode;
Cyclic Sense & HSx=
ON (no load);
P_4.4.33
LIN, CAN,
WK1..3 = OFF
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
Table 4
Current Consumption (cont’d)
Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)
Parameter
Symbol
Values
Typ.
575
Unit Note or
Test Condition
Number
Min.
Max.
Current consumption for
HSx in SBC Stop Mode
IStop,HSx,85
–
700
µA
2)3)6)SBC Stop Mode; P_4.4.34
Tj = 85°C;
Cyclic Sense & HSx =
ON (no load);
LIN, CAN,
WK1..3 = OFF
Current consumption for
cyclic sense function
IStop,CS25
IStop,CS85
–
–
20
24
28
35
µA
µA
3)7)8)SBC Stop Mode; P_4.4.23
WD = OFF
2)3)7)8)SBC Stop Mode; P_4.4.27
Tj = 85°C;
Current consumption for
cyclic sense function
WD = OFF
Current consumption for
watchdog active in Stop
Mode
IStop,WD25
IStop,WD85
IStop,FOx
–
–
–
–
20
28
µA
µA
mA
µA
2)SBC Stop Mode;
Watchdog running
P_4.4.30
P_4.4.31
P_4.4.24
P_4.4.37
Current consumption for
watchdog active in Stop
Mode
24
35
2)SBC Stop Mode;
Tj = 85°C;
Watchdog running
2)all SBC Modes;
Tj = 25°C; FOx = ON (no
load);
2)SBC Stop/Sleep
mode; GPIO
Current consumption for
active fail outputs (FO1..3)
1.0
450
2.0
550
Current consumption for
GPIOx if configured as low-
side/high-side for SBC Stop
or Sleep mode
IStop,GPIOx,LS/
HS
configured as LS/HS
(no load);
Current consumption for
GPIOx if configured as low-
side/high-side for SBC Stop
or Sleep mode
IStop,GPIOx,LS/
–
450
600
µA
2)SBC Stop/Sleep
mode; Tj = -
40…150°C;
GPIO configured as
LS/HS (no load);
P_4.4.38
HS
1) If the load current on VCC1 will exceed the configured VCC1 active peak threshold IVCC1,Ipeak1,r or IVCC1,Ipeak2,r
,
the current consumption will increase by typ. 2.9mA to ensure optimum dynamic load behavior. Same applies to
VCC2. For VCC3 the current consumption will increase by typ. 1.4mA. See also Chapter 6, Chapter 7, Chapter 8.
2) Not subject to production test, specified by design.
3) Current consumption adders of features defined for SBC Sleep Mode also apply for SBC Stop Mode and vice versa
(unless otherwise specified).
4) No pull-up or pull-down configuration selected.
5) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are
activated.
6) A typ. 75µA / max 125µA (Tj = 85°C) adder applies for every additionally activated HSx switch in SBC Stop Mode;
In SBC Normal Mode every HSx switch consumes the typ. 75µA / max 125µA (Tj = 85°C) without the initial adder
because the biasing is already enabled.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
General Product Characteristics
7) HS1 used for cyclic sense, Timer 2, 20ms period, 0.1ms on-time, no load on HS1.
In general the current consumption adder for cyclic sense in SBC Stop Mode can be calculated with below equation:
IStop,CS = 20µA + (550µA *tON/TPer)
8) Also applies to Cyclic Wake
Note:
There is no additional current consumption contribution due to PWM generators.
Datasheet
21
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
System Features
5
System Features
This chapter describes the system features and behavior of the TLE9262BQX:
•
•
•
•
•
•
State machine
SBC mode control
Device configuration
State of supply and peripherals
System functions such as cyclic sense or cyclic wake
Supervision and diagnosis functions
The System Basis Chip (SBC) offers six operating modes:
•
•
•
•
•
SBC Init Mode: Power-up of the device and after a soft reset,
SBC Normal Mode: The main operating mode of the device,
SBC Stop Mode: The first-level power saving mode with the main voltage regulator VCC1 enabled,
SBC Sleep Mode: The second-level power saving mode with VCC1 disabled,
SBC Restart Mode: An intermediate mode after a wake event from SBC Sleep or Fail-Safe Mode or after a
failure (e.g. WD failure, VCC1 undervoltage reset) to bring the microcontroller into a defined state via a
reset. Once the failure condition is not present anymore the device will automatically change to SBC
Normal Mode after a delay time (tRD1).
•
SBC Fail-Safe Mode: A safe-state mode after critical failures (e.g. WD failure, VCC1 undervoltage reset) to
bring the system into a safe state and to ensure a proper restart of the system. VCC1 is disabled. It is a
permanent state until either a wake event (via CAN, LINx or WKx) occurs or the overtemperature condition
is not present anymore.
A special mode, called SBC Development Mode, is available during software development or debugging of the
system. All above mentioned operating modes can be accessed in this mode. However, the watchdog counter
is stopped and does not need to be triggered. This mode can be accessed by setting the TEST pin to GND
during SBC Init Mode.
The device can be configured via hardware (external component) to determine the device behavior after a
watchdog trigger failure. See Chapter 5.1.1 for further information.
The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in
Chapter 16.The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the
TLE9262BQX is compatible to other devices of the TLE926x and TLE927x families.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
System Features
5.1
Block Description of State Machine
The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register
M_S_CTRL. The SBC MODE bits are cleared when going through SBC Restart Mode and thus always show the
current SBC mode.
First battery connection
SBC Soft Reset
SBC Init Mode
*
Config.: settings can be
(Long open window)
changed in this SBC mode;
VCC1
ON
VCC2
OFF
CAN(3)
OFF
VCC3
OFF Config.
LINx(3)
OFF
WD Cyc. Sense
OFF
Fixed: settings stay as defined
in SBC Normal Mode
Any SPI
command
Cyc. Wake
OFF
FOx
inact.
HSx
OFF
* The SBC Development Mode
is a super set of state machine
where the WD timer is stopped
and CAN/LINx behavior differs
in SBC Init Mode. Otherwise,
there are no differences in
behavior.
SBC Normal Mode
Cyc. Sense
config.
VCC1
ON
VCC2
VCC3
WD
WD trigger
config.
config. config.
CAN(3)
config.
Cyc.Wake
config.
FOx
act/inact
LINx(3)
config. config.
HSx
.
.
Reset is released
WD starts with long open window
Automatic
SPI cmd
SPI cmd
SPI cmd
SBC Stop Mode
SBC Sleep Mode
VCC3(2)
VCC1
ON
VCC2
fixed
VCC3
fixed
WD
fixed
Cyc. Sense
fixed
VCC1
OFF
VCC2
WD
OFF.
Cyc. Sense
fixed
Fixed /
fixed
OFF
VCC1 over voltage
Config 1/3 (if VCC_OV_RST set)
CAN(6)
FOx
fixed
CAN
fixed
LINx
fixed
HSx
fixed
LINx
Cyc. Wake
fixed
FOx
fixed
HSx
fixed
Cyc.Wake
OFF
Wake
Wake
capable/off
capable/off
Wake up event
SBC Restart Mode
(RO pin is asserted)
Watchdog Failure:
Config 1/3 & 1st WD failure
in Config4
VCC3(2)
After 4x consecutive VCC1
under voltage events
(if VS > VS_UV)
VCC1
ON/
ramping
VCC2
OFF
WD
OFF
Cyc.Sense
OFF
VCC1 over voltage
Config 2/4 (if VCC_OV_RST set)
fixed/
ramping
FOx(5)
active/
fixed
CAN (4)
woken /
OFF
LINx (4)
woken /
OFF
HSx
OFF
Cyc. Wake
OFF
VCC1
Undervoltage
SBC Fail-Safe Mode (1)
TSD2 event,
1st Watchdog Failure Config 2,
2nd Watchdog Failure, Config 4
Cyc.Sense
OFF
VCC1
OFF
VCC2
OFF
VCC3
OFF
WD
OFF
CAN, LINx, WKx wake-up event
OR
Release of over temperature
TSD2 after tTSD2
(1) After Fail-Safe Mode entry, the device will stay for at least
typ. 1s in this mode (with RO low) after a TSD2 event and
min. typ. 100ms after other Fail-Safe Events. Only then the device
can leave the mode via a wake-up event. Wake events are stored
during this time.
FOx(5)
active
HSx Cyc. Wake
OFF
CAN
Wake
capable
LINx
Wake
capable
VCC1 Short to GND
OFF
(2) According to VCC3 configuration.
(3) For SBC Development Mode CAN/LINx/VCC2 are ON in SBC Init
Mode and stay ON when going from there to SBC Normal Mode.
(4) See chapter CAN & LIN for detailed behavior in SBC Restart Mode.
(5) See Chapter 5.1.5 and 14.1 for detailed FOx behavior.
(6) Must be set to CAN wake capable / CAN OFF mode before
entering SBC Sleep Mode.
Figure 3
State Diagram showing the SBC Operating Modes
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
System Features
5.1.1
Device Configuration and SBC Init Mode
The SBC starts up in SBC Init Mode after crossing the power-on reset VPOR,r threshold (see also Chapter 15.3)
and the watchdog will start with a long open window (tLW).
During this power-on phase following configurations are stored in the device:
•
The device behavior regarding a watchdog trigger failure and a VCC1 overvoltage condition is determined
by the external circuitry on the INT pin (see below)
•
The selection of the normal device operation or the SBC Development Mode (watchdog disabled for
debugging purposes) will be set depending on the voltage level of the FO3/TEST pin (see also
Chapter 5.1.7).
5.1.1.1 Device Configuration
The configuration selection is intended to select the SBC behavior regarding a watchdog trigger failure.
Depending on the requirements of the application, the VCC1 output shall be switched OFF and the device shall
go to SBC Fail-Safe Mode in case of a watchdog failure (1 or 2 fails). To set this configuration (Config 2/4), the
INT pin does not need an external pull-up resistor. In case VCC1 should not be switched OFF (Config 1/3), the
INT pin needs to have an external pull-up resistor connected to VCC1 (see application diagram in
Chapter 17.1).
Figure 5 shows the timing diagram of the hardware configuration selection. The hardware configuration is
defined during SBC Init Mode. The INT pin is internally pulled LOW with a weak pull-down resistor during the
reset delay time tRD1, i.e.after VCC1 crosses the reset threshold VRT1 and before the RO pin goes HIGH. The INT
pin is monitored during this time (with a continuos filter time of tCFG_F) and the configuration (depending on
the voltage level at INT) is stored at the rising edge of RO.
Note:
If the POR bit is not cleared then the internal pull-down resistor will be reactivated every time RO is
pulled LOW the configuration will be updated at the rising edge of RO. Therefore it is recommended
to clear the POR bit right after initialization. In case there is no stable signal at INT, then the default
value ‘0’ will taken as the config select value = SBC Fail-Safe Mode.
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System Features
VS
VPOR,r
t
t
VCC1
VRT1,r
RO
tCFG_F
Continuous Filtering with
t
tRD1
Configuration selection monitoring period
Figure 4
Hardware Configuration Selection Timing Diagram
There are four different device configurations (Table 5) available defining the watchdog failure and the VCC1
overvoltage behavior. The configurations can be selected via the external connection on the INT pin and the
SPI bit CFG in the HW_CTRL register (see also Chapter 16.4):
•
•
CFGP = ‘1’: Config 1 and Config 3:
–
A watchdog trigger failure leads to SBC Restart Mode and depending on CFG the Fail Outputs (FOx) are
activated after the 1st (Config 1) or 2nd (Config 3) watchdog trigger failure;
–
A VCC1 overvoltage detection will lead to SBC Restart Mode if VCC1_OV_RST is set.
VCC1_ OV will be set and the Fail Outputs are activated;
CFGP = ‘0’: Config 2 and Config 4:
–
A watchdog trigger failure leads to SBC Fail-Safe Mode and depending on CFG the Fail Outputs (FOx)
are activated after the 1st (Config 2) or 2nd (Config 4) watchdog trigger failure. The first watchdog
trigger failure in Config 4 will lead to SBC Restart Mode;
–
A VCC1 overvoltage detection will lead to SBC Fail-Safe Mode if VCC1_OV_RST is set.
VCC1_ OV will be set and the Fail Outputs are activated;
The respective device configuration can be identified by reading the SPI bit CFG in the HW_CTRL register and
the CFGP bit in the WK_LVL_STAT register.
Table 5 shows the configurations and the device behavior in case of a watchdog trigger failure:
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System Features
Table 5
Watchdog Trigger Failure Configuration
Config INT Pin (CFGP) SPI Bit CFG RO activation
FOx activation
SBC Mode Entry
1
2
External pull-up
No ext. pull-up
1
1
each watchdog failure after 1st WD failure SBC Restart Mode
each watchdog failure after 1st WD failure SBC Fail-Safe Mode
after 1st WD failure
3
4
External pull-up
No ext. pull-up
0
0
each watchdog failure after 2nd WD failure SBC Restart Mode
each watchdog failure after 2nd WD failure SBC restart mode after
1st WD failure.
SBC Fail-Safe Mode
after 2nd WD failure
Table 6 shows the configurations and the device behavior in case of a VCC1 overvoltage detection when
VCC1_OV_RST is set:
Table 6
Device Behavior in Case of VCC1 Overvoltage Detection
Config INT Pin (CFGP) CFG Bit VCC1_O Event
V_RST
VCC1_ FOx Activation
OV
SBC Mode Entry
1-4
1
any value
x
0
1
1 x VCC1 OV
1 x VCC1 OV
1
1
no FOx activation unchanged
External pull-
up
1
after 1st VCC1 OV SBC Restart Mode
2
3
No ext. pull-up 1
1
1
1 x VCC1 OV
1 x VCC1 OV
1
1
after 1st VCC1 OV SBC Fail-Safe Mode
after 1st VCC1 OV SBC Restart Mode
External pull-
up
0
4
No ext. pull-up 0
1
1 x VCC1 OV
1
after 1st VCC1 OV SBC Fail-Safe Mode
The respective configuration will be stored for all conditions and can only be changed by powering down the
device (VS < VPOR,f).
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System Features
5.1.1.2 SBC Init Mode
In SBC Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. In
the SBC Init Mode any valid SPI command will bring the SBC to SBC Normal Mode. During the long open
window the watchdog has to be triggered. Thereby the watchdog will be automatically configured.
A missing watchdog trigger during the long open window will cause a watchdog failure and the device will
enter SBC Restart Mode.
Wake events are ignored during SBC Init Mode and will therefore be lost.
Notes
1. Any SPI command will bring the SBC to SBC Normal Mode even if it is a illegal SPI command (see
Chapter 16.2).
2. For a safe start-up, it is recommended to use the first SPI command to trigger and to configure the watchdog
(see Chapter 15.2).
3. At power up no VCC1_UV will be issued nor will FOx be triggered as long as VCC1 is below the VRT,x threshold
and if VS is below the VCC1 short circuit detection threshold VS,UV. The RO pin will be kept low as long as VCC1
is below the selected VRT,x threshold.
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System Features
5.1.2
SBC Normal Mode
The SBC Normal Mode is the standard operating mode for the SBC. All configurations have to be done in SBC
Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining
the Fail-Safe Mode behavior). A wake-up event on CAN, LINx and WKx will create an interrupt on pin INT -
however, no change of the SBC mode will occur. The configuration options are listed below:
•
•
•
VCC1 is active
VCC2 can be switched ON or OFF (default = OFF)
VCC3 is configurable (OFF coming from SBC Init Mode; as previously programmed coming from SBC Restart
Mode)
•
•
•
CAN is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart Mode,
see also Chapter 5.1.5)
LIN is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart Mode,
see also Chapter 5.1.5)
HS Outputs can be switched ON or OFF (default = OFF) or can be controlled by PWM; HS Outputs are OFF
coming from SBC Restart Mode
•
•
•
•
•
Wake pins show the input level and can be selected to be wake capable (interrupt)
Cyclic sense can be configured with HS1...4 and Timer1 or Timer 2
Cyclic wake can be configured with Timer1 or Timer2
Watchdog is configurable
All FOx outputs are OFF by default. Coming from SBC Restart Mode FOx can be active (due to a failure event,
e.g. watchdog trigger failure, VCC1 short circuit, etc.) or inactive (no failure occurred)
In SBC Normal Mode, there is the possibility of testing the FO outputs, i.e. to verify if setting the FO pin to low
will create the intended behavior within the system. The FO output can be enabled and then disabled again
by the microcontroller by setting the FO_ON SPI bit. This feature is only intended for testing purposes.
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System Features
5.1.3
SBC Stop Mode
The SBC Stop Mode is the first level technique to reduce the overall current consumption by setting the
voltage regulators VCC1, VCC2 and VCC3 into a low-power mode. In this mode VCC1 is still active and supplying
the microcontroller, which can enter a power down mode. The VCC2 supply, CAN & LIN mode as well as the
HSx outputs can be configured to stay enabled. All kind of settings have to be done before entering SBC Stop
Mode. In SBC Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for
changing to SBC Normal Mode, triggering a SBC Soft Reset, refreshing the watchdog as well as for reading and
clearing the SPI status registers. A wake-up event on CAN, LINx and WKx will create an interrupt on pin INT -
however, no change of the SBC mode will occur. The configuration options are listed below:
•
•
•
•
•
•
•
•
•
•
•
•
VCC1 is ON
VCC2 is fixed as configured in SBC Normal Mode
VCC3 is fixed as configured in SBC Normal Mode
CAN mode is fixed as configured in SBC Normal Mode
LIN mode is fixed as configured in SBC Normal Mode
WK pins are fixed as configured in SBC Normal Mode
HS Outputs are fixed as configured in SBC Normal Mode
Cyclic sense is fixed as configured in SBC Normal Mode
Cyclic wake is fixed as configured in SBC Normal Mode
Watchdog is fixed as configured in SBC Normal Mode
SBC Soft Reset can be triggered
FOx outputs are fixed, i.e. the state from SBC Normal Mode is maintained
An interrupt is triggered on the pin INT when SBC Stop Mode is entered and not all wake source signalization
flags from WK_STAT_1 and WK_STAT_2 were cleared.
Notes
1. If switches are enabled during SBC Stop Mode, e.g. HSx on with or without PWM, then the SBC current
consumption will increase (see Chapter 4.4).
2. It is not possible to switch directly from SBC Stop Mode to SBC Sleep Mode. Doing so will also set the SPI_FAIL
flag and will bring the SBC into Restart Mode.
3. When WK1 and WK2 are configured for the alternate measurement function (WK_MEAS = 1) then the wake
inputs cannot be selected as wake input sources.
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System Features
5.1.4
SBC Sleep Mode
The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum
needed to react on wake-up events or for the SBC to perform autonomous actions (e.g. cyclic sense). In this
mode, VCC1 is OFF and not supplying the microcontroller anymore.The VCC2 supply as well as the HSx outputs
can be configured to stay enabled. The settings have to be done before entering SBC Sleep Mode. A wake-up
event on CAN, LINx or WKx will bring the device via SBC Restart Mode into SBC Normal Mode again and signal
the wake source. The configuration options are listed below:
•
•
•
•
VCC1 is OFF
VCC2 is fixed as configured in SBC Normal Mode
VCC3 is fixed or OFF as configured in SBC Normal Mode
CAN mode changes automatically from ON or Receive Only Mode to wake capable mode or can be selected
to be OFF
•
•
CAN must be set to CAN wake capable / CAN off mode before entering SBC Sleep Mode
LIN mode changes automatically from ON or Receive Only Mode to wake capable mode or can be selected
to be OFF
•
•
•
•
•
•
•
•
WK pins are fixed as configured in SBC Normal Mode
HS Outputs are fixed as configured in SBC Normal Mode
Cyclic sense is fixed as configured in SBC Normal Mode
Cyclic wake is not available
Watchdog is OFF
FOx outputs are fixed, i.e. the state from SBC Normal Mode is maintained
As VCC1 is OFF during SBC Sleep Mode, no SPI communication is possible;
The Sleep Mode entry is signalled in the SPI register DEV_STAT with the bit DEV_STAT
It is not possible to switch all wake sources off in SBC Sleep Mode. Doing so will set the SPI_FAIL flag and will
bring the SBC into SBC Restart Mode.
In order to enter SBC Sleep Mode successfully, all wake source signalization flags from WK_STAT_1 and
WK_STAT_2 need to be cleared. A failure to do so will result in an immediate wake-up from SBC Sleep Mode
by going via SBC Restart to Normal Mode.
All settings must be done before entering SBC Sleep Mode.
Notes
1. If switches are enabled during SBC Sleep mode, e.g. HSx on with or without PWM, then the SBC current
consumption will increase (see Chapter 4.4).
2. Cyclic Sense function will not work properly anymore in case of an overcurrent, overtemperature, under- or
overvoltage (in case function is selected) event because the respective HS switch will be disabled.
3. When WK1 and WK2 are configured for the alternate measurement function (WK_MEAS = 1) then the wake
inputs cannot be selected as wake input sources.
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System Features
5.1.5
SBC Restart Mode
There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the
microcontroller:
•
•
•
in case of undervoltage on VCC1 in SBC Normal and in SBC Stop Mode,
in case of overvoltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘1’,
due to 1st incorrect Watchdog triggering (only if Config1, Config3 or Config 4 is selected, otherwise SBC
Fail-Safe Mode is immediately entered),
•
In case of a wake event from SBC Sleep or SBC Fail-Safe Mode or a release of overtemperature shutdown
(TSD2) out of SBC Fail-Safe Mode this transition is used to ramp up VCC1 after a wake in a defined way.
From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode, i.e the mode is left automatically
by the SBC without any microcontroller influence. The SBC MODE bits are cleared. As shown in Figure 47 the
Reset Output (RO) is pulled low when entering Restart Mode and is released at the transition to Normal Mode
after the reset delay time (tRD1). The watchdog timer will start with a long open window starting from the
moment of the rising edge of RO and the watchdog period setting in the register WD_CTRL will be changed to
the respective default value ‘100’.
Leaving the SBC Restart Mode will not result in changing / deactivating the Fail outputs.
The behavior of the blocks is listed below:
•
All FOx outputs are activated in case of a 1st watchdog trigger failure (if Config1 or Config2 is selected) or
in case of VCC1 overvoltage detection (if VCC1_OV_RST is set)
•
•
•
•
VCC1 is ON or ramping up
VCC2 will be disabled if it was activated before
VCC3 is fixed or ramping as configured in SBC Normal Mode
CAN is “woken” due to a wake event or OFF depending on previous SBC and transceiver mode (see also
Chapter 10). It is wake capable when it was in CAN Normal-, Receive Only or wake capable mode before
SBC Restart Mode
•
LIN is “woken” or OFF depending on previous SBC and transceiver mode (see also Chapter 11). It is wake
capable when it was in LIN Normal-, Receive Only or wake capable mode before SBC Restart Mode.
•
•
•
•
HS Outputs will be disabled if they were activated before
RO is pulled low during SBC Restart Mode
SPI communication is ignored by the SBC, i.e. it is not interpreted
The Restart Mode entry is signalled in the SPI register DEV_STAT with the bits DEV_STAT
Table 7
Reasons for Restart - State of SPI Status Bits after Return to Normal Mode
Prev. SBC Mode
Normal
Normal
Normal
Normal
Stop
Event
DEV_STAT WD_FAIL VCC1_UV VCC1_OV VCC1_SC
1x Watchdog Failure
2x Watchdog Failure
01
01
01
10
xx
xx
01
10
xx
xx
x
x
1
x
x
x
1
x
x
x
x
1
x
x
x
1
x
x
x
x
x
x
x
x
VCC1 undervoltage reset 01
VCC1 overvoltage reset 01
1x Watchdog Failure
2x Watchdog Failure
01
01
Stop
Stop
VCC1 undervoltage reset 01
VCC1 overvoltage reset 01
Stop
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System Features
Table 7
Reasons for Restart - State of SPI Status Bits after Return to Normal Mode (cont’d)
Prev. SBC Mode
Sleep
Event
DEV_STAT WD_FAIL VCC1_UV VCC1_OV VCC1_SC
Wake-up event
Wake-up event
10
01
xx
x
x
x
Fail-Safe
see “Reasons for Fail Safe, Table 8”
Notes
1. An overvoltage event on VCC1 will only lead to SBC Restart Mode if the bit VCC1_OV_RST is set and if CFGP =
‘1’ (Config 1/3).
2. The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.
5.1.6
SBC Fail-Safe Mode
The purpose of this mode is to bring the system in a safe status after a failure condition by turning off the VCC1
supply and powering off the microcontroller. After a wake event the system is then able to restart again.
The Fail-Safe Mode is automatically reached for following events:
•
•
•
after an SBC thermal shutdown (TSD2) (see also Chapter 15.9.3),
in case of overvoltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘0’,
after a 1st incorrect watchdog trigger in Config2 (CFG = 1) and after a 2nd incorrect watchdog trigger in
Config4 (CFG = 0) (see also Chapter 5.1.1),
•
•
if VCC1 is shorted to GND (see also Chapter 15.7),
After 4 consecutive VCC1 undervoltage events (only if VS > VS,UV, see Chapter 15.6).
In this case, the default wake sources (CAN, LINx, WK1...3, see also registers WK_CTRL_2, BUS_CTRL_1) are
activated, the wake events are cleared in the register WK_STAT_1, and all output drivers and all voltage
regulators are switched off. When WK1 and WK2 are configured for the alternate measurement function
(WK_MEAS = 1) then WK1 and WK2 will stay configured for the measurement function when SBC Fail-Safe
Mode is entered, i.e. they will not be activated as wake sources.
The SBC Fail-Safe Mode will be maintained until a wake event on the default wake sources occurs. To avoid
any fast toggling behavior a filter time of typ. 100ms (tFS,min) is implemented. Wake events during this time will
be stored and will automatically lead to entering SBC Restart Mode after the filter time.
In case of an VCC1 overtemperature shutdown (TSD2) the SBC Restart Mode will be reached automatically
after a filter time of typ. 1s (tTSD2) without the need of a wake event.
Leaving the SBC Fail-Safe Mode will not result in deactivation of the Fail Output pins.
The following functions are influenced during SBC Fail-Safe Mode:
•
•
•
•
•
•
•
•
•
•
All FOx outputs are activated (see also Chapter 14)
VCC1 is OFF
VCC2 is OFF
VCC3 is OFF
CAN is wake capable
LINx is wake capable
HS Outputs are OFF
WK pins are wake capable through static sense (with default 16µs filter time)
Cyclic sense and Cyclic wake is disabled
SPI communication is disabled because VCC1 is OFF
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System Features
•
The Fail-Safe Mode activation is signalled in the SPI register DEV_STAT with the bits FAILURE and
DEV_STAT
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System Features
Table 8
Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode
Prev. SBC Failure Event
Mode
DEV_
STAT
TSD2
WD_
FAIL
VCC1_
UV
VCC1_
UV_FS
VCC1_
OV
VCC1_
SC
Normal
Normal
Normal
Normal
Normal
Normal
Stop
1 x Watchdog Failure 01
2 x Watchdog Failure 01
x
x
1
x
x
x
x
x
1
x
x
x
01
10
xx
xx
xx
xx
01
10
xx
xx
xx
xx
x
x
x
1
1
x
x
x
x
1
1
x
x
x
x
x
1
x
x
x
x
x
1
x
x
x
x
x
x
1
x
x
x
x
x
1
x
x
x
1
x
x
x
x
x
1
x
x
TSD2
01
01
01
01
VCC1 short to GND
4x VCC1 UV
VCC1 overvoltage
1 x Watchdog Failure 01
2 x Watchdog Failure 01
Stop
Stop
TSD2
01
01
01
01
Stop
VCC1 short to GND
4x VCC1 UV
Stop
Stop
VCC1 overvoltage
Notes
1. An overvoltage event on VCC1 will only lead to SBC Fail-Safe Mode if the bit VCC1_OV_RST is set and if CFGP =
‘0’ (Config 2/4).
2. The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.
3. See Chapter 15.6.1 for detailed description of the 4x VCC1 undervoltage behavior.
5.1.7
SBC Development Mode
The SBC Development Mode is used during the development phase of the module. It is especially useful for
software development.
Compared to the default SBC user mode operation, this mode is a super set of the state machine. The device
will start also in SBC Init Mode and it is possible to use all the SBC Modes and functions with following
differences:
•
•
•
Watchdog is stopped and does not need to be triggered. Therefore no reset is triggered due to watchdog
failure
SBC Fail-Safe and SBC Restart Mode are not reached due to watchdog failure but the other reasons to enter
these modes are still valid
LINx, CAN and VCC2 default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is
ON instead of OFF
The SBC Development Mode is reached automatically if the FO3/TEST pin is set and kept LOW during SBC Init
Mode. The voltage level monitoring is started as soon as VS > VPOR,f. The Development Mode is configured and
maintained if SBC Init Mode is left by sending any SPI command while FO3/TEST is LOW. In case the FO3/TEST
level will be HIGH for longer than tTEST during the monitoring period then the SBC Development Mode is not
reached .
The SBC will remain in this mode for all conditions and can only be left by powering down the device
(VS < VPOR,f).
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System Features
Note:
The absolute maximum ratings of the pin FO3/TEST must be observed. To increase the robustness of
this pin during debugging or programming a series resistor between FO3/TEST and the connector
can be added (see Figure 61).
5.2
Wake Features
Following wake sources are implemented in the device:
•
•
•
•
•
Static Sense: WK inputs are permanently active (see Chapter 12)
Cyclic Sense: WK inputs only active during on-time of cyclic sense period (see below)
Cyclic Wake: internal wake source controlled via internal timer (see below)
CAN wake: Wake-up via CAN message (see Chapter 10)
LIN wake: Wake-up via LIN message (see Chapter 11)
5.2.1
Cyclic Sense
The cyclic sense feature is intended to reduce the quiescent current of the device and the application.
In the cyclic sense configuration, one or more high-side drivers are switched on periodically controlled by
TIMER1_CTRL and TIMER2_CTRL. The respective high-side drivers supply external circuitries e.g. switches
and/or resistor arrays, which are connected to one or more wake inputs (see Figure 5). Any edge change of the
WKx input signal during the on-time of the cyclic sense period causes a wake. Depending on the SBC mode,
either the INT is pulled low (SBC Normal Mode and Stop Mode) or the SBC is woken enabling the VCC1 (after
SBC Sleep and SBC Fail-Safe Mode).
High Side
1-4
HS x
HS_CTRL
Signals
GND
Switching
Circuitry
TIMER_CTRL
Period / On-Time
INT
SBC
to uC
STATE
MACHINE
WK x
WK
1-3
WK_FLT_CTRL
Figure 5
Cyclic Sense Working Principle
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System Features
5.2.1.1 Configuration and Operation of Cyclic Sense
The correct sequence to configure the cyclic sense is shown in Figure 6. All the configurations have to be
performed before the on-time is set in the TIMERx_CTRL registers. The settings “OFF / LOW” and “OFF / HIGH”
define the voltage level of the respective HS driver before the start of the cyclic sense. The intention of this
selection is to avoid an unintentional wake due to a voltage level change at the start of the cyclic sense.
Cyclic Sense (=TimerX) will start as soon as the respective on-time has been selected independently from the
assignment of the HS and filter configuration. The selection of the respective timer (Config C/D see
Chapter 12.2.1) must therefore be done before starting the timer. The correct configuration sequence is as
follows:
•
•
•
•
Configure the initial level
Mapping of a Timer to the respective HSx outputs
Configuring the respective filter timing and WK pins
Configuring the timer period and on-time
Cyclic Sense Configuration
Assign TIMERx_ON to OFF/Low or
Timer1, Timer2
Timer1, Timer2
OFF/High in TIMERx_CTRL
Assign Timer to selected HS switch
in HS_CTRL_X
Enable WKx as wake source with
configured Timer in WK_FLT_CTRL
WK1, WK2, WK3 with
above selected timer
Select WKx pull-up / pull-down
configuration in WK_PUPD_CTRL
No pull-up/-down, pull-down or pull-up
selected, automatic switching
Select Timer Period and desired
Period: 10, 20, 50, 100, 200ms, 1s, 2s
On-Time: 0.1, 0.3, 1.0, 10, 20ms
On-Time in TIMERx_CTRL
Changing the settings can be done on the
fly, changes become effective at the next
on-time or period
Cyclic Sense starts / ends by
setting / clearing On-time
Figure 6
Cyclic Sense: Configuration and Sequence
Note:
All configurations of period and on-time can be selected. However, recommended on-times for cyclic
sense are 0.1ms, 0.3ms and 1ms. The SPI_FAIL will be set if the on-time is longer than the period.
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System Features
The first sample of the WK input value (HIGH or LOW) is taken as the reference for the next cycle. A change of
the WK input value between the first and second cycle recognized during the on-time of the second cycle will
cause a wake from SBC Sleep Mode or an interrupt during SBC Normal or SBC Stop Mode.
A filter time of 16µs is implemented to avoid a parasitic wake-up due to transients or EMC disturbances. The
filter time tFWK1 is triggered right at the end of the selected on-time and a wake signal is recognized if:
•
the input level will not cross the switching threshold level of typ. 3V during the selected filter time (i.e. if the
signal will keep the HIGH or LOW level) and
•
there was an input level change between the current and previous cycle
A wake event due to cyclic sense will set the respective bit WK1_WU, WK2_WU, or WK3_WU.
During Cyclic Sense, WK_LVL_STAT is updated only with the sampled voltage levels of the WKx pins in SBC
Normal or SBC Stop Mode.
The functionality of the sampling and different scenarios are depicted in Figure 7 to Figure 9. The behavior in
SBC Stop and SBC Sleep Mode is identical except that in Stop Mode INT will be triggered to signal a change of
WK input levels and in SBC Sleep Mode, VCC1 will power-up instead.
HS on
Cyclic Sense
Periode
HS switch
Filter time
tFWK1
Filter time
tFWK1
On Time
t
1st sample taken
as reference
Wake detection possible
on 2nd sample
Figure 7
Wake Input Timing
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
System Features
HS
Filter time
High
Low
Switch
open
closed
WK
High
Low
n-1
n
n+1
n+2
WKn+2= High
WKn+2 ≠WKn+ 1
ðwake event
WKn+1 = Low
WKn = WKn+1
ð
Learning
Cycle
WKn-1= High
WKn= Low
WKn ≠WKn-1
ðwake event
no wake
INT
High
Low
INT &
WK Bit Set
Figure 8
Cyclic Sense Example in SBC Stop Mode, HSx starts “OFF”/LOW, GND based WKx input
HS
Filter time
High
Low
Spike
Switch
open
closed
WK
High
Low
n-1
n
n+1
n+2
WKn+2= High
WKn+2 ≠WKn+ 1
ðwake event
WK = WKn+1 = Low
n
(but ignored because
change during filter time )
WKn = WKn+1
Learning
Cycle
WKn-1= Low
WKn= Low
WKn = WKn-1
ðno wake event
VCC1
ð
no wakTe ervaennst ition to:
High
SBC Sleep Mode
SBC Normal Mode
INT &
WK Bit Set
Low
Start of
Cyclic Sense
Figure 9
Cyclic Sense Example in SBC Sleep Mode, HSx starts “OFF”/HIGH,
GND based WKx input
The cyclic sense function will not work properly anymore in case of following conditions:
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
System Features
•
•
in case SBC Fail-Safe Mode is entered: The respective HS Switch will be disabled and the respective wake
pin will be changed to static sensing
In SBC Normal, Stop, or Sleep Mode in case of an overcurrent, overtemperature, under- or overvoltage (in
case function is selected) event: the respective HS switch will be disabled
Note:
The internal timers for cyclic sense are not disabled automatically in case the HS switch is turned off
due to above mentioned failures.This must be considered to avoid loss of wake events.
5.2.1.2 Cyclic Sense in Low Power Mode
If cyclic sense is intended for SBC Stop or SBC Sleep Mode mode, it is necessary to activate the cyclic sense in
SBC Normal Mode before going to the low power mode. A wake event due to cyclic sense will set the respective
bit WK1_WU, WK2_WU or WK3_WU. In Stop Mode the wake event will trigger an interrupt, in Sleep Mode the
wake event will send the device via Restart Mode to Normal Mode. Before returning to SBC Sleep Mode, the
wake status register WK_STAT_1 and WK_STAT_2 needs to be cleared. Trying to go to SBC Sleep mode with
uncleared wake flags, such as WKx_WU the SBC will directly wake-up from Sleep Mode by going via Restart
Mode to Normal Mode, a reset is issued. The WKx_WU bit is seen as source for the wake. This is implemented
in order not to loose an wake event during the transition.
5.2.2
Cyclic Wake
The cyclic wake feature is intended to reduce the quiescent current of the device and application.
For the cyclic wake feature one or both timers are configured as internal wake-up source and will periodically
trigger an interrupt in SBC Normal and SBC Stop Mode.
The correct sequence to configure the cyclic wake is shown in Figure 10. The sequence is as follows:
•
•
•
First, disable the timers to ensure that there is not unintentional interrupt when activating cyclic wake,
Enable Timer1 and/or Timer2 as a wake-up source in the register WK_CTRL_1,
Configure the respective period Timer1 and/or Timer2. Also an on-time (any value) must be selected to
start the cyclic wake even if the value is ignored.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
System Features
Cyclic Wake Configuration
Disable Timer1 and/or Timer2 as a
To avoid unintentional interrupts
wake source in WK_CTRL_1
Periods : 10, 20, 50, 100, 200ms, 1s, 2s
On-times: any
(OFF/LOW & OFF/HIGH are not allowed)
Select Timer Period and any
On-Time in TIMERX_CTRL
No interrupt will be generated ,
if the timer is not enabled as a wake source
Select Timer1 and/or Timer2 as a
wake source in WK_CTRL_1
Cyclic Wake starts / ends by
setting / clearing On-time
INT is pulled low at every rising edge
of On-time except first one
Figure 10 Cyclic Wake: Configuration and Sequence
As in cyclic sense, the cyclic wake function will start as soon as the on-time is configured. An interrupt is
generated for every start of the on time except for the very first time when the timer is started
5.2.3
Internal Timer
The integrated Timer1 and Timer2 are typically used to wake up the microcontroller periodically (cyclic wake)
or to perform cyclic sense on the wake inputs. Therefore, the timers can be mapped to the dedicated HS
switches by SPI (via HS_CTRL1...2).
Following periods and on-times can be selected via the register TIMER1_CTRL and TIMER2_CTRL
respectively:
•
•
Period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s
On time: 0.1ms / 0.3ms / 1.0ms / 10ms / 20ms / OFF at HIGH or LOW
5.3
Supervision Features
The device offers various supervision features to support functional safety requirements. Please see
Chapter 15 for more information.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Voltage Regulator 1
6
Voltage Regulator 1
6.1
Block Description
VS
VCC1
Vref
1
Overtemperature
Shutdown
State
Machine
Bandgap
Reference
INH
GND
Figure 11 Module Block Diagram
Functional Features
•
•
5V low-drop voltage regulator
Undervoltage monitoring with adjustable reset level, VCC1 prewarning and VCC1 short circuit detection
(VRT1/2/3/4, VPW,f ). Please refer to Chapter 15.6 and Chapter 15.7 for more information.
•
•
Short circuit detection and switch off with undervoltage fail threshold, device enters SBC Fail-Safe Mode
≥470nF ceramic capacitor at voltage output for stability, with ESR < 1Ω @ f = 10 kHz, to achieve the voltage
regulator control loop stability based on the safe phase margin (bode diagram).
•
Output current capability up to IVCC1,lim.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Voltage Regulator 1
6.2
Functional Description
The Voltage Regulator 1 (=VCC1) is “ON” in SBC Normal and SBC Stop Mode and is disabled in SBC Sleep and
in SBC Fail-Safe Mode. The regulator can provide an output current up to IVCC1,lim
.
For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because only
a low-power mode regulator with a lower accuracy (VCC1,out41) will be active for small loads. If the load current
on VCC1 exceeds the selected threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) then the high-power mode regulator will be
also activated to support an optimum dynamic load behavior. The current consumption will then increase by
typ. 2.9mA.
If the load current on VCC1 falls below the selected threshold (IVCC1,Ipeak1,f or IVCC1,Ipeak2,f), then the low-quiescent
current mode is resumed again by disabling the high-power mode regulator.
Both regulators (low-power mode and high-power mode) are active in SBC Normal Mode.
Two different active peak thresholds can be selected via SPI:
•
I_PEAK_TH = ‘0’(default): the lower VCC1 active peak threshold 1 is selected with lowest quiescent current
consumption in SBC Stop Mode (IStop_1,25, IStop_1,85);
•
I_PEAK_TH = ‘1’: the higher VCC1 active peak threshold 2 is selected with an increased quiescent current
consumption in SBC Stop Mode (IStop_2,25, IStop_2,85);
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Voltage Regulator 1
6.3
Electrical Characteristics
Table 9
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Output Voltage including line VCC1,out1
and Load regulation
4.9
5.0
5.1
V
1)SBC Normal Mode;
10µA < IVCC1 < 250mA
6V < VS < 28V
P_6.3.1
Output Voltage including line VCC1,out2
and Load regulation
4.9
5.0
–
5.1
V
V
1)SBC Normal Mode;
10µA < IVCC1 < 150mA
1)2)SBC Normal Mode; P_6.3.12
20mA < IVCC1 < 90mA
8V < VS < 18V
P_6.3.7
Output Voltage including line VCC1,out3
and Load regulation
4.97
5.07
25°C < Tj < 125°C
Output Voltage including line VCC1,out41
and Load regulation
4.9
4.9
–
5.05 5.2
V
SBC Stop Mode;
1mA < IVCC1 < IVCC1,Ipeak
P_6.3.2
P_6.3.20
P_6.3.4
P_6.3.13
Output Voltage including line VCC1,out42
and Load regulation
5.05 5.25
V
SBC Stop Mode;
10µA < IVCC1 < 1mA
Output Drop
VCC1,d2
–
500
5.5
mV
mA
IVCC1 = 150mA
VS=5V
2)
VCC1 Active Peak Threshold 1 IVCC1,Ipeak1,r
(Transition threshold
–
2.9
I
rising;
CC1
VS = 13.5V
between low-power and high-
power mode regulator)
-40°C < Tj < 150°C;
I_PEAK_TH = ‘0’
2)
VCC1 Active Peak Threshold 1 IVCC1,Ipeak1,f 0.5
(Transition threshold
between high-power and low-
power mode regulator)
2.2
5.5
4.5
–
–
mA
mA
mA
I
falling;
P_6.3.17
P_6.3.18
P_6.3.19
CC1
VS = 13.5V
-40°C < Tj < 150°C;
I_PEAK_TH = ‘0’
2)
VCC1 Active Peak Threshold 2 IVCC1,Ipeak2,r
(Transition threshold
between low-power and high-
power mode regulator)
–
9.0
–
I
rising;
CC1
VS = 13.5V
-40°C < Tj < 150°C;
I_PEAK_TH = ‘1’
2)
VCC1 Active Peak Threshold 2 IVCC1,Ipeak2,f 1.7
(Transition threshold
between high-power and low-
power mode regulator)
I
falling;
CC1
VS = 13.5V
-40°C < Tj < 150°C;
I_PEAK_TH = ‘1’
Overcurrent Limitation
IVCC1,lim
250
12002) mA
current flowing out of P_6.3.6
pin, VCC1 = 0V
1) In SBC Stop Mode, the specified output voltage tolerance applies when IVCC1 has exceeded the selected active peak
threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) but with increased current consumption.
2) Not subject to production test, specified by design.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Voltage Regulator 1
Figure 12 Typical on-resistance of VCC1 pass device during low drop operation for ICC1 = 100mA
Datasheet
44
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Voltage Regulator 1
Figure 13 On-resistance range of VCC1 pass device during low drop operation for ICC1 = 150mA
Datasheet
45
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Voltage Regulator 2
7
Voltage Regulator 2
7.1
Block Description
VS
VCC2
Vref
1
Overtemperature
Shutdown
State
Machine
Bandgap
Reference
INH
GND
Figure 14 Module Block Diagram
Functional Features
•
•
•
•
•
•
5 V low-drop voltage regulator
Protected against short to battery voltage, e.g. for off-board sensor supply
Can also be used for CAN supply
VCC2 undervoltage monitoring. Please refer to Chapter 15.8 for more information
Can be active in SBC Normal, SBC Stop, and SBC Sleep Mode (not SBC Fail-Safe Mode)
VCC2 switch off after entering SBC Restart Mode. Switch off is latched, LDO must be enabled via SPI after
shutdown.
•
•
Overtemperature protection
≥ 470nF ceramic capacitor at output voltage for stability, with ESR < 1Ω @ f = 10 kHz, to achieve the voltage
regulator control loop stability based on the safe phase margin (bode diagram).
•
Output current capability up to IVCC2,lim.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Voltage Regulator 2
7.2
Functional Description
In SBC Normal Mode VCC2 can be switched on or off via SPI.
For SBC Stop- or Sleep Mode, the VCC2 has to be switched on or off before entering the respective SBC mode.
The regulator can provide an output current up to IVCC2,lim
.
For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because only
a low-power mode regulator with a lower accuracy (VCC2,out5) will be active for small loads. If the load current
on VCC2 exceeds IVCC2 > IVCC2,Ipeak,r then the high-power mode regulator will also be enabled to support an
optimum dynamic load behavior. The current consumption will then increase by typ. 2.9mA.
If the load current on VCC2 falls below the threshold (IVCC2 < IVCC2,Ipeak,f), then the low-quiescent current mode
is resumed again by disabling the high-power mode regulator.
Both regulators are active in SBC Normal Mode.
Note:
If the VCC2 output voltage is supplying external off-board loads, the application must consider the
series resonance circuit built by cable inductance and decoupling capacitor at the load. Sufficient
damping must be provided.
7.2.1
Short to Battery Protection
The output stage is protected for short to VBAT.
Datasheet
47
Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Voltage Regulator 2
7.3
Electrical Characteristics
Table 10
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Output Voltage including line VCC2,out1
and Load regulation
(SBC Normal Mode)
4.9
5.0
5.1
V
1)SBC Normal Mode;
10µA < IVCC2 < 100mA
6.5V < VS < 28V
P_7.3.1
Output Voltage including line VCC2,out2
and Load regulation
(SBC Normal Mode)
4.9
5.0
5.1
V
1)SBC Normal Mode;
10µA < IVCC2 < 80mA
6V < VS < 28V
P_7.3.16
Output Voltage including line VCC2,out3
and Load regulation
(SBC Normal Mode)
4.9
5.0
–
5.1
V
V
1)SBC Normal Mode;
10µA < IVCC2 < 40mA
P_7.3.2
Output Voltage including line VCC2,out4
and Load regulation
(SBC Normal Mode)
4.97
5.07
2)SBC Normal Mode;
10µA < IVCC2 < 5mA
8V < VS < 18V
P_7.3.14
25°C < Tj < 125°C
Output Voltage including line VCC2,out5
and Load regulation
(SBC Stop/Sleep Mode)
4.9
4.9
5.05 5.2
V
V
Stop, Sleep Mode;
1mA < IVCC2 < IVCC2,Ipeak
P_7.3.3
Output Voltage including line VCC2,out6
and Load regulation
5.05 5.25
Stop, Sleep Mode;
10µA < IVCC2 < 1mA
P_7.3.18
(SBC Stop/Sleep Mode)
Output Drop
VCC2,d1
–
–
–
500 mV
IVCC2 = 30mA
VS = 5V
P_7.3.4
2)
VCC2 Active Peak Threshold IVCC2,Ipeak,r
(Transition threshold
2.9
5.5
mA
I
rising;
P_7.3.15
CC2
VS = 13.5V
between low-power and high-
power mode regulator)
-40°C < Tj < 150°C
2)
VCC2 Active Peak Threshold IVCC2,Ipeak,f 0.5
(Transition threshold
between high-power and low-
power mode regulator)
2.4
–
–
mA
I
falling;
P_7.3.17
CC2
VS = 13.5V
-40°C < Tj < 150°C
Overcurrent limitation
IVCC2,lim
100
7502) mA
current flowing out of P_7.3.5
pin, VCC2 = 0V
1) In SBC Stop Mode, the specified output voltage tolerance applies when IVCC2 has exceeded the selected active peak
threshold (IVCC2,Ipeak,r) but with increased current consumption.
2) Not subject to production test, specified by design.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Voltage Regulator 2
Figure 15 Typical on-resistance of VCC2 pass device during low drop operation for ICC2 = 30mA
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Voltage Regulator 2
Figure 16 On-resistance range of VCC2 pass device during low drop operation for ICC2 = 50mA
Datasheet
50
Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
8
External Voltage Regulator 3
8.1
Block Description
VS
VCC3SH
VCC3B
VCC3REF
RBE
ICC3base
VS - VCC3shunt
> Vshunt_threshold
+
-
VREF
State Machine
Figure 17 Functional Block Diagram
Functional Features
•
•
•
Low-drop voltage regulator with external PNP transistor (up to 350mA with 470mΩ shunt resistor)
Four high-voltage pins are used: VS, VCC3B, VCC3SH, VCC3REF
Configurable as stand-alone regulator (5V or 3.3V output voltage selectable via SPI) or in load-sharing
mode with VCC1 (5V output voltage)
•
≥ 4.7µF ceramic capacitor at output voltage for stability, with ESR < 150mΩ @ f = 10 kHz to achieve the
voltage regulator control loop stability based on the safe phase margin (bode diagram).
•
•
•
Overcurrent limitation with external shunt in stand-alone configuration
Adjustable load current sharing ratio between VCC1 and VCC3 for load-sharing configuration
Undervoltage shutdown in stand-alone configuration only
Table 11
VCC1 configuration VCC3 voltage for VCC3_ V_CFG = 0
VCC1 = 5.0V VCC3 = 5.0V
1)External Voltage Regulator Configurations depending on VCC1 output voltage
VCC3 voltage for VCC3_ V_CFG = 1
VCC3 = 3.3V
1) This settings are valid only for the VCC3 stand-alone configuration. The bit VCC3_ V_CFG is ignored for VCC3 load
sharing configuration
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
8.2
Functional Description
The external voltage regulator can be used as an independent voltage regulator or in load-sharing mode with
VCC1. Setting VCC3_ON in the M_S_CTRL register in SBC Normal Mode sets the stand-alone configuration of
VCC3 as an independent voltage regulator. The load sharing configuration is set via the SPI bit VCC3_LS in the
HW_CTRL register.
VCC3
load sharing?
Default value of
VCC3_LS = ‘0'
No
VCC3
output voltage
in stand-alone
configuration
Yes
5.0V
3.3V
Set bit
Set bit
Set bit
VCC3_LS = 1
VCC3_V_CFG = 0
VCC3_V_CFG = 1
VCC3_V_CFG is
automatically set to 0
Set bit
Set bit
VCC3_ON = 0 or 1
VCC3_ON = 0 or 1
VCC3_LS, VCC3_ON and
VCC3_V_CFG cannot be
changed anymore
VCC3_LS and VCC3_V_CFG
cannot be changed anymore
(once VCC3_ON is set for the first time)
stand-alone
configuration
VCC3 = 5V
stand-alone
configuration
VCC3 = 3.3V
VCC3 load sharing
VCC3 = VCC1
Figure 18 Selecting the Configuration of the VCC3 Regulator
Depending on the configuration the regulator will act in the respective SBC Mode as described in Table 12.
After the VCC3 configuration has been selected, it cannot be changed anymore.
In stand-alone configuration the maximum current ICC3max is defined by the current limitation determined by
the used shunt. In load sharing configuration, the shunt is used to determine the current ratio between VCC1
and VCC3. Since the junction temperature of the external PNP transistor cannot be sensed by the SBC, it
cannot be protected against overtemperature by the SBC. Therefore the thermal behavior has to be analyzed
by the application.
For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because a
low-power mode regulator with a lower accuracy will be active for small loads. If the base current on VCC3
exceeds IVCC3base > IVCC3base,Ipeak,r then the high-power mode regulator is enabled additionally to support an
optimum dynamic load behavior. If the base current on VCC3 falls below the threshold (IVCC3base
<
IVCC3base,Ipeak,f), then the low-quiescent current consumption is resumed again by disabling the high-power
mode regulator.
Only the high-power mode regulator is active in SBC Normal Mode.
The status of VCC3 is reported in the SUP_STAT_2 SPI register. The regulator will switch OFF in case of VS
dropping below VS_UV regardless of the VCC3 configuration and will be automatically enabled again when
exceeding this threshold voltage unless the control bit VCC3_VS_ UV_OFF is set, i.e. in order to keep VCC3
enabled below VS_UV the bit VCC3_VS_ UV_OFF must be set. VCC3 will also stay active in SBC Stop Mode
when the bit VCC3_LS_ STP_ON is set and when load sharing is configured (for detailed protection features
see Chapter 15.7 and Chapter 16.3).
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
Table 12
External Voltage Regulator State by SBC Mode
SBC Mode
Load Sharing Mode1)
Independent Voltage Regulator
INIT Mode
OFF
OFF
Normal Mode
Stop Mode
Sleep Mode
Restart Mode
Fail-Safe Mode
Configurable
OFF/Fixed2)
OFF
Configurable
Fixed
Fixed
ON or ramping
Fixed
OFF
OFF
1) Behaves as VCC1 and has to be configured in SBC Normal Mode
2) Load Sharing operation in SBC Stop Mode is by default disabled for power saving reasons but VCC3_LS bit will stay
set. However, it can be also configured via the SPI bit VCC3_LS_ STP_ON to stay enabled in SBC Stop Mode.
Notes
1. The configuration of the VCC3 voltage regulator behavior must be done immediately after power-up of the
device and cannot be changed afterwards as long as the device is supplied.
2. As soon as the bit VCC3_ON or VCC3_LS is set for the first time, the configuration for VCC3 cannot be changed
anymore. This configuration is valid - also after a SBC Soft Reset - as long as the SBC is powered.
3. If the VCC3 output voltage is supplying external off-board loads, the application must consider the series
resonance circuit built by cable inductance and decoupling capacitor at the load. Sufficient damping must be
provided (e.g. a 100Ohm resistor between the PNP collector and VCC3REF with 10uF capacitor on collector -
see also Figure 19).
8.2.1
External Voltage Regulator as Independent Voltage Regulator
Configured as an independent voltage regulator the SBC offers with VCC3 a third supply which could be used
as off-board supply e.g. for sensors due to the integrated HV pins VCC3B, VCC3SH, VCC3REF.
This configuration is set and locked by enabling VCC3_ON while keeping VCC3_LS = 0. VCC3 can be switched
ON or OFF but the configuration cannot be changed anymore. However, the SPI_FAIL is not set while trying to
change the configuration.
An overcurrent limitation function is realized with the external shunt (see Chapter 8.4 for calculating the
desired shunt value) and the output current shunt voltage threshold (Vshunt_threshold). If this threshold is
reached, then ICC3 is limited and only the current limitation bit VCC3_OC is set (no other reaction) and can be
cleared via SPI once the overcurrent condition is not present anymore. If the overcurrent limitation feature is
not needed, then connect the pins VCC3SH and VS together.
In this configuration VCC3 has the undervoltage signalization enabled and an undervoltage event is signaled
with the bit VCC3_UV in the SUP_STAT_2 SPI register.
Note:
To avoid undesired current consumption increase of the device it must be ensured that VCC3 is not
connected to VCC1 in this configuration.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
VS
VCC3
RSHUNT
T1
ICC3
C2
C1
RLim
100Ω
VS
VCC3SH
VCC3B
RBE
VCC3REF
ICC3base
VS - VCC3shunt
> Vshunt_threshold
+
-
VREF
State Machine
Figure 19 Protecting the VCC3 against inductive short circuits when configured as an independent
voltage regulator for off-board supply
8.2.2
External Voltage Regulator in Load Sharing Mode
The purpose of the load sharing mode is to increase the total current capability of VCC1 without increase of
the power dissipation within the SBC. The load current is shared between the VCC1 internal regulator and the
external PNP transistor of VCC3. Figure 20 shows the setup for Load Sharing. Load Sharing is active in SBC
Normal Mode. It can also be configured via SPI to stay active in SBC Stop Mode.
An input voltage up to VSx,MAX is regulated to VCC3,nom = 5.0 V with a precision of ±2% when used in the load
sharing configuration in SBC Normal Mode.
This configuration is set and locked by enabling VCC3_LS for the first time while VCC3_ON has no function, i.e.
keep VCC3_ON = 0. Trying to change the VCC3 configuration after VCC3_LS has been set will result in the
SPI_FAIL bit being set and keeping the VCC3 configurations unchanged. Load sharing will be automatically
disabled (only if VCC3_LS_ STP_ON = 0) during SBC Stop Mode due to power saving reasons but the bit will
remain set to automatically switch back on after returning to SBC Normal Mode. It must be ensured that the
same VCC3 output voltage level is selected as for VCC1.
In this configuration VCC3 has no undervoltage signalization. VCC3 shuts down if Fail-Safe Mode is reached,
e.g. due to undervoltage shutdown (VS,UV monitoring).
VCC3 has no overcurrent limitation in this configuration and the shunt resistor is defining the load sharing
ratio between the VCC1 and VCC3 load currents (see Equation (8.2) in Chapter 8.4). Thus, no overcurrent
condition VCC3_OC will be signaled in this configuration.
Datasheet
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
VS
VCC13
RSHUNT
T1
ICC3
C1
C2
VS
VCC3SH
VCC3B
VCC3REF
Vcc3
Vcc1
ICC1
Figure 20 VCC3 in Load Sharing Configuration
8.3
External Components
Characterization is performed with the BCP52-16 from Infineon (ICC3 < 200 mA) and with MJD253.
Other PNP transistors can be used. However, the functionality must be checked in the application.
Figure 20 shows one hardware set up used.
Table 13
Device
C2
Bill of Materials for the VCC3 Function with and without load sharing configuration
Vendor
Murata
-
Reference / Value
10 µF/10 V GCM31CR71A106K64L
1 Ω (with / without LS)
BCP52-16
RSHUNT
T1
Infineon
Note:
The SBC is not able to ensure a thermal protection of the external PNP transistor. The power
handling capabilities for the application must therefore be chosen according to the selected PNP
device, the PCB layout and properties of the application to prevent thermal damage, e.g. via the
shunt current limitation in stand alone configuration or by selecting the proper ICC1/ICC3 ratio in
load-sharing configuration.
Note:
To ensure an optimum EMC behavior of the VCC3 regulator when the VCC3 output is leaving the PCB,
it is necessary to optimize the PCB layout to have the PNP very close to the SBC. If this is not sufficient
or possible, an external capacitance should be placed to the off-board connector (see also
Chapter 17.1).
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
8.4
Calculation of RSHUNT
As a independent regulator, the maximum current ICC3max where the limit starts and the bit ICC3 > ICC3max is set is
determined by the shunt resistor RSHUNT and the Output Current Shunt Voltage Threshold Vshunt_threshold
.
The resistor can be calculated as following:
Ushunt _ threshold
(8.1)
RSHUNT
=
ICC3 max
If VCC3 is configured for load sharing, then the shunt resistor determines the load sharing ratio between VCC1
and VCC3. The ratio can be calculated as following:
I CC
I CC
110 Ω 105 − 15 mV
I CC
1
3
1
=
( a )
(8.2)
R
SHUNT
I CC ⋅ 110 Ω 105 − 15 mV
1
I CC
=
( b )
3
R
SHUNT
Example: A shunt resistor with 470mΩ and a load current of 100mA out of VCC1 would result in ICC3 = 191mA.
8.5
Unused Pins
In case the VCC3 is not used in the application, it is recommended to connect the unused pins of VCC3 as
followed:
•
•
•
•
Connect VCC3SH to VS or leave open;
Leave VCC3B open;
Leave VCC3REF open
Do not enable the VCC3 via SPI as this leads to increased current consumption
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
8.6
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all outputs open; all voltages with respect to ground;
positive current defined flowing into pin; unless otherwise specified.
Table 14
Electrical Characteristics
Symbol
Parameter
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Parameters independent from Test Set-up
External Regulator Control IVCC3base
Drive Current Capability
40
60
3
80
10
10
310
5
mA VVCC3base = 13.5 V
P_8.6.1
P_8.6.2
P_8.6.3
P_8.6.6
P_8.6.7
P_8.6.8
P_8.6.9
Input Current VCC3ref
IVCC3ref
0
0
µA
µA
mV
µs
VVCC3ref = 5 V
Input Current VCC3
IVCC3shunt
3
VVCC3shunt = VS
Shunt Pin
1)
Output Current Shunt
Voltage Threshold
Vshunt_threshold 180
245
–
5)
Current increase regulation trIinc
reaction time
–
–
–
V
= 5 V to 0 V;
CC3
ICC3base = 20 mA Figure 21
5)
Current decrease regulation trIdec
reaction time
–
5
µs
V
= 0 V to 5V;
CC3
ICC3base = 20 mA Figure 21
Leakage current of
VCC3base when VCC3
disabled
IVCC3base_lk
–
5
µA
VCC3base = VS;
Tj = 25°C
Leakage current of VCC3shunt IVCC3shunt_lk
when VCC3 disabled
–
–
5
µA
VCC3shunt = VS;
Tj = 25°C
P_8.6.11
P_8.6.12
P_8.6.33
Base to emitter resistor
RBE
120
–
150
50
185
65
kΩ VCC3 = OFF;
Active Peak Threshold VCC3 IVCC3base,Ipeak,r
(Transition threshold
between low-power and
µA
5)Drive current IVCC3base
VCC3base rising
;
;
I
VS =13.5V;
-40°C < Tj < 150°C
5)Drive current IVCC3base
high-power mode regulator)
Active Peak Threshold VCC3 IVCC3base,Ipeak,f 15
(Transition threshold
between high-power and
30
–
µA
P_8.6.34
P_8.6.13
IVCC3base falling
VS =13.5V;
-40°C < Tj < 150°C
low-power mode regulator)
Parameters dependent on the Test Set-up (with external PNP device MJD-253)
External Regulator Output VCC3.out1
Voltage (VCC3 = 5.0V)
4.9
5
5.1
V
2)SBC Normal Mode;
load sharing
configuration with 470
mΩ shunt resistor;
10 µA < IVCC1 + IVCC3
< 300 mA;
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
Table 14
Electrical Characteristics (cont’d)
Symbol
Parameter
Values
Unit Note or Test Condition Number
Min. Typ. Max.
External Regulator Output VCC3,out2
Voltage
(VCC3 = 5.0V)
4.9
5
5.1
V
V
V
V
–
2)SBC Normal Mode;
stand-alone
configuration
10 mA < IVCC3 < 300 mA;
2)SBC Stop-, Sleep Mode; P_8.6.15
Stand-alone
configuration
10µA < IVCC3 < IVCC3_peak,r
2)SBC Normal Mode;
stand-alone
configuration
10 mA < IVCC3 < 300 mA;
2)SBC Stop-, Sleep Mode; P_8.6.23
Stand-alone
configuration
10µA < IVCC3 < IVCC3_peak,r
5)6)6.0V < VS < 28V;
SBC Normal Mode;
LS ratio for a 470 mΩ
shunt resistor and total
load current of 300mA
5)6)6.0V < VS < 28V;
P_8.6.14
External Regulator Output VCC3,out3
Voltage
(VCC3 = 5.0V)
4.8
5
5.24)
3)
External Regulator Output VCC3,out4
Voltage
(VCC3 = 3.3V)
3.23 3.3V 3.37
3.15 3.3V 3.454)
P_8.6.22
External Regulator Output VCC3,out5
Voltage
(VCC3 = 3.3V)
3)
Load Sharing Ratio
ICC1 : ICC3
RatioLS_1,VCC3 1 :
1 :
1 :
P_8.6.16
P_8.6.20
P_8.6.27
1.35 1.9
2.45
Load Sharing Ratio
ICC1 : ICC3
RatioLS_2,VCC3 1 :
1 :
1 :
–
–
0.67 0.95 1.23
SBC Normal Mode;
LS ratio for a 1 Ω shunt
resistor and total load
current of 300mA
5)6) Tj = 150°C;
8.0V < VS < 18V;
Load Sharing Ratio
ICC1 : ICC3
RatioLS_3,VCC3 1 :
1 :
1 :
1.50 1.95 2.40
SBC Normal Mode;
LS ratio for a 470 mΩ
shunt resistor and total
load current of 300mA
Load Sharing Ratio
ICC1 : ICC3
RatioLS_4,VCC3 1 :
1 :
1 :
–
5)6) Tj = 150°C;
8.0V < VS < 18V;
P_8.6.28
0.75 0.98 1.21
SBC Normal Mode;
LS ratio for a 1 Ω shunt
resistor and total load
current of 300mA
1) Threshold at which the current limitation starts to operate. This threshold is only active when VCC3 is configured for
stand-alone configuration.
2) Tolerance includes load regulation and line regulation.
3)
I
VCC3_peak refers to the load current out of the collector of the external PNP device. This value can be calculated by
multiplying the VCC3base active peak threshold (IVCC3base,Ipeak) with the current gain of the PNP
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External Voltage Regulator 3
4) At Tj > 125°C, the power transistor leakage could be increased, which has to be added to the quiescent current of the
application independently if the regulator is turned on/off. To prevent an overvoltage condition at no load due to this
increased leakage, an internal clamping structure will automatically turn on at typ. 200mV above the upper limit of the
programmed output voltage.
5) Not subject to production test, specified by design.
6) a) Ratio will change depending on the chosen shunt resistor which value is correlating to the maximum power
dissipation of the PNP pass device. See Chapter 8.4 for the ratio calculation. The ratio will also change at low-drop
operation.
For supply voltages of 5.5V < VS < 6V the accuracy applies only for a total load current of 250mA.
The load sharing ratio in SBC Stop Mode has +/-10% wider limits than specified.
b) The output voltage precision in load sharing in SBC Stop Mode is according to VCC1 +/-4% or better for loads up to
20mA and +/-2% with loads greater than 20mA.
In SBC Normal the +/-2% precision for 5V/3.3V tolerance is valid regardless of the applied load.
Notes
1. There is no thermal protection available for the external PNP transistor. Therefore, the application must be
designed to avoid overheating of the PNP via the shunt current limitation in stand alone configuration and by
selecting the proper ICC1/ICC3 ratio in load-sharing configuration.
2. In SBC Stop Mode, the same output voltage tolerance applies as in SBC Normal Mode when IVCC3 has exceeded
the selected active peak threshold (IVCC3base,Ipeak) but with increased current consumption.
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External Voltage Regulator 3
Timing diagram for regulator reaction time “current increase regulation reaction time” and “current decrease
regulation reaction time”
VCC3
t
ICCbase
ICC3base, 50%
t
trlinc
trldec
Figure 21 Regulator Reaction Time
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OPTIREG™ SBC TLE9262BQX
External Voltage Regulator 3
Typical Load Sharing Characteristics using the BCP52-16 PNP transistor and a 1 Ω shunt resistor
0,35
Tj = 27°C
0,30
Tj = 150°C
0,25
0,20
0,15
0,10
0,05
0
Tj = -40°C
0
0,2
0,4
0,6
0,8
- Icc3 vs. Icc1
1,0
1,2
1,4
Load Sharing Ratio
Figure 22 Load Sharing Ratio ICC1 : ICC3 vs. the total load current
0,35
Tj = 27°C
0,30
Tj = 150°C
0,25
0,20
0,15
0,10
0,05
0
Tj = -40°C
0
0,02
0,04
0,06
0,08
0,10
0,12
0,14
0,16
Load Current - Icc1
Figure 23 Load Sharing Behavior of ICC1 vs. the total load current
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OPTIREG™ SBC TLE9262BQX
High-Side Switch
9
High-Side Switch
9.1
Block Description
HSx
VSHS
HS Gate Control
Overcurrent Detection
Open Load (On)
Figure 24 High-Side Module Block Diagram
Features
•
•
•
•
•
•
Dedicated supply pin VSHS for high-side outputs
Overvoltage and undervoltage switch off - configurable via SPI
Overcurrent detection and switch off
Open load detection in ON-state
PWM capability with internal timer configurable via SPI
Switch recovery after removal of OV or UV condition configurable via SPI
9.2
Functional Description
The High-Side switches can be used for control of LEDs, as supply for the wake inputs and for other loads. The
High-Side outputs can be controlled either directly via SPI by (HS_CTRL1, HS_CTRL2), by the integrated
timers or by the integrated PWM generators.
The high-side outputs are supplied by a dedicated supply pin VSHS (different to VS). The topology supports
improved cranking condition behavior.
The configuration of the High-Side (Permanent On, PWM, cyclic sense, etc.) drivers must be done in SBC
Normal Mode. The configuration is taken over in SBC Stop- or SBC Sleep Mode and cannot be modified. When
entering SBC Restart Mode or SBC Fail-Safe Mode the HSx outputs are disabled.
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OPTIREG™ SBC TLE9262BQX
High-Side Switch
9.2.1
Over- and Undervoltage Switch Off
All HS drivers in on-state are switched off in case of overvoltage on VSHS (VSHS,OVD). If the voltage drops below
the overvoltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit
HS_OV_SD_EN.
The HS drivers are switched off in case of undervoltage on VSHS (VSHS,UVD). If the voltage rises above the
undervoltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit
HS_UV_SD_EN.
So after release of undervoltage or overvoltage condition the HS switch goes back to programmed state in
which it was configured via SPI. This behavior is only valid if the bit HS_OV_UV_REC is set to ‘1’. Otherwise the
switches will stay off and the respective SPI control bits are cleared.
The overvoltage and undervoltage is signaled in the bits VSHS_OV and VSHS_UV, no other error bits are set.
9.2.2
Overcurrent Detection and Switch Off
If the load current exceeds the overcurrent shutdown threshold for a time longer then the overcurrent
shutdown filter time the output is switched off.
The overcurrent condition and the switch off is signaled with the respective HSx_OC_OT bit in the register
HS_OC_OT_STAT. The HSx configuration is then reset to 000 by the SBC. To activate the High-Side again the
HSx configuration has to be set to ON (001) or be programmed to a timer function. It is recommended to clear
the overcurrent bit before activation the High-Side switch, as the bits are not cleared automatically by the
SBC.
9.2.3
Open Load Detection
Open load detection on the High-Side outputs is done during on state of the output. If the current in the
activated output falls below then Open Load Detection current, the open load is detected and signaled via the
respective bit HS1_OL, HS2_OL, HS3_OL, or HS4_OL in the register HS_OL_STAT. The High-Side output stays
activated. If the open load condition disappears the Open Load bit in the SPI can be cleared. The bits are not
cleared automatically by the SBC.
9.2.4
HSx Operation in Different SBC Modes
•
During SBC Stop and SBC Sleep Mode the HSx outputs can be used for the cyclic sense feature. The open-
load detection, overcurrent shut down as well as overvoltage and undervoltage shutdown are available.
The overcurrent shutdown protection feature may influence the wake-up behavior1).
•
•
the HSx output can also be enabled for SBC Stop and SBC Sleep Mode as well as controlled by the PWMx
generator. The HSx outputs must be configured in SBC Normal Mode before entering a low-power mode.
The HSx outputs are switched off during SBC Restart or SBC Fail-Safe Mode. They can be enabled via SPI if
the failure condition is removed.
9.2.5
PWM and Timer Function
Two 8-bit PWM generators are dedicated to generate a PWM signal on the HS outputs, e.g. for brightness
adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated
HS outputs, and the duty cycle can be independently configured with a 8bit resolution via SPI (PWM1_CTRL,
1) For the wake feature, the forced overcurrent shut down case must be considered in the user software for all SBC Modes, i.e. due to
disabled HSx switches a level change might not be detected anymore at WKx pins.
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OPTIREG™ SBC TLE9262BQX
High-Side Switch
PWM2_CTRL). Two different frequencies (200Hz, 400Hz) can be selected independently for every PWM
generator in the register PWM_FREQ_CTRL.
PWM Assignment and Configuration:
•
Configure duty cycle and frequency for respective PWM generator in PWM1_CTRL/PWM2_CTRL and
PWM_FREQ_CTRL
•
•
Assign PWM generator to respective HS switch(es) in HSx_CTRL
The PWM generation will start right after the HSx is assigned to the PWM generator (HS_CTRL1, HS_CTRL2)
Assignment options of HS1... HS4
•
•
•
•
Timer 1
Timer 2
PWM 1
PWM 2
Minimum On-time during PWM Operation
The min. on-time during PWM is limited by the actual on- and off-time of the respective HS switch, e.g. the
PWM setting ‘0000 0001’ could not be realized.
Reliable Open-Load Detection during PWM Operation
The minimum PWM setting for a reliable open-load detection is 3digits for a period of 400Hz and >2 digits for
the frequency setting of 200Hz, i.e. the high-side on-time must be longer than tOL,HS
.
Reliable Overcurrent Detection during PWM Operation
The minimum PWM setting for a reliable overcurrent detection is >1 digit for a period of 400Hz and 1 digit for
the frequency setting of 200Hz, i.e. the high-side on-time must be longer than tSD,HS
.
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OPTIREG™ SBC TLE9262BQX
High-Side Switch
9.3
Electrical Characteristics
Table 15
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Output HS1, HS2, HS3, HS4
Static Drain-Source ON
Resistance HS1...HS4
RON,HS25
RON,HS150
Ileak,HS
–
–
–
7
10
16
2
Ω
Ids = 60mA,
Tj < 25°C
P_9.3.1
P_9.3.2
P_9.3.11
Static Drain-Source ON
Resistance HS1...HS4
11.5
–
Ω
Ids = 60mA,
Tj < 150°C
1)0 V < VHSx
Leakage Current HSx / per
channel
µA
< VSHS
;
Tj < 85°C
Output Slew Rate (rising)
Output Slew Rate (falling)
Switch-on time HSx
SRraise,HS
SRfall,HS
tON,HS
0.8
-2.5
3
–
–
–
2.5
-0.8
30
V/µs 1)20 to 80%
VSHS = 6 to 18V
RL = 220Ω
P_9.3.3
P_9.3.4
P_9.3.5
V/µs 1)80 to 20%
VSHS = 6 to 18V
RL = 220Ω
µs
CSN = HIGH to
0.8*VSHS;
RL = 220Ω;
VSHS = 6 to 18V
Switch-off time HSx
tOFF,HS
3
–
30
µs
CSN = HIGH to
0.2*VSHS;
RL = 220Ω;
P_9.3.6
P_9.3.7
VSHS = 6 to 18V
Short Circuit Shutdown
Current
ISD,HS
150
245
300
mA
VSHS = 6 to 20V,
hysteresis
included
2) 3)
Short Circuit Shutdown
Filter Time
tSD,HS
12
16
–
20
3
µs
,
P_9.3.8
P_9.3.9
P_9.3.14
P_9.3.10
Open Load Detection
Current
IOL,HS
0.4
0.05
50
mA
mA
µs
hysteresis
included
1)
Open Load Detection
hysteresis
IOL,HS,hys
0.45
64
1.0
80
2) 3)
Open Load Detection Filter tOL,HS
,
Time
1) Not subject to production test, specified by design.
2) Not subject to production test, tolerance defined by internal oscillator tolerance.
3) Configure proper minimum PWM settings for reliable detection of overcurrent and open load measurement (see also
Chapter 9.2.5).
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OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
10
High Speed CAN Transceiver
10.1
Block Description
VCAN
VCC1
SPI Mode
Control
RTXD
Driver
CANH
CANL
Output
Stage
TXDCAN
Temp.-
Protection
+
timeout
To SPI diagnostic
VCAN
VBIAS = 2.5V
VCC1
RXDCAN
MUX
Receiver
Vs
Wake
Receiver
Figure 25 Functional Block Diagram
10.2
Functional Description
The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode
data transmission (up to 2 Mbaud) and reception in automotive and industrial applications. It works as an
interface between the CAN protocol controller and the physical bus lines compatible to ISO 11898-2:2016 and
SAE J2284.
The CAN transceiver offers low power modes to reduce current consumption. This supports networks with
partially powered down nodes. To support software diagnostic functions, a CAN Receive-only Mode is
implemented.
It is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks,
clamp15/30 applications).
A wake-up from the CAN wake capable mode is possible via a message on the bus. Thus, the microcontroller
can be powered down or idled and will be woken up by the CAN bus activities.
The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support
12 V applications.
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High Speed CAN Transceiver
The different transceiver modes can be controlled via the SPI CAN bits.
Figure 26 shows the possible transceiver mode transitions when changing the SBC mode.
SBC Mode
CAN Transceiver Mode
SBC Stop Mode
Receive Only Wake Capable Normal Mode
OFF
OFF
SBC Normal Mode
SBC Sleep Mode
SBC Restart Mode
SBC Fail-Safe Mode
Receive Only Wake Capable Normal Mode
Wake Capable2
OFF2
OFF
Woken1
Wake Capable
Behavior after SBC Restart Mode - not coming from SBC Sleep Mode due to a wake up of the respective transceiver:
If the transceivers had been configured to Normal Mode, or Receive Only Mode, then the mode will be changed to Wake
Capable. If it was Wake Capable, then it will remain Wake Capable. If it had been OFF before SBC Restart Mode, then it
will remain OFF.
Behavior in SBC Development Mode:
CAN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF.
1 After a wake event on CAN Bus.
2 Must be set to CAN wake capable / CAN off mode before entering SBC Sleep Mode.
Figure 26 CAN Mode Control Diagram
CAN FD Support
CAN FD stands for ‘CAN with Flexible Data Rate’. It is based on the well established CAN protocol as specified
in ISO 11898-1. CAN FD still uses the CAN bus arbitration method. The benefit is that the bit rate can be
increased by switching to a shorter bit time at the end of the arbitration process and then to return to the
longer bit time at the CRC delimiter, before the receivers transmit their acknowledge bits. See also Figure 27.
In addition, the effective data rate is increased by allowing longer data fields. CAN FD allows the transmission
of up to 64 data bytes compared to the 8 data bytes from the standard CAN.
Standard CAN
message
Data phase
(Byte 0 – Byte 7)
CAN Header
CAN Footer
Example:
- 11bit identifier + 8Byte data
CAN FD with
reduced bit time
Data phase
(Byte 0 – Byte 7)
CAN Header
CAN Footer
- Arbitration Phase
- Data Phase
500kbps
2Mbps
àaverage bit rate
1.14Mbps
Figure 27 Bite Rate Increase with CAN FD vs. Standard CAN
Not only the physical layer must support CAN FD but also the CAN controller. In case the CAN controller is not
able to support CAN FD then the respective CAN node must at least tolerate CAN FD communication. This
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High Speed CAN Transceiver
CAN FD tolerant mode is realized in the physical layer in combination with CAN Partial Networking.
The TLE926x-3BQX variants of this family also support the CAN FD tolerant mode.
10.2.1
CAN OFF Mode
The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is
intended to completely stop CAN activities or when CAN communication is not needed. The CANH/L bus
interface acts as a high impedance input with a very small leakage current. In CAN OFF Mode, a wake-up event
on the bus will be ignored.
10.2.2
CAN Normal Mode
The CAN Transceiver is enabled via SPI in SBC Normal Mode. CAN Normal Mode is designed for normal data
transmission/reception within the HS-CAN network. The Mode is available in SBC Normal Mode and in SBC
Stop Mode. The bus biasing is set to VCAN/2.
Transmission
The signal from the microcontroller is applied to the TXDCAN input of the SBC. The bus driver switches the
CANH/L output stages to transfer this input signal to the CAN bus lines.
Enabling sequence
The CAN transceiver requires an enabling time tCAN,EN before a message can be sent on the bus. This means
that the TXDCAN signal can only be pulled LOW after the enabling time. If this is not ensured, then the TXDCAN
needs to be set back to HIGH (=recessive) until the enabling time is completed.
Only the next dominant bit will be transmitted on the bus.
Figure 28 shows different scenarios and explanations for CAN enabling.
V
TXDCAN
t
CAN
Mode
t CAN,EN
tCAN,EN
t CAN,EN
CAN
NORMAL
CAN
OFF
t
t
V
CANDIFF
Dominant
Recessive
recessive TXD level
required before start of
transmission
Correct sequence ,
Bus is enabled after tCAN,
tCAN, EN not ensured , no
transmission on bus
tCAN, not ensured ,
no transmission on bus
recessive TXD
level required
EN
EN
Figure 28 CAN Transceiver Enabling Sequence
Reduced Electromagnetic Emission
To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically.
Reception
Analog CAN bus signals are converted into digital signals at RXD via the differential input receiver.
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High Speed CAN Transceiver
10.2.3
CAN Receive Only Mode
In CAN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still operational. This
mode is accessible by an SPI command in Normal Mode and in Stop Mode. The bus biasing is set to VCAN/2.
10.2.4
CAN Wake Capable Mode
This mode can be used in SBC Stop, Sleep, Restart and Normal Mode and it is used to monitor bus activities.
It is automatically accessed in SBC Fail-Safe Mode. Both bus pins CANH/L are connected to GND via the input
resistors.
A wake-up signal on the bus results in a change of behavior of the SBC, as described in Table 16. The pins
CANH/L are terminated to typ. 2.5V through the input resistors. As a wake-up signalization to the
microcontroller, the RXD_CAN pin is set LOW and will stay LOW until the CAN transceiver is changed to any
other mode. After a wake-up event, the transceiver can be switched to CAN Normal Mode for communication
via SPI.
As shown in Figure 29, a wake-up pattern (WUP) is signaled on the bus by two consecutive dominant bus
levels for at least tWake1 (filter time t > tWake1) and shorter than tWake2, each separated by a recessive bus level
of greater than tWake1 and shorter than tWake2
.
Datasheet
69
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
Entering low-power mode,
when selective wake-up
function is disabled
or not supported
Bus recessive > tWAKE1
Ini
Wait
Bias off
Bias off
Bus dominant > tWAKE1
optional:
tWAKE2 expired
1
Bias off
Bus recessive > tWAKE1
optional:
tWAKE2 expired
2
Bias off
Bus dominant > tWAKE1
Silence expired AND
t
Entering CAN Normal
or CAN Recive Only
Device in low-power mode
3
Bias on
Bus dominant > tWAKE1
Bus recessive > tWAKE1
tSilence expired AND
device in low-power mode
4
Bias on
Figure 29 WUP detection following the definition in ISO 11898-2:2016
Rearming the Transceiver for Wake Capability
After a BUS wake-up event, the transceiver is woken. However, the CAN transceiver mode bits will still show
wake capable (=‘01’) so that the RXD signal will be pulled low. There are two possibilities how the CAN
transceiver’s wake capable mode is enabled again after a wake event:
•
•
•
The CAN transceiver mode must be toggled, i.e. switched from Wake Capable Mode to CAN Normal Mode,
CAN Receive Only Mode or CAN Off, before switching to CAN Wake Capable Mode again.
Rearming is done automatically when the SBC is changed to SBC Stop or SBC Fail-Safe Mode to ensure
wake-up capability.
CAN must be set to CAN wake capable / CAN off mode before entering SBC Sleep Mode
Notes
1. It is not necessary to clear the CAN wake-up bit CAN_WU to become wake capable again. It is sufficient to
toggle the CAN mode.
2. The CAN module is supplied by an internal voltage when in CAN Wake Capable Mode, i.e. the module does not
need to be supplied by the VCAN pin during this time. Before changing the CAN Mode to Normal Mode, the
supply of VCAN has to be activated first.
Datasheet
70
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
Wake-Up in SBC Stop and Normal Mode
In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INT output and in the WK_STAT_1 SPI
register. It is also signaled by RXDCAN pulled to low. The same applies for the SBC Normal Mode. The
microcontroller should set the device from SBC Stop Mode to SBC Normal Mode, there is no automatic
transition to Normal Mode.
For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a Bus wake
event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to HIGH before).
Wake-Up in SBC Sleep Mode
Wake-up is possible via a CAN message (filter time t > tWake1). The wake-up automatically transfers the SBC into
the SBC Restart Mode and from there to Normal Mode the corresponding RXD pin in set to LOW. The
microcontroller is able to detect the low signal on RXD and to read the wake source out of the WK_STAT_1
register via SPI. No interrupt is generated when coming out of Sleep Mode. The microcontroller can now for
example switch the CAN transceiver into CAN Normal Mode via SPI to start communication.
Table 16
Action due to CAN Bus Wake-Up
SBC Mode after Wake
Normal Mode
SBC Mode
Normal Mode
Stop Mode
Sleep Mode
Restart Mode
VCC1
INT
RXD
LOW
LOW
LOW
LOW
LOW
ON
LOW
LOW
HIGH
HIGH
HIGH
Stop Mode
ON
Restart Mode
Ramping Up
ON
Restart Mode
Fail-Safe Mode
Restart Mode
Ramping up
10.2.5
TXD Time-out Feature
If the TXD signal is dominant for a time t > tTXD_CAN_TO, in CAN Normal Mode, the TXD time-out function
deactivates the transmission of the signal at the bus. This is implemented to prevent the bus from being
blocked permanently due to an error. The transmitter is disabled and the transceiver is switched to Receive
Only Mode. The failure is stored in the SPI flag CAN_FAIL. The CAN transmitter stage is activated again after
the dominant time-out condition is removed and the transceiver is automatically switched back to CAN
Normal Mode. The transceiver configuration stays unchanged.
10.2.6
Bus Dominant Clamping
If the HS CAN bus signal is dominant for a time t > tBUS_CAN_TO in CAN Normal and Receive Only Mode a bus
dominant clamping is detected and the SPI bit CAN_FAIL is set. The transceiver configuration stays
unchanged.
10.2.7
Undervoltage Detection
The voltage at the CAN supply pin is monitored only in CAN Normal and Receive Only Mode for SBC Normal
and Stop Mode . In case of VCAN undervoltage a signalization via SPI bit VCAN_UV is triggered and the SBC
disables the transmitter stage. If the CAN supply reaches a higher level than the undervoltage detection
threshold (VCAN > VCAN_UV), the transceiver is automatically switched back to CAN Normal Mode. The
transceiver configuration stays unchanged.
Datasheet
71
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
10.3
Electrical Characteristics
Table 17
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Uni Note or
Number
t
Test Condition
Min.
Max.
CAN Bus Receiver
Differential Receiver
Threshold Voltage,
recessive to dominant edge
Vdiff,rd_N
–
0.80
0.90
V
Vdiff = VCANH - VCANL
;
P_10.3.2
-12V ≤ VCM(CAN) ≤ +12V;
0.9 V ≤ Vdiff,D_Range ≤ 8 V;
CAN Normal Mode
1)
Dominant state differential Vdiff_D_range 0.9
input voltage range
–
8.0
–
V
V
V
= VCANH - VCANL
;
P_10.3.59
P_10.3.3
diff
-12V ≤ VCM(CAN) ≤ +12V;
CAN Normal Mode
Differential Receiver
Threshold Voltage,
dominant to recessive edge
Vdiff,dr_N
0.50
0.60
Vdiff = VCANH -VCANL;
-12V ≤ VCM(CAN) ≤ +12V;
-3 V ≤ Vdiff,R_Range ≤ 0.5 V;
CAN Normal Mode
1)
Recessive state differential Vdiff_R_range -3.0
input voltage range
–
0.5
V
V
V
= VCANH - VCANL
;
P_10.3.60
diff
-12V ≤ VCM(CAN) ≤ +12V;
CAN Normal Mode
1)
Common Mode Range
CMR
-12
20
–
12
50
P_10.3.4
P_10.3.6
CANH, CANL Input
Resistance
Rin
40
kΩ CAN Normal / Wake
capable Mode;
Recessive state;
-2 V ≤ VCANL/H ≤ +7 V
Differential Input Resistance Rdiff
40
80
100
kΩ CAN Normal / Wake
capable Mode;
P_10.3.7
Recessive state;
-2 V ≤ VCANL/H ≤ +7 V
Input Resistance Deviation ΔRi
between CANH and CANL
-3
–
–
3
%
pF
pF
V
1)Recessive state;
VCANH = VCANL = 5 V
P_10.3.38
P_10.3.39
P_10.3.40
2)
Input Capacitance CANH,
CANL versus GND
Cin
20
10
0.8
40
20
1.15
V
= 5 V
TXD
2)
Differential Input
Capacitance
Cdiff
–
V
= 5 V
TXD
Wake-up Receiver
Vdiff, rd_W
–
-12V ≤ VCM(CAN) ≤ +12V; P_10.3.8
1.15 V ≤Vdiff,D_Range ≤8 V;
CAN Wake Capable
Mode
Threshold Voltage,
recessive to dominant edge
Datasheet
72
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
Table 17
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Uni Note or
Number
t
Test Condition
Min.
Max.
Wake-up Receiver Dominant Vdiff,D_range 1.15
state differential input
8.0
V
1)-12V ≤ VCM(CAN) ≤
+12V;
P_10.3.61
_W
voltage range
CAN Wake Capable
Mode
Wake-up Receiver
Threshold Voltage,
dominant to recessive edge
Vdiff, dr_W
0.4
0.7
–
–
V
V
-12V ≤ VCM(CAN) ≤ +12V; P_10.3.9
-3 V ≤ Vdiff,R_Range ≤ 0.4 V;
CAN Wake Capable
Mode
Wake-up Receiver Recessive Vdiff,R_range_ -3.0
state differential input
0.4
1)-12V ≤ VCM(CAN) ≤
+12V;
P_10.3.62
W
voltage range
CAN Wake Capable
Mode
CAN Bus Transmitter
CANH/CANL Recessive
Output Voltage
(CAN Normal Mode)
VCANL/H_NM 2.0
–
–
–
3.0
0.1
50
V
V
CAN Normal Mode;
P_10.3.11
P_10.3.43
P_10.3.12
VTXD = VCC1
;
no load
CANH/CANL Recessive
Output Voltage
(CAN Wake Capable Mode)
VCANL/H_LP -0.1
CAN Wake Capable
Mode; VTXD = VCC1
;
no load
CANH, CANL Recessive
Output Voltage Difference
Vdiff = VCANH - VCANL
Vdiff_r_N
Vdiff_r_W
VCANL
-500
-200
0.5
mV CAN Normal Mode
VTXD = VCC1
;
no load
(CAN Normal Mode)
CANH, CANL Recessive
Output Voltage Difference
Vdiff = VCANH - VCANL
–
200
2.25
4.5
mV CAN Wake Capable
Mode;
P_10.3.41
P_10.3.13
P_10.3.14
P_10.3.16
V
TXD = VCC1
no load
CAN Normal Mode;
TXD = 0 V;
VCAN = 5 V
;
(CAN Wake Capable Mode)
CANL Dominant Output
Voltage
–
V
V
V
V
;
50Ω ≤ RL ≤ 65Ω
CANH Dominant Output
Voltage
VCANH
2.75
1.5
–
CAN Normal Mode;
V
V
TXD = 0 V;
CAN = 5 V;
50Ω ≤ RL ≤ 65Ω
CANH, CANL Dominant
Output Voltage Difference
Vdiff = VCANH - VCANL
Vdiff_d_N
2.0
2.5
CAN Normal Mode;
VTXD = 0 V;
VCAN = 5 V;
50Ω ≤ RL ≤ 65Ω
Datasheet
73
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
Table 17
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Uni Note or
Number
t
Test Condition
1)CAN Normal Mode;
TXD = 0 V;
Min.
Max.
CANH, CANL Dominant
Output Voltage Difference
Vdiff = VCANH - VCANL
Vdiff_d_N
1.5
5.0
V
P_10.3.55
V
VCAN = 5 V;
RL = 2240Ω
CANH, CANL Dominant
Output Voltage Difference
Vdiff = VCANH - VCANL
Vdiff_d_N
1.4
–
–
–
–
–
3.3
70
V
1)CAN Normal Mode;
P_10.3.56
P_10.3.57
P_10.3.58
P_10.3.42
VTXD = 0 V;
VCAN = 5 V;
45Ω ≤ RL ≤ 70Ω
CANH, CANL output voltage Vdiff_slope_rd
difference slope, recessive
to dominant
V/us 1)30% to 70% of
measured differential
bus voltage,
CL = 100 pF, RL = 60 Ω
CANH, CANL output voltage Vdiff_slope_dr
difference slope, dominant
to recessive
–
70
V/us 1)70% to 30% of
measured differential
bus voltage,
CL = 100 pF, RL = 60 Ω
Driver Symmetry
VSYM = VCANH + VCANL
VSYM
4.5
5.5
V
3)CAN Normal Mode;
TXD = 0 V / 5 V;
VCAN = 5 V;
SPLIT = 4.7nF;
RL = 60Ω;
V
C
CANH Short Circuit Current ICANHsc
CANL Short Circuit Current ICANLsc
-115
50
–
-80
80
5
-50
115
7.5
mA CAN Normal Mode;
P_10.3.17
P_10.3.18
P_10.3.19
VCANHshort = -3 V
mA CAN Normal Mode
VCANLshort = 18 V
Leakage Current
ICANH,lk
ICANL,lk
µA VS = VCAN = 0V;
(unpowered device)
0V < VCANH,L ≤ 5V;
4)
R
= 0 / 47 kΩ
test
Receiver Output RXD
HIGH level Output Voltage
VRXD,H
VRXD,L
0.8 ×
VCC1
–
–
–
V
V
CAN Normal Mode
RXD(CAN) = -2 mA;
CAN Normal Mode
IRXD(CAN) = 2 mA;
P_10.3.21
P_10.3.22
I
LOW Level Output Voltage
–
0.2 ×
VCC1
Transmission Input TXD
HIGH Level Input Voltage
Threshold
VTXD,H
–
–
0.7 ×
VCC1
V
CAN Normal Mode
recessive state
P_10.3.23
Datasheet
74
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
Table 17
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Uni Note or
Number
t
Test Condition
Min.
Max.
LOW Level Input Voltage
Threshold
VTXD,L
0.3 ×
VCC1
–
V
CAN Normal Mode
dominant state
1)
P_10.3.24
P_10.3.25
TXD Input Hysteresis
VTXD,hys
0.08 × 0.12 × 0.5 ×
V
VCC1
20
8
VCC1
VCC1
TXD Pull-up Resistance
RTXD
40
80
kΩ
–
P_10.3.26
P_10.3.27
CAN Transceiver Enabling
Time
tCAN,EN
13
18
µs 5)CSN = HIGH to first
valid transmitted TXD
dominant
Dynamic CAN-Transceiver Characteristics
Min. Dominant Time for Bus tWake1
0.50
–
1.8
µs -12V ≤ VCM(CAN) ≤ +12 V; P_10.3.28
Wake-up
CAN Wake capable
Mode
Wake-up Time-out,
Recessive Bus
tWake2
0.8
–
–
–
10
ms 5)CAN Wake capable
Mode
µs 5)6)7) Wake-up reaction P_10.3.44
time after a valid WUP
P_10.3.29
WUP Wake-up
Reaction Time
tWU_WUP
100
on CAN bus;
Loop delay
tLOOP,f
–
–
150
150
255
255
ns 3)CAN Normal Mode
CL = 100 pF;
P_10.3.30
(recessive to dominant)
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF
Loop delay
tLOOP,r
ns 3)CAN Normal Mode
CL = 100 pF;
P_10.3.31
(dominant to recessive)
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF
Propagation Delay
TXD LOW to bus dominant
td(L),T
td(H),T
td(L),R
–
–
–
50
–
–
–
ns CAN Normal Mode
CL = 100pF;
P_10.3.32
P_10.3.33
P_10.3.34
50Ω ≤ RL ≤ 65Ω;
VCAN = 5 V;
Propagation Delay
TXD HIGH to bus recessive
50
ns CAN Normal Mode
CL = 100 pF;
50Ω ≤ RL ≤ 65Ω;
VCAN = 5 V;
Propagation Delay
bus dominant to RXD LOW
100
ns CAN Normal Mode
CL = 100pF;
50Ω ≤ RL ≤ 60Ω;
VCAN = 5 V;
CRXD = 15 pF
Datasheet
75
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
Table 17
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
100
Uni Note or
Number
t
Test Condition
Min.
Max.
Propagation Delay
bus recessive to RXD HIGH
td(H),R
–
–
ns CAN Normal Mode
CL = 100pF;
P_10.3.35
50Ω ≤ RL ≤ 60Ω;
VCAN = 5 V;
CRXD = 15 pF
Received Recessive Bit
Width
(CAN FD up to 2Mbps)
tbit(RXD)
400
435
-65
–
–
–
–
550
530
40
ns CAN Normal Mode
CL = 100pF;
P_10.3.46
P_10.3.47
P_10.3.48
P_10.3.52
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF;
tbit(TXD) = 500ns;
Timing definition
according to Figure 31
TransmittedRecessive Bit
Width
(CAN FD up to 2Mbps)
tbit(BUS)
ns CAN Normal Mode
CL = 100pF;
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF;
tbit(TXD) = 500ns;
Timing definition
according to Figure 31
Receiver Timing Symmetry ∆tRec
(CAN FD up to 2Mbps)
ns CAN Normal Mode
CL = 100pF;
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF;
tbit(TXD) = 500ns;
Timing definition
according to Figure 31
Received Recessive Bit
Width
tbit(RXD)
120
220
ns CAN Normal Mode;
CL = 100pF;
(CAN FD up to 5 Mbps)
RL = 60 Ω;
V
CAN = 5 V;
CRXD = 15 pF;
bit(TXD) = 200 ns;
t
Parameter definition in
according to
Figure 31.
Datasheet
76
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
Table 17
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Uni Note or
Number
t
Test Condition
Min.
Max.
Transmitted Recessive Bit
Width
tbit(BUS)
155
210
ns CAN Normal Mode;
CL = 100pF;
P_10.3.53
(CAN FD up to 5 Mbps)
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF;
tbit(TXD) = 200 ns;
Parameter definition in
according to
Figure 31.
Receiver Timing Symmetry ∆tRec
(CAN FD up to 5 Mbps)
-45
–
15
ns CAN Normal Mode;
CL = 100pF;
P_10.3.54
RL = 60 Ω;
V
CAN = 5 V;
CRXD = 15 pF;
bit(TXD) = 200 ns;
t
Parameter definition in
according to
Figure 31.
TXD Permanent Dominant tTxD_CAN_TO 1.6
Time-out
2
2
2.4
2.4
ms 5)CAN Normal Mode
P_10.3.36
P_10.3.37
BUS Permanent Dominant tBUS_CAN_TO 1.6
ms 5)CAN Normal Mode
Time-out
5)
Timeout for bus inactivity
Bus Bias reaction time
tSILENCE
tBias
0.6
–
–
–
1.2
s
P_10.3.50
P_10.3.51
5)
200
µs
1) Not subject to production test, specified by design.
2) Not subject to production test, specified by design, S2P - Method; f = 10 MHz.
3) VSYM shall be observed during dominant and recessive state and also during the transition dominant to recessive and
vice versa while TXD is simulated by a square signal (50% duty cycle) with a frequency of up to 1 MHz (2 MBit/s).
4) Rtest between supply (VS / VCAN) and 0V (GND).
5) Not subject to production test, tolerance defined by internal oscillator tolerance.
6) Wake-up is signalized via INT pin activation in SBC Stop Mode and via VCC1 ramping up with wake from SBC Sleep
Mode.
7) Time starts with end of last dominant phase of WUP.
Datasheet
77
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
High Speed CAN Transceiver
V
TXDCAN
Vcc1
GND
t
t
VDIFF
td(L),T
td(H),T
V diff, rd_N
Vdiff, dr_N
t d(L),R
t d(H),R
tLOOP,f
tLOOP,r
VRXDCAN
V
cc1
0.8 x Vcc1
0.2 x Vcc1
GND
t
Figure 30 Timing Diagrams for Dynamic Characteristics
70%
TXDCAN
30%
tLoop_f
5x tBit(TXD)
tBit(TXD)
Vdiff=CANH-CANL
900mV
tBit(Bus)
500mV
70%
RXDCAN
30%
tLoop_r
Figure 31 From ISO 11898-2: tloop, tbit(TXD), tbit(Bus), tbit(RXD) definitions
tBit(RXD)
Datasheet
78
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
LIN Transceiver
11
LIN Transceiver
11.1
Block Description
VSHS
SPI Mode Control
VCC1
Driver
TxD Input
Temp.-
Protection
Current
RTxD
RBUS
Output
Stage
TXDLIN
Timeout
Limit
LIN
To SPI Diagnostic
Receiver
VCC1
Filter
VSHS
RXDLIN
Wake
Receiver
Figure 32 Block Diagram
11.1.1
LIN Specifications
The LIN network is standardized by international regulations.
The device is compliant to the physical layer standard LIN 2.2/ISO 17987-4 and SAE J2602-2. The SAE J2602-2
standard differs from the LIN 2.2/ISO 17987-4 standard mainly by the lower data rate (10.4 kbit/s).
Datasheet
79
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
LIN Transceiver
11.2
Functional Description
The LIN Bus is a single wire, bi-directional bus, used for in-vehicle networks. The LIN transceivers implemented
inside the TLE9262BQX are the interface between the micro controller and the physical LIN Bus. The digital
output data from the micro controller are driven to the LIN bus via the TXD input pin on the TLE9262BQX. The
transmit data stream on the TXD input is converted to a LIN bus signal with optimized slew rate to minimize
the EME level of the LIN network. The RXD output sends back the information from the LIN bus to the micro
controller. The receiver has an integrated filter network to suppress noise on the LIN Bus and to increase the
EMI (Electro Magnetic Immunity) level of the transceiver.
Two logical states are possible on the LIN Bus according to LIN 2.2/ISO 17987-4.
Every LIN network consists of a master node and one or more slave nodes. To configure the TLE9262BQX for
master node applications, a resistor in the range of 1 kΩ and a reverse diode must be connected between the
LIN bus and the power supply VSHS.
The different transceiver modes can be controlled via the SPI LIN1 bits.
Figure 33 shows the possible transceiver mode transitions when changing the SBC mode.
SBC Mode
LIN Transceiver Mode
SBC Stop Mode
Receive Only Wake Capable Normal Mode
OFF
OFF
SBC Normal Mode
SBC Sleep Mode
SBC Restart Mode
SBC Fail-Safe Mode
Receive Only Wake Capable Normal Mode
Wake Capable
OFF
OFF
Woken1
Wake Capable
1after a wake event on LIN Bus
Behavior after SBC Restart Mode - not coming from SBC Sleep Mode due to a wake up of the respective transceive:r
If the transceivers had been configured to Normal Mode, or Receive Only Mode, then the mode will be changed to Wake
Capable. If it was Wake Capable, then it will remainWake Capable. If it had been OFF before SBC Restart Mode, then it
will remain OFF.
Behavior in SBC Development Mode:
LIN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF.
Figure 33 LIN Mode Control Diagram
11.2.1
LIN OFF Mode
The LIN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is
intended to completely stop LIN activities or when LIN communication is not needed. In LIN OFF Mode, a
wake-up event on the bus will be ignored.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
LIN Transceiver
11.2.2
LIN Normal Mode
The LIN Transceiver is enabled via SPI in SBC Normal Mode. LIN Normal Mode is designed for normal data
transmission/reception within the LIN network. The Mode is available in SBC Normal Mode and in SBC Stop
Mode.
Transmission
The signal from the microcontroller is applied to the TXDLIN input of the SBC. The bus driver switches the
LIN output stage to transfer this input signal to the LIN bus line.
Enabling Sequence
The LIN transceiver requires an enabling time tLIN,EN before a message can be sent on the bus. This means that
the TXDLIN signal can only be pulled LOW after the enabling time. If this is not ensured, then the TXDLIN needs
to be set back to high (=recessive) until the enabling time is completed.
Only the next dominant bit will be transmitted on the bus.
Figure 34 shows different scenarios and explanations for LIN enabling.
VTXDLIN
t
LIN
Mode
t LIN ,EN
t LIN,EN
t LIN,EN
LIN
NORMAL
LIN OFF
t
t
V
LIN_BUS
Recessive
Dominant
recessive TXD level
required before start of
transmission
Correct sequence ,
Bus is enabled after tLIN, EN
tLIN, EN not ensured , no
transmission on bus
tLIN, not ensured ,
no transmission on bus
recessive TXD
level required
EN
Figure 34 LIN Transceiver Enabling Sequence
Reduced Electromagnetic Emission
To reduce electromagnetic emissions (EME), the bus driver controls LIN slopes symmetrically. The
configuration of the different slopes is described in Chapter 11.2.8.
Reception
Analog LIN bus signals are converted into digital signals at RXD via the differential input receiver.
11.2.3
LIN Receive Only Mode
In LIN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still possible. This mode
is accessible by an SPI command and is available in SBC Normal and SBC Stop Mode.
11.2.4
LIN Wake Capable Mode
This mode can be used in SBC Stop, Sleep, Restart and Normal Mode by programming via SPI and it is used to
monitor bus activities. It is automatically accessed in SBC Fail-Safe Mode. A wake up is detected, if a recessive
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
LIN Transceiver
to dominant transition on the LIN bus is followed by a dominant level of longer than tWK,Bus, followed by a
dominant to recessive transition. The dominant to recessive transition will cause a wake up of the LIN
transceiver. A wake-up results in a different behavior of the SBC, as described in below Table 18. As a
signalization to the microcontroller, the RXD_LIN pin is set LOW and will stay LOW until the LIN transceiver is
changed to any other mode. After a wake-up event the transceiver can be switched to LIN Normal Mode for
communication.
Rearming the transceiver for wake capability
After a BUS wake-up event, the transceiver is woken. However, the LIN1 transceiver mode bits will still show
wake capable (=‘01’) so that the RXD signal will be pulled low. There are two possibilities how the LIN
transceiver’s wake capable mode is enabled again after a wake event:
•
The LIN transceiver mode must be toggled, i.e. switched to LIN Normal Mode, LIN Receive Only Mode or LIN
Off, before switching to LIN Wake Capable Mode again.
•
Rearming is done automatically when the SBC is changed to SBC Stop, SBC Sleep, or SBC Fail-Safe Mode
to ensure wake-up capability.
Wake-Up in SBC Stop and SBC Normal Mode
In SBC Stop Mode, if a wake-up is detected, it is signaled by the INT output and in the WK_STAT_1 SPI register.
It is also signaled by RXDLIN put to LOW. The same applies for the SBC Normal Mode. The microcontroller
should set the device to SBC Normal Mode, there is no automatic transition to Normal Mode.
For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a Bus wake
event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to HIGH before).
Wake-Up in SBC Sleep Mode
Wake-up is possible via a LIN message (filter time t > tWK,Bus). The wake-up automatically transfers the SBC into
the SBC Restart Mode and from there to Normal Mode the corresponding RXD pin in set to LOW. The
microcontroller is able to detect the low signal on RXD and to read the wake source out of the WK_STAT_1
register via SPI. No interrupt is generated when coming out of Sleep Mode. The microcontroller can now
switch the LIN transceiver into LIN Normal Mode via SPI to start communication.
Table 18
Action due to a LIN BUS Wake-up
SBC Mode after Wake
Normal Mode
SBC Mode
Normal Mode
Stop Mode
Sleep Mode
Restart Mode
VCC1
INT
RXD
LOW
LOW
LOW
LOW
LOW
ON
LOW
LOW
HIGH
HIGH
HIGH
Stop Mode
ON
Restart Mode
Ramping Up
ON
Restart Mode
Fail-Safe Mode
Restart Mode
Ramping up
11.2.5
TXD Time-out Feature
If the TXD signal is dominant for the time t >tTxD_LIN _TO, the TXD time-out function deactivates the LIN
transmitter output stage temporarily. The transceiver remains in recessive state. The TXD time-out functions
prevents the LIN bus from being blocked by a permanent LOW signal on the TXD pin, caused by a failure. The
failure is stored in the SPI flag LIN1_FAIL . The LIN transmitter stage is activated again after the dominant
time-out condition is removed. The transceiver configuration stays unchanged.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
LIN Transceiver
Recovery of the
microcontroller error
TxD Time-Out due to
microcontroller error
Release after TxD
Time-out
Normal Communication
ttimeout
ttorec
Normal Communication
TxD
LIN
t
t
Figure 35 TXD Time-Out Function
11.2.6
Bus Dominant Clamping
If the LIN bus signal is dominant for a time t > tBUS_LIN_TO in LIN Normal and Receive Only Mode, then a bus
dominant clamping is detected and the SPI bit LIN1_FAIL is set. The transceiver configuration stays
unchanged.
11.2.7
Undervoltage Detection
In case the supply voltage is dropping below the VSHS undervoltage detection threshold (VSHS < VSHS,UVD), the
TLE9262BQX disables the output and receiver stages. If the power supply reaches a higher level than the
undervoltage detection threshold (VSHS > VSHS,UVD), the TLE9262BQX continues with normal operation. The
transceiver configuration stays unchanged.
11.2.8
Slope Selection
The LIN transceiver offers a LIN Low-Slope Mode for 10.4 kBaud communication and a LIN Normal-Slope Mode
for 20 kBaud communication. The only difference is the behavior of the transmitter. In LIN Low-Slope Mode,
the
transmitter uses a lower slew rate to further reduce the EME compared to Normal-Slope Mode. This complies
with SAE J2602 requirements.By default, the device works in LIN Normal-Slope Mode. The selection of LIN
Low-Slope Mode is done by an SPI bit LIN_LSM and will become effective as soon as CSN goes ‘HIGH’. Only the
LIN Slope is changed. The selection is accessible in SBC Normal Mode only.
11.2.9
Flash Programming via LIN
The device allows LIN flash programming, e.g. of another LIN Slave with a communication of up to 115 kBaud.
This feature is enabled by de-activating the slope control mechanism via a SPI command (bit LIN_FLASH) and
will become effective as soon as CSN goes ‘HIGH’. The SPI bit can be set in SBC Normal Mode.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
LIN Transceiver
Note:
It is recommended to perform flash programming only at nominal supply voltage VSHS = 13.5V to
ensure stable data communication.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
LIN Transceiver
11.3
Electrical Characteristics
Table 19
Electrical Characteristics
VSHS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Receiver Output (RXD pin)
HIGH Level Output Voltage
VRXD,H
VRXD,L
0.8 ×
VCC1
–
–
–
V
V
IRXD = -1.6 mA;
Bus = VSHS
IRXD = 1.6 mA
Bus = 0 V
P_11.3.1
P_11.3.2
V
LOW Level Output Voltage
–
0.2 ×
VCC1
V
Transmission Input (TXD pin)
HIGH Level Input Voltage
VTXD,H
0.7 ×
VCC1
–
–
V
V
V
Recessive State
P_11.3.3
P_11.3.4
P_11.3.5
P_11.3.6
1)
TXD Input Hysteresis
VTXD,hys 0.08 × 0.12 × 0.5 ×
VCC1
VCC1
VCC1
LOW Level Input Voltage
VTXD,L
RTXD
–
–
0.3 ×
VCC1
Dominant State
TXD Pull-up Resistance
20
40
80
kΩ VTXD = 0 V
LIN Bus Receiver (LIN Pin)
Receiver Threshold Voltage, VBus,rd
Recessive to Dominant Edge
0.4 × 0.45 × –
V
P_11.3.7
P_11.3.8
VSHS
VSHS
Receiver Dominant State
VBus,dom
–
–
0.4 ×
V
LIN 2.2/ISO 17987-4
VSHS
Param 17
Receiver Threshold Voltage, VBus,dr
Dominant to Recessive Edge
–
0.55 × 0.60 × V
P_11.3.9
P_11.3.10
P_11.3.11
VSHS
VSHS
Receiver Recessive State
Receiver Center Voltage
VBus,rec
VBus,c
0.6 ×
VSHS
–
–
V
V
LIN 2.2/ISO 17987-4
Param 18
0.475 0.5 × 0.525
× VSHS VSHS × VSHS
LIN 2.2/ISO 17987-4
Param 19
6 V < VSHS < 18 V
Receiver Hysteresis
VBus,hys
0.07 × 0.1 × 0.175
VSHS VSHS × VSHS
V
Vbus,hys = Vbus,dr - Vbus,rd
LIN 2.2/ISO 17987-4
Param 20
P_11.3.12
Wake-up Threshold Voltage VBus,wk
0.40 × 0.5 × 0.6 ×
V
–
P_11.3.13
P_11.3.14
VSHS
VSHS
VSHS
2)
Dominant Time for Bus
Wake-up
tWK,Bus
30
–
150
µs
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
LIN Transceiver
Table 19
Electrical Characteristics (cont’d)
VSHS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
LIN Bus Transmitter (LIN Pin)
1)
Bus Serial Diode Voltage
Drop
Vserdiode 0.4
0.7
1.0
V
V
= VCC1;
P_11.3.15
TXD
LIN 2.2/ISO 17987-4
Param 21
Bus Recessive Output
Voltage
VBUS,ro
0.8 ×
VSHS
–
VSHS
V
VTXD = HIGH Level
P_11.3.16
P_11.3.17
Bus Short Circuit Current
IBUS,sc
40
100
150
mA VBUS = 18 V;
LIN 2.2/ISO 17987-4
Param 12
Leakage Current
Loss of Ground
IBUS,lk1
-1000 -450 20
µA VSHS = 12 V = GND;
0 V < VBUS < 18 V;
LIN 2.2/ISO 17987-4
Param 15
P_11.3.18
P_11.3.19
P_11.3.20
P_11.3.21
P_11.3.22
Leakage Current
Loss of Battery
IBUS,lk2
IBUS,lk3
IBUS,lk4
–
–
20
–
µA VSHS = 0 V;
V
BUS = 18 V;
LIN 2.2/ISO 17987-4
Param 16
Leakage Current
Driver Off
-1
–
–
mA VSHS = 18 V;
BUS = 0 V;
V
LIN 2.2/ISO 17987-4
Param 13
Leakage Current
Driver Off
–
20
47
µA VSHS = 8 V;
VBUS = 18 V;
LIN 2.2/ISO 17987-4
Param 14
Bus Pull-up Resistance
RBUS
20
30
kΩ Normal Mode
LIN 2.2/ISO 17987-4
Param 26
1)
LIN Input Capacitance
CBUS
20
1
25
6
pF
P_11.3.23
P_11.3.24
Receiver propagation delay td(L),R
bus dominant to RXD LOW
–
µs VCC = 5 V;
CRXD = 20 pF;
LIN 2.2/ISO 17987-4
Param 31
Receiver propagation delay td(H),R
bus recessive to RXD HIGH
–
1
–
6
2
µs VCC = 5 V;
RXD = 20 pF;
P_11.3.25
P_11.3.26
C
LIN 2.2/ISO 17987-4
Param 31
Receiver delay symmetry
tsym,R
-2
µs tsym,R = td(L),R - td(H),R;
LIN 2.2/ISO 17987-4
Param 32
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
LIN Transceiver
Table 19
Electrical Characteristics (cont’d)
VSHS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
LIN Transceiver Enabling
Time
tLIN,EN
8
13
20
20
10
–
18
24
24
14
–
µs 2)CSN = HIGH to first valid P_11.3.27
transmitted TXD dominant
1)2)
Bus Dominant Time Out
tBUS_LIN 16
ms
ms
µs
P_11.3.28
P_11.3.29
P_11.3.30
_TO
1)2)
TXD Dominant Time Out
tTxD_LIN
16
V
= 0 V
TXD
_TO
1)2)
TXD Dominant Time Out
Recovery Time
ttorec
5
Duty Cycle D1
D1
D2
D3
D4
0.396
3) THRec(max) = 0.744 × VSHS; P_11.3.31
THDom(max) = 0.581 × VSHS
SHS = 7.0 … 18 V;
(For worst case at 20 kbit/s)
LIN 2.2/ISO 17987-4 Normal
Slope
;
V
tbit = 50 µs;
D1 = tbus_rec(min)/2 tbit
LIN 2.2/ISO 17987-4
Param 27
;
Duty Cycle D2
–
–
–
–
0.581
3)THRec(min.) = 0.422 × VSHS; P_11.3.32
THDom(min.) = 0.284 × VSHS
SHS = 7.6 … 18 V;
bit = 50 µs;
(for worst case at 20 kbit/s)
LIN 2.2/ISO 17987-4 Normal
Slope
;
V
t
D2 = tbus_rec(max)/2 tbit
LIN 2.2/ISO 17987-4
Param 28
;
Duty Cycle D3
(for worst case at 10.4 kbit/s)
SAE J2602 Low Slope
0.417
–
3)THRec(max) = 0.778 × VSHS P_11.3.33
THDom(max) = 0.616 × VSHS
;
VSHS = 7.0 … 18 V;
t
bit = 96 µs;
D3 = tbus_rec(min)/2 tbit
LIN 2.2/ISO 17987-4
Param 29
;
Duty Cycle D4
–
0.590
3)THRec(min.) = 0.389 × VSHS; P_11.3.34
(for worst case at 10.4 kbit/s)
SAE J2602 Low Slope
THDom(min.) = 0.251 × VSHS
VSHS = 7.6 … 18 V;
;
t
bit = 96 µs;
D4 = tbus_rec(max)/2 tbit
LIN 2.2/ISO 17987-4
Param 30
;
1) Not subject to production test, specified by design.
2) Not subject to production test, tolerance defined by internal oscillator tolerance
3) Bus load conditions concerning LIN 2.2/ISO 17987-4 CLIN, RLIN = 1 nF, 1 kΩ / 6.8 nF, 660 Ω/ 10 nF, 500 Ω
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
LIN Transceiver
VSHS
TxD
RxD
100 nF
RLIN
CRxD
WK
LIN
GND
CLIN
Figure 36 Simplified Test Circuit for Dynamic Characteristics
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
LIN Transceiver
tBit
tBit
tBit
TxD
(input to
transmitting node )
tBus _dom (max )
tBus_rec (min)
Thresholds of
receiving node 1
THRec (max)
THDom (max)
VSUP
(Transceiver supply
of transmitting
node )
Thresholds of
receiving node 2
THRec(min)
THDom(min)
tBus _dom (min)
tBus_rec(max )
RxD
(output of receiving
node 1)
td(L),R (1)
td(H),R(1)
RxD
(output of receiving
node 2)
t(L),R(2)
td(H),r(2)
Duty Cycle1 = tBUS_rec(min) / (2 x t
)
BIT
Duty Cycle2 = tBUS_rec(max ) / (2 x tBIT
)
Figure 37 Timing Diagram for Dynamic Characteristics
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Wake and Voltage Monitoring Inputs
12
Wake and Voltage Monitoring Inputs
12.1
Block Description
Internal Supply
IPU_WK
WKx
+
-
tWK
IPD_WK
VRef
Logic
MONx_Input_Circuit_ext.vsd
Figure 38 Wake Input Block Diagram
Features
•
•
•
•
•
•
•
Three High-Voltage inputs with a 3V (typ.) threshold voltage
Alternate Measurement function for high-voltage sensing via WK1 and WK2
Wake-up capability for power saving modes
Edge sensitive wake feature LOW to HIGH and HIGH to LOW
Pull-up and Pull-down current sources, configurable via SPI
Selectable configuration for static sense or cyclic sense working with TIMER1, TIMER2
In SBC Normal and SBC Stop Mode the level of the WK pin can be read via SPI even if the respective WK is
not enabled as a wake source.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Wake and Voltage Monitoring Inputs
12.2
Functional Description
The wake input pins are edge-sensitive inputs with a switching threshold of typically 3V. This means that both
transitions, HIGH to LOW and LOW to HIGH, result in a signalization by the SBC. The signalization occurs either
in triggering the interrupt in SBC Normal Mode and SBC Stop Mode or by a wake up of the device in SBC Sleep
and SBC Fail-Safe Mode.
Two different wake detection modes can be selected via SPI:
•
•
Static sense: WK inputs are always active
Cyclic sense: WK inputs are only active for a certain time period (see Chapter 5.2.1)
Two different filter times of 16µs or 64µs can be selected to avoid a parasitic wake-up due to transients or EMC
disturbances in static sense configuration.
The filter time (tFWK1, tFWK2) is triggered by a level change crossing the switching threshold and a wake signal is
recognized if the input level will not cross again the threshold during the selected filter time.
Figure 39 shows a typical wake-up timing and parasitic filter.
VWK
VWK,th
VWK,th
t
t
VINT
tWK,f
tWK,f
tINT
No Wake Event
Wake Event
Figure 39 Wake-up Filter Timing for Static Sense
The wake-up capability for each WK pin can be enabled or disabled via SPI command in the WK_CTRL_2
register.
The wake source for a wake via a WKx pin can always be read in the register WK_STAT_1 at the bits WK1_WU,
WK2_WU, and WK3_WU.
The actual voltage level of the WK pin (LOW or HIGH) can always be read in SBC Normal and SBC Stop Mode in
the register WK_LVL_STAT. During Cyclic Sense, the register show the sampled levels of the respective WK pin.
If FO2...3 are configured as WK inputs in its alternative function (16µs static filter time), then the wake events
will be signalled in the register WK_STAT_2.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Wake and Voltage Monitoring Inputs
12.2.1
Wake Input Configuration
To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure
integrated current sources via the SPI register WK_PUPD_CTRL. In addition, the wake detection modes
(including the filter time) can be configured via the SPI register WK_FLT_CTRL. An example illustration for the
automatic switching configuration is shown in Figure 40.
Table 20
Pull-Up / Pull-Down Resistor
WKx_PUPD_1 WKx_PUPD_0 Current Sources Note
0
0
no current
source
WKx input is floating if left open (default setting)
0
1
1
1
0
1
pull-down
pull-up
WKx input internally pulled to GND
WKx input internally pulled to internal 5V supply
Automatic
switching
If a high level is detected at the WKx input the pull-up
source is activated, if low level is detected the pull down
is activated.
Note:
If there is no pull-up or pull-down configured on the WK input, then the respective input should be
tied to GND or VS on board to avoid unintended floating of the pin and subsequent wake events.
IWKth_min
IWKth_max
IWK
VWKth
Figure 40 Illustration for Pull-Up / Down Current Sources with Automatic Switching Configuration
Table 21
Wake Detection Configuration and Filter Time
WKx_FLT_1 WKx_FLT_0 Filter Time
Description
0
0
1
0
1
0
Config A
Config B
Config C
static sense, 16µs filter time
static sense, 64µs filter time
Cyclic sense, Timer 1, 16µs filter time. Period, On-time
configurable in register TIMER1_CTRL
1
1
Config D
Cyclic sense, Timer 2, 16µs filter time. Period, On-time
configurable in register TIMER2_CTRL
Config A and B are intended for static sense with two different filter times.
Datasheet
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OPTIREG™ SBC TLE9262BQX
Wake and Voltage Monitoring Inputs
Config C or D are intended for cyclic sense configuration. With the filter settings, the respective timer needs to
be assigned to one or more HS output, which supplies an external circuit connected to the WKx pin, e.g. HS1
controlled by Timer 2 (HS1 = 010) and connected to WK3 via an switch circuitry - see also Chapter 5.2.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Wake and Voltage Monitoring Inputs
12.2.2
Alternate Measurement Function with WK1 and WK2
12.2.2.1 Block Description
This function provides the possibility to measure a voltage, e.g. the unbuffered battery voltage, with the
protected WK1 HV-input. The measured voltage is routed out at WK2. It allows for example a voltage
compensation for LED lighting by changing the duty cycle of the High-Side outputs. A simple voltage divider
needs to be placed externally to provide the correct voltage level to the microcontroller A/D converter input.
The function is available in SBC Normal Mode and it is disabled in all other modes to allow a low-quiescent
current operation.The measurement function can be used instead of the WK1 and WK2 wake and level
signalling capability.
The benefits of the function is that the signal is measured by a HV-input pin and that there is no current flowing
through the resistor divider during low-power modes.
The functionality is shown in a simplified application diagram in Figure 60.
12.2.2.2 Functional Description
This measurement function is by default disabled. In this case, WK1 and WK2 have the regular wake and
voltage level signalization functionality. The switch S1 is open for this configuration (see Figure 60).
The measurement function can be enabled via the SPI bit WK_MEAS.
If WK_MEAS is set to ‘1’, then the measurement function is enabled and switch S1 is closed in SBC Normal
Mode. S1 is open in all other SBC modes. If this function the pull-up and down currents of WK1 and WK2 are
disabled, and the internal WK1 and WK2 signals are gated. In addition, the settings for WK1 and WK2 in the
registers WK_PUPD_CTRL, WK_FLT_CTRL and WK_CTRL_2 are ignored but changing these setting is not
prevented. The registers WK_STAT_1 and WK_LVL_STAT are not updated with respect to the inputs WK1 and
WK2.
However, if only WK1 or WK2 are set as wake sources and a SBC Sleep Mode command is set, then the SPI_FAIL
flag will be set and the SBC will be changed into SBC Restart Mode (see Chapter 5.1 also for wake capability
of WK1 and WK2).
Table 22
Differences between Normal WK Function and Measurement Function
Affected Settings/Modules WK_MEAS = 0
for WK1 and WK2 Inputs
WK_MEAS = 1
S1 configuration
‘open’
‘closed’ in SBC Normal Mode,
‘open’ in all other SBC Modes
Internal WK1 & WK2 signal
processing
Default wake and level signaling
‘WK1...2 inputs are gated internally,
function, WK_STAT_1, WK_STAT_2 WK_STAT_1, WK_STAT_2 are not
are updated accordingly updated
Wake-up via WK1 and WK2 possible if setting the bits is ignored and not
WK1_EN, WK2_EN
bits are set
prevented. If only WK1_EN, WK2_EN
are set while trying to go to SBC Sleep
Mode, then the SPI_FAIL flag will be
set and the SBC will be changed into
SBC Restart Mode.
WK_PUPD_CTRL
WK_FLT_CTRL
normal configuration is possible
normal configuration is possible
no pull-up or pull-down enabled
setting the bits is ignored and not
prevented
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OPTIREG™ SBC TLE9262BQX
Wake and Voltage Monitoring Inputs
Note:
There is a diode in series to the switch S1 (not shown in the Figure 60), which will influence the
temperature behavior of the switch.
Electrical Characteristics
Electrical Characteristics
12.3
Table 23
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
WK1...WK3 Input Pin Characteristics
Max.
Wake-up/monitoring VWKth
threshold voltage
2
3
4
V
without external
serial resistor RS (with
RS:
P_12.3.1
ΔV = IPD/PU * RS);
hysteresis included
Threshold hysteresis
VWKNth,hys 0.1
-
0.7
V
without external
serial resistor RS (with
RS:
P_12.3.2
ΔV = IPD/PU * RS);
WK pin Pull-up Current IPU_WK
-20
3
-10
10
-3
µA
µA
VWK_IN = 4V
VWK_IN = 2V
P_12.3.3
P_12.3.4
WK pin Pull-down
Current
IPD_WK
20
Input leakage current ILK,l
-2
–
2
µA
0 V < VWK_IN < 40V
P_12.3.5
Drop Voltage across S1 VDrop,S1
switch
1000
1100
mV 1)Drop Voltage
between WK1 and
WK2 when enabled
for voltage
P_12.3.13
measurement; IWK1
500µA;
=
Tj = 25°C
Refer to Figure 41
Timing
Wake-up filter time 1 tFWK1
12
50
16
64
20
80
µs
µs
2)SPI Setting
2)SPI Setting
P_12.3.6
P_12.3.7
Wake-up filter time 2 tFWK2
1) Not subject to production test; specified by design
2) Not subject to production test, tolerance defined by internal oscillator tolerance
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OPTIREG™ SBC TLE9262BQX
Wake and Voltage Monitoring Inputs
1100
1000
900
800
700
600
500
VS = 13.5V
500 μA
250 μA
100 μA
50 μA
ꢁ50
0
50
100
150
Tjꢀꢀꢀꢁ JUNCTIONꢀTEMPERATUREꢀ(°C)
Figure 41 Typical Drop Voltage Characteristics of S1 (between WK1 & WK2)
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OPTIREG™ SBC TLE9262BQX
Interrupt Function
13
Interrupt Function
13.1
Block and Functional Description
Vcc1
INT
Time
out
Interrupt logic
Figure 42 Interrupt Block Diagram
The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is
designed as a push/pull output stage as shown in Figure 42. An interrupt is triggered and the INT pin is pulled
low (active low) for tINT in SBC Normal and Stop Mode and it is released again once tINT is expired. The minimum
HIGH-time of INT between two consecutive interrupts is tINTD. An interrupt does not cause a SBC mode change.
Two different interrupt classes could be selected via the SPI bit INT_ GLOBAL:
•
Class 1 (wake interrupt - INT_ GLOBAL=0): all wake-up events stored in the wake status SPI register
(WK_STAT_1 and WK_STAT_2) cause an interrupt (default setting). An interrupt is only triggered if the
respective function is also enabled as a wake source (including GPIOx if configured as a wake input).
•
Class 2 (global interrupt - INT_ GLOBAL=1): in addition to the wake-up events, all signalled failures stored
in the other status registers cause an interrupt (the register WK_LVL_STAT is not generating interrupts)
Note:
The errors which will cause SBC Restart or SBC Fail-Safe Mode (Vcc1_UV, WD_FAIL, VCC1_SC, TSD2,
FAILURE) are the exceptions of an INT generation on status bits. Also POR and DEV_STAT_x and will
not generate interrupts.
In addition to this behavior, an INT will be triggered when the SBC is sent to SBC Stop Mode and not all bits
were cleared in the WK_STAT_1 and WK_STAT_2register.
The SPI status registers are updated at every falling edge of the INT pulse. All interrupt events are stored in the
respective register (except the register WK_LVL_STAT) until the register is read and cleared via SPI command.
A second SPI read after reading out the respective status register is optional but recommended to verify that
the interrupt event is not present anymore. The interrupt behavior is shown in Figure 43 for class 1 interrupts.
The behavior for class 2 is identical.
The INT pin is also used during SBC Init Mode to select the hardware configuration of the device. See
Chapter 5.1.1 for further information.
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OPTIREG™ SBC TLE9262BQX
Interrupt Function
WK1
WK2
INT
tINTD
tINT
Update of
WK_STAT register
Update of
WK_STAT register
optional
no WK
SPI
Read & Clear
WK_STAT
contents
WK1
no WK
WK2
SPI
Read & Clear
No SPI Read & Clear
Command sent
WK_STAT
contents
WK1 + WK2
no WK
Interrupt_Behavior.vsd
Figure 43 Interrupt Signalization Behavior
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OPTIREG™ SBC TLE9262BQX
Interrupt Function
13.2
Electrical Characteristics
Table 24
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Interrupt Output; Pin INT
1)
INT High Output Voltage VINT,H
0.8 ×
VCC1
–
–
–
V
V
I
= -1 mA;
P_13.2.1
P_13.2.2
INT
INT = OFF
1)
INT Low Output Voltage VINT,L
–
0.2 ×
I
= 1 mA;
INT
VCC1
INT = ON
2)
INT Pulse Width
tINT
80
80
100
100
120
120
µs
µs
P_13.2.3
P_13.2.4
INT Pulse Minimum Delay tINTD
2) between
Time
consecutive pulses
Configuration Select; Pin INT
Config Pull-down
Resistance
RCFG
180
5
250
10
350
14
kΩ
VINT = 5 V
P_13.2.5
P_13.2.6
2)
Config Select Filter Time tCFG_F
µs
1) Output Voltage Value also determines device configuration during SBC Init Mode
2) Not subject to production test, tolerance defined by internal oscillator tolerance.
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OPTIREG™ SBC TLE9262BQX
Fail Outputs
14
Fail Outputs
14.1
Block and Functional Description
5V_int
T test
SBC Init
Mode
RTEST
FO1/2
Failure logic
FO3/TEST
TFO_PL
Failure Logic
Figure 44 Simplified Fail Output Block Diagram for FO1/2 and for FO3/TEST
The fail outputs consist of a failure logic block and three open-drain outputs (FO1, FO2, FO3) with active-low
signalization.
The fail outputs are activated due to following failure conditions:
•
Watchdog trigger failure (For config 3&4 only after the 2nd watchdog trigger failure and for config 1&2 after
1st watchdog trigger failure)
•
•
•
•
Thermal shutdown TSD2
VCC1 short to GND
VCC1 overvoltage (only if the SPI bit VCC1_OV_RST is set)
After 4 consecutive VCC1 undervoltage event (see Chapter 15.6 for details)
At the same time SBC Fail-Safe Mode is entered (exceptions are watchdog trigger failures depending on
selected
configurations - see Chapter 5.1.1).
The fail output activation is signalled in the SPI bit FAILURE of the register DEV_STAT.
For testing purposes only the Fail Outputs can also be activated via SPI by setting the bit FO_ON. This bit is
independent of the FO failure bits. In case that there is no failure condition, the FO outputs can also be turned
off again via SPI, i.e. no successful watchdog trigger is needed.
The entry of SBC Fail-Safe Mode due to a watchdog failure can be configured as described in Chapter 5.1.1.
In order to deactivate the fail outputs in SBC Normal Mode the failure conditions must not be present anymore
(e.g. TSD2, VCC1 short circuit, etc) and the bit FAILURE needs to be cleared via SPI command.
In case of a watchdog failure the correct procedure to deactivate the fail outputs is:
•
•
a successful WD trigger, i.e. WD_FAIL must be cleared
clearing of the FAILURE bit
WD_FAIL will also be cleared when going to SBC Sleep or SBC Fail-Safe Mode due to another failure (not a WD
failure) or if the watchdog is disabled in SBC Stop Mode
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OPTIREG™ SBC TLE9262BQX
Fail Outputs
Note:
The Fail output pin is triggered for any of the above described failures. No FAILURE is caused for the
1st watchdog failure if selected for Config2.
The three fail outputs are activated simultaneously with following output functionalities:
•
•
•
FO1: Static fail output
FO2: 1.25Hz, 50% (typ.) duty cycle, e.g. to generate an indicator signal
FO3: 100Hz PWM, 20% (typ.) duty cycle, e.g. to generate a dimmed rear light from a break light.
Note:
The duty cycle for FO3 can be configured via SPI option to 20%, 10%, 5% or 2.5%. Default value is
20%. See the register FO_DC for configuration.
14.1.1
General Purpose I/O Functionality of FO2 and FO3 as Alternate Function
In case that FO2 and FO3 are not used in the application, those pins can also be configured with an alternate
function as high-voltage (VSHS related) General Purpose I/O pins.
VSHS
Config &
Control Logic
FOx/
GPIOx
Figure 45 Simplified General Purpose I/O block diagram for FO2 and FO3/TEST
The pins are by default configured as FO pins. The configuration is done via the SPI register GPIO_CTRL. The
alternate function can be:
•
•
•
•
Wake Inputs: The detection threshold VGPIOI,th is similar as for the WK inputs. The wake-up detection
behavior is the same as for WKx pins. Wake events are stored and reported in WK_STAT_2.
Low-Side Switches: The switch is able to drive currents of up to 10mA (see also VGPIOL,L1). It is self-protected
with regards to current limitation. No other diagnosis is implemented.
High-Side Switches: The switch is able to drive currents up to 10mA (see also VGPIOH,H1). It is self-protected
with regards to current limitation. No other diagnosis is implemented.
If configured as GPIO then the respective level at the pin will be shown in WK_LVL_STAT in SBC Normal and
Stop Mode. This is also the case if configured as LS/HS and can serve as a feedback about the respective
state. GPIO2 is shared with the TEST level bit.
Table 25 describes the behavior of the FO/GPIO pins in their different configurations and SBC modes.
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Fail Outputs
Table 25
FOx
Configuration Mode
FOx (default)
OFF
Fail-Output and GPIO configuration behavior during the respective SBC Modes
SBC Normal
SBC Stop Mode SBC Sleep Mode SBC Restart
Mode
SBC Fail-Safe
Mode
fixed
fixed
active / fixed
OFF
active
OFF
OFF
OFF
configurable
Wake Input
Low-Side
High-Side
wake capable
fixed
wake capable
fixed
wake capable
OFF
OFF
OFF
fixed
fixed
OFF
OFF
Explanation of FO/GPIO states:
•
•
•
configurable: settings can be changed in this SBC mode
fixed: settings stay as configured in SBC Normal Mode
active: FOx is activated due to a failure leading to SBC Restart or Fail-Safe Mode.
Restart Behavior:
The behavior during SBC Restart and Fail-Safe Mode as well as the transition to SBC Normal Mode is as follows:
•
•
•
if configured as Wake Input: it will stay wake capable during SBC Restart Mode and OFF while in SBC Fail-
Safe Mode. It will resume wake capability when leaving SBC Restart Mode (SPI register is not modified)
if configured as Low-Side or High-Side: They will be disabled during SBC Restart and Fail-Safe Mode. After
leaving SBC Restart Mode the previously configured function will be resumed (SPI register is not modified)
if configured as FO and activated due to a failure: FO will stay activated during SBC Restart Mode and when
entering SBC Normal Mode (SPI register is not modified)
Notes
1. In order to avoid unintentional entry of SBC Development Mode care must be taken that the level of FO3/TEST
is HIGH during device power up and SBC Init Mode.
2. The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS
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OPTIREG™ SBC TLE9262BQX
Fail Outputs
14.2
Electrical Characteristics
Table 26
Electrical Characteristics
VSHS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.1)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Pin FO1
FO1 low output voltage
(active)
VFO,L1
–
0
–
–
1.0
2
V
IFO = 4mA
P_14.2.1
P_14.2.2
FO1 high output current IFO,H
µA
VFO = 28V
(inactive)
Pin FO2
3)
3)
FO2 side indicator
frequency
fFO2SI
1.00
45
1.25
50
1.50
55
Hz
%
P_14.2.3
P_14.2.4
FO2 side indicator duty
cycle
dFO2SI
Pin FO3/TEST2)
Pull-up Resistance at pin RTEST
FO3/TEST
2.5
5
10
kΩ
VTEST =0V;
SBC Init Mode
3)
P_14.2.5
TEST Input Filter Time
tTEST
50
80
64
80
µs
Hz
P_14.2.6
P_14.2.7
3)
FO3 pulsed
fFO3PL
100
120
light frequency
FO3 pulsed
dFO3PL
16
20
24
%
3)4)default setting
P_14.2.8
light duty cycle
Alternate FO2...3
Electrical Characteristics: GPIO
GPIO low-side output
voltage (active)
VGPIOL,L1
–
–
–
1
V
IGPIO = 10mA
P_14.2.9
5)
GPIO low-side output
voltage (active)
VGPIOL,L2
–
5
mV
V
I
= 50µA
P_14.2.17
P_14.2.10
P_14.2.18
GPIO
GPIO high-side output
voltage (active)
VGPIOH,H1 VSHS-1
VGPIOH,H2 VSHS-5
–
–
IGPO = -10mA
5)
GPIO high-side output
voltage (active)
–
–
mV
V
I
= -50µA
GPO
GPIO input threshold
voltage
VGPIOI,th
1.5
2.5
400
3.5
700
6) hysteresis included P_14.2.11
5)
GPIO input threshold
hysteresis
VGPIOI,hys 100
mV
P_14.2.12
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Fail Outputs
Table 26
Electrical Characteristics (cont’d)
VSHS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.1)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
IGPIOL,max 10
Max.
GPIO low-side current
limitation
30
mA
VGPIO = 28V
P_14.2.13
P_14.2.14
GPIO high-side current
limitation
IGPIOH,max -45
–
-10
mA
VGPIO = 0V
1) The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS
2) The external capacitance on this pin must be limited to less than 10nF to ensure proper detection of SBC
Development Mode and SBC User Mode operation.
3) Not subject to production test, tolerance defined by internal oscillator tolerance.
4) The duty cyclic is adjustable via the SPI bits FO_DC.
5) Not subject to production test, specified by design.
6) Applies also for TEST voltage input level
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
15
Supervision Functions
15.1
Reset Function
VCC1
RO
Resetlogic
Incl. filter & delay
Figure 46 Reset Block Diagram
15.1.1
Reset Output Description
The reset output pin RO provides a reset information to the microcontroller, for example, in the event that the
output voltage has fallen below the undervoltage threshold VRT1/2/3/4. In case of a reset event, the reset output
RO is pulled to low after the filter time tRF and stays low as long as the reset event is present plus a reset delay
time tRD1. When connecting the SBC to battery voltage, the reset signal remains LOW initially. When the output
voltage Vcc1 has reached the reset default threshold VRT1,r, the reset output RO is released to HIGH after the
reset delay time tRD1. A reset can also occur due to a watchdog trigger failure. The reset threshold can be
adjusted via SPI, the default reset threshold is VRT1,f. The RO pin has an integrated pull-up resistor. In case reset
is triggered, it will be pulled low for Vcc1 ≥ 1V and for VS ≥ VPOR,f (see also Chapter 15.3).
The timings for the RO triggering regarding VCC1 undervoltage and watchdog trigger is shown in Figure 47.
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Supervision Functions
VCC
VRT1
t < tRF
The reset threshold can be
configured via SPI in SBC
Normal Mode, default is VRT1
undervoltage
t
tCW
tOW
tRD1
tCW
tLW
tRD1
tLW
tCW
tOW
SPI
RO
SPI
Init
WD
Trigger
WD
Trigger
SPI
Init
t
t
tRF
tLW= long open window
tCW= closed window
tOW= open window
SBC Init
SBC Normal
SBC Restart
SBC Normal
Figure 47 Reset Timing Diagram
15.1.2
Soft Reset Description
In SBC Normal and SBC Stop Mode, it is also possible to trigger a device internal reset via a SPI command in
order to bring the SBC into a defined state in case of failures. In this case the microcontroller must send a SPI
command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid,
the SBC is set back to SBC INIT Mode and all SPI registers are set to their default values (see SPI Chapter 16.5
and Chapter 16.6).
Two different soft reset configurations are possible via the SPI bit SOFT_ RESET_RO:
•
The reset output (RO) is triggered when the soft reset is executed (default setting, the same reset delay
time tRD1 applies)
•
The reset output (RO) is not triggered when the soft reset is executed
Note:
The device must be in SBC Normal Mode or SBC Stop Mode when sending this command.
Otherwise, the command will be ignored.
15.2
Watchdog Function
The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the
microcontroller stops serving the watchdog due to a lock up in the software.
Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN:
•
•
Time-Out Watchdog (default value)
Window Watchdog
The respective watchdog functions can be selected and programmed in SBC Normal Mode. The configuration
stays unchanged in SBC Stop Mode.
Please refer to Table 27 to match the SBC Modes with the respective watchdog modes.
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Supervision Functions
Table 27
Watchdog Functionality by SBC Modes
SBC Mode
INIT Mode
Watchdog Mode
Remarks
Starts with Long Open
Window
Watchdog starts with Long Open Window after RO is
released
Normal Mode
WD Programmable
Window Watchdog, Time-Out watchdog or switched
OFF for SBC Stop Mode
Stop Mode
Sleep Mode
Watchdog is fixed or OFF
OFF
SBC will start with Long Open Window when
entering SBC Normal Mode.
Restart Mode
OFF
SBC will start with Long Open Window when
entering SBC Normal Mode.
The watchdog timing is programmed via SPI command. As soon as the watchdog is programmed, the timer
starts with the new setting and the watchdog must be served. The watchdog is triggered by sending a valid
SPI-write command to the watchdog configuration register. The trigger SPI command is executed when the
Chip Select input (CSN) becomes HIGH.
When coming from SBC Init, SBC Restart Mode or in certain cases from SBC Stop Mode, the watchdog timer is
always started with a long open window. The long open window (tLW = 200ms) allows the microcontroller to
run its initialization sequences and then to trigger the watchdog via SPI.
The watchdog timer period can be selected via the watchdog timing bit field (WD_TIMER) and is in the range
of 10 ms to 1000 ms. This setting is valid for both watchdog types.
The following watchdog timer periods are available:
•
•
•
•
•
•
•
WD Setting 1: 10ms
WD Setting 2: 20ms
WD Setting 3: 50ms
WD Setting 4: 100ms
WD Setting 5: 200ms
WD Setting 6: 500ms
WD Setting 7: 1000ms
In case of a watchdog reset, SBC Restart or SBC Fail-Safe Mode is entered according to the configuration and
the SPI bits WD_FAIL are set. Once the RO goes HIGH again the watchdog immediately starts with a long open
window the SBC enters automatically SBC Normal Mode.
In SBC Development Mode the watchdog is OFF and therefore no reset and interrupt are generated due to a
watchdog failure.
Depending on the configuration, the WD_FAIL bits will be set after a watchdog trigger failure as follows:
•
In case an incorrect WD trigger is received (triggering in the closed watchdog window or when the
watchdog counter expires without a valid trigger) then the WD_FAIL bits will be increased (showing the
number of incorrect WD triggers)
•
•
For config 2: the bits can have the maximum value of ‘01’
For config 1, 3 and 4: the bits can have the maximum value of ‘10’
The WD_FAIL bits are cleared automatically when following conditions apply:
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
•
•
After a successful watchdog trigger
When the watchdog is OFF: in SBC Stop Mode after successfully disabling it, in SBC Sleep Mode, or in SBC
Fail-Safe Mode (except for a watchdog failure)
15.2.1
Time-Out Watchdog
The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog
trigger can be done at any time within the configured watchdog timer period.
A correct watchdog service immediately results in starting a new watchdog timer period. Taking the
tolerances of the internal oscillator into account leads to the safe trigger area as defined in Figure 48.
If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RO low and
the SBC switches to SBC Restart or SBC Fail-Safe Mode.
Typical timout watchdog trigger period
t
WD x 1.50
open window
uncertainty
Watchdog Timer Period (WD_TIMER)
tWD x 1.20
tWD x 1.80
t / [tWD_TIMER
]
safe trigger area
Wd1_TimeOut_per.vsd
Figure 48 Time-out Watchdog Definition
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Supervision Functions
15.2.2
Window Watchdog
Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer
period is divided between an closed and an open window. The watchdog must be triggered within the open
window.
A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an
open window.
The watchdog timer period is at the same time the typical trigger time and defines the middle of the open
window. Taking the oscillator tolerances into account leads to a safe trigger area of:
tWD x 0.72 < safe trigger area < tWD x 1.20.
The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking
the tolerances of the internal oscillator into account leads to the timings as defined in Figure 49.
A correct watchdog service immediately results in starting the next closed window.
Should the trigger signal meet the closed window or should the watchdog timer period elapse, then a
watchdog reset is created by setting the reset output RO low and the SBC switches to SBC Restart or SBC Fail-
Safe Mode.
tWD x 0.6
tWD x 0.9
Typ. closed window
Typ. open window
tWD x 0.48
tWD x 0.72
tWD x 1.0
tWD x 1.20
tWD x 1.80
closed window
uncertainty
open window
uncertainty
Watchdog Timer Period (WD_TIMER)
t / [tWD_TIMER
]
safe trigger area
Figure 49 Window Watchdog Definition
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Supervision Functions
15.2.3
Watchdog Setting Check Sum
A check sum bit is part of the SPI commend to trigger the watchdog and to set the watchdog setting.
The sum of the 8 data bits in the register WWD_CTRL needs to have even parity (see Equation (15.1)). This is
realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is
ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set.
The checksum is calculated by taking all 8 data bits into account. The written value of the reserved bit 3 of the
WWD_CTRL register is considered (even if read as ‘0’ in the SPI output) for checksum calculation, i.e. if a 1 is
written on the reserved bit position, then a 1 will be used in the checksum calculation.
(15.1)
CHKSUM = Bit15 ⊕ … ⊕ Bit8
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Supervision Functions
15.2.4
Watchdog during SBC Stop Mode
The watchdog can be disabled for SBC Stop Mode in SBC Normal Mode. For safety reasons, there is a special
sequence to be followed in order to disable the watchdog as described in Figure 50. Two different SPI bits
(WD_STM_ EN_0, WD_STM_ EN_1) in the registers WK_CTRL_1 and WD_CTRL need to be set.
Correct WD disabling
Sequence Errors
sequence
•
Missing to set bit
WD_STM_EN_0 with the
next watchdog trigger after
having set WD_STM_EN_1
Set bit
WD_STM_EN_1 = 1
with next WD Trigger
•
Staying in Normal Mode
instead of going to Stop
Mode with the next trigger
Set bit
WD_STM_EN_0 = 1
Before subsequent WD Trigger
Will enable the WD:
Change to
SBC Stop Mode
•
Switching back to SBC
Normal Mode
•
Triggering the watchdog
WD is switched off
Figure 50 Watchdog disabling sequence in SBC Stop Mode
If a sequence error occurs, then the bit WD_STM_ EN_1 will be cleared and the sequence has to be started
again.
The watchdog can be enabled by triggering the watchdog in SBC Stop Mode or by switching back to SBC
Normal Mode via SPI command. In both cases the watchdog will start with a long open window and the bits
WD_STM_EN_1 and WD_STM_ EN_0 are cleared. After the long open window the watchdog has to be served
as configured in the WD_CTRL register.
Note:
The bit WD_STM_ EN_0 will be cleared automatically when the sequence is started and it was 1
before.
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Supervision Functions
15.2.5
Watchdog Start in SBC Stop Mode due to Bus Wake
In SBC Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the
watchdog with any BUS wake (CAN or LIN) during SBC Stop Mode. The feature is enabled by setting the bit
WD_EN_ WK_BUS = 1
(= default value after POR). The bit can only be changed in SBC Normal Mode and needs to be programmed
before starting the watchdog disable sequence.
A wake on CAN and LINx will generate an interrupt and the RXD pin for LINx or CAN is pulled to low. By these
signals the microcontroller is informed that the watchdog is startedwith a long open window. After the long
open window the watchdog has to be served as configured in the WD_CTRL register.
To disable the watchdog again, the SBC needs to be switched to Normal Mode and the sequence needs to be
sent again.
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Supervision Functions
15.3
VS Power On Reset
At power up of the device, the VS Power on Reset is detected when VS > VPOR,r and the SPI bit POR is set to
indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be
kept LOW and will only be released once VCC1 has crossed VRT1,r and after tRD1 has elapsed.
In case VS < VPOR,f, an device internal reset will be generated and the SBC is switched OFF and will restart in
INIT mode at the next VS rising. This is shown in Figure 51.
VS
VPOR,r
VPOR,f
t
t
VCC1
VRT1,r
The reset threshold can be
configured via SPI in SBC
VRTx,f
Normal Mode, default is VRT1
RO
SBC Restart Mode is
entered whenever the
Reset is triggered
t
tRD1
SBC Mode
Re-
start
SBC OFF
SBC INIT MODE
Any SBC MODE
SBC OFF
t
SPI
Command
Figure 51 Ramp up / down example of Supply Voltage
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
15.4
Undervoltage VS and VSHS
If the supply voltage VS reaches the undervoltage threshold VS,UV then the SBC does the following measures:
•
SPI bit VS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present
anymore,
•
•
VCC3 is disabled (see Chapter 8.2) unless the control bit VCC3_VS_ UV_OFF is set
The VCC1 short circuit protection becomes inactive (see Chapter 15.7). However, the thermal protection
of the device remains active.
If the undervoltage threshold is exceeded (VS rising) then functions will be automatically enabled again.
If the supply voltage VSHS passes below the undervoltage threshold (VSHS,UVD) the SBC does the following
measures:
•
•
•
HS1...4 are acting accordingly to the SPI setting (see Chapter 9)
LINx: Transmitter and Receiver are disabled during the VSHS undervoltage condition (see Chapter 11.2.7);
SPI bit VSHS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present
anymore,
•
VCC1, VCC2, WKx and CAN are not affected by VSHS undervoltage
15.5
Overvoltage VSHS
If the supply voltage VSHS reaches the overvoltage threshold (VSHS,OVD) the SBC triggers the following
measures:
•
•
HS1...4 are acting accordingly to the SPI setting (see Chapter 9)
SPI bit VSHS_OV is set. No other error bits are set. The bit can be cleared once the condition is not present
anymore,
•
VCC1, VCC2, VCC3, WKx, LIN and CAN are not affected by VS overvoltage
15.6
VCC1 Over-/ Undervoltage and Undervoltage Prewarning
VCC1 Undervoltage and Undervoltage Prewarning
15.6.1
A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The
prewarning event is signaled with the bit VCC1_ WARN. No other actions are taken.
As described in Chapter 15.1 and Figure 52, a reset will be triggered (RO pulled ‘low’) when the VCC1 output
voltage falls below the selected undervoltage threshold (VRTx). The bit VCC1_UV is set and the SBC will enter
SBC Restart Mode.
Note:
The VCC1_ WARN or VCC1_UV bits are not set in Sleep Mode as VCC1 = 0V in this case
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
VCC1
VRTx
t
t
tRF
tRD1
RO
SBC Normal
SBC Restart
SBC Normal
Figure 52 VCC1 Undervoltage Timing Diagram
An additional safety mechanism is implemented to avoid repetitive VCC1 undervoltage resets due to high
dynamic loads on VCC1:
•
A counter is increased for every consecutive VCC1 undervoltage event (regardless on the selected reset
threshold),
•
•
The counter is active in SBC Init-, Normal-, and Stop Mode,
For VS < VS,UV the counter will be stopped in SBC Normal Mode (i.e. the VS UV comparator is always enabled
in SBC Normal Mode),
•
•
A 4th consecutive VCC1 undervoltage event will lead to SBC Fail-Safe Mode entry and to setting the bit
VCC1_UV _FS
This counter is cleared:
–
–
–
when SBC Fail-Safe Mode is entered,
when the bit VCC1_UV is cleared,
when a Soft Reset is triggered.
Note:
It is recommended to clear the VCC1_UV bit once it was set and detected.
15.6.2
VCC1 Overvoltage
For fail-safe reasons a configurable VCC1 overvoltage detection feature is implemented for SBC Init- and
Normal Mode.
In case the VCC1,OV,r threshold is crossed, the SBC triggers following measures depending on the configuration:
•
•
The bit VCC1_ OV is always set;
If the bit VCC1_OV_RST is set and CFGP = ‘1’, then SBC Restart Mode is entered. The FOx outputs are
activated. After the reset delay time (tRD1), the SBC Restart Mode is left and SBC Normal Mode is resumed
even if the VCC1 overvoltage event is still present (see also Figure 53). The VCC1_OV_RST bit is cleared
automatically;
•
If the bit VCC1_OV_RST is set and CFGP = ‘0’, then SBC Fail-Safe Mode is entered and FOx outputs are
activated.
Note:
Before entering SBC Stop Mode the bit VCC1_OV_RST must be set to ‘0’ to avoid unintentional SBC
Restart or Fail-Safe Mode entry. The status bit VCC1_ OV could be set unintentionally. The reason is
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
that external noise could be coupled into the VCC1 supply line. Especially, in case the VCC1 output
current in SBC STOP Mode is below the active peak threshold (IVCC1,Ipeak).
VCC1
VCC1,OV
t
t
tVCC1,OV_F
RO
tRD1
SBC Normal
SBC Restart
SBC Normal
Figure 53 VCC1 Overvoltage Timing Diagram
15.7
VCC1 Short Circuit and VCC3 Diagnostics
The short circuit protection feature for VCC1 is implemented as follows (VS needs to be higher than VS,UV):
•
If VCC1 is not above the VRTx within tVCC1,SC after device power up or after waking from SBC Sleep Mode then
the SPI bit VCC1_SC bit is set, VCC1 is turned OFF, the FOx pins are enabled, FAILURE is set and SBC Fail-
Safe Mode is entered. The SBC can be activated again via wake on CAN, LINx, WKx.
•
The same behavior applies, if VCC1 falls below VRTx for longer than tVCC1,SC
.
VCC3 diagnosis features are implemented as follows:
•
Load Sharing: The external PNP is disabled when VS < VS,UV if VCC3_VS_ UV_OFF = 0 or when in SBC Stop
Mode if VCC3_LS_ STP_ON = ‘0’. All other diagnostic features are disabled because they are provided via
VCC1.
•
Stand-alone configuration: The external PNP is disabled when VS < VS,UV if VCC3_VS_ UV_OFF = 0. The
overcurrent limitation is signalled via the bit VCC3_OC according to the selected shunt resistor, VCC3
undervoltage is signalled via the bit VCC3_UV and the regulator is disabled due to VS undervoltage when
is reached.
Note:
Neither VCC1_SC nor VCC3_UV flags are set during power up of VCC1 or turn on of VCC3 respectively.
15.8
VCC2 Undervoltage and VCAN Undervoltage
An undervoltage warning is implemented for VCC2 and VCAN as follows:
•
V
CC2 undervoltage Detection: In case VCC2 will drop below the VCC2,UV,f threshold, then the SPI bit VCC2_UV
is set and can be only cleared via SPI.
CAN undervoltage Detection: In case the voltage on VCAN will drop below the VCAN_UV threshold, then the SPI
bit VCAN_UV is set and can be only cleared via SPI.
•
V
Note:
The VCC2_UV flag is not set during turn-on or turn-off of VCC2.
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
15.9
Thermal Protection
Three independent and different thermal protection features are implemented in the SBC according to the
system impact:
•
•
•
Individual thermal shutdown of specific blocks
Temperature prewarning of main microcontroller supply VCC1
SBC thermal shutdown due to VCC1 overtemperature
15.9.1
Individual Thermal Shutdown
As a first-level protection measure the output stages VCC2, CAN, LINx, and HSx are independently switched
OFF if the respective block reaches the temperature threshold TjTSD1. Then the TSD1 bit is set. This bit can only
be cleared via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the
thermal shutdown protection is only active if the respective block is ON.
The respective modules behave as follows:
•
VCC2: Is switched to OFF and the control bits VCC2_ON are cleared. The status bit VCC2_OT is set. Once
the overtemperature condition is not present anymore, then VCC2 has to be configured again by SPI.
•
VCC3 as a stand-alone regulator: Is switched to OFF and the control bits VCC3_ON are cleared. The status
bit VCC3_OT is set. Once the overtemperature condition is not present anymore VCC3 has to be configured
again by SPI. It is recommended to clear the VCC3_OT bit before enabling the regulator again.
•
•
•
•
VCC3 in load sharing configuration: in case of overtemperature at VCC3 the bit VCC3_OT is set and VCC3 is
switched off. The regulator will be switched on again automatically once the overtemperature event is not
present anymore. Also in this case it is recommended to clear the VCC3_OT bit right away.
CAN: The transmitter is disabled and stays in CAN Normal Mode acting like CAN Receive only mode. The
status bits CAN_FAIL = ‘01’ are set. Once the overtemperature condition is not present anymore, then the
CAN transmitter is automatically switched on.
LINx: The transmitter is disabled and stays in LIN Normal Mode acting like LIN Receive only mode. The
status bit LIN1_FAIL respectively set to ‘01’. Once the overtemperature condition is not present anymore,
then the LIN transmitter is automatically switched on.
HSx: If one or more HSx switches reach the TSD1 threshold, then all HSx switches are turned OFF and the
control bits for HSx are cleared (see registers HS_CTRL1 and HS_CTRL2). The status bits HSx_OC_OT are
set (see register HS_OC_OT_STAT). Once the overtemperature condition is not present anymore, then HSx
has to be configured again by SPI.
Note:
The diagnosis bits are not cleared automatically and have to be cleared via SPI once the
overtemperature condition is not present anymore.
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
15.9.2
Temperature Prewarning
As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1
reaches the thermal prewarning temperature threshold TjPW. Then the status bit TPW is set. This bit can only
be cleared via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the
thermal prewarning is only active if the VCC1 is ON.
15.9.3
SBC Thermal Shutdown
As a highest level of thermal protection a temperature shutdown of the SBC is implemented if the main supply
VCC1 reaches the thermal shutdown temperature threshold TjTSD2. Once a TSD2 event is detected SBC Fail-
Safe Mode is entered for tTSD2 to allow the device to cool down. After this time has expired, the SBC will
automatically change via SBC Restart Mode to SBC Normal Mode (see also Chapter 5.1.6).
When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in SBC
Normal Mode once the overtemperature is not present anymore. Independent of the SBC Mode the thermal
shutdown is only active if VCC1 is ON.
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
15.10
Electrical Characteristics
Table 28
Electrical Specification
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
VCC1 Monitoring; VCC1 = 5.0V Version
Undervoltage Prewarning
Threshold Voltage PW,f
VPW,f
VPW,r
VRT1,f
VRT1,r
VRT2,f
VRT2,r
VRT3,f
VRT3,r
VRT4,f
VRT4,r
4.6
4.7
4.85
4.90
4.75
4.85
4.05
4.15
3.45
3.55
2.8
V
V
V
V
V
V
V
V
V
V
VCC1 falling,
SPI bit is set
P_15.10.1
P_15.10.2
P_15.10.3
P_15.10.4
P_15.10.5
P_15.10.6
P_15.10.7
P_15.10.8
P_15.10.9
P_15.10.10
Undervoltage Prewarning
Threshold Voltage PW,r
4.65
4.5
4.80
4.6
VCC1 rising
Reset Threshold
Voltage RT1,f
default setting;
VCC1 falling
Reset Threshold
Voltage RT1,r
4.6
4.7
default setting;
VCC1 rising
Reset Threshold
Voltage RT2,f
3.75
3.85
3.15
3.25
2.4
3.9
VCC1 falling
Reset Threshold
Voltage RT2,r
4.0
VCC1 rising
Reset Threshold
Voltage RT3,f
3.3
VS ≥ 4V;
VCC1 falling
Reset Threshold
Voltage RT3,r
3.4
VS ≥ 4V;
VCC1 rising
Reset Threshold
Voltage RT4,f
2.65
2.75
VS ≥ 4V;
VCC1 falling
Reset Threshold
Voltage RT4,r
2.5
2.9
VS ≥ 4V;
VCC1 rising
Reset Threshold Hysteresis VRT,hys
50
100
–
200
5.6
mV
V
–
P_15.10.11
P_15.10.50
VCC1 Overvoltage Detection VCC1,OV,r
5.3
1)rising VCC1
Threshold Voltage
VCC1 Overvoltage Detection VCC1,OV,f
Threshold Voltage
5.2
5
–
5.5
14
V
falling VCC1
P_15.10.72
P_15.10.51
P_15.10.12
3)
VCC1 OV Detection Filter
Time
tVCC1,OV_F
tVCC1,SC
10
4
us
ms
3)
VCC1 Short to GND Filter
Time
3.2
4.8
Reset Generator; Pin RO
Reset Low Output Voltage
VRO,L
–
0.2
0.4
V
V
IRO = 1 mA for
P_15.10.14
P_15.10.15
VCC1 ≥ 1 V &
VS ≥ VPOR,f
Reset High Output Voltage VRO,H
0.8 x
–
VCC1
+
IRO = -20 µA
VCC1
0.3 V
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
Table 28
Electrical Specification (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Values
Typ.
20
Unit Note or
Test Condition
Number
Min.
10
Max.
40
Reset Pull-up Resistor
Reset Filter Time
RRO
tRF
kΩ
VRO = 0 V
3)
P_15.10.16
P_15.10.17
4
10
26
µs
V
< VRT1x
CC1
to RO = L see also
Chapter 15.3
2) 3)
Reset Delay Time
tRD1
1.5
2
2.5
ms
P_15.10.18
VCC2 Monitoring
VCC2 Undervoltage
Threshold Voltage (falling)
VCC2,UV,f
VCC2,UV,r
4.5
4.6
20
–
4.75
4.9
V
VCC2 falling
VCC2 rising
–
P_15.10.19
P_15.10.77
P_15.10.20
VCC2 Undervoltage
Threshold Voltage (rising)
–
V
VCC2 Undervoltage detection VCC2,UV, hys
100
250
mV
hysteresis
VCC3 Monitoring
VCC3 Undervoltage Detection VCC3,UV
4.0
4.25
2.85
4.5
V
V
VCC3_ V_CFG=0
hysteresis
included
P_15.10.21
P_15.10.47
VCC3 Undervoltage Detection VCC3,UV
2.65
3.00
3.3V option or
VCC3_ V_CFG=1
hysteresis
included
VCC3 Undervoltage detection VCC3,UV, hys
hysteresis
20
100
–
250
mV
V
–
P_15.10.22
P_15.10.23
VCAN Monitoring
CAN Supply undervoltage
detection threshold
VCAN_UV
4.45
4.85
CAN Normal
Mode,
hysteresis
included;
Watchdog Generator
Long Open Window
Internal Oscillator
3)4)
tLW
160
0.8
200
1.0
240
1.2
ms
P_15.10.24
P_15.10.25
fCLKSBC
MHz
–
Minimum Waiting time during SBC Fail-Safe Mode
Min. waiting time Fail-Safe tFS,min 80 100
Power-on Reset, Over- / Undervoltage Protection
3)5)
120
ms
P_15.10.75
VS Power on reset rising
VS Power on reset falling
VPOR,r
VPOR,f
–
–
4.7
3
V
V
VS increasing
VS decreasing
P_15.10.26
P_15.10.27
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OPTIREG™ SBC TLE9262BQX
Supervision Functions
Table 28
Electrical Specification (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
VS Undervoltage Detection VS,UV
5.3
6.0
V
Supply UV
P_15.10.13
Threshold
threshold for VCC3
and VCC1 SC
detection;
hysteresis
included
VSHS Overvoltage Detection VSHS,OVD
Threshold
20
22
V
Supply OV
supervision for
HSx;
P_15.10.28
hysteresis
included
6)
VSHS Overvoltage Detection VSHS,OVD,hys 100
hysteresis
500
–
mV
V
P_15.10.29
P_15.10.30
VSHS Undervoltage
Detection Threshold
VSHS,UVD
4.8
5.5
Supply UV
supervision for
LINx, HSx, and HS
of GPIOx;
hysteresis
included
6)
VSHS Undervoltage
Detection hysteresis
Overtemperature Shutdown6)
VSHS,UVD,hys 50
200
145
350
165
mV
°C
P_15.10.31
P_15.10.32
Thermal Prewarning
Temperature
TjPW
125
Thermal Shutdown TSD1
Thermal Shutdown TSD2
TjTSD1
165
165
5
185
185
15
200
200
25
°C
°C
°C
P_15.10.33
P_15.10.34
P_15.10.68
TjTSD2
Thermal Shutdown
hysteresis
TjTSD,hys
3)
Deactivation time after
thermal shutdown TSD2
tTSD2
0.8
1
1.2
s
P_15.10.35
1) It is ensured that the threshold VCC1,OV,r is always higher than the highest regulated VCC1 output voltage VCC1,out42
.
2) The reset delay time will start when VCC1 crosses above the selected Vrtx threshold
3) Not subject to production test, tolerance defined by internal oscillator tolerance.
4) An additional safety factor of 1.5 needs to be applied like shown in Figure 48.
5) This time applies for all failure entries except a device thermal shutdown (TSD2 has a typ. 1s waiting time tTSD2
)
6) Not subject to production test, specified by design.
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OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
16
Serial Peripheral Interface
16.1
SPI Block Description
The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input
CLK provided by the microcontroller. The output word appears synchronously at the data output SDO (see
Figure 54).
The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After
the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content.
The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for
other use. The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is
shifted out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy chain capable.
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
CSN low to high: data from shift register is transferred to output functions
CLK
time
Actual data
New data
0 1
+ +
SDI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
time
SDI: will accept data on the falling edge of CLK signal
Actual status
New status
0
1
+
ERR
SDO
ERR
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-
+
time
SDO: will change state on the rising edge of CLK signal
Figure 54 SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure
compared to the register description)
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OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
16.2
Failure Signalization in the SPI Data Output
When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong
SPI commands are either invalid SBC mode commands or commands which are prohibited by the state
machine to avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set
and the SPI Write command is ignored (mostly no partial interpretation). This bit can be only reset by actively
clearing it via a SPI command.
Invalid SPI Commands leading to SPI_FAIL are listed below:
•
Illegal state transitions: Going from SBC Stop to SBC Sleep Mode. In this case the SBC enters in addition the
SBC Restart Mode;
Trying to go to SBC Stop or SBC Sleep mode from SBC Init Mode. In this case SBC Normal Mode is entered;
•
•
Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored or the
new watchdog settings are ignored respectively;
In SBC Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration, PWM
settings and HS configuration settings during SBC Stop Mode, etc.;
the SPI command is ignored in this case;
only WD trigger, returning to Normal Mode, triggering a SBC Soft Reset, and Read & Clear status registers
commands are valid SPI commands in SBC Stop Mode;
•
•
•
When entering SBC Stop Mode and WK_STAT_1 and WK_STAT_2 are not cleared; SPI_FAIL will not be set
but the INT pin will be triggered;
Changing from SBC Stop to Normal Mode and changing the other bits of the M_S_CTRL register. The other
modifications will be ignored;
SBC Sleep Mode: attempt to go to Sleep Mode when all bits in the BUS_CTRL_1 and WK_CTRL_2 registers
are cleared. In this case the SPI_FAIL bit is set and the SBC enters Restart Mode.
Even though the Sleep Mode command is not entered in this case, the rest of the command (e.g modifying
VCC2 or VCC3) is executed and the values stay unchanged during SBC Restart Mode;
Note: At least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode,
i.e. the SBC would not be able to wake up anymore.
If the only wake source is a timer and the timer is OFF then the SBC will wake immediately from Sleep Mode
and enter Restart Mode;
No failure handling is done for the attempt to go to SBC STOP Mode when all bits in the registers
BUS_CTRL_1 and WK_CTRL_2 are cleared because the microcontroller can leave this mode via SPI;
•
•
If VCC3 load sharing VCC3_LS is enabled and the microcontroller tries to clear the bit, then the rest of the
command executed but VCC3_LS will remain set;
Attempt to enter SBC Sleep Mode if WK_MEAS is set to ‘1’ and only WK1_EN or WK2_EN are set as wake
sources. Also in this case the SPI_FAIL bit is set and the SBC enters Restart Mode;
•
•
Setting a longer or equal on-time than the timer period of the respective timer;
SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’;
Note:
There is no SPI fail information for unused addresses.
Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 54):
The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set
for following conditions:
•
•
in case the number of received SPI clocks is not 0 or 16,
in case RO is LOW and SPI frames are being sent at the same time.
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Note:
In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is
not valid if the CLK is high on a falling edge of CSN
The number of received SPI clocks is not 0 or 16:
The number of received input clocks is supervised to be 0- or 16 clock cycles and the input word is discarded
in case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high
during CSN edges. Both errors - 0 bit and 16 bit CLK mismatch or CLK high during CSN edges - are flagged in
the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the
clock is received. The complete SPI command is ignored in this case.
RO is LOW and SPI frames are being sent at the same time:
The ERR flag will be set when the RO pin is triggered (during SBC Restart) and SPI frames are being sent to the
SBC at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below
conditions:
•
•
•
if the command begins when RO is HIGH and it ends when RO is LOW,
if a SPI command will be sent while RO is LOW,
If a SPI command begins when RO is LOW and it ends when RO is HIGH.
and the SDO output will behave as follows:
•
•
always when RO is LOW then SDO will be HIGH,
when a SPI command begins with RO is LOW and ends when RO is HIGH, then the SDO should be ignored
because wrong data will be sent.
Notes
1. It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled low and
SDO is observed - no SPI Clocks are sent in this case
2. The ERR flag could also be set after the SBC has entered SBC Fail-Safe Mode because the SPI communication
is stopped immediately.
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16.3
SPI Programming
For the TLE9262BQX, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between Read
Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the
actual configuration and status information, 8 data bits (BIT15...8) are used.
Writing, clearing and reading is done byte wise. The SPI status bits are not cleared automatically and must be
cleared by the microcontroller, e.g. if the TSD2 was set due to overtemperature. The configuration bits will be
partially automatically cleared by the SBC - please refer to the individual registers description for detailed
information. During SBC Restart Mode the SPI communication is ignored by the SBC, i.e. it is not interpreted.
There are two types of SPI registers:
•
•
Control registers: Those are the registers to configure the SBC, e.g. SBC mode, watchdog trigger, etc
Status registers: Those are the registers where the status of the SBC is signalled, e.g. wake events,
warnings, failures, etc.
For the status registers, the requested information is given in the same SPI command in DO.
For the control registers, also the status of the respective byte is shown in the same SPI command. However,
if the setting is changed this is only shown with the next SPI command (it is only valid after CSN high) of the
same register.
The SBC status information from the SPI status registers, is transmitted in a compressed way with each SPI
response on SDO in the so called Status Information Field register (see also Figure 55). The purpose of this
register is to quickly signal the information to the microcontroller if there was a change in one of the SPI status
registers. In this way, the microcontroller does not need to read constantly all the SPI status registers but only
those registers, which were changed.
Each bit in the Status Information Field represents a SPI status register (see Table 29). As soon as one bit is set
in one of the status registers, then the respective bit in the Status Information Field register will be set. The
register WK_LVL_STAT is not included in the status Information field. This is listed in Table 29.
For Example if bit 0 in the Status Information Field is set to 1, one or more bits of the register 100 0001
(SUP_STAT_1) is set to 1. Then this register needs to be read in a second SPI command. The bit in the Status
Information Field will be set to 0 when all bits in the register 100 0001 are set back to 0.
Table 29
Status Information Field
Corresponding
Bit in Status
Status Register Description
Information Field
Address Bit
100 0001
100 0010
100 0011
0
SUP_STAT_1: Supply Status -VSHS fail, VCCx fail, POR
THERM_STAT: Thermal Protection Status
1
2
DEV_STAT: Device Status - Mode before Wake, WD Fail,
SPI Fail, Failure
3
4
100 0100
100 0110
BUS_STAT: Bus Failure Status: CAN, LINx;
WK_STAT_1, WK_STAT_2: Wake Source Status;
Status bit is set as combinational OR of both registers
5
6
7
100 0000
101 0100
101 0101
SUP_STAT_2: VCC1_WARN/OV, VCC3 Status
HS_OC_OT_STAT: High-Side Over Load Status
HS_OL_STAT: High-Side Open Load Status
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Serial Peripheral Interface
LSB
MSB
DI
0
1
2
3
4
5
6
7
8
x
9
x
10 11 12 13 14 15
R/W
Address Bits
Data Bits
x
x
x
x
x
x
Register content of
selected address
DO
0
1
2
3
4
5
6
7
8
x
9
x
10 11 12 13 14 15
Data Bits
Status Information Field
x
x
x
x
x
x
time
LSB is sent first in SPI message
Figure 55 SPI Operation Mode
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Serial Peripheral Interface
16.4
SPI Bit Mapping
The following figures show the mapping of the registers and the SPI bits of the respective registers.
The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only
read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after write can be seen
with a new read / write command.
The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if
possible) depending on bit 7. To clear a Data Byte of one of the Status Registers bit 7 must be set to 1. The
registers WK_LVL_STAT, and FAM_PROD_STAT are an exception as they show the actual voltage level at the
respective WK pin (LOW/HIGH), or a fixed family/ product ID respectively and can thus not be cleared. It is
recommended for proper diagnosis to clear respective status bits for wake events or failure. However, in
general it is possible to enable drivers without clearing the respective failure flags.
When changing to a different SBC Mode, certain configurations bits will be cleared automatically or modified:
•
•
The SBC Mode bits are updated to the actual status, e.g. when returning to Normal Mode
When changing to a low-power mode (Stop/Sleep), the diagnosis bits of the switches and transceivers are
not cleared. FOx will stay activated if it was triggered before.
•
•
When changing to SBC Stop Mode, the CAN and LIN control bits will not be modified.
When changing to SBC Sleep Mode, the CAN and LIN control bits will be modified if they were not OFF or
wake capable before.
•
•
HSx, VCC2 and VCC3 will stay on when going to Sleep-/Stop Mode (configuration can only be done in
Normal Mode). Diagnosis is active (OC, OL, OT). In case of a failure the switch is turned off and no wake-up
is issued
The configuration bits for HSx and VCC2 in stand-alone configuration are cleared in SBC Restart Mode. FOx
will stay activated if it was triggered before. Depending on the respective configuration, CAN/LIN
transceivers will be either OFF, woken or still wake capable.
Note:
The detailed behavior of the respective SPI bits and control functions is described in Chapter 16.5,
Chapter 16.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the SBC
will modify respective control bits.
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Serial Peripheral Interface
MSB
LSB
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reg.
Type
7 Address Bits [bits 0...6]
8 Data Bits [bits 8...15]
for Configuration & Status Information
for Register Selection
M_S_CTRL
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0 0 0 0 0 0 1
0 0 0 0 0 1 0
0 0 0 0 0 1 1
0 0 0 0 1 0 0
0 0 0 0 1 0 1
0 0 0 0 1 1 0
0 0 0 0 1 1 1
0 0 0 1 0 0 0
0 0 0 1 0 0 1
0 0 0 1 1 0 0
0 0 0 1 1 0 1
0 0 1 0 0 0 0
0 0 1 0 1 0 0
0 0 1 0 1 0 1
0 0 1 0 1 1 1
0 0 1 1 0 0 0
0 0 1 1 0 0 1
0 0 1 1 1 0 0
0 0 1 1 1 1 0
HW_CTRL
WD_CTRL
BUS_CTRL_1
BUS_CTRL_2
WK_CTRL_1
WK_CTRL_2
WK_PUPD_CTRL
WK_FLT_CTRL
TIMER1_CTRL
TIMER2_CTRL
SW_SD_CTRL
HS_CTRL_1
HS_CTRL_2
GPIO_CTRL
PWM1_CTRL
PWM2_CTRL
PWM_FREQ_CTRL
SYS_STAT_CTRL
rw
rw
5
0
1
2
3
3
4
4
-
SUP_STAT_2
SUP_STAT_1
THERM_STAT
rc
rc
rc
1 0 0 0 0 0 0
1 0 0 0 0 0 1
1 0 0 0 0 1 0
1 0 0 0 0 1 1
1 0 0 0 1 0 0
DEV_STAT
BUS_STAT_1
BUS_STAT_2
WK_STAT_1
rc
rc
rc
rc
rc
r
1 0 0 0 1 0 1
1 0 0 0 1 1 0
WK_STAT_2
1 0 0 0 1 1 1
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 0 1 0 1 0 1
1 1 1 1 1 1 0
WK_LVL_STAT
HS_OC_OT_STAT
HS_OL_STAT
FAM_PROD_STAT
rc
rc
r
6
7
Figure 56
SPI Register Mapping
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Serial Peripheral Interface
Figure 57
TLE9262BQX SPI Bit Mapping
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OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
16.5
SPI Control Registers
READ/WRITE Operation (see also Chapter 16.3):
•
•
•
The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Reset.
The ‘Restart Value’ defines the register content after SBC Restart, where ‘x’ means the bit is unchanged.
One 16-bit SPI command consist of two bytes:
- the 7-bit address and one additional bit for the register access mode and
- following the data byte
The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to
the SPI bits 8...15 (see also figure before).
•
•
There are three different bit types:
- ‘r’ = READ: read only bits (or reserved bits)
- ‘rw’ = READ/WRITE: readable and writable bits
- ‘rwh’ = READ/WRITE/Hardware: readable/writable bits, which can also be modified by the SBC hardware
Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be
programmed as “0”.
•
•
•
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only).
Writing to a register is done byte wise by setting the SPI bit 7 to “1”.
SPI control bits are in general not cleared or changed automatically. This must be done by the
microcontroller via SPI programming. Exceptions to this behavior are stated at the respective register
description and the respective bit type is marked with a ‘h’ meaning that the SBC is able to change the
register content.
The registers are addressed wordwise.
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16.5.1
General Control Registers
M_S_CTRL
Mode- and Supply Control (Address 000 0001B)
POR / Soft Reset Value: 0000 0000B; Restart Value: 00x0 00xxB
7
6
5
4
3
2
1
0
VCC1_OV_RS
T
MODE_1
MODE_0
VCC3_ON
VCC2_ON_1 VCC2_ON_0
VCC1_RT_1 VCC1_RT_0
r
rwh
rwh
rwh
rwh
rwh
rwh
rw
rw
Field
Bits
Type
Description
MODE
7:6
rwh
SBC Mode Control
00B , SBC Normal Mode
01B , SBC Sleep Mode
10B , SBC Stop Mode
11B , SBC Reset: Soft Reset is executed (configuration of RO
triggering in bit SOFT_ RESET_RO)
VCC3_ON
VCC2_ON
5
rwh
rwh
VCC3 Mode Control
0B , VCC3 OFF
1B , VCC3 is enabled (as independent voltage regulator)
4:3
VCC2 Mode Control
00B , VCC2 off
01B , VCC2 on in Normal Mode
10B , VCC2 on in Normal and Stop Mode
11B , VCC2 always on (except in SBC Fail-Safe Mode)
VCC1_OV_R
ST
2
rwh
rw
VCC1 Overvoltage leading to Restart / Fail-Safe Mode enable
0B , VCC1_ OV is set in case of VCC1_OV; no SBC Restart or Fail-
Safe is entered for VCC1_OV
1B , VCC1_ OV is set in case of VCC1_OV; depending on the
device configuration SBC Restart or SBC Fail-Safe Mode is
entered (see Chapter 5.1.1);
VCC1_RT
1:0
VCC1 Reset Threshold Control
00B , Vrt1 selected (highest threshold)
01B , Vrt2 selected
10B , Vrt3 selected
11B , Vrt4 selected
Notes
1. It is not possible to change from Stop to Sleep Mode via SPI Command. See also the State Machine Chapter
2. After entering SBC Restart Mode, the MODE bits will be automatically set to SBC Normal Mode. The VCC2_ON
bits will be automatically set to OFF after entering SBC Restart Mode and after OT.
3. The SPI output will always show the previously written state with a Write Command (what has been
programmed before)
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HW_CTRL
Mode- and Supply Control (Address 000 0010B)
POR / Soft Reset Value: y000 y000B;
Restart Value: xx0x x00xB
7
6
5
4
3
2
1
0
SOFT_RESET
_RO
VCC3_VS_UV
_OFF
VCC3_LS_ST
P_ON
VCC3_V_CFG
FO_ON
VCC3_LS
Reserved
CFG
r
rw
rw
rwh
rw
rw
r
rw
rw
Field
Bits
Type
Description
VCC3_
V_CFG
7
rw
VCC3 Output Voltage Configuration (if configured as
independent voltage regulator)
0B , VCC3 has same output voltage as VCC1
1B , VCC3 is configured to either 3.3V or 1.8V (depending on VCC1
derivative)
SOFT_
RESET_RO
6
5
rw
Soft Reset Configuration
0B , RO will be triggered (pulled low) during a Soft Reset
1B , No RO triggering during a Soft Reset
FO_ON
rwh
Failure Output Activation (FO1..3)
0B , FOx not activated by software, FO can be activated by
defined failures (see Chapter 14)
1B , FOx activated by software (via SPI)
VCC3_VS_
UV_OFF
4
3
rw
rw
VCC3 VS_UV shutdown configuration
0B , VCC3 will be disabled automatically at VS_UV
1B , VCC3 will stay enabled even below VS_UV
VCC3_LS
VCC3 Configuration
0B , VCC3 operating as a stand-alone regulator
1B , VCC3 in load sharing operation with VCC1
Reserved
2
1
r
Reserved, always reads as 0
VCC3_LS_
STP_ON
rw
VCC3 Load Sharing in SBC Stop Mode configuration
0B , VCC3 in LS configuration during SBC Stop Mode and high-
power mode: disabled
1B , VCC3 in LS configuration during SBC Stop Mode and high-
power mode: enabled
CFG
0
rw
Configuration Select (see also Table 5)
0B , Depending on hardware configuration, SBC Restart or Fail-
Safe Mode is reached after the 2. watchdog trigger failure
(=default) - Config 3/4
1B , Depending on hardware configuration, SBC Restart or Fail-
Safe Mode is reached after the 1. watchdog trigger failure -
Config 1/2
Notes
1. Clearing the FO_ON bit will not disable the FOx outputs for the case a failure occurred which triggered the FOx
outputs. In this case the FOx outputs have to be disabled by clearing the FAILURE bit.
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If the FO_ON bit is set by the software then it will be cleared by the SBC after SBC Restart Mode was entered
and the FOx outputs will be disabled. See also Chapter 14 for FOx activation and deactivation.
2. After triggering a SBC Soft Reset the bits VCC3_V_CFG and VCC3_LS are not reset if they were set before, i.e. it
stays unchanged, which is stated by the ‘y’ in the POR / Soft Reset Value. POR value: 0000 0000 and Soft Reset
value: xx00 x00x
3. VCC3_LS_STP_ON: Is a combination of load sharing and VCC1 active peak in Stop mode
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Serial Peripheral Interface
WD_CTRL
Watchdog Control (Address 000 0011B)
POR / Soft Reset Value: 0001 0100B;
Restart Value: x0xx 0100B
7
6
5
4
3
2
1
0
WD_STM_
EN_0
WD_EN_
WK_BUS
CHECKSUM
WD_WIN
Reserved WD_TIMER_2 WD_TIMER_1 WD_TIMER_0
r
rw
rwh
rw
rw
r
rwh
rwh
rwh
Field
Bits
Type
Description
CHECKSUM
7
rw
Watchdog Setting Check Sum Bit
The sum of bits 7:0 needs to have even parity (see Chapter 15.2.3)
0B , Counts as 0 for checksum calculation
1B , Counts as 1 for checksum calculation
WD_STM_
EN_0
6
rwh
Watchdog Deactivation during Stop Mode, bit 0
(Chapter 15.2.4)
0B , Watchdog is active in Stop Mode
1B , Watchdog is deactivated in Stop Mode
WD_WIN
5
4
rw
rw
Watchdog Type Selection
0B , Watchdog works as a Time-Out watchdog
1B , Watchdog works as a Window watchdog
WD_EN_
WK_BUS
Watchdog Enable after Bus (CAN/LIN) Wake in SBC Stop Mode
0B , Watchdog will not start after a CAN/LINx wake
1B , Watchdog starts with a long open window after CAN/LINx
Wake
Reserved
3
r
Reserved, always reads as 0
WD_TIMER 2:0
rwh
Watchdog Timer Period
000B , 10ms
001B , 20ms
010B , 50ms
011B , 100ms
100B , 200ms
101B , 500ms
110B , 1000ms
111B , reserved
Notes
1. See also Chapter 15.2.4 for more information on disabling the watchdog in SBC Stop Mode.
2. See Chapter 15.2.5 for more information on the effect of the bit WD_EN_WK_BUS.
3. See Chapter 15.2.3 for calculation of checksum.
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Serial Peripheral Interface
BUS_CTRL_1
Bus Control (Address 000 0100B)
POR / Soft Reset Value: 0010 0000B;
Restart Value: xxxy y0yyB
7
6
5
4
3
2
1
0
LIN_FLASH
LIN_LSM
LIN_TXD_TO
LIN1_1
LIN1_0
Reserved
CAN_1
CAN_0
r
rw
rw
rw
rwh
rwh
r
rwh
rwh
Field
Bits
Type
Description
LIN_FLASH
7
rw
LINx Flash Programming Mode
0B , Slope control mechanism active
1B , Deactivation of slope control for baud rates up to 115kBaud
LIN_LSM
6
rw
LINx Low-Slope Mode Selection
0B , LIN Normal-Mode is activated
1B , LIN Low-Slope Mode (10.4kBaud) activated
LIN_TXD_
TO
5
rw
LINx TXD Time-Out Control
0B , TXD Time-Out feature disabled
1B , TXD Time-Out feature enabled
LIN1
4:3
rwh
LIN1-Module Mode
00B , LIN1 OFF
01B , LIN1 is wake capable
10B , LIN1 Receive Only Mode
11B , LIN1 Normal Mode
Reserved
CAN
2
r
Reserved, always reads as 0
1:0
rwh
HS-CAN Module Modes
00B , CAN OFF
01B , CAN is wake capable
10B , CAN Receive Only Mode
11B , CAN Normal Mode
Notes
1. Changes in the bits LIN_FLASH, LIN_LSM, and LIN_TXD_ TO will be effective immediately once CSN goes to
‘1’ and applies for both LIN transceivers.’
2. The reset values for the LINx and CAN transceivers are marked with ‘y’ because they will vary depending on
the cause of change - see below.
3. see Figure 26 and Figure 33 for detailed state changes of LIN and CAN Transceiver for different SBC modes.
4. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),
then the wake registers BUS_CTRL_1 and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0
1001’ and ‘x0x0 0111’ in order to ensure that the device can be woken again.
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Serial Peripheral Interface
BUS_CTRL_2
Bus Control (Address 000 0101B)
POR / Soft Reset Value: 0000 0000B; Restart Value: 00x0 0000B
7
6
5
4
3
2
1
0
Reserved
Reserved
I_PEAK_TH
Reserved
Reserved
Reserved
Reserved
Reserved
r
r
r
rw
r
r
r
r
r
Field
Bits
Type
r
Description
Reserved
7:6
5
Reserved, always reads as 0
I_PEAK_TH
rw
VCC1 Active Peak Threshold Selection
0B , low VCC1 active peak threshold selected (ICC1,peak_1)
1B , higher VCC1 active peak threshold selected (ICC1,peak_2)
Reserved
4:0
r
Reserved, always reads as 0
Notes
1. The bit I_PEAK_TH can be modified in SBC Init and Normal Mode. In SBC Stop Mode this bit is Read only but
SPI_FAIL will not be set when trying to modify the bit in SBC STOP Mode and no INT is triggered in case INT_
GLOBAL is set.
2. see Figure 26 for detailed state changes of CAN Transceiver for different SBC modes
3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),
then the wake registers , and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0 1001’, and ‘x0x0
0111’ in order to ensure that the device can be woken again.
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Serial Peripheral Interface
WK_CTRL_1
Internal Wake Input Control (Address 000 0110B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xx00 0000B
7
6
5
4
3
2
1
0
TIMER2_WK_ TIMER1_WK_
WD_STM_
EN_1
Reserved
Reserved
Reserved
Reserved
Reserved
EN
EN
r
rw
rw
r
r
r
rwh
r
r
Field
Bits
Type
Description
TIMER2_WK 7
_EN
rw
Timer2 Wake Source Control (for cyclic wake)
0B , Timer2 wake disabled
1B , Timer2 is enabled as a wake source
TIMER1_WK 6
_EN
rw
Timer1 Wake Source Control (for cyclic wake)
0B , Timer1 wake disabled
1B , Timer1 is enabled as a wake source
Reserved
5:3
r
Reserved, always reads as 0
WD_STM_
EN_1
2
rwh
Watchdog Deactivation during Stop Mode, bit 1
(Chapter 15.2.4)
0B , Watchdog is active in Stop Mode
1B , Watchdog is deactivated in Stop Mode
Reserved
1:0
r
Reserved, always reads as 0
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Serial Peripheral Interface
WK_CTRL_2
External Wake Source Control (Address 000 0111B)
POR / Soft Reset Value: 0000 0111B;
Restart Value: x0x0 0xxxB
7
6
5
4
3
2
1
0
INT_GLOBAL Reserved
WK_MEAS
Reserved
Reserved
WK3_EN
WK2_EN
WK1_EN
w
r
rw
r
rw
r
r
rw
rw
rw
Field
INT_
GLOBAL
Bits
Type
Description
7
rw
Global Interrupt Configuration (see also Chapter 13.1)
0B , Only wake sources trigger INT (default)
1B , All status information register bits will trigger INT (including
all wake sources)
Reserved
WK_MEAS
6
5
r
Reserved, always reads as 0
rw
WK / Measurement selection (see also Chapter 12.2.2)
0B , WK functionality enabled for WK1 and WK2
1B , Measurement functionality enabled; WK1 & WK2 are
disabled as wake sources, i.e. bits WK1/2_EN bits are ignored
Reserved
WK3_EN
4:3
2
r
Reserved, always reads as 0
rw
WK3 Wake Source Control
0B , WK3 wake disabled
1B , WK3 is enabled as a wake source
WK2_EN
WK1_EN
1
0
rw
rw
WK2 Wake Source Control
0B , WK2 wake disabled
1B , WK2 is enabled as a wake source
WK1 Wake Source Control
0B , WK1 wake disabled
1B , WK1 is enabled as a wake source
Notes
1. WK_MEAS is by default configured for standard WK functionality (WK1 and WK2). The bits WK1_EN and
WK2_EN are ignored in case WK_MEAS is activated. If the bit is set to ‘1’ then the measurement function is
enabled during Normal Mode & the bits WK1_EN and WK2_EN are ignored. The bits WK1/”_LVL bits need to be
ignored as well.
2. The wake sources LINx and CAN are selected in the register BUS_CTRL_1 by setting the respective bits to
‘wake capable’
3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),
then the wake registers BUS_CTRL_1 and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0
1001’ and ‘x0x0 0111’ in order to ensure that the device can be woken again.
Datasheet
138
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
WK_PUPD_CTRL
Wake Input Level Control (Address 000 1000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 00xx xxxxB
7
6
5
4
3
2
1
0
Reserved
Reserved WK3_PUPD_1 WK3_PUPD_0 WK2_PUPD_1 WK2_PUPD_0 WK1_PUPD_1 WK1_PUPD_0
r
r
r
rw
rw
rw
rw
rw
rw
Field
Reserved
Bits
Type
Description
7:6
r
Reserved, always reads as 0
WK3_PUPD 5:4
WK2_PUPD 3:2
WK1_PUPD 1:0
rw
WK3 Pull-Up / Pull-Down Configuration
00B , No pull-up / pull-down selected
01B , Pull-down resistor selected
10B , Pull-up resistor selected
11B , Automatic switching to pull-up or pull-down
rw
rw
WK2 Pull-Up / Pull-Down Configuration
00B , No pull-up / pull-down selected
01B , Pull-down resistor selected
10B , Pull-up resistor selected
11B , Automatic switching to pull-up or pull-down
WK1 Pull-Up / Pull-Down Configuration
00B , No pull-up / pull-down selected
01B , Pull-down resistor selected
10B , Pull-up resistor selected
11B , Automatic switching to pull-up or pull-down
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
WK_FLT_CTRL
Wake Input Filter Time Control (Address 000 1001B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 00xx xxxxB
7
6
5
4
3
2
1
0
Reserved
Reserved
WK3_FLT_1 WK3_FLT_0 WK2_FLT_1 WK2_FLT_0 WK1_FLT_1 WK1_FLT_0
r
r
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Reserved
WK3_FLT
7:6
5:4
r
Reserved, always reads as 0
rw
WK3 Filter Time Configuration
00B , Configuration A: Filter with 16µs filter time (static sensing)
01B , Configuration B: Filter with 64µs filter time (static sensing)
10B , Configuration C: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer1
11B , Configuration D: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer2
WK2_FLT
WK1_FLT
3:2
1:0
rw
rw
WK2 Filter Time Configuration
00B , Configuration A: Filter with 16µs filter time (static sensing)
01B , Configuration B: Filter with 64µs filter time (static sensing)
10B , Configuration C: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer1
11B , Configuration D: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer2
WK1 Filter Time Configuration
00B , Configuration A: Filter with 16µs filter time (static sensing)
01B , Configuration B: Filter with 64µs filter time (static sensing)
10B , Configuration C: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer1
11B , Configuration D: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer2
Note:
When selecting a filter time configuration, the user must make sure to also assign the respective
timer to at least one HS switch during cyclic sense operation
Datasheet
140
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
TIMER1_CTRL
Timer1 Control and Selection (Address 000 1100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
TIMER1_
ON_2
TIMER1_
ON_1
TIMER1_
ON_0
TIMER1_
PER_2
TIMER1_
PER_1
TIMER1_
PER_0
Reserved
Reserved
r
r
rwh
rwh
rwh
r
rwh
rwh
rwh
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
TIMER1_
ON
6:4
rwh
Timer1 On-Time Configuration
000B , OFF / Low (timer not running, HSx output is low)
001B , 0.1ms on-time
010B , 0.3ms on-time
011B , 1.0ms on-time
100B , 10ms on-time
101B , 20ms on-time
110B , OFF / HIGH (timer not running, HSx output is high)
111B , reserved
Reserved
3
r
Reserved, always reads as 0
TIMER1_
PER
2:0
rwh
Timer1 Period Configuration
000B , 10ms
001B , 20ms
010B , 50ms
011B , 100ms
100B , 200ms
101B , 1s
110B , 2s
111B , reserved
Notes
1. A timer must be first assigned and is then automatically activated as soon as the on-time is configured.
2. If cyclic sense is selected and the HS switches are cleared during SBC Restart Mode, then also the timer
settings (period and on-time) are cleared to avoid incorrect switch detection.
3. In case the timer are set as wake sources and cyclic sense is running, then both cyclic sense and cyclic wake
will be active at the same time.
Datasheet
141
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
TIMER2_CTRL
Timer2 Control and selection (Address 000 1101B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
TIMER2_
ON_2
TIMER2_
ON_1
TIMER2_
ON_0
TIMER2_
PER_2
TIMER2_
PER_1
TIMER2_
PER_0
Reserved
Reserved
r
r
rwh
rwh
rwh
r
rwh
rwh
rwh
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
TIMER2_
ON
6:4
rwh
Timer2 On-Time Configuration
000B , OFF / Low (timer not running, HSx output is low)
001B , 0.1ms on-time
010B , 0.3ms on-time
011B , 1.0ms on-time
100B , 10ms on-time
101B , 20ms on-time
110B , OFF / HIGH (timer not running, HSx output is high)
111B , reserved
Reserved
3
r
Reserved, always reads as 0
TIMER2_
PER
2:0
rwh
Timer2 Period Configuration
000B , 10ms
001B , 20ms
010B , 50ms
011B , 100ms
100B , 200ms
101B , 1s
110B , 2s
111B , reserved
Notes
1. A timer must be first assigned and is then automatically activated as soon as the on-time is configured.
2. If cyclic sense is selected and the HS switches are cleared during SBC Restart Mode, then also the timer
settings (period and on-time) are cleared to avoid incorrect switch detection.
Datasheet
142
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
SW_SD_CTRL
Switch Shutdown Control (Address 001 0000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0xxx 0000B
7
6
5
4
3
2
1
0
HS_OV_SD_E HS_UV_SD_E HS_OV_UV_R
Reserved
Reserved
Reserved
Reserved
Reserved
N
N
EC
r
r
rw
rw
rw
r
r
r
r
Field
Bits
7
Type
Description
Reserved
r
Reserved, always reads as 0
HS_OV_SD_
EN
6
rw
Shutdown Disabling of HS1...4 in case of VSHS OV
0B , shutdown enabled in case of VSHS OV
1B , shutdown disabled in case of VSHS OV
HS_UV_SD_
EN
5
4
rw
rw
Shutdown Disabling of HS1...4 in case of VSHS UV
0B , shutdown enabled in case of VSHS UV
1B , shutdown disabled in case of VSHS UV
HS_OV_UV_
REC
Switch Recovery after Removal of VSHS OV/UV for HS1...4
0B , Switch recovery is disabled
1B , Previous state before VSHS OV/UV is enabled after OV/UV
condition is removed
Reserved
3:0
r
Reserved, always reads as 0
Datasheet
143
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
HS_CTRL1
High-Side Switch Control 1 (Address 001 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
Reserved
HS2_2
HS2_1
HS2_0
Reserved
HS1_2
HS1_1
HS1_0
r
rw
rwh
rwh
rwh
r
rwh
rwh
rwh
Field
Bits
Type
Description
Reserved
HS2
7
r
Reserved, always reads as 0
6:4
rwh
HS2 Configuration
000B , Off
001B , On
010B , Controlled by Timer1
011B , Controlled by Timer2
100B , Controlled by PWM1
101B , Controlled by PWM2
110B , Reserved
111B , Reserved
Reserved
HS1
3
r
Reserved, always reads as 0
2:0
rwh
HS1 Configuration
000B , Off
001B , On
010B , Controlled by Timer1
011B , Controlled by Timer2
100B , Controlled by PWM1
101B , Controlled by PWM2
110B , Reserved
111B , Reserved
Note:
The bits for the switches are also reset in case of overcurrent and overtemperature.
Datasheet
144
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
HS_CTRL2
High-Side Switch Control 2 (Address 001 0101B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
Reserved
HS4_2
HS4_1
HS4_0
Reserved
HS3_2
HS3_1
HS3_0
r
r
rwh
rwh
rwh
r
rwh
rwh
rwh
Field
Bits
Type
Description
Reserved
HS4
7
r
Reserved, always reads as 0
6:4
rwh
HS4 Configuration
000B , Off
001B , On
010B , Controlled by Timer1
011B , Controlled by Timer2
100B , Controlled by PWM1
101B , Controlled by PWM2
110B , Reserved
111B , Reserved
Reserved
HS3
3
r
Reserved, always reads as 0
2:0
rwh
HS3 Configuration
000B , Off
001B , On
010B , Controlled by Timer1
011B , Controlled by Timer2
100B , Controlled by PWM1
101B , Controlled by PWM2
110B , Reserved
111B , Reserved
Note:
The bits for the switches are also reset in case of overcurrent and overtemperature.
Datasheet
145
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
GPIO_CTRL
GPIO Configuration Control (Address 001 0111B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
FO_DC_1
FO_DC_0
GPIO2_2
GPIO2_1
GPIO2_0
GPIO1_2
GPIO1_1
GPIO1_0
r
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
FO_DC
7:6
rw
Duty Cycle Configuration of FO3 (if selected)
00B , 20%
01B , 10%
10B , 5%
11B , 2.5%
GPIO2
5:3
rw
GPIO2 Configuration
000B , FO3 selected
001B , FO3 selected
010B , FO3 selected
011B , FO3 selected
100B , OFF
101B , Wake input enabled (16µs static filter)
110B , Low-Side Switch ON
111B , High-Side Switch ON
GPIO1
2:0
rw
GPIO1 Configuration
000B , FO2 selected
001B , FO2 selected
010B , FO2 selected
011B , FO2 selected
100B , OFF
101B , Wake input enabled (16µs static filter)
110B , Low-Side Switch ON
111B , High-Side Switch ON
Note:
When selecting a filter time configuration, the user must make sure to also assign the respective
timer to at least one HS switch during cyclic sense operation
Datasheet
146
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
PWM1_CTRL
PWM1 Configuration Control (Address 001 1000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0
r
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
rw
Description
PWM1_DC
7:0
PWM1 Duty Cycle (bit0=LSB; bit7=MSB)
0000 0000B, 100% OFF
xxxx xxxx B, ON with DC fraction of 255
1111 1111B, 100% ON
Note:
The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch,
e.g. the PWM setting ‘000 0001’ could not be realized.
PWM2_CTRL
PWM2 Configuration Control (Address 001 1001B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
PWM2_DC_7 PWM2_DC_6 PWM2_DC_5 PWM2_DC_4 PWM2_DC_3 PWM2_DC_2 PWM2_DC_1 PWM2_DC_0
r
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
rw
Description
PWM2_DC
7:0
PWM2 Duty Cycle (bit0=LSB; bit7=MSB)
0000 0000B, 100% OFF
xxxx xxxxB, ON with DC fraction of 255
1111 1111B, 100% ON
Note:
The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch,
e.g. the PWM setting ‘000 0001’ could not be realized.
Datasheet
147
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
PWM_FREQ_CTRL
PWM Frequency Configuration Control (Address 001 1100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0x0xB
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved PWM2_FREQ Reserved PWM1_FREQ
r
r
r
r
r
r
rw
r
rw
Field
Bits
Type
Description
Reserved
7:3
2
r
Reserved, always reads as 0
PWM2_
FREQ
rw
PWM2 Frequency Selection
0B , 200Hz configuration
1B , 400Hz configuration
Reserved
1
0
r
Reserved, always reads as 0
PWM1_
FREQ
rw
PWM1 Frequency Selection
0B , 200Hz configuration
1B , 400Hz configuration
Notes
1. The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g. the
PWM setting ‘000 0001’ could not be realized.
2. The actual PWM frequency correlates with the internal clock tolerance as specified in parameter fCLKSBC
.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
SYS_STATUS_CTRL
System Status Control (Address 001 1110B)
POR Value: 0000 0000B;
Restart Value/Soft Reset Value: xxxx xxxxB
7
6
5
4
3
2
1
0
SYS_STAT_7 SYS_STAT_6 SYS_STAT_5 SYS_STAT_4 SYS_STAT_3 SYS_STAT_2 SYS_STAT_1 SYS_STAT_0
r
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
rw
Description
SYS_STAT
7:0
System Status Control Byte (bit0=LSB; bit7=MSB)
Dedicated byte for system configuration, access only by
microcontroller. Cleared after power up and Soft Reset
Notes
1. The SYS_STATUS_CTRL register is an exception for the default values, i.e. it will keep its configured value also
after a Soft Reset.
2. This byte is intended for storing system configurations of the ECU by the microcontroller and is only accessible
in SBC Normal Mode. The byte is not accessible by the SBC and is also not cleared after Fail-Safe or SBC
Restart Mode. It allows the microcontroller to quickly store system configuration without loosing the data.
Datasheet
149
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
16.6
SPI Status Information Registers
READ/CLEAR Operation (see also Chapter 16.3):
•
One 16-bit SPI command consist of two bytes:
- the 7-bit address and one additional bit for the register access mode and
- following the data byte
The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to
the SPI bits 8...15 (see also figure).
•
There are two different bit types:
- ‘r’ = READ: read only bits (or reserved bits)
- ‘rc’ = READ/CLEAR: readable and clearable bits
•
•
•
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only)
Clearing a register is done byte wise by setting the SPI bit 7 to “1”
SPI status registers are in general not cleared or changed automatically (an exception are the WD_FAIL
bits). This must be done by the microcontroller via SPI command
The registers are addressed wordwise.
Datasheet
150
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
16.6.1
General Status Registers
SUP_STAT_2
Supply Voltage Fail Status (Address 100 0000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0x0x xxxxB
7
6
5
4
3
2
1
0
Reserved
VS_UV
Reserved
VCC3_OC
VCC3_UV
VCC3_OT
VCC1_OV
VCC1_WARN
r
r
rc
r
rc
rc
rc
rc
rc
Field
Bits
Type
Description
Reserved
VS_UV
7
6
r
Reserved, always reads as 0
rc
VS Undervoltage Detection (VS,UV)
0B , No VS undervoltage detected
1B , VS undervoltage detected
Reserved
VCC3_OC
5
4
r
Reserved, always reads as 0
rc
VCC3 Overcurrent Detection
0B , No OC
1B , OC detected
VCC3_UV
VCC3_OT
3
2
1
0
rc
rc
rc
rc
VCC3 Undervoltage Detection
0B , No VCC3 UV detection
1B , VCC3 UV Fail detected
VCC3 Overtemperature Detection
0B , No overtemperature
1B , VCC3 overtemperature detected
VCC1_
OV
VCC1 Overvoltage Detection (VCC1,OV,r
0B , No VCC1 overvoltage warning
1B , VCC1 overvoltage detected
)
VCC1_
WARN
VCC1 Undervoltage Prewarning (VPW,f
0B , No VCC1 undervoltage prewarning
1B , VCC1 undervoltage prewarning detected
)
Notes
1. The VCC1 undervoltage prewarning threshold VPW,f / VPW,r is a fixed threshold and independent of the VCC1
undervoltage reset thresholds.
Datasheet
151
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
SUP_STAT_1
Supply Voltage Fail Status (Address 100 0001B)
POR / Soft Reset Value: y000 0000B;
Restart Value: xxxx xx0xB
7
6
5
4
3
2
1
0
POR
VSHS_UV
VSHS_OV
VCC2_OT
VCC2_UV
VCC1_SC VCC1_UV_FS VCC1_UV
r
rc
rc
rc
rc
rc
rc
rc
rc
Field
Bits
Type
Description
POR
7
6
5
4
3
2
1
0
rc
rc
rc
rc
rc
rc
rc
rc
Power-On Reset Detection
0B , No POR
1B , POR occurred
VSHS_UV
VSHS_OV
VCC2_OT
VCC2_UV
VCC1_SC
VSHS Undervoltage Detection (VSHS,UVD
0B , No VSHS-UV
1B , VSHS-UV detected
)
VSHS Overvoltage Detection (VSHS,OVD
0B , No VSHS-OV
1B , VSHS-OV detected
)
VCC2 Overtemperature Detection
0B , No overtemperature
1B , VCC2 overtemperature detected
VCC2 Undervoltage Detection (VCC2,UV,f
0B , No VCC2 undervoltage
1B , VCC2 undervoltage detected
)
VCC1 Short to GND Detection (<Vrtx for t>4ms after switch on)
0B , No short
1B , VCC1 short to GND detected
VCC1_UV
_FS
VCC1 UV-Detection (due to Vrtx reset)
0B , No Fail-Safe Mode entry due to 4th consecutive VCC1_UV
1B , Fail-Safe Mode entry due to 4th consecutive VCC1_UV
VCC1_UV
VCC1 UV-Detection (due to Vrtx reset)
0B , No VCC1_UV detection
1B , VCC1 UV-Fail detected
Notes
1. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on
reset (POR value = 1000 0000). However it will be cleared after a SBC Soft Reset command (Soft Reset value =
0000 0000).
2. During Sleep Mode, the bits VCC1_SC,VCC1_OV and VCC1_UV will not be set when VCC1 is off
3. The VCC1_UV bit is never updated in SBC Restart Mode, in SBC Init Mode it is only updated after RO was
released for the first time, it is always updated in SBC Normal and Stop Mode, and it is always updated in any
SBC modes in a VCC1_SC condition (after VCC1_UV = 1 for >4ms).
Datasheet
152
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
THERM_STAT
Thermal Protection Status (Address 100 0010B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0xxxB
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
TSD2
TSD1
TPW
r
r
r
r
r
r
rc
rc
rc
Field
Bits
Type
Description
Reserved
TSD2
7:3
2
r
Reserved, always reads as 0
rc
TSD2 Thermal Shut-Down Detection
0B , No TSD2 event
1B , TSD2 OT detected - leading to SBC Fail-Safe Mode
TSD1
TPW
1
0
rc
rc
TSD1 Thermal Shut-Down Detection
0B , No TSD1 fail
1B , TSD1 OT detected
Thermal Pre Warning
0B , No Thermal Pre warning
1B , Thermal Pre warning detected
Note:
TSD1 and TSD2 are not reset automatically, even if the temperature pre warning or TSD1 OT
condition is not present anymore. Also TSD2 is not reset.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
DEV_STAT
Device Information Status (Address 100 0011B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xx00 xxxxB
7
6
5
4
3
2
1
0
DEV_STAT_1 DEV_STAT_0 Reserved
rc rc
Reserved
WD_FAIL_1 WD_FAIL_0
rh rh
SPI_FAIL
FAILURE
r
r
r
rc
rc
Field
Bits
Type
Description
DEV_STAT 7:6
rc
Device Status before Restart Mode
00B , Cleared (Register must be actively cleared)
01B , Restart due to failure (WD fail, TSD2, VCC1_UV); also after a
wake from Fail-Safe Mode
10B , Sleep Mode
11B , Reserved
Reserved
WD_FAIL
5:4
3:2
r
Reserved, always reads as 0
rh
Number of WD-Failure Events (1/2 WD failures depending on
CFG)
00B , No WD Fail
01B , 1x WD Fail, FOx activation - Config 2 selected
10B , 2x WD Fail, FOx activation - Config 1 / 3 / 4 selected
11B , Reserved (never reached)
SPI_FAIL
FAILURE
1
0
rc
rc
SPI Fail Information
0B , No SPI fail
1B , Invalid SPI command detected
Activation of Fail Output FO
0B , No Failure
1B , Failure occurred
Notes
1. The bits DEV_STAT show the status of the device before it went through Restart. Either the device came from
regular Sleep Mode (‘10’) or a failure (‘01’ - SBC Restart or SBC Fail-Safe Mode: WD fail, TSD2 fail, VCC_UV fail
or VCC1_OV if bit VCC1_OV_RST is set) occurred. Failure is also an illegal command from SBC Stop to SBC
Sleep Mode or going to SBC Sleep Mode without activation of any wake source. Coming from SBC Sleep Mode
(‘10’) will also be shown if there was a trial to enter SBC Sleep Mode without having cleared all wake flags
before.
2. The WD_FAIL bits are configured as a counter and are the only status bits, which are cleared automatically
by the SBC. They are cleared after a successful watchdog trigger and when the watchdog is stopped (also in
SBC Sleep and Fail-Safe Mode unless it was reached due to a watchdog failure). See also Chapter 14.1.
3. The SPI_FAIL bit is cleared only by SPI command
4. In case of Config 2/4 the WD_Fail counter is frozen in case of WD trigger failure until a successful WD trigger.
5. If CFG = ‘0’ then a 1st watchdog failure will not trigger the FO outputs or the FAILURE bit but only force the SBC
into SBC Restart Mode.
Datasheet
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Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
BUS_STAT_1
Bus Communication Status (Address 100 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0xx0 0xxxB
7
6
5
4
3
2
1
0
Reserved LIN1_FAIL_1 LIN1_FAIL_0 Reserved
Reserved
CAN_FAIL_1 CAN_FAIL_0
VCAN_UV
r
r
rc
rc
r
r
rc
rc
rc
Field
Bits
7
Type
Description
Reserved
LIN1_FAIL
r
Reserved, always reads as 0
6:5
rc
LIN1 Failure Status
00B , No error
01B , LIN1 TSD
10B , LIN1_TXD_DOM: TXD dominant time out for more than 20ms
11B , LIN1_BUS_DOM: BUS dominant time out for more than
20ms
Reserved
CAN_FAIL
4:3
2:1
r
Reserved, always reads as 0
rc
CAN Failure Status
00B , No error
01B , CAN TSD
10B , CAN_TXD_DOM: TXD dominant time out for longer than
tTxD_CAN_TO
11B , CAN_BUS_DOM: BUS dominant time out for longer than
tBUS_CAN_TO
VCAN_UV
Notes
0
rc
Undervoltage CAN Bus Supply
0B , Normal operation
1B , CAN Supply undervoltage detected. Transmitter disabled
1. The VCAN_UV comparator is enabled if the mode bit CAN_1 = ‘1’, i.e. in CAN Normal or CAN Receive Only Mode.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
WK_STAT_1
Wake-up Source and Information Status (Address 100 0110B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0xxx 0xxxB
7
6
5
4
3
2
1
0
Reserved
LIN1_WU
CAN_WU
TIMER_WU
Reserved
WK3_WU
WK2_WU
WK1_WU
r
r
rc
rc
rc
r
rc
rc
rc
Field
Bits
Type
Description
Reserved
LIN1_WU
7
6
r
Reserved, always reads as 0
rc
Wake up via LIN1 Bus
0B , No Wake up
1B , Wake up
CAN_WU
5
4
rc
rc
Wake up via CAN Bus
0B , No Wake up
1B , Wake up
TIMER_WU
Wake up via TimerX
0B , No Wake up
1B , Wake up
Reserved
WK3_WU
3
2
r
Reserved, always reads as 0
rc
Wake up via WK3
0B , No Wake up
1B , Wake up
WK2_WU
WK1_WU
1
0
rc
rc
Wake up via WK2
0B , No Wake up
1B , Wake up
Wake up via WK1
0B , No Wake up
1B , Wake up
Note:
The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode
Datasheet
156
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
WK_STAT_2
Wake-up Source and Information Status (Address 100 0111B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 00xx 0000B
7
6
5
4
3
2
1
0
Reserved
Reserved
GPIO2_WU GPIO1_WU
Reserved
Reserved
Reserved
Reserved
r
r
r
rc
rc
r
r
r
r
Field
Bits
Type
Description
Reserved
7:6
5
r
Reserved, always reads as 0
GPIO2_WU
rc
Wake up via GPIO2
0B , No Wake up
1B , Wake up
GPIO1_WU
Reserved
4
rc
r
Wake up via GPIO1
0B , No Wake up
1B , Wake up
3:0
Reserved, always reads as 0
Datasheet
157
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
WK_LVL_STAT
WK Input Level (Address 100 1000B)
POR / Soft Reset Value: xx00 0xxxB;
Restart Value: xxxx 0xxxB
7
6
5
4
3
2
1
0
SBC_DEV
_LVL
CFGP
GPIO2_LVL GPIO1_LVL
Reserved
WK3_LVL
WK2_LVL
WK1_LVL
r
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
SBC_DEV
_LVL
7
6
5
4
r
Status of SBC Operating Mode at FO3/TEST Pin
0B , User Mode activated
1B , SBC Development Mode activated
CFGP
r
r
r
Device Configuration Status
0B , No external pull-up resistor connected on INT (Config 2/4)
1B , External pull-up resistor connected on INT (Config 1/3)
GPIO2_LVL
GPIO1_LVL
Status of GPIO2 (if selected as GPIO)
0B , Low Level (=0)
1B , High Level (=1)
Status of GPIO1 (if selected as GPIO)
0B , Low Level (=0)
1B , High Level (=1)
Reserved
WK3_LVL
3
2
r
r
Reserved, always reads as 0
Status of WK3
0B , Low Level (=0)
1B , High Level (=1)
WK2_LVL
WK1_LVL
1
0
r
r
Status of WK2
0B , Low Level (=0)
1B , High Level (=1)
Status of WK1
0B , Low Level (=0)
1B , High Level (=1)
Note:
GPIOx_LVL is updated in SBC Normal and Stop Mode if configured as wake input, low-side switch or
high-side switch.
In cyclic sense or wake mode, the registers contain the sampled level, i.e. the registers are updated
after every sampling. The GPIOs are not capable of cyclic sensing.
If selected as GPIO then the respective level is shown even if configured as low-side or high-side.
Datasheet
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Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
HS_OC_OT_STAT
High-Side Switch Overload Status (Address 101 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 xxxxB
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT
r
r
r
r
r
rc
rc
rc
rc
Field
Reserved
Bits
7:4
Type
Description
r
Reserved, always reads as 0
HS4_OC_OT 3
HS3_OC_OT 2
HS2_OC_OT 1
HS1_OC_OT 0
rc
Overcurrent & Overtemperature Detection HS4
0B , No OC or OT
1B , OC or OT detected
rc
rc
rc
Overcurrent & Overtemperature Detection HS3
0B , No OC or OT
1B , OC or OT detected
Overcurrent & Overtemperature Detection HS2
0B , No OC or OT
1B , OC or OT detected
Overcurrent & Overtemperature Detection HS1
0B , No OC or OT
1B , OC or OT detected
Note:
The OC/OT bit might be set for VPOR,f < VS < 5.5V (see also Chapter 4.2)
Datasheet
159
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
HS_OL_STAT
High-Side Switch Open-Load Status (Address 101 0101B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 xxxxB
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
HS4_OL
HS3_OL
HS2_OL
HS1_OL
r
r
r
r
r
rc
rc
rc
rc
Field
Bits
Type
Description
Reserved
HS4_OL
7:4
3
r
Reserved, always reads as 0
rc
Open-Load Detection HS4
0B , No OL
1B , OL detected
HS3_OL
HS2_OL
HS1_OL
2
1
0
rc
rc
rc
Open-Load Detection HS3
0B , No OL
1B , OL detected
Open-Load Detection HS2
0B , No OL
1B , OL detected
Open-Load Detection HS1
0B , No OL
1B , OL detected
Datasheet
160
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
16.6.2
Family and Product Information Register
FAM_PROD_STAT
Family and Product Identification Register (Address 111 1110B)
POR / Soft Reset Value: 0111 yyyy B; Restart Value: 0111 yyyyB
7
6
5
4
3
2
1
0
FAM_3
FAM_2
FAM_1
FAM_0
PROD_3
PROD_2
PROD_1
PROD_0
r
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
FAM
7:4
r
SBC Family Identifier (bit4=LSB; bit7=MSB)
0 010B, DC/DC-SBC Family
0 011B, Mid-Range SBC Family
0 100B, Multi-CAN SBC Family
0 101B, Lite-CAN SBC Family
0 111B, Mid-Range+ SBC Family
x x x xB, reserved for future products
PROD
3:0
r
SBC Product Identifier (bit0=LSB; bit3=MSB)
0 0 0 0B, reserved
0 1 0 0B, TLE9261BQX (VCC1 = 5V, no LIN, VCC3, no SWK)
1 0 0 0B, TLE9262BQX (VCC1 = 5V, 1 LIN, VCC3, no SWK)
1 1 0 0B, TLE9263BQX (VCC1 = 5V, 2 LIN, VCC3, no SWK)
Notes
1. The actual default register value after POR, Soft Reset or Restart of PROD will depend on the respective
product. Therefore the value ‘y’ is specified.
2. SWK = Selective Wake feature in CAN Partial Networking standard
Datasheet
161
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
16.7
Electrical Characteristics
Table 30
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
SPI frequency
1)
Maximum SPI frequency
fSPI,max
–
–
4.0
MHz
P_16.7.1
SPI Interface; Logic Inputs SDI, CLK and CSN
H-input Voltage Threshold
L-input Voltage Threshold
Hysteresis of input Voltage
VIH
–
–
–
0.7*
VCC1
V
V
V
–
P_16.7.2
P_16.7.3
P_16.7.4
VIL
0.3*
VCC1
–
–
1)
VIHY
0.08 × 0.12 × 0.5 ×
VCC1
VCC1
VCC1
Pull-up Resistance at pin CSN RICSN
20
40
80
kΩ
kΩ
VCSN = 0.7 x VCC1
P_16.7.5
P_16.7.6
Pull-down Resistance at pin RICLK/SDI
20
40
80
VSDI/CLK =
SDI and CLK
0.2 x VCC1
1)
Input Capacitance at pin
CSN, SDI or CLK
CI
–
10
–
–
pF
V
P_16.7.7
P_16.7.8
Logic Output SDO
H-output Voltage Level
VSDOH
VCC1
0.4
-
VCC1
0.2
-
IDOH = -1.6 mA
IDOL = 1.6 mA
L-output Voltage Level
Tristate Leakage Current
VSDOL
ISDOLK
–
0.2
–
0.4
10
V
P_16.7.9
-10
µA
VCSN = VCC1
;
P_16.7.10
0 V < VDO < VCC1
1)
Tristate Input Capacitance
Data Input Timing1)
Clock Period
CSDO
–
10
15
pF
P_16.7.11
tpCLK
tCLKH
tCLKL
tbef
250
125
125
125
250
250
125
100
50
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
P_16.7.12
P_16.7.13
P_16.7.14
P_16.7.15
P_16.7.16
P_16.7.17
P_16.7.18
P_16.7.19
P_16.7.20
P_16.7.21
Clock High Time
–
Clock Low Time
–
Clock Low before CSN Low
CSN Setup Time
–
tlead
tlag
–
CLK Setup Time
–
Clock Low after CSN High
SDI Set-up Time
tbeh
–
tDISU
tDIHO
–
SDI Hold Time
–
Input Signal Rise Time at pin trIN
–
50
SDI, CLK and CSN
Datasheet
162
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Serial Peripheral Interface
Table 30
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
Input Signal Fall Time at pin tfIN
–
50
ns
–
P_16.7.22
SDI, CLK and CSN
Delay Time for Mode
Changes2)
tDel,Mode
–
3
–
–
6
–
µs
includes internal P_16.7.23
oscillator
tolerance
CSN High Time
tCSN(high)
µs
–
P_16.7.24
Data Output Timing1)
SDO Rise Time
trSDO
–
–
–
–
–
30
30
–
80
80
50
50
50
ns
ns
ns
ns
ns
CL = 100 pF
P_16.7.25
P_16.7.26
P_16.7.27
SDO Fall Time
tfSDO
CL = 100 pF
SDO Enable Time
SDO Disable Time
SDO Valid Time
tENSDO
tDISSDO
tVASDO
low impedance
–
high impedance P_16.7.28
–
CL = 100 pF
P_16.7.29
1) Not subject to production test; specified by design
2) Applies to all mode changes triggered via SPI commands
24
CSN
15
16
17
18
13
14
CLK
SDI
19
20
LSB
MSB
not defined
27
28
29
SDO
Flag
LSB
MSB
Figure 58 SPI Timing Diagram
Note:
Numbers in drawing correlate to the last 2 digits of the Number field in the Electrical Characteristics
table.
Datasheet
163
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Application Information
17
Application Information
17.1
Application Diagram
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
VBAT
T2
VCC3
VS
R12
D1
VBAT
C1
C13
D2
C2
Q1
Q2
Q1
Q2
IC1
VCC
C3
C14
GND
R8
VCC3REF
VCC3SH
VS
VS
VCC3B
VSHS
VSHS
VCC1
VCC1
VCC2
D3
VCC2
C5
C7
C4
HS1
HS2
HS3
R9
C6
VS
VSHS
VSHS
C17
CSN
VDD
CSN
CLK
SDI
R7
CLK
SDI
µC
D4
SDO
SDO
C18
C8
TxD LIN1
RxD LIN1
TxD LIN1
RxD LIN1
Other loads , e.g.
sensor , opamp, ...
LOGIC
State
Machine
TxD CAN
RxD CAN
INT
TxD CAN
RxD CAN
INT
VSHS
RO
Reset
Hall1
Q1
Q2
HS4
Hall2
VSS
VSHS
R5
R3
D5
R6
R4
TLE9262
WK1
WK2
WK3
R13
S3
LIN cell
C9
LIN1
LIN1
C15
VBAT
S2
C10
S1
VCC2
R2
VCAN
CANH
C11
R1
CANH
CANL
CAN cell
R10
R11
C12
VS
T1
CANL
FOx
GND
LH
Note: The external capacitance on FO3/TEST must be
<=10nF in oder to ensure proper detection of SBC
Development Mode und SBC user mode operation
Application _information
_TLE9262 .vsd
Figure 59 Simplified Application Diagram
Datasheet
164
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Application Information
Note:
Unused outputs are recommended to be left unconnected on the application board. If unused
output pins are routed to an external connector which leaves the ECU, then these pins should have
provision for a zero ohm jumper (depopulated if unused) or ESD protection.
Table 31
Ref.
Bill of Material for Simplified Application Diagram
Typical Value
Purpose / Comment
Capacitances
C1
C2
C3
68µF
100nF
22µF
Buffering capacitor to cut off battery spikes, depending on application
EMC, blocking capacitor
Buffering capacitor to cut off battery spikes from VSHS as separate supply
input; Depending on application, only needed if VSHS is not connected to
VS;
C4
C5
C6
2.2µF low ESR
100nF ceramic
2.2µF low ESR
As required by application, min. 470nF for stability and max. 68µF
recommended
Spike filtering, improve stability of supply for microcontroller;
not needed for SBC
Blocking capacitor, min. 470nF for stability;
if used for CAN supply place a 100nF ceramic capacitor in addition very
close to VCAN pin for optimum EMC behavior
C7
33nF
33nF
47pF
47pF
10nF
As required by application, mandatory protection for off-board
connections
C8
As required by application, mandatory protection for off-board
connections
C17
C18
C9
Only required in case of off-board connection to optimize EMC behavior,
place close to pin
Only required in case of off-board connection to optimize EMC behavior,
place close to pin
Spike filtering, as required by application, mandatory protection for off-
board connections (see also Simplified Application Diagram with the
Alternate Measurement Function)
C10
C11
10nF
10nF
Spike filtering, as required by application, mandatory protection for off-
board connections
Spike filtering, as required by application, mandatory protection for off-
board connections
C12
C13
4.7nF / OEM dependent Split termination stability
10µF low ESR
Stability of VCC3, ceramic capacitor, e.g. Murata 10 µF/10 V
GCM31CR71A106K64L or 2x 4.7 µF/10 V
C14
C15
47nF
Only required in case of off-board connection to optimize EMC behavior,
place close to connector
1nF / OEM dependent
LIN master termination
Resistances
R1
R2
10kΩ
10kΩ
Wetting current of the switch, as required by application
Limit the WK pin current, e.g. for ISO pulses
Datasheet
165
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Application Information
Table 31
Ref.
R3
Bill of Material for Simplified Application Diagram (cont’d)
Typical Value
10kΩ
Purpose / Comment
Wetting current of the switch, as required by application
Limit the WK pin current, e.g. for ISO pulses
Wetting current of the switch, as required by application
Limit the WK pin current, e.g. for ISO pulses
R4
10kΩ
R5
10kΩ
R6
10kΩ
R7
depending on LED config. LED current limitation, as required by application
depending on LED config. LED current limitation, as required by application
R8
R9
47kΩ
Selection of hardware configuration 1/3, i.e. in case of WD failure SBC
Restart Mode is entered.
If not connected, then hardware configuration 2/4 is selected
R10
R11
R12
60Ω / OEM dependent
60Ω / OEM dependent
CAN bus termination
CAN bus termination
1Ω shunt, depending on Sense shunt for ICC3 current limitation (configured to typ. 235mA with 1Ω
required current shunt) for stand-alone configuration;
limitation or load sharing Setting of load sharing ratio (here ICC3/ICC1 = 1) in load sharing
ratio
configuration.
R13
R15
1kΩ / OEM dependent
10kΩ
LIN master termination (if configured as a LIN master)
WK1 pin current limitation, e.g. for ISO pulses, for alternate measurement
function (see also Simplified Application Diagram with the Alternate
Measurement Function)
R16
R17
depending on
application and
microcontroller
Voltage Divider resistor to adjust measurement voltage to
microcontroller ADC input range (see also Simplified Application Diagram
with the Alternate Measurement Function)
depending on
application and
microcontroller
Voltage Divider resistor to adjust measurement voltage to
microcontroller ADC input range (see also Simplified Application Diagram
with the Alternate Measurement Function)
Active Components
D1
D2
e.g. BAS 3010A, Infineon Reverse polarity protection for VS supply pins
e.g. BAS 3010A, Infineon Reverse polarity protection for VSHS supply pin; if separate supplies are
not needed, then connect VSHS to VS pins
D3
D4
D5
T1
T2
LED
As required by application, configure series resistor accordingly
As required by application, configure series resistor accordingly
Requested by LIN standard; reverse polarity protection of network
High active FO control
LED
e.g. BAS70
e.g. BCR191W
BCP 52-16, Infineon
Power element of VCC3, current limit or load sharing ratio to be
configured via shunt
MJD 253, ON Semi
e.g. TC2xxx
Alternative power element of VCC3
Microcontroller
µC
Note:
This is a simplified example of an application circuit. The function must be verified in the real
application.
Datasheet
166
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Application Information
VBAT
VS
D1
VBAT
C2
C1
D2
e.g.
470uF
VS
VCC1
VCC1
CSN
C5
C4
VS
VDD
CSN
CLK
SDI
SDO
CLK
SDI
µC
SDO
TxD LIN1
TxD LIN1
RxD LIN1
RxD LIN1
LOGIC
State
Machine
TxD CAN
RxD CAN
TxD CAN
RxD CAN
INT
RO
INT
Reset
ADC_x
Vbat_uC
TLE9262
max.
500uA
R6
WK1
VSS
≥10k
C9
≥10n
ISO Pulse
protection
S1
WK2
Note:
Vbat_uC
R17
Max. WK1 input current limited to
500µA to ensure accuracy and
proper operation ;
R16
GND
Figure 60 Simplified Application Diagram with the Alternate Measurement Function via WK1 and WK2
Note:
This is a very simplified example of an application circuit. The function must be verified in the real
application.WK1 must be connected to signal to be measured and WK2 is the output to the
microcontroller supervision function. The maximum current into WK1 must be <500uA. The
minimum current into WK1 should be >5uA to ensure proper operation.
Datasheet
167
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Application Information
5V_int
SBC Init
Mode
T test
RTEST
Connector/
Jumper
FO3/
TEST
REXT
T FO_PL
Failure Logic
Figure 61 Hint for Increasing the Robustness of pin FO3/TEST during Debugging or Programming
Datasheet
168
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Application Information
17.2
ESD Tests
Note:
Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) has been performed.
The results and test conditions are available in a test report. The target values for the test are listed
in Table 32 below.
Table 32
ESD “Gun Test”
Performed Test
Result
Unit
Remarks
1)2)positive pulse
ESD at pin CANH, CANL,
LIN, VS, WK1..3, HSx, VCC2,
VCC3 versus GND
>6
kV
ESD at pin CANH, CANL,
LIN, VS, WK1..3, HSx, VCC2,
VCC3 versus GND
< -6
kV
1)2)negative pulse
1) ESD Test “Gun Test” is specified with external components for pins VS, WK1..3, HSx, VCC3 and VCC2. See the
application diagram in Chapter 17.1 for more information.
2) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external
test house (IBEE Zwickau, EMC Test report Nr. 04-01-17)
EMC and ESD susceptibility tests according to SAE J2962-2 (2010) have been performed. Tested by external
test house (UL LLC).
Datasheet
169
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Application Information
17.3
Thermal Behavior of Package
Below figure shows the thermal resistance (Rth_JA) of the device vs. the cooling area on the bottom of the PCB
for Ta = 85°C. Every line reflects a different PCB and thermal via design.
Figure 62 Thermal Resistance (Rth_JA) vs. Cooling Area
Datasheet
170
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Application Information
Cross Section(JEDEC 2s2p) with Cooling Area
Cross Section(JEDEC 1s0p) with Cooling Area
70µm modelled(traces)
35µm, 90% metalization*
35µm, 90% metalization*
70µm / 5% metalization+ cooling area
*: means percentualCu metalization on each layer
PCB (top view)
PCB (bottom view)
Detail SolderArea
Figure 63 Board Setup
Board setup is defined according to JESD 51-2,-5,-7.
Board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35µm thick), with thermal via array under the exposed
pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm).
Datasheet
171
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Package Outlines
18
Package Outlines
Figure 64 PG-VQFN-48 1)
The PG-VQFN-48 package is a leadless exposed pad power package featuring Lead Tip Inspection (LTI) to
support Automatic Optical Inspection (AOI).
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
1) Dimensions in mm
Datasheet
172
Rev. 1.2
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OPTIREG™ SBC TLE9262BQX
Revision History
19
Revision History
Revision Date
Changes
Rev. 1.2 2022-05-04 Datasheet updated:
•
•
•
•
Editorial changes
Updated package outline drawing
P_15.10.26: Updated max value of VPOR,r to 4.7 V
Updated Ipeak parameter (P_6.3.13, P_6.3.17, P_6.3.18, P_6.3.19, P_7.3.15,
P_7.3.17)
•
•
•
•
•
P_4.1.27: parameter VCAN_Diff,max improved to -40V min. and 40V max.
P_4.1.3: parameter VCC1,max: added Note/Testconditions
Table 4 footnote 7): corrected 18µA to 20µA to match with parameter values
Corrected note 2 at CAN wake capable mode: must not -> not need to
Corrected POR/Soft Reset value of FAM_PROD_STAT register. No product
change
•
•
Added note about clock tolerance at PWM_FREQ_CTRL register description
Pin configuration (Chapter 3): Improved Cooling tab description - connect the
exposed pad to GND
•
•
•
•
Updated CDM specification reference to JS-002
Improved wording of Table 5. No product change.
Added explaining footnote to parameter tLW (P_15.10.24). No product change.
Added current consumption for GPIOx in Highside/Lowside switch confguration
in SBC Stop/Sleep mode (P_4.4.37 and P_4.4.38). No product change.
•
•
Added “not subject to production test” footnote to tCFG_F (P_13.2.6)
Two definitions for VCC1 voltage drop were available. Apply P_6.3.3 to 3.3V
variant only, and P_6.3.4 to 5V variant only. No product change.
Datasheet
173
Rev. 1.2
2022-05-04
OPTIREG™ SBC TLE9262BQX
Revision History
Revision Date
Changes
Rev. 1.1 2019-09-27 Datasheet updated:
•
•
•
Editorial changes
General: added ISO 17987-4 to LIN 2.2
Updated Table 4
–
corrected footnote 9) to match P_4.4.33, i.e changed 525µA to 550µA
•
•
•
•
Chapter 5.1.4 “SBC Sleep Mode”: added condition for CAN mode handling
before SBC Sleep Mode entry
Figure 3 “State Diagram ...”: added footnote with condition for CAN mode
handling before SBC Sleep Mode entry
Figure 26 “CAN Mode Control Diagram”: added Footnote 2) with condition for
CAN mode handling before SBC Sleep Mode entry
Updated Table 17
–
–
–
–
added P_10.3.57 and P_10.3.58 (no product change)
added P_10.3.59, P_10.3.60, P_10.3.61 and P_10.3.62
tightened P_10.3.16
tightened P_10.3.39 and P_10.3.40 by additional footnote
•
Figure 10.2.4 “CAN Wake Capable Mode”, rearming the transceiver for wake
capability: added condition for CAN mode handling before SBC Sleep Mode
entry
Rev. 1.0 2017-07-31 Initial Release
Datasheet
174
Rev. 1.2
2022-05-04
Trademarks
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IMPORTANT NOTICE
The information given in this document shall in no For further information on technology, delivery terms
Edition 2022-05-04
Published by
Infineon Technologies AG
81726 Munich, Germany
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest
characteristics ("Beschaffenheitsgarantie").
Infineon Technologies Office (www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
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customer's products and any use of the product of
Infineon Technologies in customer's applications.
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dangerous substances. For information on the types
in question please contact your nearest Infineon
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