TLE9263-3BQX V33_技术文档

OPTIREG™ SBC TLE9263-3BQXV33

Mid-Range+ System Basis Chip Family

Features

•

Two integrated Low-Drop Voltage Regulators: Main regulator with

3.3 V up to 250 mA (5 V variant available) and auxiliary regulator

(5 V up to 100 mA) with off-board usage protection

•

Voltage regulator (3.3 V or 1.8 V selectable) with external PNP

transistor configurable for off-board usage or for load sharing

1 high-speed CAN transceiver supporting FD communication up to

5 Mbit/s featuring CAN Partial Networking & CAN FD tolerant mode

according to ISO 11898-2:2016 & SAE J2284

•

2 LIN transceivers supporting LIN 2.2/ISO 17987-4/SAE J2602

4 high-side outputs 7 Ω typ., 2 HV GPIOs, 3 HV wake inputs

Integrated fail-safe and supervision functions, e.g. fail-safe, watchdog, interrupt- and reset outputs

16-bit SPI for configuration and diagnostics

Potential applications

•

Body Control Modules (BMC), Passive keyless entry and start modules, Gateway applications

Heating, ventilation and air conditioning (HVAC)

Seat, roof, tailgate, trailer, door and other closure modules

Light control modules

Gear shifters and selectors

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100.

Description

Body System IC with Integrated Voltage Regulators, Power Management Functions, HS-CAN Transceiver

supporting CAN FD featuring Partial Networking (incl. FD Tolerant Mode) and Multiple LIN Transceiver.

Featuring Multiple High-Side Switches and High-Voltage Wake Inputs.

Type

Package

Marking

TLE9263-3BQXV33

PG-VQFN-48

TLE9263-3BQXV33

Datasheet

www.infineon.com/sbc

Rev. 1.2

2022-05-04

1

OPTIREG™ SBC TLE9263-3BQXV33

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1

2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Hints for Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Hints for Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1

3.2

3.3

3.4

4

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1

4.2

4.3

4.4

5

5.1

System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block Description of State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Device Configuration and SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SBC Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SBC Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SBC Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SBC Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Configuration and Operation of Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Cyclic Sense in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Supervision Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Partial Networking on CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

CAN Partial Networking - Selective Wake Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SBC Partial Networking Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Activation of SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Wake-up Pattern (WUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Wake-up Frame (WUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

CAN Protocol Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Diagnoses Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.1.1

5.1.1.1

5.1.1.2

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.2

5.2.1

5.2.1.1

5.2.1.2

5.2.2

5.2.3

5.3

5.4

5.4.1

5.4.2

5.4.2.1

5.4.2.2

5.4.2.3

5.4.2.4

5.4.3

Datasheet

2

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OPTIREG™ SBC TLE9263-3BQXV33

5.4.3.1

5.4.3.2

5.4.3.3

5.4.3.4

5.4.3.5

5.4.3.6

5.4.3.7

5.4.3.8

5.4.3.9

5.4.3.10

5.4.3.11

5.4.4

5.4.4.1

5.4.4.2

5.4.4.3

5.4.4.4

5.4.4.5

5.4.5

PWRON/RESET-FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

BUSERR-Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

TXD Dominant Time-out flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

WUP Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

WUF Flag (WUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SYSERR Flag (SYSERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

CAN Bus Timeout-Flag (CANTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

CAN Bus Silence-Flag (CANSIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SYNC-FLAG (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SWK_SET FLAG (SWK_SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SBC Modes for Selective Wake (SWK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SBC Normal Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SBC Stop Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SBC Sleep Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

SBC Restart Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

SBC Fail-Safe Mode with SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Configuration for SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

CAN Flexible Data Rate (CAN FD) Tolerant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Configuring the Clock Data Recovery for SWK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Setup of Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4.6

5.4.7

5.4.8

5.4.8.1

5.4.8.2

5.4.9

6

Voltage Regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.1

6.2

6.3

7

Voltage Regulator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Short to Battery Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.1

7.2

7.2.1

7.3

8

External Voltage Regulator 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

External Voltage Regulator as Independent Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

External Voltage Regulator in Load Sharing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Calculation of R_SHUNT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.1

8.2

8.2.1

8.2.2

8.3

8.4

8.5

8.6

9

High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Over- and Undervoltage Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.1

9.2

9.2.1

Datasheet

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OPTIREG™ SBC TLE9263-3BQXV33

9.2.2

9.2.3

9.2.4

9.2.5

9.3

Overcurrent Detection and Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

HSx Operation in Different SBC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

PWM and Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10

10.1

10.2

High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

CAN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.2.1

10.2.2

10.2.3

10.2.4

10.2.5

10.2.6

10.2.7

10.3

11

11.1

11.1.1

11.2

LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

LIN Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

LIN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

LIN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

LIN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

LIN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Slope Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Flash Programming via LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.2.7

11.2.8

11.2.9

11.3

12

12.1

12.2

12.2.1

12.2.2

12.2.2.1

12.2.2.2

12.3

Wake and Voltage Monitoring Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Alternate Measurement Function with WK1 and WK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13

13.1

13.2

Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

14

Fail Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

General Purpose I/O Functionality of FO2 and FO3 as Alternate Function . . . . . . . . . . . . . . . . . . . 118

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

14.1

14.1.1

14.2

Datasheet

4

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

15

15.1

Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Watchdog Setting Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Watchdog during SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Watchdog Start in SBC Stop Mode due to Bus Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

VS Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Undervoltage VS and VSHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Overvoltage VSHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

VCC1 Over-/ Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

VCC1 Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

VCC1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

VCC1 Short Circuit and VCC3 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

VCC2 Undervoltage and VCAN Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Individual Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

SBC Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

15.1.1

15.1.2

15.2

15.2.1

15.2.2

15.2.3

15.2.4

15.2.5

15.3

15.4

15.5

15.6

15.6.1

15.6.2

15.7

15.8

15.9

15.9.1

15.9.2

15.9.3

15.10

16

16.1

16.2

16.3

16.4

16.5

16.5.1

16.5.2

16.5.3

16.6

16.6.1

16.6.2

16.6.3

16.7

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

SPI Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Selective Wake Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Selective Wake Trimming and Calibration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

SPI Status Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Selective Wake Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Family and Product Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

17

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

17.1

17.2

17.3

18

19

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Datasheet

5

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Overview

1

Overview

Scalable System Basis Chip Family

•

Product family with various products for complete scalable application coverage

Dedicated Data Sheets are available for the different product variants

Complete compatibility (hardware and software) across the family

TLE9263 with 2 LIN transceivers, 3 voltage regulators

TLE9262 with 1 LIN transceiver, 3 voltage regulators

TLE9261 without LIN transceivers, 3 voltage regulators

Product variants for 5 V (TLE926xBQX) and 3.3 V (TLE926xBQXV33) output voltage for main voltage

regulator

•

CAN Partial Networking variants for 5 V (TLE926x-3BQX) and 3.3 V (TLE926x-3BQXV33) output voltage

Device Description

The TLE9263-3BQXV33 is a monolithic integrated circuit in an exposed pad VQFN-48 (7 mm x 7 mm) power

package with Lead Tip Inspection (LTI) feature to support Automatic Optical Inspection (AOI).

The device is designed for various CAN-LIN automotive applications as main supply for the microcontroller

and as interface for a LIN and CAN bus network including the CAN Partial Networking feature.

To support these applications, the System Basis Chip (SBC) provides the main functions, such as a 3.3 V low-

dropout voltage regulator (LDO) for e.g. a microcontroller supply, another 5 V low-dropout voltage regulator

with off-board protection for e.g. sensor supply, another 3.3 V/1.8 V regulator to drive an external PNP

transistor, which can be used as an independent supply for off-board usage or in load sharing configuration

with the main regulator VCC1, a HS-CAN transceiver supporting CAN FD and CAN Partial Networking (incl. FD

tolerant mode) and LIN transceiver for data transmission, high-side switches with embedded protective

functions and a 16-bit Serial Peripheral Interface (SPI) to control and monitor the device. Also implemented

are a configurable timeout / window watchdog circuit with a reset feature, three Fail Outputs and an

undervoltage reset feature.

The device offers low-power modes in order to minimize current consumption on applications that are

connected permanently to the battery. A wake-up from the low-power mode is possible via a message on the

buses, via the bi-level sensitive monitoring/wake-up inputs as well as via cyclic wake.

The device is designed to withstand the severe conditions of automotive applications.

Datasheet

6

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Overview

Product Features

•

Very low quiescent current consumption in Stop- and Sleep Mode

Periodic Cyclic Wake in SBC Normal- and Stop Mode

Periodic Cyclic Sense in SBC Normal-, Stop- and Sleep Mode

Low-Drop Voltage Regulator 3.3 V, 250 mA

Low-Drop Voltage Regulator 5 V, 100 mA, protected features for off-board usage

Low-Drop Voltage Regulator, driving an external PNP transistor - 3.3 V in load sharing configuration or

3.3 V/1.8 V in stand-alone configuration, protected features for off-board usage. Current limitation by

shunt resistor (up to 350 mA with 470 mΩ external shunt resistor) in stand-alone configuration

•

High-Speed CAN Transceiver:

–

fully compliant to HS-CAN standard ISO 11898-2:2016

fully compliant to CAN Partial Networking including CAN FD tolerant feature (acc. ISO 11898-2:2016)

supporting CAN FD communication up to 5 Mbps

•

Two LIN Transceivers LIN 2.2/ISO 17987-4/SAE J2602 with configurable TXD timeout feature and

LIN Flash Mode

Fully compliant to “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive

Applications” Revision 1.3, 2012-05-04

•

Four High-Side Outputs 7 Ω typ.

Dedicated supply pin for High-Side Outputs

Two General Purpose High-Voltage In- and Outputs (GPIOs) configurable as add. Fail Outputs, Wake Inputs,

Low-Side switches or High-Side switches

•

Three universal High-Voltage Wake Inputs for voltage level monitoring

Alternate High-Voltage Measurement Function, e.g. for battery voltage sensing

Configurable wake-up sources

Reset Output

Configurable timeout and window watchdog

Up to three Fail Outputs (depending on configuration)

Overtemperature and short circuit protection feature

Wide supply input voltage and temperature range

Software compatible to all SBC families TLE926x and TLE927x

Green Product (RoHS compliant) & AEC Qualified

PG-VQFN-48 leadless exposed-pad power package with Lead Tip Inspection (LTI) feature to support

Automatic Optical Inspection (AOI)

Datasheet

7

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Block Diagram

2

Block Diagram

VSHS

VS

V_S

V_CC1

V_CC3

HS1

HS2

High Side

HS3

HS4

FO1

FO2

V_CC2

VCC2

FO3/TEST

Fail Safe

Alternative function

for FO2/3: GPIO1/2

SDI

SDO

SBC

STATE

SPI

CLK

CSN

MACHINE

INT

Interrupt

Control

Window Watchdog

RO

RESET

GENERATOR

WK1

WK

VCAN

Alternative

function for WK 1/2:

Voltage measurement

WAKE

REGISTER

WK2

TXDCAN

RXDCAN

WK

CAN cell

CANH

CANL

WK3

WK

Selective Wake

Logic

VSHS

TXDLIN1

RXDLIN1

LIN cell

LIN 1

TXDLIN2

RXDLIN2

LIN 2

LIN cell

GND

Figure 1

Block Diagram with CAN Partial Networking

Datasheet

8

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

VCAN 37

GND 38

CANL 39

CANH 40

n.c. 41

24 WK3

23 WK2

22 WK1

21 FO1

20 GND

19 n.c.

TLE9263

LIN1 42

GND 43

LIN2 44

n.c. 45

18 VCC2

17 VCC1

16 n.c.

PG-VQFN-48

n.c. 46

15 VS

FO2 47

14 VS

FO3/TEST 48

13 VSHS

TLE9263.vsd

Figure 2

Pin Configuration

Datasheet

9

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Pin Configuration

3.2

Pin Definitions and Functions

1

Symbol

Function

GND

n.c.

Ground

2

not connected; internally not bonded.

VCC3REF; Collector connection for external PNP, reference input

VCC3B; Base connection for external PNP

VCC3SH; Emitter connection for external PNP, shunt connection

not connected; internally not bonded.

High Side Output 1; typ. 7Ω

3

VCC3REF

VCC3B

VCC3SH

n.c.

4

5

6

7

n.c.

8

HS1

9

HS2

High Side Output 2; typ. 7Ω

10

11

12

13

HS3

High Side Output 3; typ. 7Ω

HS4

High Side Output 4; typ. 7Ω

n.c

not connected; internally not bonded.

VSHS

Supply Voltage for High-Side Switches and LIN and GPIO 1/2 in HS

configuration; Connected to battery voltage with reverse protection diode and

filter against EMC; Connect to VS if separate supply is not needed

14

15

VS

Supply Voltage for chip internal supply and voltage regulators; Connected to

Battery Voltage with external reverse protection Diode and Filter against EMC

Supply Voltage for chip internal supply and voltage regulators; Connected to

Battery Voltage with external reverse protection Diode and Filter against EMC

16

17

18

19

20

21

22

n.c.

not connected; internally not bonded.

Voltage Regulator Output 1

Voltage Regulator Output 2

not connected; internally not bonded.

Ground

VCC1

VCC2

n.c.

GND

FO1

WK1

Fail Output 1

Wake Input 1; Alternative function: HV-measurement function input pin

(only in combination with WK2, see Chapter 12.2.2)

23

WK2

Wake Input 2; Alternative function: HV-measurement function output pin

(only in combination with WK1, see Chapter 12.2.2)

24

25

26

27

28

29

30

WK3

Wake Input 3

TXDLIN2

RXDLIN2

CLK

Transmit LIN2

Receive LIN2

SPI Clock Input

SDI

SPI Data Input; into SBC (=MOSI)

SPI Data Output; out of SBC (=MISO)

SPI Chip Select Not Input

SDO

CSN

Datasheet

10

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Pin Configuration

Symbol

Function

31

INT

Interrupt Output; used as wake-up flag for microcontroller in SBC Stop or

Normal Mode and for indicating failures. Active low.

During start-up used to set the SBC configuration. External pull-up sets config

1/3, no external pull-up sets config 2/4.

32

33

34

35

36

37

38

39

40

41

42

RO

Reset Output

TXDLIN1

RXDLIN1

TXDCAN

RXDCAN

VCAN

GND

Transmit LIN1

Receive LIN1

Transmit CAN; alternate function: calibration of high-precision oscillator

Receive CAN

Supply Input; for internal HS-CAN cell

Ground

CANL

CAN Low Bus Pin

CANH

n.c.

CAN High Bus Pin

not connected; internally not bonded.

LIN1

LIN1 Bus; Bus line for the LIN interface, according to LIN 2.2/ISO 17987-4 as well

as SAE J2602-2.

43

44

GND

LIN2

Ground

LIN2 Bus; Bus line for the LIN interface, according to LIN 2.2/ISO 17987-4 as well

as SAE J2602-2.

45

46

47

n.c.

FO2

not connected; internally not bonded.

Fail Output 2 - Side Indicator; Side indicators 1.25Hz 50% duty cycle output;

Open drain. Active LOW.

Alternative Function: GPIO1; configurable pin as WK, or LS, or HS supplied by

VSHS (default is FO2, see also Chapter 14.1.1)

48

FO3/TEST

Fail Output 3 - Pulsed Light Output; Break/rear light 100Hz 20% duty cycle

output;

Open drain. Active LOW

TEST; Connect to GND to activate SBC Development Mode;

Integrated pull-up resistor. Connect to VS with pull-up resistor or leave open for

normal operation.

Alternative Function: GPIO2; configurable pin as WK, or LS, or HS supplied by

VSHS (default is FO3, see also Chapter 14.1.1)

Cooling GND

Tab

Cooling Tab - Exposed Die Pad; connect the exposed pad to GND. It is

recommended to connect the exposed pad to a heat sink.

Note:

All VS Pins must be connected to battery potential or insert a reverse polarity diodes where required;

all GND pins as well as the Cooling Tab must be connected to one common GND potential;

note that the tie bars at each package corner are connected to the cooling tab (see also Chapter 18)

Datasheet

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OPTIREG™ SBC TLE9263-3BQXV33

Pin Configuration

3.3

Hints for Unused Pins

It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that

they are disabled via SPI:

•

WK1/2/3: connect to GND and disable WK inputs via SPI

HSx: leave open

LINx, RXDLINx, TXDLINx, CANH/L, RXDCAN, TXDCAN: leave all pins open

RO / FOx: leave open

INT: leave open

TEST: connect to GND during power-up to activate SBC Development Mode;

connect to VS or leave open for normal user mode operation

•

VCC2: leave open and keep disabled

VCC3: See Chapter 8.5

VCAN: connect to VCC1

n.c.: not connected; internally not bonded; connect to GND

If unused pins are routed to an external connector which leaves the ECU, then these pins should have

provision for a zero ohm jumper (depopulated if unused) or ESD protection.

3.4

Hints for Alternate Pin Functions

In case of alternate pin functions, selectable via SPI, it must be ensured that the correct configurations are also

selected via SPI, in case it is not done automatically. Please consult the respective chapter. In addition,

following topics shall be considered:

•

WK1..2: The pins can be either used as HV wake / voltage monitoring inputs or for a voltage measurement

function (via bit WK_MEAS). In the second case, the WK1..2 pins shall not be used / assigned for any wake

detection nor cyclic sense functionality, i.e. WK1 and WK2 must be disabled in the register WK_CTRL_2 and

the level information is to be ignored in the register WK_LVL_STAT.

FO2..3: The pins can also be configured as GPIOs in the GPIO_CTRL register. In this case, the pins shall not

be used for any fail output functionality. The default function after Power on Reset (POR) is FOx.

Datasheet

12

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OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Voltages

Supply Voltage (VS, VSHS)

VS_{x, max}

-0.3

–

28

40

V

–

P_4.1.1

P_4.1.2

Load Dump,

max. 400 ms

Voltage Regulator 1

Voltage Regulator 2

V_{CC1, max}

V_{CC2, max}

-0.3

–

5.5

28

V

V_CC1= 5.6V for

max. 10s

P_4.1.3

P_4.1.4

V_CC2= 40V for

Load Dump,

max. 400 ms;

Voltage Regulator 3

(VCC3REF)

V_CC3REF,max-0.3

–

28

V

V_CC3REF= 40V for P_4.1.5

Load Dump,

max. 400 ms;

Voltage Regulator 3 (VCC3B) V_CC3B,max

-0.3

V_S

+ 10

V_CC3B= 40V for

Load Dump,

max. 400 ms;

P_4.1.25

P_4.1.26

Voltage Regulator 3

(VCC3SH)

V_CC3SH,max

V_S

+ 0.30

–

- 0.30

Wake Inputs WK1..3

Fail Pin FO1

V_{WK, max}

-0.3

–

40

V

–

P_4.1.6

P_4.1.7

P_4.1.23

V_{FO1, max}

V_{FO2_3, max}

Fail Pins FO2, FO3/TEST

V_S

+ 0.3

LINx, CANH, CANL

V_{BUS, max}

-27

–

40

V

–

P_4.1.8

Maximum Differential CAN V_{CAN_Diff, max}-40

P_4.1.27

Bus Voltage

Logic Input Pins (CSN, CLK, V_{I, max}

SDI, TXDLINx, TXDCAN)

-0.3

–

V_CC1

+ 0.3

V

–

P_4.1.9

Logic Output Pins (SDO, RO, V_{O, max}

V_CC1

P_4.1.10

INT, RXDLINx, RXDCAN)

+ 0.3

VCAN Input Voltage

High Side 1...4

V_{VCAN, max}

V_{HS, max}

-0.3

–

5.5

V

–

P_4.1.11

P_4.1.12

V_SHS

+ 0.3

Currents

2)

Wake input WK1

I_WK1,max

0

–

500

µA

P_4.1.13

Datasheet

13

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

Table 1

Absolute Maximum Ratings¹⁾(cont’d)

T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

2)

Wake input WK2

I_WK2,max

-500

0

µA

P_4.1.14

Temperatures

Junction Temperature

Storage Temperature

ESD Susceptibility

ESD Resistivity

T_j

-40

-55

–

150

°C

–

P_4.1.15

P_4.1.16

T_stg

V_ESD,11

-2

-8

–

2

8

kV

HBM³⁾

HBM⁴⁾³⁾

P_4.1.17

P_4.1.18

P_4.1.19

ESD Resistivity to GND, HSx V_ESD,12

ESD Resistivity to GND,

CANH, CANL, LINx

V_ESD,13

ESD Resistivity to GND

V_ESD,21

V_ESD,22

-500

-750

–

500

750

V

CDM⁵⁾

P_4.1.20

P_4.1.21

ESD Resistivity Pin 1,

12,13,24,25,36,37,48 (corner

pins) to GND

1) Not subject to production test, specified by design

2) Applies only if WK1 and WK2 are configured as alternative HV-measurement function

3) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF)

4) For ESD “GUN” Resistivity 6KV (according to IEC61000-4-2 “gun test” (150pF, 330Ω)), will be shown in Application

Information and test report will be provided from IBEE

5) ESD susceptibility, Charged Device Model according to ANSI/ESDA/JEDEC JS-002

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

Datasheet

14

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

1)

Supply Voltage

V_S,func

V_POR

28

V

see

P_4.2.1

POR

Chapter 15.10

2)

LIN Bus Voltage

CAN Supply Voltage

SPI frequency

V_S,LIN,func

V_CAN,func

f_SPI

6

–

18

5.25

4

V

P_4.2.2

P_4.2.3

P_4.2.4

4.75

–

MHz see

Chapter 16.7 for

f_SPI,max

–

Junction Temperature

T_j

-40

–

150

°C

P_4.2.5

1) Including Power-On Reset, Over- and Undervoltage Protection

2) Parameter Specification according to LIN 2.2/ISO 17987-4

Note:

Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

Device Behavior Outside of Specified Functional Range:

•

28V < V_S,func< 40V: Device will still be functional including the state machine; the specified electrical

characteristics might not be ensured anymore. The regulators VCC1/2/3 are working properly, however, a

thermal shutdown might occur due to high power dissipation. HSx switches might be turned OFF

depending on VSHS_OV configurations. The specified SPI communication speed is ensured; the absolute

maximum ratings are not violated, however the device is not intended for continuous operation of VS >28V.

The device operation at high junction temperatures for long periods might reduce the operating life time;

•

18V < V_S,LIN<28V: The LIN transceiver is still functional. However, the communication might fail due to out-

of-LIN-spec operation;

V

_SHS,UVD< V_S,LIN< 6V: The LIN transceiver is still functional. However, the communication might fail due to

out-of-LIN-spec operation;

V_CAN< 4.75V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_1 and the transmitter

will be disabled as long as the UV condition is present;

5.25V < V_CAN< 5.50V: CAN transceiver still functional. However, the communication might fail due to out-of-

spec operation;

V

_POR,f< VS < 5.5V: Device will still be functional; the specified electrical characteristics might not be ensured

anymore.

–

The voltage regulators will enter the low-drop operation mode

(applies for VCC3 only if bit VCC3_VS_ UV_OFF is set),

–

A VCC1_UV reset could be triggered depending on the Vrtx settings,

The LIN transmitter will be disabled if V_SHS,UVDis reached,

HSx switch behavior will depend on the respective configuration:

- HS_UV_SD_EN = ‘0’ (default): HSx will be turned OFF for VSHS < VSHS_UV and will stay OFF;

- HS_UV_SD_EN = ‘1’: HSx stays on as long as possible. An unwanted overcurrent shut down may occur.

OC shut down bit set and the respective HSx switch will stay OFF;

Datasheet

15

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

–

FOx outputs will remain ON if they were enabled before VS > 5.5V,

The specified SPI communication speed is ensured.

4.3

Thermal Resistance

Table 3

Thermal Resistance¹⁾

Symbol

Parameter

Values

Typ.

6

Unit Note or

Test Condition

Number

Min.

Max.

Junction to Soldering Point R_thJSP

Junction to Ambient R_thJA

–

K/W Exposed Pad

P_4.3.1

P_4.3.2

2)

–

33

K/W

1) Not subject to production test, specified by design.

2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for 1.5W. Board: 76.2x114.3x1.5mm3 with

2 inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper

layer and 300mm2 cooling area on the bottom layer (70µm).

Datasheet

16

Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

4.4

Current Consumption

Table 4

Current Consumption

Current consumption values are specified at T_j= 25°C, V_S= 13.5V, all outputs open (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

SBC Normal Mode

Normal Mode current

consumption

I_Normal

–

3.5

44

6.5

mA

µA

V_S= 5.5 V to 28 V;

T_j= -40 °C to +150 °C;

VCC2, CAN, LIN, VCC3,

HSx = OFF

P_4.4.1

SBC Stop Mode

Stop Mode current

consumption

I_{Stop_1,25}

–

60

70

¹⁾VCC2/3, HSx = OFF; P_4.4.2

CAN²⁾, LINx, WKx not

wake capable;

Watchdog = OFF;

no load on VCC1;

I_PEAK_TH = ‘0’

¹⁾³⁾T_j= 85°C;

VCC2/3, HSx = OFF;

CAN²⁾, LINx, WKx not

wake capable;

Stop Mode current

consumption

I_{Stop_1,85}

50

µA

P_4.4.3

Watchdog = OFF;

no load on VCC1;

I_PEAK_TH = ‘0’

Stop Mode current

consumption

(high active peak threshold)

I_{Stop_2,25}

–

64

70

90

µA

¹⁾VCC2/3, HSx = OFF; P_4.4.35

CAN²⁾, LINx, WKx not

wake capable;

Watchdog = OFF;

no load on VCC1;

I_PEAK_TH = ‘1’

Stop Mode current

consumption

(high active peak threshold)

I_{Stop_2,85}

100

¹⁾³⁾T_j= 85°C;

P_4.4.36

VCC2/3, HSx = OFF;

CAN²⁾, LINx, WKx not

wake capable;

Watchdog = OFF;

no load on VCC1;

I_PEAK_TH = ‘1’

SBC Sleep Mode

Sleep Mode current

consumption

I_Sleep,25

–

15

25

35

µA

VCC2/3, HSx = OFF;

CAN²⁾, LINx, WKx not

wake capable

³⁾T_j= 85°C;

VCC2/3, HSx = OFF;

CAN²⁾, LINx, WKx not

wake capable

P_4.4.5

P_4.4.6

Sleep Mode current

consumption

I_Sleep,85

Datasheet

17

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at T_j= 25°C, V_S= 13.5V, all outputs open (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Feature Incremental Current Consumption

Max.

Current consumption for

CAN module, recessive state

I_CAN,rec

–

2

3

mA

µA

SBC Normal/Stop

Mode; CAN Normal

Mode; VCC1

connected to VCAN;

VTXDCAN = VCC1; no

RL on CAN

³⁾SBC Normal/Stop

Mode; CAN Normal

Mode; VCC1

connected to VCAN;

VTXDCAN = GND;

no RL on CAN

³⁾⁴⁾SBC Normal/Stop P_4.4.9

Mode; CAN Receive

Only Mode; VCC1

connected to VCAN;

VTXDCAN = VCC1; no

RL on CAN

P_4.4.7

Current consumption for

CAN module, dominant

state

I_CAN,dom

3

4.5

1.2

690

P_4.4.8

Current consumption for

CAN module, Receive Only

Mode

I_CAN,RcvOnly

0.9

560

Current consumption during I_CAN,SWK,25

CAN Partial Networking

frame detect mode

³⁾T_j= 25°C;

P_4.4.4

SBC Stop Mode;

VCC2, HSx = OFF;

LIN, WKx not wake

capable;

(RX_WK_ SEL = ‘1’)

CAN SWK wake

capable, SWK

Receiver enabled,

WUF detect;

no RL on CAN

Current consumption during I_CAN,SWK,85

CAN Partial Networking

frame detect mode

–

600

720

µA

³⁾T_j= 85°C;

P_4.4.29

SBC Stop Mode;

VCC2, HSx = OFF;

LIN, WKx not wake

capable;

(RX_WK_ SEL = ‘1’)

CAN SWK wake

capable, SWK

Receiver enabled,

WUF detect;

no RL on CAN

Datasheet

18

Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at T_j= 25°C, V_S= 13.5V, all outputs open (unless otherwise specified)

Parameter

Symbol

Values

Typ.

0.1

Unit Note or

Test Condition

Number

Min.

Max.

Current consumption per

LIN module, recessive state

I_LIN,rec

–

1

mA

SBC Normal/Stop

Mode; LIN Normal

Mode; VTXDLIN =

VCC1;

P_4.4.10

no RL on LIN

Current consumption per

LIN module, dominant state

I_LIN,dom

–

1.0

1.5

mA

³⁾SBC Normal/Stop

Mode; LIN Normal

Mode; VTXDLIN =

GND;

P_4.4.11

P_4.4.12

no RL on LIN

Current consumption per

LIN module, Receive Only

Mode

I_LIN,RcvOnly

I_Wake,WKx,25

I_Wake,WKx,85

–

0.2

0.5

2

mA

µA

³⁾SBC Normal/Stop

Mode; LIN Receive

OnlyMode; VTXDLIN =

VCC1; no RL on LIN

Current consumption for

WK1..3 wake capability

(all wake inputs)

⁵⁾⁶⁾⁷⁾SBC Sleep Mode; P_4.4.13

WK1..3 wake capable

(all WKx enabled);

LIN, CAN = OFF

^3)5)6)7)SBC Sleep

Mode; T_j= 85°C;

WK1..3 wake capable;

(all WKx enabled);

LIN, CAN = OFF

Current consumption for

WK1..3 wake capability

(all wake inputs)

3

P_4.4.14

Current consumption per

LIN module wake capability

I_Wake,LIN,25

–

0.2

0.5

2

3

µA

⁵⁾SBC Sleep Mode;

LIN wake capable;

WK1..3, CAN = OFF

³⁾⁵⁾SBC Sleep Mode;

T_j= 85°C;

P_4.4.15

P_4.4.16

Current consumption per

LIN module wake capability

I_Wake,LIN,85

LIN wake capable;

WK1..3, CAN = OFF

Current consumption for

CAN wake capability

(tsilence expired)

I_Wake,CAN,25

–

4.5

5.5

6

7

µA

²⁾⁵⁾SBC Sleep Mode;

CAN wake capable;

WK1..3, LIN = OFF

²⁾³⁾⁵⁾SBC Sleep Mode; P_4.4.18

T_j= 85°C;

P_4.4.17

Current consumption for

CAN wake capability

(tsilence expired)

I_Wake,CAN,85

CAN wake capable;

WK1..3, LIN = OFF

VCC2 Normal Mode current I_Normal,VCC2

–

2.5

3.5

mA

V_S= 5.5 V to 28 V;

P_4.4.32

consumption

T_j= -40 °C to +150 °C;

VCC2 = ON (no load)

Datasheet

19

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at T_j= 25°C, V_S= 13.5V, all outputs open (unless otherwise specified)

Parameter

Symbol

Values

Typ.

25

Unit Note or

Test Condition

Number

Min.

Max.

Current consumption for

VCC2 in SBC Sleep Mode

I_{Sleep,VCC2,25}

–

35

µA

¹⁾⁵⁾SBC Sleep Mode;

VCC2 = ON (no load);

LIN, CAN,

P_4.4.19

WK1..3 = OFF

Current consumption for

VCC2 in SBC Sleep Mode

I_{Sleep,VCC2,85}

–

30

40

60

¹⁾³⁾⁵⁾SBC Sleep Mode; P_4.4.20

T_j= 85°C; VCC2 = ON

(no load); LIN, CAN,

WK1..3 = OFF

¹⁾⁵⁾SBC Sleep Mode;

VCC3 = ON (no load,

stand-along config.);

LIN, CAN,

Current consumption for

VCC3 in SBC Sleep Mode in

stand-alone configuration

I_{Sleep,VCC3,25}

P_4.4.21

WK1..3 = OFF

Current consumption for

VCC3 in SBC Sleep Mode in

stand-alone configuration

I_{Sleep,VCC3,85}

I_Stop,HSx,25

I_Stop,HSx,85

–

50

70

µA

¹⁾³⁾⁵⁾SBC Sleep Mode; P_4.4.22

T_j= 85°C; VCC3 = ON

(no load, stand-along

config.); LIN, CAN,

WK1..3 = OFF

Current consumption for

HSx in SBC Stop Mode

550

575

675

700

⁵⁾⁸⁾SBC Stop Mode;

Cyclic Sense & HSx=

ON (no load);

P_4.4.33

LIN, CAN,

WK1..3 = OFF

³⁾⁵⁾⁸⁾SBC Stop Mode; P_4.4.34

T_j= 85°C;

Current consumption for

HSx in SBC Stop Mode

Cyclic Sense & HSx =

ON (no load);

LIN, CAN,

WK1..3 = OFF

Current consumption for

cyclic sense function

I_Stop,CS25

I_Stop,CS85

–

20

24

28

35

µA

^5)9)10)SBC Stop Mode; P_4.4.23

WD = OFF

^3)5)9)10)SBCStopMode; P_4.4.27

T_j= 85°C;

Current consumption for

cyclic sense function

WD = OFF

Current consumption for

watchdog active in Stop

Mode

I_Stop,WD25

–

20

24

28

35

µA

³⁾SBC Stop Mode;

Watchdog running

P_4.4.30

P_4.4.31

Current consumption for

watchdog active in Stop

Mode

I_Stop,WD85

³⁾SBC Stop Mode;

T_j= 85°C;

Watchdog running

Datasheet

20

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at T_j= 25°C, V_S= 13.5V, all outputs open (unless otherwise specified)

Parameter

Symbol

Values

Typ.

1.0

Unit Note or

Test Condition

Number

Min.

Max.

Current consumption for

active fail outputs (FO1..3)

I_Stop,FOx

–

2.0

mA

³⁾all SBC Modes;

T_j= 25°C; FOx = ON (no

load);

P_4.4.24

Current consumption for

GPIOx if configured as low-

side/high-side for SBC Stop

or Sleep mode

I_{Stop,GPIOx,LS/}

–

450

550

600

µA

³⁾SBC Stop/Sleep

mode; GPIO

configured as LS/HS

(no load);

³⁾SBC Stop/Sleep

mode; Tj = -

40…150°C;

P_4.4.37

P_4.4.38

HS

Current consumption for

GPIOx if configured as low-

side/high-side for SBC Stop

or Sleep mode

I_{Stop,GPIOx,LS/}

µA

HS

GPIO configured as

LS/HS (no load);

1) If the load current on VCC1 will exceed the configured VCC1 active peak threshold I_{VCC1,Ipeak1,r}or I_{VCC1,Ipeak2,r}

,

the current consumption will increase by typ. 2.9mA to ensure optimum dynamic load behavior. Same applies to

VCC2. For VCC3 the current consumption will increase by typ. 1.4mA. See also Chapter 6, Chapter 7, Chapter 8.

2) CAN not configured in selective wake mode.

3) Not subject to production test, specified by design.

4) Current consumption adder also applies for during WUF detection (frame detect mode) when CAN Partial Networking

is activated.

5) Current consumption adders of features defined for SBC Sleep Mode also apply for SBC Stop Mode and vice versa

(unless otherwise specified).

6) No pull-up or pull-down configuration selected.

7) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are

activated.

8) A typ. 75µA / max 125µA (T_j= 85°C) adder applies for every additionally activated HSx switch in SBC Stop Mode;

In SBC Normal Mode every HSx switch consumes the typ. 75µA / max 125µA (T_j= 85°C) without the initial adder

because the biasing is already enabled.

9) HS1 used for cyclic sense, Timer 2, 20ms period, 0.1ms on-time, no load on HS1.

In general the current consumption adder for cyclic sense in SBC Stop Mode can be calculated with below equation:

IStop,CS = 20µA + (550µA *tON/TPer)

10) Also applies to Cyclic Wake

Note:

There is no additional current consumption contribution due to PWM generators.

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System Features

5

System Features

This chapter describes the system features and behavior of the TLE9263-3BQXV33:

•

State machine

SBC mode control

Device configuration

State of supply and peripherals

System functions such as cyclic sense or cyclic wake

Supervision and diagnosis functions

The System Basis Chip (SBC) offers six operating modes:

•

SBC Init Mode: Power-up of the device and after a soft reset,

SBC Normal Mode: The main operating mode of the device,

SBC Stop Mode: The first-level power saving mode with the main voltage regulator VCC1 enabled,

SBC Sleep Mode: The second-level power saving mode with VCC1 disabled,

SBC Restart Mode: An intermediate mode after a wake event from SBC Sleep or Fail-Safe Mode or after a

failure (e.g. WD failure, VCC1 undervoltage reset) to bring the microcontroller into a defined state via a

reset. Once the failure condition is not present anymore the device will automatically change to SBC

Normal Mode after a delay time (t_RD1).

•

SBC Fail-Safe Mode: A safe-state mode after critical failures (e.g. WD failure, VCC1 undervoltage reset) to

bring the system into a safe state and to ensure a proper restart of the system. VCC1 is disabled. It is a

permanent state until either a wake event (via CAN, LINx or WKx) occurs or the overtemperature condition

is not present anymore.

A special mode, called SBC Development Mode, is available during software development or debugging of the

system. All above mentioned operating modes can be accessed in this mode. However, the watchdog counter

is stopped and does not need to be triggered. This mode can be accessed by setting the TEST pin to GND

during SBC Init Mode.

The device can be configured via hardware (external component) to determine the device behavior after a

watchdog trigger failure. See Chapter 5.1.1 for further information.

The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in

Chapter 16.The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the TLE9263-

3BQXV33 is compatible to other devices of the TLE926x and TLE927x families.

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OPTIREG™ SBC TLE9263-3BQXV33

System Features

5.1

Block Description of State Machine

The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register

M_S_CTRL. The SBC MODE bits are cleared when going through SBC Restart Mode and thus always show the

current SBC mode.

First battery connection

SBC Soft Reset

SBC Init Mode

*

Config.: settings can be

changed in this SBC mode;

(Long open window)

Cyc.Sense

VCC1

ON

VCC2

VCC3

WD

OFF

OFF Config.

Fixed: settings stay as

defined in SBC Normal Mode

Any SPI

CAN⁽³⁾

OFF

Cyc. Wake

OFF

LINx⁽³⁾

OFF

HSx

OFF

command

FOx

inact.

* The SBC Development

Mode is a super set of state

machine where the WD timer

is stopped and CAN/LINx

behavior differs in SBC Init

Mode. Otherwise, there are

no differences in behavior.

SBC Normal Mode

Cyc.Sense

config.

VCC1

ON

VCC2

VCC3

WD

WD trigger

config.

config. config.

CAN⁽³⁾

config.

Cyc. Wake

config.

FOx

act/inact

LINx⁽³⁾

config. config.

HSx

.

Reset is released

WD starts with long open window

Automatic

SPI cmd

SBC Stop Mode

SBC Sleep Mode

VCC3⁽²⁾

VCC1

ON

VCC2

fixed

CAN ⁽⁵⁾LINx

fixed fixed

VCC3

fixed

WD

fixed

Cyc. Sense

fixed

VCC1

OFF

VCC2

WD

OFF.

Cyc. Sense

fixed

Fixed /

fixed

OFF

VCC1 over voltage

Config 1/3 (if VCC_OV_RST set)

CAN ⁽⁵⁾⁽⁷⁾

FOx

fixed

HSx

fixed

LINx

Cyc.Wake

fixed

FOx

fixed

HSx

fixed

Cyc. Wake

OFF

Wake

capable/off

Wake up event

SBC Restart Mode

(RO pin is asserted)

Watchdog Failure:

Config 1/3 & 1st WD failure

in Config4

VCC3⁽²⁾

After 4x consecutive VCC1

under voltage events

(if VS > VS_UV)

VCC1

ON/

ramping

VCC2

OFF

WD

OFF

Cyc. Sense

OFF

VCC1 over voltage

Config 2/4 (if VCC_OV_RST set)

fixed/

ramping

FOx⁽⁶⁾

active/

fixed

CAN ⁽⁴⁾LINx ⁽⁴⁾

HSx

OFF

Cyc.Wake

OFF

VCC1

Undervoltage

woken /

OFF

woken /

OFF

SBC Fail-Safe Mode ⁽¹⁾

TSD2 event,

1st Watchdog Failure Config 2,

2nd Watchdog Failure, Config 4

VCC1

OFF

VCC2

OFF

VCC3

OFF

WD Cyc. Sense

OFF

CAN, LINx, WKx wake-up event

OR

Release of over temperature

TSD2 after t_TSD2

¹⁾After Fail-Safe Mode entry, the device will stay for at least typ. 1s in

(

FOx⁽⁶⁾

active

CAN

Wake

capable

LINx

Wake

capable

this mode (with RO low) after a TSD2 event and min. typ. 100ms after

other Fail-Safe Events. Only then the device can leave the mode via a

wake-up event. Wake events are stored during this time.

Cyc.Wake

HSx

VCC1 Short to GND

OFF

⁽²⁾According to VCC3 configuration.

⁽³⁾For SBC Development Mode CAN/LINx/VCC2 are ON in SBC Init

Mode and stay ON when going from there to SBC Normal Mode.

⁽⁴⁾See chapter CAN & LIN for detailed behavior in SBC Restart Mode.

⁽⁵⁾CAN transceiver can be SWK capable, depending on configuration.

⁽⁶⁾See Chapter 5.1.5 and 14.1 for detailed FOx behavior.

⁽⁷⁾Must be set to CAN wake cabaple / CAN OFF mode before entering

SBC Sleep Mode.

Figure 3

State Diagram showing the SBC Operating Modes including CAN Partial Networking

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OPTIREG™ SBC TLE9263-3BQXV33

System Features

5.1.1

Device Configuration and SBC Init Mode

The SBC starts up in SBC Init Mode after crossing the power-on reset V_POR,rthreshold (see also Chapter 15.3)

and the watchdog will start with a long open window (t_LW).

During this power-on phase following configurations are stored in the device:

•

The device behavior regarding a watchdog trigger failure and a VCC1 overvoltage condition is determined

by the external circuitry on the INT pin (see below)

•

The selection of the normal device operation or the SBC Development Mode (watchdog disabled for

debugging purposes) will be set depending on the voltage level of the FO3/TEST pin (see also

Chapter 5.1.7).

5.1.1.1 Device Configuration

The configuration selection is intended to select the SBC behavior regarding a watchdog trigger failure.

Depending on the requirements of the application, the VCC1 output shall be switched OFF and the device shall

go to SBC Fail-Safe Mode in case of a watchdog failure (1 or 2 fails). To set this configuration (Config 2/4), the

INT pin does not need an external pull-up resistor. In case VCC1 should not be switched OFF (Config 1/3), the

INT pin needs to have an external pull-up resistor connected to VCC1 (see application diagram in

Chapter 17.1).

Figure 5 shows the timing diagram of the hardware configuration selection. The hardware configuration is

defined during SBC Init Mode. The INT pin is internally pulled LOW with a weak pull-down resistor during the

reset delay time t_RD1, i.e.after VCC1 crosses the reset threshold VRT1 and before the RO pin goes HIGH. The INT

pin is monitored during this time (with a continuos filter time of t_{CFG_F}) and the configuration (depending on

the voltage level at INT) is stored at the rising edge of RO.

Note:

If the POR bit is not cleared then the internal pull-down resistor will be reactivated every time RO is

pulled LOW the configuration will be updated at the rising edge of RO. Therefore it is recommended

to clear the POR bit right after initialization. In case there is no stable signal at INT, then the default

value ‘0’ will taken as the config select value = SBC Fail-Safe Mode.

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OPTIREG™ SBC TLE9263-3BQXV33

System Features

VS

V_POR,r

t

VCC1

V_RT1,r

RO

t_{CFG_F}

Continuous Filtering with

t

t_RD1

Configuration selection monitoring period

Figure 4

Hardware Configuration Selection Timing Diagram

There are four different device configurations (Table 5) available defining the watchdog failure and the VCC1

overvoltage behavior. The configurations can be selected via the external connection on the INT pin and the

SPI bit CFG in the HW_CTRL register (see also Chapter 16.4):

•

CFGP = ‘1’: Config 1 and Config 3:

–

A watchdog trigger failure leads to SBC Restart Mode and depending on CFG the Fail Outputs (FOx) are

activated after the 1st (Config 1) or 2nd (Config 3) watchdog trigger failure;

–

A VCC1 overvoltage detection will lead to SBC Restart Mode if VCC1_OV_RST is set.

VCC1_ OV will be set and the Fail Outputs are activated;

CFGP = ‘0’: Config 2 and Config 4:

–

A watchdog trigger failure leads to SBC Fail-Safe Mode and depending on CFG the Fail Outputs (FOx)

are activated after the 1st (Config 2) or 2nd (Config 4) watchdog trigger failure. The first watchdog

trigger failure in Config 4 will lead to SBC Restart Mode;

–

A VCC1 overvoltage detection will lead to SBC Fail-Safe Mode if VCC1_OV_RST is set.

VCC1_ OV will be set and the Fail Outputs are activated;

The respective device configuration can be identified by reading the SPI bit CFG in the HW_CTRL register and

the CFGP bit in the WK_LVL_STAT register.

Table 5 shows the configurations and the device behavior in case of a watchdog trigger failure:

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System Features

Table 5

Watchdog Trigger Failure Configuration

Config INT Pin (CFGP) SPI Bit CFG RO activation

FOx activation

SBC Mode Entry

1

2

External pull-up

No ext. pull-up

1

each watchdog failure after 1st WD failure SBC Restart Mode

each watchdog failure after 1st WD failure SBC Fail-Safe Mode

after 1st WD failure

3

4

External pull-up

No ext. pull-up

0

each watchdog failure after 2nd WD failure SBC Restart Mode

each watchdog failure after 2nd WD failure SBC restart mode after

1st WD failure.

SBC Fail-Safe Mode

after 2nd WD failure

Table 6 shows the configurations and the device behavior in case of a VCC1 overvoltage detection when

VCC1_OV_RST is set:

Table 6

Device Behavior in Case of VCC1 Overvoltage Detection

Config INT Pin (CFGP) CFG Bit VCC1_O Event

V_RST

VCC1_ FOx Activation

OV

SBC Mode Entry

1-4

1

any value

x

0

1

1 x VCC1 OV

1

no FOx activation unchanged

External pull-

up

1

after 1st VCC1 OV SBC Restart Mode

2

3

No ext. pull-up 1

1

1 x VCC1 OV

1

after 1st VCC1 OV SBC Fail-Safe Mode

after 1st VCC1 OV SBC Restart Mode

External pull-

up

0

4

No ext. pull-up 0

1

1 x VCC1 OV

1

after 1st VCC1 OV SBC Fail-Safe Mode

The respective configuration will be stored for all conditions and can only be changed by powering down the

device (VS < V_POR,f).

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OPTIREG™ SBC TLE9263-3BQXV33

System Features

5.1.1.2 SBC Init Mode

In SBC Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. In

the SBC Init Mode any valid SPI command will bring the SBC to SBC Normal Mode. During the long open

window the watchdog has to be triggered. Thereby the watchdog will be automatically configured.

A missing watchdog trigger during the long open window will cause a watchdog failure and the device will

enter SBC Restart Mode.

Wake events are ignored during SBC Init Mode and will therefore be lost.

Notes

1. Any SPI command will bring the SBC to SBC Normal Mode even if it is a illegal SPI command (see

Chapter 16.2).

2. For a safe start-up, it is recommended to use the first SPI command to trigger and to configure the watchdog

(see Chapter 15.2).

3. At power up no VCC1_UV will be issued nor will FOx be triggered as long as VCC1 is below the V_RT,xthreshold

and if VS is below the VCC1 short circuit detection threshold V_S,UV. The RO pin will be kept low as long as VCC1

is below the selected V_RT,xthreshold.

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OPTIREG™ SBC TLE9263-3BQXV33

System Features

5.1.2

SBC Normal Mode

The SBC Normal Mode is the standard operating mode for the SBC. All configurations have to be done in SBC

Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining

the Fail-Safe Mode behavior). A wake-up event on CAN, LINx and WKx will create an interrupt on pin INT -

however, no change of the SBC mode will occur. The configuration options are listed below:

•

VCC1 is active

VCC2 can be switched ON or OFF (default = OFF)

VCC3 is configurable (OFF coming from SBC Init Mode; as previously programmed coming from SBC Restart

Mode)

•

CAN is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart Mode,

see also Figure 24).

8.2.1

External Voltage Regulator as Independent Voltage Regulator

Configured as an independent voltage regulator the SBC offers with VCC3 a third supply which could be used

as off-board supply e.g. for sensors due to the integrated HV pins VCC3B, VCC3SH, VCC3REF.

This configuration is set and locked by enabling VCC3_ON while keeping VCC3_LS = 0. VCC3 can be switched

ON or OFF but the configuration cannot be changed anymore. However, the SPI_FAIL is not set while trying to

change the configuration.

An overcurrent limitation function is realized with the external shunt (see Chapter 8.4 for calculating the

desired shunt value) and the output current shunt voltage threshold (V_{shunt_threshold}). If this threshold is

reached, then ICC3 is limited and only the current limitation bit VCC3_OC is set (no other reaction) and can be

cleared via SPI once the overcurrent condition is not present anymore. If the overcurrent limitation feature is

not needed, then connect the pins VCC3SH and VS together.

In this configuration VCC3 has the undervoltage signalization enabled and an undervoltage event is signaled

with the bit VCC3_UV in the SUP_STAT_2 SPI register.

Note:

To avoid undesired current consumption increase of the device it must be ensured that VCC3 is not

connected to VCC1 in this configuration.

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External Voltage Regulator 3

V_S

V_CC3

R_SHUNT

T1

I_CC3

C₂

C₁

R_Lim

100Ω

VS

VCC3SH

VCC3B

R_BE

VCC3REF

I_CC3base

V_S- V_CC3shunt

> V_{shunt_threshold}

+

-

V_REF

State Machine

Figure 24 Protecting the VCC3 against inductive short circuits when configured as an independent

voltage regulator for off-board supply

8.2.2

External Voltage Regulator in Load Sharing Mode

The purpose of the load sharing mode is to increase the total current capability of VCC1 without increase of

the power dissipation within the SBC. The load current is shared between the VCC1 internal regulator and the

external PNP transistor of VCC3. Figure 25 shows the setup for Load Sharing. Load Sharing is active in SBC

Normal Mode. It can also be configured via SPI to stay active in SBC Stop Mode.

An input voltage up to V_Sx,MAXis regulated to V_CC3,nom= 3.3 V with a precision of ±2% when used in the load

sharing configuration in SBC Normal Mode.

This configuration is set and locked by enabling VCC3_LS for the first time while VCC3_ON has no function, i.e.

keep VCC3_ON = 0. Trying to change the VCC3 configuration after VCC3_LS has been set will result in the

SPI_FAIL bit being set and keeping the VCC3 configurations unchanged. Load sharing will be automatically

disabled (only if VCC3_LS_ STP_ON = 0) during SBC Stop Mode due to power saving reasons but the bit will

remain set to automatically switch back on after returning to SBC Normal Mode. It must be ensured that the

same VCC3 output voltage level is selected as for VCC1.

In this configuration VCC3 has no undervoltage signalization. VCC3 shuts down if Fail-Safe Mode is reached,

e.g. due to undervoltage shutdown (V_S,UVmonitoring).

VCC3 has no overcurrent limitation in this configuration and the shunt resistor is defining the load sharing

ratio between the VCC1 and VCC3 load currents (see Equation (8.2) in Chapter 8.4). Thus, no overcurrent

condition VCC3_OC will be signaled in this configuration.

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External Voltage Regulator 3

V_S

V_CC13

R_SHUNT

T1

I_CC3

C₁

C₂

VS

VCC3SH

VCC3B

VCC3REF

Vcc3

Vcc1

I_CC1

Figure 25 VCC3 in Load Sharing Configuration

8.3

External Components

Characterization is performed with the BCP52-16 from Infineon (I_CC3< 200 mA) and with MJD253.

Other PNP transistors can be used. However, the functionality must be checked in the application.

Figure 25 shows one hardware set up used.

Table 20

Device

C2

Bill of Materials for the V_CC3Function with and without load sharing configuration

Vendor

Murata

-

Reference / Value

10 µF/10 V GCM31CR71A106K64L

1 Ω (with / without LS)

BCP52-16

RSHUNT

T1

Infineon

Note:

The SBC is not able to ensure a thermal protection of the external PNP transistor. The power

handling capabilities for the application must therefore be chosen according to the selected PNP

device, the PCB layout and properties of the application to prevent thermal damage, e.g. via the

shunt current limitation in stand alone configuration or by selecting the proper ICC1/ICC3 ratio in

load-sharing configuration.

Note:

To ensure an optimum EMC behavior of the VCC3 regulator when the VCC3 output is leaving the PCB,

it is necessary to optimize the PCB layout to have the PNP very close to the SBC. If this is not sufficient

or possible, an external capacitance should be placed to the off-board connector (see also

Chapter 17.1).

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External Voltage Regulator 3

8.4

Calculation of R_SHUNT

As a independent regulator, the maximum current I_CC3maxwhere the limit starts and the bit I_CC3> I_CC3maxis set is

determined by the shunt resistor R_SHUNTand the Output Current Shunt Voltage Threshold V_{shunt_threshold}

.

The resistor can be calculated as following:

U_{shunt _ threshold}

(8.1)

R_SHUNT

=

I_{CC3 max}

If VCC3 is configured for load sharing, then the shunt resistor determines the load sharing ratio between VCC1

and VCC3. The ratio can be calculated as following:

I _CC

110 Ω 105 − 15 mV

I _CC

1

3

1

=

( a )

(8.2)

R

SHUNT

I _CC⋅ 110 Ω 105 − 15 mV

1

I _CC

=

( b )

3

R

SHUNT

Example: A shunt resistor with 470mΩ and a load current of 100mA out of VCC1 would result in I_CC3= 191mA.

8.5

Unused Pins

In case the VCC3 is not used in the application, it is recommended to connect the unused pins of VCC3 as

followed:

•

Connect VCC3SH to VS or leave open;

Leave VCC3B open;

Leave VCC3REF open

Do not enable the VCC3 via SPI as this leads to increased current consumption

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External Voltage Regulator 3

8.6

Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all outputs open; all voltages with respect to ground;

positive current defined flowing into pin; unless otherwise specified.

Table 21

Electrical Characteristics

Symbol

Parameter

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Parameters independent from Test Set-up

External Regulator Control I_VCC3base

Drive Current Capability

40

60

3

80

10

310

5

mA V_VCC3base= 13.5 V

P_8.6.1

P_8.6.2

P_8.6.3

P_8.6.6

P_8.6.7

P_8.6.8

P_8.6.9

Input Current V_CC3ref

I_VCC3ref

0

µA

mV

µs

V_VCC3ref= 3.3 V

Input Current V_CC3

I_VCC3shunt

3

V_VCC3shunt= V_S

Shunt Pin

1)

Output Current Shunt

Voltage Threshold

V_{shunt_threshold}180

245

–

5)

Current increase regulation t_rIinc

reaction time

–

V

= 3.3 V to 0 V;

CC3

I_CC3base= 20 mA Figure 26

5)

Current decrease regulation t_rIdec

reaction time

–

5

µs

V

= 0 V to 3.3V;

CC3

I_CC3base= 20 mA Figure 26

Leakage current of

VCC3base when VCC3

disabled

I_{VCC3base_lk}

–

5

µA

V_CC3base= V_S;

T_j= 25°C

Leakage current of V_CC3shuntI_{VCC3shunt_lk}

when VCC3 disabled

–

5

µA

V_CC3shunt= V_S;

T_j= 25°C

P_8.6.11

P_8.6.12

P_8.6.33

Base to emitter resistor

R_BE

120

–

150

50

185

65

kΩ V_CC3= OFF;

Active Peak Threshold VCC3 I_{VCC3base,Ipeak,r}

(Transition threshold

between low-power and

µA

⁵⁾Drive current I_VCC3base

_VCC3baserising

;

I

V_S=13.5V;

-40°C < T_j< 150°C

⁵⁾Drive current I_VCC3base

high-power mode regulator)

Active Peak Threshold VCC3 I_{VCC3base,Ipeak,f}15

(Transition threshold

between high-power and

30

–

µA

P_8.6.34

P_8.6.26

I_VCC3basefalling

V_S=13.5V;

-40°C < T_j< 150°C

low-power mode regulator)

Parameters dependent on the Test Set-up (with external PNP device MJD-253)

External Regulator Output V_CC3.out1

Voltage (VCC3 = 3.3V)

3.23 3.3

3.37

V

²⁾SBC Normal Mode;

load sharing

configuration with 470

mΩ shunt resistor;

10 µA < I_VCC1+ I_VCC3

< 300 mA;

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External Voltage Regulator 3

Table 21

Electrical Characteristics (cont’d)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

External Regulator Output V_CC3,out4

Voltage

(VCC3 = 3.3V)

3.23 3.3V 3.37

V

–

SBC Normal Mode;

stand-alone

configuration

P_8.6.22

P_8.6.23

P_8.6.24

10 mA < I_VCC3< 300 mA;

External Regulator Output V_CC3,out5

Voltage

(VCC3 = 3.3V)

3.15 3.3V 3.45³⁾

SBC Stop-, Sleep Mode;

Stand-alone

configuration

10µA < I_VCC3< I_{VCC3_peak,r}

²⁾SBC Normal Mode;

stand-alone

configuration

10 mA < I_CC3< 300 mA;

²⁾SBC Stop-, Sleep Mode; P_8.6.25

Stand-alone

configuration

4)

External Regulator Output V_CC3,out6

Voltage

(VCC3 = 1.8V)

1.75 1.8

1.70 1.8

1.85

External Regulator Output V_CC3,out7

Voltage

(VCC3 = 1.8V)

1.90³⁾

4)

10µA < I_CC3< I_{VCC3_peak,r}

;

Load Sharing Ratio

ICC1 : ICC3

Ratio_{LS_1,VCC3}1 :

1 :

⁵⁾⁶⁾6.0V < V_S< 28V;

SBC Normal Mode;

LS ratio for a 470 mΩ

P_8.6.16

P_8.6.20

P_8.6.27

1.35 1.9

2.45

shunt resistor and total

load current of 300mA

⁵⁾⁶⁾6.0V < V_S< 28V;

SBC Normal Mode;

LS ratio for a 1 Ω shunt

resistor and total load

current of 300mA

Load Sharing Ratio

ICC1 : ICC3

Ratio_{LS_2,VCC3}1 :

1 :

–

0.67 0.95 1.23

Load Sharing Ratio

ICC1 : ICC3

Ratio_{LS_3,VCC3}1 :

1 :

⁵⁾⁶⁾T_j= 150°C;

8.0V < V_S< 18V;

1.50 1.95 2.40

SBC Normal Mode;

LS ratio for a 470 mΩ

shunt resistor and total

load current of 300mA

Load Sharing Ratio

ICC1 : ICC3

Ratio_{LS_4,VCC3}1 :

1 :

–

⁵⁾⁶⁾T_j= 150°C;

8.0V < V_S< 18V;

P_8.6.28

0.75 0.98 1.21

SBC Normal Mode;

LS ratio for a 1 Ω shunt

resistor and total load

current of 300mA

1) Threshold at which the current limitation starts to operate. This threshold is only active when VCC3 is configured for

stand-alone configuration.

2) Tolerance includes load regulation and line regulation.

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OPTIREG™ SBC TLE9263-3BQXV33

External Voltage Regulator 3

3) At Tj > 125°C, the power transistor leakage could be increased, which has to be added to the quiescent current of the

application independently if the regulator is turned on/off. To prevent an overvoltage condition at no load due to this

increased leakage, an internal clamping structure will automatically turn on at typ. 200mV above the upper limit of the

programmed output voltage.

4) I_{VCC3_peak}refers to the load current out of the collector of the external PNP device. This value can be calculated by

multiplying the VCC3base active peak threshold (I_{VCC3base,Ipeak}) with the current gain of the PNP

5) Not subject to production test, specified by design.

6) a) Ratio will change depending on the chosen shunt resistor which value is correlating to the maximum power

dissipation of the PNP pass device. See Chapter 8.4 for the ratio calculation. The ratio will also change at low-drop

operation.

For supply voltages of 5.5V < VS < 6V the accuracy applies only for a total load current of 250mA.

The load sharing ratio in SBC Stop Mode has +/-10% wider limits than specified.

b) The output voltage precision in load sharing in SBC Stop Mode is according to VCC1 +/-4% or better for loads up to

20mA and +/-2% with loads greater than 20mA.

In SBC Normal the +/-2% precision for 5V/3.3V tolerance is valid regardless of the applied load.

Notes

1. There is no thermal protection available for the external PNP transistor. Therefore, the application must be

designed to avoid overheating of the PNP via the shunt current limitation in stand alone configuration and by

selecting the proper ICC1/ICC3 ratio in load-sharing configuration.

2. In SBC Stop Mode, the same output voltage tolerance applies as in SBC Normal Mode when I_VCC3has exceeded

the selected active peak threshold (I_{VCC3base,Ipeak}) but with increased current consumption.

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OPTIREG™ SBC TLE9263-3BQXV33

External Voltage Regulator 3

Timing diagram for regulator reaction time “current increase regulation reaction time” and “current decrease

regulation reaction time”

V_CC3

t

I_CCbase

I_{CC3base, 50%}

t

t_rlinc

t_rldec

Figure 26 Regulator Reaction Time

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External Voltage Regulator 3

Typical Load Sharing Characteristics using the BCP52-16 PNP transistor and a 1 Ω shunt resistor

0,35

Tj = 27°C

0,30

Tj = 150°C

0,25

0,20

0,15

0,10

0,05

0

Tj = -40°C

0

0,2

0,4

0,6

0,8

- Icc3 vs. Icc1

1,0

1,2

1,4

Load Sharing Ratio - Icc1 vs. Icc3

Figure 27 Load Sharing Ratio ICC1 : ICC3 vs. the total load current

0,35

Tj = 27°C

0,30

Tj = 150°C

0,25

0,20

0,15

0,10

0,05

0

Tj = -40°C

0

0,02

0,04

0,06

0,08

0,10

0,12

0,14

0,16

Load Current - Icc1

Figure 28 Load Sharing Behavior of ICC1 vs. the total load current

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High-Side Switch

9

High-Side Switch

9.1

Block Description

HSx

VSHS

HS Gate Control

Overcurrent Detection

Open Load (On)

Figure 29 High-Side Module Block Diagram

Features

•

Dedicated supply pin VSHS for high-side outputs

Overvoltage and undervoltage switch off - configurable via SPI

Overcurrent detection and switch off

Open load detection in ON-state

PWM capability with internal timer configurable via SPI

Switch recovery after removal of OV or UV condition configurable via SPI

9.2

Functional Description

The High-Side switches can be used for control of LEDs, as supply for the wake inputs and for other loads. The

High-Side outputs can be controlled either directly via SPI by (HS_CTRL1, HS_CTRL2), by the integrated

timers or by the integrated PWM generators.

The high-side outputs are supplied by a dedicated supply pin VSHS (different to VS). The topology supports

improved cranking condition behavior.

The configuration of the High-Side (Permanent On, PWM, cyclic sense, etc.) drivers must be done in SBC

Normal Mode. The configuration is taken over in SBC Stop- or SBC Sleep Mode and cannot be modified. When

entering SBC Restart Mode or SBC Fail-Safe Mode the HSx outputs are disabled.

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High-Side Switch

9.2.1

Over- and Undervoltage Switch Off

All HS drivers in on-state are switched off in case of overvoltage on VSHS (V_SHS,OVD). If the voltage drops below

the overvoltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit

HS_OV_SD_EN.

The HS drivers are switched off in case of undervoltage on VSHS (V_SHS,UVD). If the voltage rises above the

undervoltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit

HS_UV_SD_EN.

So after release of undervoltage or overvoltage condition the HS switch goes back to programmed state in

which it was configured via SPI. This behavior is only valid if the bit HS_OV_UV_REC is set to ‘1’. Otherwise the

switches will stay off and the respective SPI control bits are cleared.

The overvoltage and undervoltage is signaled in the bits VSHS_OV and VSHS_UV, no other error bits are set.

9.2.2

Overcurrent Detection and Switch Off

If the load current exceeds the overcurrent shutdown threshold for a time longer then the overcurrent

shutdown filter time the output is switched off.

The overcurrent condition and the switch off is signaled with the respective HSx_OC_OT bit in the register

HS_OC_OT_STAT. The HSx configuration is then reset to 000 by the SBC. To activate the High-Side again the

HSx configuration has to be set to ON (001) or be programmed to a timer function. It is recommended to clear

the overcurrent bit before activation the High-Side switch, as the bits are not cleared automatically by the

SBC.

9.2.3

Open Load Detection

Open load detection on the High-Side outputs is done during on state of the output. If the current in the

activated output falls below then Open Load Detection current, the open load is detected and signaled via the

respective bit HS1_OL, HS2_OL, HS3_OL, or HS4_OL in the register HS_OL_STAT. The High-Side output stays

activated. If the open load condition disappears the Open Load bit in the SPI can be cleared. The bits are not

cleared automatically by the SBC.

9.2.4

HSx Operation in Different SBC Modes

•

During SBC Stop and SBC Sleep Mode the HSx outputs can be used for the cyclic sense feature. The open-

load detection, overcurrent shut down as well as overvoltage and undervoltage shutdown are available.

The overcurrent shutdown protection feature may influence the wake-up behavior¹⁾.

•

the HSx output can also be enabled for SBC Stop and SBC Sleep Mode as well as controlled by the PWMx

generator. The HSx outputs must be configured in SBC Normal Mode before entering a low-power mode.

The HSx outputs are switched off during SBC Restart or SBC Fail-Safe Mode. They can be enabled via SPI if

the failure condition is removed.

9.2.5

PWM and Timer Function

Two 8-bit PWM generators are dedicated to generate a PWM signal on the HS outputs, e.g. for brightness

adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated

HS outputs, and the duty cycle can be independently configured with a 8bit resolution via SPI (PWM1_CTRL,

1) For the wake feature, the forced overcurrent shut down case must be considered in the user software for all SBC Modes, i.e. due to

disabled HSx switches a level change might not be detected anymore at WKx pins.

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OPTIREG™ SBC TLE9263-3BQXV33

High-Side Switch

PWM2_CTRL). Two different frequencies (200Hz, 400Hz) can be selected independently for every PWM

generator in the register PWM_FREQ_CTRL.

PWM Assignment and Configuration:

•

Configure duty cycle and frequency for respective PWM generator in PWM1_CTRL/PWM2_CTRL and

PWM_FREQ_CTRL

•

Assign PWM generator to respective HS switch(es) in HSx_CTRL

The PWM generation will start right after the HSx is assigned to the PWM generator (HS_CTRL1, HS_CTRL2)

Assignment options of HS1... HS4

•

Timer 1

Timer 2

PWM 1

PWM 2

Minimum On-time during PWM Operation

The min. on-time during PWM is limited by the actual on- and off-time of the respective HS switch, e.g. the

PWM setting ‘0000 0001’ could not be realized.

Reliable Open-Load Detection during PWM Operation

The minimum PWM setting for a reliable open-load detection is 3digits for a period of 400Hz and >2 digits for

the frequency setting of 200Hz, i.e. the high-side on-time must be longer than t_OL,HS

.

Reliable Overcurrent Detection during PWM Operation

The minimum PWM setting for a reliable overcurrent detection is >1 digit for a period of 400Hz and 1 digit for

the frequency setting of 200Hz, i.e. the high-side on-time must be longer than t_SD,HS

.

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OPTIREG™ SBC TLE9263-3BQXV33

High-Side Switch

9.3

Electrical Characteristics

Table 22

Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Output HS1, HS2, HS3, HS4

Static Drain-Source ON

Resistance HS1...HS4

R_ON,HS25

R_ON,HS150

I_leak,HS

–

7

10

16

2

Ω

I_ds= 60mA,

T_j< 25°C

P_9.3.1

P_9.3.2

P_9.3.11

Static Drain-Source ON

Resistance HS1...HS4

11.5

–

Ω

I_ds= 60mA,

T_j< 150°C

¹⁾0 V < V_HSx

Leakage Current HSx / per

channel

µA

< V_SHS

;

T_j< 85°C

Output Slew Rate (rising)

Output Slew Rate (falling)

Switch-on time HSx

SR_raise,HS

SR_fall,HS

t_ON,HS

0.8

-2.5

3

–

2.5

-0.8

30

V/µs ¹⁾20 to 80%

V_SHS= 6 to 18V

R_L= 220Ω

P_9.3.3

P_9.3.4

P_9.3.5

V/µs ¹⁾80 to 20%

V_SHS= 6 to 18V

R_L= 220Ω

µs

CSN = HIGH to

0.8*VSHS;

R_L= 220Ω;

V_SHS= 6 to 18V

Switch-off time HSx

t_OFF,HS

3

–

30

µs

CSN = HIGH to

0.2*VSHS;

R_L= 220Ω;

P_9.3.6

P_9.3.7

V_SHS= 6 to 18V

Short Circuit Shutdown

Current

I_SD,HS

150

245

300

mA

V_SHS= 6 to 20V,

hysteresis

included

2) 3)

Short Circuit Shutdown

Filter Time

t_SD,HS

12

16

–

20

3

µs

,

P_9.3.8

P_9.3.9

P_9.3.14

P_9.3.10

Open Load Detection

Current

I_OL,HS

0.4

0.05

50

mA

µs

hysteresis

included

1)

Open Load Detection

hysteresis

I_OL,HS,hys

0.45

64

1.0

80

2) 3)

Open Load Detection Filter t_OL,HS

,

Time

1) Not subject to production test, specified by design.

2) Not subject to production test, tolerance defined by internal oscillator tolerance.

3) Configure proper minimum PWM settings for reliable detection of overcurrent and open load measurement (see also

Chapter 9.2.5).

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OPTIREG™ SBC TLE9263-3BQXV33

High Speed CAN Transceiver

10

High Speed CAN Transceiver

10.1

Block Description

VCAN

V_CC1

SPI Mode

Control

R_TXD

Driver

CANH

Output

TXDCAN

Stage

Temp.-

Protection

+

CANL

timeout

To SPI diagnostic

VCAN

V_BIAS= 2.5V

V_CC1

RXDCAN

MUX

Receiver

Vs

Wake

Receiver

Figure 30 Functional Block Diagram

10.2

Functional Description

The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode

data transmission (up to 2 Mbaud) and reception in automotive and industrial applications. It works as an

interface between the CAN protocol controller and the physical bus lines compatible to ISO 11898-2:2016 and

SAE J2284.

The CAN transceiver offers low power modes to reduce current consumption. This supports networks with

partially powered down nodes. To support software diagnostic functions, a CAN Receive-only Mode is

implemented.

It is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks,

clamp15/30 applications).

A wake-up from the CAN wake capable mode is possible via a message on the bus. Thus, the microcontroller

can be powered down or idled and will be woken up by the CAN bus activities.

The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support

12 V applications.

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High Speed CAN Transceiver

The different transceiver modes can be controlled via the SPI CAN bits.

Figure 31 shows the possible transceiver mode transitions when changing the SBC mode.

SBC Mode

CAN Transceiver Mode

SBC Stop Mode

Receive Only Wake Capable Normal Mode

OFF

SBC Normal Mode

SBC Sleep Mode

SBC Restart Mode

SBC Fail-Safe Mode

Receive Only Wake Capable Normal Mode

Wake Capable²

OFF²

OFF

Woken¹

Wake Capable

Behavior after SBC Restart Mode - not coming from SBC Sleep Mode due to a wake up of the respective transceiver:

If the transceivers had been configured to Normal Mode, or Receive Only Mode, then the mode will be changed to Wake

Capable. If it was Wake Capable, then it will remain Wake Capable. If it had been OFF before SBC Restart Mode, then it

will remain OFF.

Behavior in SBC Development Mode:

CAN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF.

¹After a wake event on CAN Bus.

²Must be set to CAN wake capable / CAN off mode before entering SBC Sleep Mode.

Figure 31 CAN Mode Control Diagram

CAN FD Support

CAN FD stands for ‘CAN with Flexible Data Rate’. It is based on the well established CAN protocol as specified

in ISO 11898-1. CAN FD still uses the CAN bus arbitration method. The benefit is that the bit rate can be

increased by switching to a shorter bit time at the end of the arbitration process and then to return to the

longer bit time at the CRC delimiter, before the receivers transmit their acknowledge bits. See also Figure 32.

In addition, the effective data rate is increased by allowing longer data fields. CAN FD allows the transmission

of up to 64 data bytes compared to the 8 data bytes from the standard CAN.

Standard CAN

message

Data phase

(Byte 0 – Byte 7)

CAN Header

CAN Footer

Example:

- 11bit identifier + 8Byte data

CAN FD with

reduced bit time

Data phase

(Byte 0 – Byte 7)

CAN Header

CAN Footer

- Arbitration Phase

- Data Phase

500kbps

2Mbps

àaverage bit rate

1.14Mbps

Figure 32 Bite Rate Increase with CAN FD vs. Standard CAN

Not only the physical layer must support CAN FD but also the CAN controller. In case the CAN controller is not

able to support CAN FD then the respective CAN node must at least tolerate CAN FD communication. This

CAN FD tolerant mode is realized in the physical layer in combination with CAN Partial Networking.

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High Speed CAN Transceiver

The TLE926x-3BQX variants of this family also support the CAN FD tolerant mode. See also Chapter 5.4.7 for

more detailed information on how to enable the CAN FD tolerant mode.

10.2.1

CAN OFF Mode

The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is

intended to completely stop CAN activities or when CAN communication is not needed. The CANH/L bus

interface acts as a high impedance input with a very small leakage current. In CAN OFF Mode, a wake-up event

on the bus will be ignored.

10.2.2

CAN Normal Mode

The CAN Transceiver is enabled via SPI in SBC Normal Mode. CAN Normal Mode is designed for normal data

transmission/reception within the HS-CAN network. The Mode is available in SBC Normal Mode and in SBC

Stop Mode. The bus biasing is set to VCAN/2.

Transmission

The signal from the microcontroller is applied to the TXDCAN input of the SBC. The bus driver switches the

CANH/L output stages to transfer this input signal to the CAN bus lines.

Enabling sequence

The CAN transceiver requires an enabling time t_CAN,ENbefore a message can be sent on the bus. This means

that the TXDCAN signal can only be pulled LOW after the enabling time. If this is not ensured, then the TXDCAN

needs to be set back to HIGH (=recessive) until the enabling time is completed.

Only the next dominant bit will be transmitted on the bus.

Figure 33 shows different scenarios and explanations for CAN enabling.

V

TXDCAN

t

CAN

Mode

t _CAN,EN

t_CAN,EN

t _CAN,EN

CAN

NORMAL

CAN

OFF

t

V

CANDIFF

Dominant

Recessive

recessive TXD level

required before start of

transmission

Correct sequence ,

Bus is enabled after t_CAN,

t_CAN,_ENnot ensured , no

transmission on bus

t_CAN,not ensured ,

no transmission on bus

recessive TXD

level required

EN

Figure 33 CAN Transceiver Enabling Sequence

Reduced Electromagnetic Emission

To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically.

Reception

Analog CAN bus signals are converted into digital signals at RXD via the differential input receiver.

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High Speed CAN Transceiver

10.2.3

CAN Receive Only Mode

In CAN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still operational. This

mode is accessible by an SPI command in Normal Mode and in Stop Mode. The bus biasing is set to VCAN/2.

10.2.4

CAN Wake Capable Mode

This mode can be used in SBC Stop, Sleep, Restart and Normal Mode and it is used to monitor bus activities.

It is automatically accessed in SBC Fail-Safe Mode. Both bus pins CANH/L are connected to GND via the input

resistors.

A wake-up signal on the bus results in a change of behavior of the SBC, as described in Table 23. The pins

CANH/L are terminated to typ. 2.5V through the input resistors. As a wake-up signalization to the

microcontroller, the RXD_CAN pin is set LOW and will stay LOW until the CAN transceiver is changed to any

other mode. After a wake-up event, the transceiver can be switched to CAN Normal Mode for communication

via SPI.

As shown in Figure 34, a wake-up pattern (WUP) is signaled on the bus by two consecutive dominant bus

levels for at least t_Wake1(filter time t > t_Wake1) and shorter than t_Wake2, each separated by a recessive bus level

of greater than t_Wake1and shorter than t_Wake2

.

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High Speed CAN Transceiver

Entering low-power mode,

when selective wake-up

function is disabled

or not supported

Bus recessive > tWAKE1

Ini

Wait

Bias off

Bus dominant > tWAKE1

optional:

tWAKE2 expired

1

Bias off

Bus recessive > t^WAKE1

optional:

tWAKE2 expired

2

Bias off

Bus dominant > tWAKE1

Silence expired AND

t

Entering CAN Normal

Device in low-power mode

3

Bias on

or CAN Recive Only

Bus dominant > tWAKE1

Bus recessive > tWAKE1

tSilence expired AND

device in low-power mode

4

Bias on

Figure 34 WUP detection following the definition in ISO 11898-2:2016

Rearming the Transceiver for Wake Capability

After a BUS wake-up event, the transceiver is woken. However, the CAN transceiver mode bits will still show

wake capable (=‘01’) so that the RXD signal will be pulled low. There are two possibilities how the CAN

transceiver’s wake capable mode is enabled again after a wake event:

•

The CAN transceiver mode must be toggled, i.e. switched from Wake Capable Mode to CAN Normal Mode,

CAN Receive Only Mode or CAN Off, before switching to CAN Wake Capable Mode again.

Rearming is done automatically when the SBC is changed to SBC Stop or SBC Fail-Safe Mode to ensure

wake-up capability.

CAN must be set to CAN wake capable / CAN off mode before entering SBC Sleep Mode

Notes

1. It is not necessary to clear the CAN wake-up bit CAN_WU to become wake capable again. It is sufficient to

toggle the CAN mode.

2. The CAN module is supplied by an internal voltage when in CAN Wake Capable Mode, i.e. the module does not

need to be supplied by the VCAN pin during this time. Before changing the CAN Mode to Normal Mode, the

supply of VCAN has to be activated first.

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High Speed CAN Transceiver

Wake-Up in SBC Stop and Normal Mode

In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INT output and in the WK_STAT_1 SPI

register. It is also signaled by RXDCAN pulled to low. The same applies for the SBC Normal Mode. The

microcontroller should set the device from SBC Stop Mode to SBC Normal Mode, there is no automatic

transition to Normal Mode.

For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a Bus wake

event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to HIGH before).

Wake-Up in SBC Sleep Mode

Wake-up is possible via a CAN message (filter time t > t_Wake1). The wake-up automatically transfers the SBC into

the SBC Restart Mode and from there to Normal Mode the corresponding RXD pin in set to LOW. The

microcontroller is able to detect the low signal on RXD and to read the wake source out of the WK_STAT_1

register via SPI. No interrupt is generated when coming out of Sleep Mode. The microcontroller can now for

example switch the CAN transceiver into CAN Normal Mode via SPI to start communication.

Table 23

Action due to CAN Bus Wake-Up

SBC Mode after Wake

Normal Mode

SBC Mode

Normal Mode

Stop Mode

Sleep Mode

Restart Mode

VCC1

INT

RXD

LOW

ON

LOW

HIGH

Stop Mode

ON

Restart Mode

Ramping Up

ON

Restart Mode

Fail-Safe Mode

Restart Mode

Ramping up

10.2.5

TXD Time-out Feature

If the TXD signal is dominant for a time t > t_{TXD_CAN_TO}, in CAN Normal Mode, the TXD time-out function

deactivates the transmission of the signal at the bus. This is implemented to prevent the bus from being

blocked permanently due to an error. The transmitter is disabled and the transceiver is switched to Receive

Only Mode. The failure is stored in the SPI flag CAN_FAIL. The CAN transmitter stage is activated again after

the dominant time-out condition is removed and the transceiver is automatically switched back to CAN

Normal Mode. The transceiver configuration stays unchanged.

10.2.6

Bus Dominant Clamping

If the HS CAN bus signal is dominant for a time t > t_{BUS_CAN_TO}in CAN Normal and Receive Only Mode a bus

dominant clamping is detected and the SPI bit CAN_FAIL is set. The transceiver configuration stays

unchanged.

10.2.7

Undervoltage Detection

The voltage at the CAN supply pin is monitored only in CAN Normal and Receive Only Mode for SBC Normal

and Stop Mode . In case of VCAN undervoltage a signalization via SPI bit VCAN_UV is triggered and the SBC

disables the transmitter stage. If the CAN supply reaches a higher level than the undervoltage detection

threshold (VCAN > V_{CAN_UV}), the transceiver is automatically switched back to CAN Normal Mode. The

transceiver configuration stays unchanged.

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OPTIREG™ SBC TLE9263-3BQXV33

High Speed CAN Transceiver

10.3

Electrical Characteristics

Table 24

Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Uni Note or

Number

t

Test Condition

Min.

Max.

CAN Bus Receiver

Differential Receiver

Threshold Voltage,

recessive to dominant edge

V_{diff,rd_N}

–

0.80

0.90

V

V_diff= V_CANH- V_CANL

;

P_10.3.2

-12V ≤ V_CM(CAN) ≤ +12V;

0.9 V ≤ V_{diff,D_Range}≤ 8 V;

CAN Normal Mode

1)

Dominant state differential V_{diff_D_range}0.9

input voltage range

–

8.0

–

V

= V_CANH- V_CANL

;

P_10.3.59

P_10.3.3

diff

-12V ≤ V_CM(CAN) ≤ +12V;

CAN Normal Mode

Differential Receiver

Threshold Voltage,

dominant to recessive edge

V_{diff,dr_N}

0.50

0.60

V_diff= V_CANH-V_CANL;

-12V ≤ V_CM(CAN) ≤ +12V;

-3 V ≤ V_{diff,R_Range}≤ 0.5 V;

CAN Normal Mode

1)

Recessive state differential V_{diff_R_range}-3.0

input voltage range

–

0.5

V

= V_CANH- V_CANL

;

P_10.3.60

diff

-12V ≤ V_CM(CAN) ≤ +12V;

CAN Normal Mode

1)

Common Mode Range

CMR

-12

20

–

12

50

P_10.3.4

P_10.3.6

CANH, CANL Input

Resistance

R_in

40

kΩ CAN Normal / Wake

capable Mode;

Recessive state;

-2 V ≤ V_CANL/H≤ +7 V

Differential Input Resistance R_diff

40

80

100

kΩ CAN Normal / Wake

capable Mode;

P_10.3.7

Recessive state;

-2 V ≤ V_CANL/H≤ +7 V

Input Resistance Deviation ΔR_i

between CANH and CANL

-3

–

3

%

pF

V

¹⁾Recessive state;

V_CANH= V_CANL= 5 V

P_10.3.38

P_10.3.39

P_10.3.40

2)

Input Capacitance CANH,

CANL versus GND

C_in

20

10

0.8

40

20

1.15

V

= 5 V

TXD

2)

Differential Input

Capacitance

C_diff

–

V

= 5 V

TXD

Wake-up Receiver

V_{diff, rd_W}

–

-12V ≤ V_CM(CAN) ≤ +12V; P_10.3.8

1.15 V ≤V_{diff,D_Range}≤8 V;

CAN Wake Capable

Mode

Threshold Voltage,

recessive to dominant edge

Datasheet

89

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

High Speed CAN Transceiver

Table 24

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Uni Note or

Number

t

Test Condition

Min.

Max.

Wake-up Receiver Dominant V_{diff,D_range}1.15

state differential input

8.0

V

¹⁾-12V ≤ V_CM(CAN) ≤

+12V;

P_10.3.61

_W

voltage range

CAN Wake Capable

Mode

Wake-up Receiver

Threshold Voltage,

dominant to recessive edge

V_{diff, dr_W}

0.4

0.7

–

V

-12V ≤ V_CM(CAN) ≤ +12V; P_10.3.9

-3 V ≤ V_{diff,R_Range}≤ 0.4 V;

CAN Wake Capable

Mode

Wake-up Receiver Recessive V_{diff,R_range_}-3.0

state differential input

0.4

¹⁾-12V ≤ V_CM(CAN) ≤

+12V;

P_10.3.62

W

voltage range

CAN Wake Capable

Mode

CAN Bus Transmitter

CANH/CANL Recessive

Output Voltage

(CAN Normal Mode)

V_{CANL/H_NM}2.0

–

3.0

0.1

50

V

CAN Normal Mode;

P_10.3.11

P_10.3.43

P_10.3.12

V_TXD= V_CC1

;

no load

CANH/CANL Recessive

Output Voltage

(CAN Wake Capable Mode)

V_{CANL/H_LP}-0.1

CAN Wake Capable

Mode; V_TXD= V_CC1

;

no load

CANH, CANL Recessive

Output Voltage Difference

V_diff= V_CANH- V_CANL

V_{diff_r_N}

V_{diff_r_W}

V_CANL

-500

-200

0.5

mV CAN Normal Mode

V_TXD= V_CC1

;

no load

(CAN Normal Mode)

CANH, CANL Recessive

Output Voltage Difference

V_diff= V_CANH- V_CANL

–

200

2.25

4.5

mV CAN Wake Capable

Mode;

P_10.3.41

P_10.3.13

P_10.3.14

P_10.3.16

V

_TXD= V_CC1

no load

CAN Normal Mode;

_TXD= 0 V;

V_{CAN = 5 V}

;

(CAN Wake Capable Mode)

CANL Dominant Output

Voltage

–

V

;

50Ω ≤ R_L≤ 65Ω

CANH Dominant Output

Voltage

V_CANH

2.75

1.5

–

CAN Normal Mode;

V

_TXD= 0 V;

_CAN= 5 V;

50Ω ≤ R_L≤ 65Ω

CANH, CANL Dominant

Output Voltage Difference

V_diff= V_CANH- V_CANL

V_{diff_d_N}

2.0

2.5

CAN Normal Mode;

V_TXD= 0 V;

V_CAN= 5 V;

50Ω ≤ R_L≤ 65Ω

Datasheet

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Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

High Speed CAN Transceiver

Table 24

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Uni Note or

Number

t

Test Condition

¹⁾CAN Normal Mode;

_TXD= 0 V;

Min.

Max.

CANH, CANL Dominant

Output Voltage Difference

V_diff= V_CANH- V_CANL

V_{diff_d_N}

1.5

5.0

V

P_10.3.55

V

V_CAN= 5 V;

R_L= 2240Ω

CANH, CANL Dominant

Output Voltage Difference

V_diff= V_CANH- V_CANL

V_{diff_d_N}

1.4

–

3.3

70

V

¹⁾CAN Normal Mode;

P_10.3.56

P_10.3.57

P_10.3.58

P_10.3.42

V_TXD= 0 V;

V_CAN= 5 V;

45Ω ≤ R_L≤ 70Ω

CANH, CANL output voltage V_{diff_slope_rd}

difference slope, recessive

to dominant

V/us ¹⁾30% to 70% of

measured differential

bus voltage,

C_L= 100 pF, R_L= 60 Ω

CANH, CANL output voltage V_{diff_slope_dr}

difference slope, dominant

to recessive

–

70

V/us ¹⁾70% to 30% of

measured differential

bus voltage,

C_L= 100 pF, R_L= 60 Ω

Driver Symmetry

V_SYM= V_CANH+ V_CANL

V_SYM

4.5

5.5

V

³⁾CAN Normal Mode;

_TXD= 0 V / 5 V;

V_CAN= 5 V;

_SPLIT= 4.7nF;

R_L= 60Ω;

V

C

CANH Short Circuit Current I_CANHsc

CANL Short Circuit Current I_CANLsc

-115

50

–

-80

80

5

-50

115

7.5

mA CAN Normal Mode;

P_10.3.17

P_10.3.18

P_10.3.19

V_CANHshort= -3 V

mA CAN Normal Mode

V_CANLshort= 18 V

Leakage Current

I_CANH,lk

I_CANL,lk

µA V_S= V_CAN= 0V;

(unpowered device)

0V < V_CANH,L≤ 5V;

4)

R

= 0 / 47 kΩ

test

Receiver Output RXD

HIGH level Output Voltage

V_RXD,H

V_RXD,L

0.8 ×

V_CC1

–

V

CAN Normal Mode

_RXD(CAN)= -2 mA;

CAN Normal Mode

I_RXD(CAN)= 2 mA;

P_10.3.21

P_10.3.22

I

LOW Level Output Voltage

–

0.2 ×

V_CC1

Transmission Input TXD

HIGH Level Input Voltage

Threshold

V_TXD,H

–

0.7 ×

V_CC1

V

CAN Normal Mode

recessive state

P_10.3.23

Datasheet

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Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

High Speed CAN Transceiver

Table 24

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Uni Note or

Number

t

Test Condition

Min.

Max.

LOW Level Input Voltage

Threshold

V_TXD,L

0.3 ×

V_CC1

–

V

CAN Normal Mode

dominant state

1)

P_10.3.24

P_10.3.25

TXD Input Hysteresis

V_TXD,hys

0.08 × 0.12 × 0.5 ×

V

V_CC1

20

8

V_CC1

TXD Pull-up Resistance

R_TXD

40

80

kΩ

–

P_10.3.26

P_10.3.27

CAN Transceiver Enabling

Time

t_CAN,EN

13

18

µs ⁵⁾CSN = HIGH to first

valid transmitted TXD

dominant

Dynamic CAN-Transceiver Characteristics

Min. Dominant Time for Bus t_Wake1

0.50

–

1.8

µs -12V ≤ V_CM(CAN) ≤ +12 V; P_10.3.28

Wake-up

CAN Wake capable

Mode

Wake-up Time-out,

Recessive Bus

t_Wake2

0.8

–

10

ms ⁵⁾CAN Wake capable

Mode

µs ⁵⁾⁶⁾⁷⁾Wake-up reaction P_10.3.44

time after a valid WUP

P_10.3.29

WUP Wake-up

Reaction Time

t_{WU_WUP}

100

on CAN bus;

Loop delay

t_LOOP,f

–

150

255

ns ³⁾CAN Normal Mode

C_L= 100 pF;

P_10.3.30

(recessive to dominant)

R_L= 60 Ω;

V_CAN= 5 V;

C_RXD= 15 pF

Loop delay

t_LOOP,r

ns ³⁾CAN Normal Mode

C_L= 100 pF;

P_10.3.31

(dominant to recessive)

R_L= 60 Ω;

V_CAN= 5 V;

C_RXD= 15 pF

Propagation Delay

TXD LOW to bus dominant

t_d(L),T

t_d(H),T

t_d(L),R

–

50

–

ns CAN Normal Mode

C_L= 100pF;

P_10.3.32

P_10.3.33

P_10.3.34

50Ω ≤ R_L≤ 65Ω;

V_CAN= 5 V;

Propagation Delay

TXD HIGH to bus recessive

50

ns CAN Normal Mode

C_L= 100 pF;

50Ω ≤ R_L≤ 65Ω;

V_CAN= 5 V;

Propagation Delay

bus dominant to RXD LOW

100

ns CAN Normal Mode

C_L= 100pF;

50Ω ≤ R_L≤ 60Ω;

V_CAN= 5 V;

C_RXD= 15 pF

Datasheet

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Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

High Speed CAN Transceiver

Table 24

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

100

Uni Note or

Number

t

Test Condition

Min.

Max.

Propagation Delay

bus recessive to RXD HIGH

t_d(H),R

–

ns CAN Normal Mode

C_L= 100pF;

P_10.3.35

50Ω ≤ R_L≤ 60Ω;

V_CAN= 5 V;

C_RXD= 15 pF

Received Recessive Bit

Width

(CAN FD up to 2Mbps)

t_bit(RXD)

400

435

-65

–

550

530

40

ns CAN Normal Mode

C_L= 100pF;

P_10.3.46

P_10.3.47

P_10.3.48

P_10.3.52

R_L= 60 Ω;

V_CAN= 5 V;

C_RXD= 15 pF;

t_bit(TXD)= 500ns;

Timing definition

according to Figure 36

TransmittedRecessive Bit

Width

(CAN FD up to 2Mbps)

t_bit(BUS)

ns CAN Normal Mode

C_L= 100pF;

R_L= 60 Ω;

V_CAN= 5 V;

C_RXD= 15 pF;

t_bit(TXD)= 500ns;

Timing definition

according to Figure 36

Receiver Timing Symmetry ∆t_Rec

(CAN FD up to 2Mbps)

ns CAN Normal Mode

C_L= 100pF;

R_L= 60 Ω;

V_CAN= 5 V;

C_RXD= 15 pF;

t_bit(TXD)= 500ns;

Timing definition

according to Figure 36

Received Recessive Bit

Width

t_bit(RXD)

120

220

ns CAN Normal Mode;

C_L= 100pF;

(CAN FD up to 5 Mbps)

R_L= 60 Ω;

V

_CAN= 5 V;

C_RXD= 15 pF;

_bit(TXD)= 200 ns;

t

Parameter definition in

according to

Figure 36.

Datasheet

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Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

High Speed CAN Transceiver

Table 24

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; 4.75 V < V_CAN< 5.25 V; R_L= 60Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Uni Note or

Number

t

Test Condition

Min.

Max.

Transmitted Recessive Bit

Width

t_bit(BUS)

155

210

ns CAN Normal Mode;

C_L= 100pF;

P_10.3.53

(CAN FD up to 5 Mbps)

R_L= 60 Ω;

V_CAN= 5 V;

C_RXD= 15 pF;

t_bit(TXD)= 200 ns;

Parameter definition in

according to

Figure 36.

Receiver Timing Symmetry ∆t_Rec

(CAN FD up to 5 Mbps)

-45

–

15

ns CAN Normal Mode;

C_L= 100pF;

P_10.3.54

R_L= 60 Ω;

V

_CAN= 5 V;

C_RXD= 15 pF;

_bit(TXD)= 200 ns;

t

Parameter definition in

according to

Figure 36.

TXD Permanent Dominant t_{TxD_CAN_TO}1.6

Time-out

2

2.4

ms ⁵⁾CAN Normal Mode

P_10.3.36

P_10.3.37

BUS Permanent Dominant t_{BUS_CAN_TO}1.6

ms ⁵⁾CAN Normal Mode

Time-out

5)

Timeout for bus inactivity

Bus Bias reaction time

t_SILENCE

t_Bias

0.6

–

1.2

s

P_10.3.50

P_10.3.51

5)

200

µs

1) Not subject to production test, specified by design.

2) Not subject to production test, specified by design, S2P - Method; f = 10 MHz.

3) V_SYMshall be observed during dominant and recessive state and also during the transition dominant to recessive and

vice versa while TXD is simulated by a square signal (50% duty cycle) with a frequency of up to 1 MHz (2 MBit/s).

4) R_testbetween supply (VS / VCAN) and 0V (GND).

5) Not subject to production test, tolerance defined by internal oscillator tolerance.

6) Wake-up is signalized via INT pin activation in SBC Stop Mode and via VCC1 ramping up with wake from SBC Sleep

Mode.

7) Time starts with end of last dominant phase of WUP.

Datasheet

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Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

High Speed CAN Transceiver

V

TXDCAN

V_cc1

GND

t

V_DIFF

t_d(L),T

t_d(H),T

V _{diff, rd_N}

V_{diff, dr_N}

t _d(L),R

t _d(H),R

t_LOOP,f

t_LOOP,r

V_RXDCAN

V

cc1

0.8 x V_cc1

0.2 x V_cc1

GND

t

Figure 35 Timing Diagrams for Dynamic Characteristics

70%

TXDCAN

30%

t_{Loop_f}

5x t_Bit(TXD)

t_Bit(TXD)

V_diff=CANH-CANL

900mV

t_Bit(Bus)

500mV

70%

RXDCAN

30%

t_{Loop_r}

Figure 36 From ISO 11898-2: t_loop, t_bit(TXD), t_bit(Bus), t_bit(RXD)definitions

t_Bit(RXD)

Datasheet

95

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

11

LIN Transceiver

11.1

Block Description

VSHS

SPI Mode Control

VCC1

Driver

TxD Input

Temp.-

Protection

Current

R_TxD

R_BUS

Output

Stage

TXDLIN

Timeout

Limit

LIN

To SPI Diagnostic

Receiver

VCC1

Filter

VSHS

RXDLIN

Wake

Receiver

Figure 37 Block Diagram

11.1.1

LIN Specifications

The LIN network is standardized by international regulations.

The device is compliant to the physical layer standard LIN 2.2/ISO 17987-4 and SAE J2602-2. The SAE J2602-2

standard differs from the LIN 2.2/ISO 17987-4 standard mainly by the lower data rate (10.4 kbit/s).

Datasheet

96

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

11.2

Functional Description

The LIN Bus is a single wire, bi-directional bus, used for in-vehicle networks. The LIN transceivers implemented

inside the TLE9263-3BQXV33 are the interface between the micro controller and the physical LIN Bus. The

digital output data from the micro controller are driven to the LIN bus via the TXD input pin on the TLE9263-

3BQXV33. The transmit data stream on the TXD input is converted to a LIN bus signal with optimized slew rate

to minimize the EME level of the LIN network. The RXD output sends back the information from the LIN bus to

the micro controller. The receiver has an integrated filter network to suppress noise on the LIN Bus and to

increase the EMI (Electro Magnetic Immunity) level of the transceiver.

Two logical states are possible on the LIN Bus according to LIN 2.2/ISO 17987-4.

Every LIN network consists of a master node and one or more slave nodes. To configure the TLE9263-3BQXV33

for master node applications, a resistor in the range of 1 kΩ and a reverse diode must be connected between

the LIN bus and the power supply VSHS.

The different transceiver modes can be controlled via the SPI and LIN2 bits.

Figure 38 shows the possible transceiver mode transitions when changing the SBC mode.

SBC Mode

LIN Transceiver Mode

SBC Stop Mode

Receive Only Wake Capable Normal Mode

OFF

SBC Normal Mode

SBC Sleep Mode

SBC Restart Mode

SBC Fail-Safe Mode

Receive Only Wake Capable Normal Mode

Wake Capable

OFF

Woken¹

Wake Capable

¹after a wake event on LIN Bus

Behavior after SBC Restart Mode - not coming from SBC Sleep Mode due to a wake up of the respective transceive:r

If the transceivers had been configured to Normal Mode, or Receive Only Mode, then the mode will be changed to Wake

Capable. If it was Wake Capable, then it will remainWake Capable. If it had been OFF before SBC Restart Mode, then it

will remain OFF.

Behavior in SBC Development Mode:

LIN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF.

Figure 38 LIN Mode Control Diagram

11.2.1

LIN OFF Mode

The LIN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is

intended to completely stop LIN activities or when LIN communication is not needed. In LIN OFF Mode, a

wake-up event on the bus will be ignored.

Datasheet

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Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

11.2.2

LIN Normal Mode

The LIN Transceiver is enabled via SPI in SBC Normal Mode. LIN Normal Mode is designed for normal data

transmission/reception within the LIN network. The Mode is available in SBC Normal Mode and in SBC Stop

Mode.

Transmission

The signal from the microcontroller is applied to the TXDLIN input of the SBC. The bus driver switches the

LIN output stage to transfer this input signal to the LIN bus line.

Enabling Sequence

The LIN transceiver requires an enabling time t_LIN,ENbefore a message can be sent on the bus. This means that

the TXDLIN signal can only be pulled LOW after the enabling time. If this is not ensured, then the TXDLIN needs

to be set back to high (=recessive) until the enabling time is completed.

Only the next dominant bit will be transmitted on the bus.

Figure 39 shows different scenarios and explanations for LIN enabling.

V_TXDLIN

t

LIN

Mode

t _{LIN ,EN}

t _LIN,EN

LIN

NORMAL

LIN OFF

t

V

LIN_BUS

Recessive

Dominant

recessive TXD level

required before start of

transmission

Correct sequence ,

Bus is enabled after t_{LIN, EN}

t_LIN,_ENnot ensured , no

transmission on bus

t_LIN,not ensured ,

no transmission on bus

recessive TXD

level required

EN

Figure 39 LIN Transceiver Enabling Sequence

Reduced Electromagnetic Emission

To reduce electromagnetic emissions (EME), the bus driver controls LIN slopes symmetrically. The

configuration of the different slopes is described in Chapter 11.2.8.

Reception

Analog LIN bus signals are converted into digital signals at RXD via the differential input receiver.

11.2.3

LIN Receive Only Mode

In LIN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still possible. This mode

is accessible by an SPI command and is available in SBC Normal and SBC Stop Mode.

11.2.4

LIN Wake Capable Mode

This mode can be used in SBC Stop, Sleep, Restart and Normal Mode by programming via SPI and it is used to

monitor bus activities. It is automatically accessed in SBC Fail-Safe Mode. A wake up is detected, if a recessive

Datasheet

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Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

to dominant transition on the LIN bus is followed by a dominant level of longer than t_WK,Bus, followed by a

dominant to recessive transition. The dominant to recessive transition will cause a wake up of the LIN

transceiver. A wake-up results in a different behavior of the SBC, as described in below Table 25. As a

signalization to the microcontroller, the RXD_LIN pin is set LOW and will stay LOW until the LIN transceiver is

changed to any other mode. After a wake-up event the transceiver can be switched to LIN Normal Mode for

communication.

Rearming the transceiver for wake capability

After a BUS wake-up event, the transceiver is woken. However, the LIN1 and LIN2 transceiver mode bits will

still show wake capable (=‘01’) so that the RXD signal will be pulled low. There are two possibilities how the

LIN transceiver’s wake capable mode is enabled again after a wake event:

•

The LIN transceiver mode must be toggled, i.e. switched to LIN Normal Mode, LIN Receive Only Mode or LIN

Off, before switching to LIN Wake Capable Mode again.

•

Rearming is done automatically when the SBC is changed to SBC Stop, SBC Sleep, or SBC Fail-Safe Mode

to ensure wake-up capability.

Wake-Up in SBC Stop and SBC Normal Mode

In SBC Stop Mode, if a wake-up is detected, it is signaled by the INT output and in the WK_STAT_1 SPI register.

It is also signaled by RXDLIN put to LOW. The same applies for the SBC Normal Mode. The microcontroller

should set the device to SBC Normal Mode, there is no automatic transition to Normal Mode.

For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a Bus wake

event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to HIGH before).

Wake-Up in SBC Sleep Mode

Wake-up is possible via a LIN message (filter time t > t_WK,Bus). The wake-up automatically transfers the SBC into

the SBC Restart Mode and from there to Normal Mode the corresponding RXD pin in set to LOW. The

microcontroller is able to detect the low signal on RXD and to read the wake source out of the WK_STAT_1

register via SPI. No interrupt is generated when coming out of Sleep Mode. The microcontroller can now

switch the LIN transceiver into LIN Normal Mode via SPI to start communication.

Table 25

Action due to a LIN BUS Wake-up

SBC Mode after Wake

Normal Mode

SBC Mode

Normal Mode

Stop Mode

Sleep Mode

Restart Mode

VCC1

INT

RXD

LOW

ON

LOW

HIGH

Stop Mode

ON

Restart Mode

Ramping Up

ON

Restart Mode

Fail-Safe Mode

Restart Mode

Ramping up

11.2.5

TXD Time-out Feature

If the TXD signal is dominant for the time t >t_{TxD_LIN _TO}, the TXD time-out function deactivates the LIN

transmitter output stage temporarily. The transceiver remains in recessive state. The TXD time-out functions

prevents the LIN bus from being blocked by a permanent LOW signal on the TXD pin, caused by a failure. The

failure is stored in the SPI flag LIN1_FAIL and LIN2_FAIL. The LIN transmitter stage is activated again after the

dominant time-out condition is removed. The transceiver configuration stays unchanged.

Datasheet

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Rev. 1.2

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

Recovery of the

microcontroller error

TxD Time-Out due to

microcontroller error

Release after TxD

Time-out

Normal Communication

t_timeout

t_torec

Normal Communication

TxD

LIN

t

Figure 40 TXD Time-Out Function

11.2.6

Bus Dominant Clamping

If the LIN bus signal is dominant for a time t > t_{BUS_LIN_TO}in LIN Normal and Receive Only Mode, then a bus

dominant clamping is detected and the SPI bit LIN1_FAIL and LIN2_FAIL is set. The transceiver configuration

stays unchanged.

11.2.7

Undervoltage Detection

In case the supply voltage is dropping below the VSHS undervoltage detection threshold (VSHS < V_SHS,UVD), the

TLE9263-3BQXV33 disables the output and receiver stages. If the power supply reaches a higher level than the

undervoltage detection threshold (VSHS > V_SHS,UVD), the TLE9263-3BQXV33 continues with normal operation.

The transceiver configuration stays unchanged.

11.2.8

Slope Selection

The LIN transceiver offers a LIN Low-Slope Mode for 10.4 kBaud communication and a LIN Normal-Slope Mode

for 20 kBaud communication. The only difference is the behavior of the transmitter. In LIN Low-Slope Mode,

the

transmitter uses a lower slew rate to further reduce the EME compared to Normal-Slope Mode. This complies

with SAE J2602 requirements.By default, the device works in LIN Normal-Slope Mode. The selection of LIN

Low-Slope Mode is done by an SPI bit LIN_LSM and will become effective as soon as CSN goes ‘HIGH’. Only the

LIN Slope is changed. The selection is accessible in SBC Normal Mode only.

11.2.9

Flash Programming via LIN

The device allows LIN flash programming, e.g. of another LIN Slave with a communication of up to 115 kBaud.

This feature is enabled by de-activating the slope control mechanism via a SPI command (bit LIN_FLASH) and

will become effective as soon as CSN goes ‘HIGH’. The SPI bit can be set in SBC Normal Mode.

Datasheet

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

Note:

It is recommended to perform flash programming only at nominal supply voltage VSHS = 13.5V to

ensure stable data communication.

Datasheet

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

11.3

Electrical Characteristics

Table 26

Electrical Characteristics

V_SHS= 5.5 V to 18 V, T_j= -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current

flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Receiver Output (RXD pin)

HIGH Level Output Voltage

V_RXD,H

V_RXD,L

0.8 ×

V_CC1

–

V

I_RXD= -1.6 mA;

_Bus= V_SHS

I_RXD= 1.6 mA

_Bus= 0 V

P_11.3.1

P_11.3.2

V

LOW Level Output Voltage

–

0.2 ×

V_CC1

V

Transmission Input (TXD pin)

HIGH Level Input Voltage

V_TXD,H

0.7 ×

V_CC1

–

V

Recessive State

P_11.3.3

P_11.3.4

P_11.3.5

P_11.3.6

1)

TXD Input Hysteresis

V_TXD,hys0.08 × 0.12 × 0.5 ×

V_CC1

LOW Level Input Voltage

V_TXD,L

R_TXD

–

0.3 ×

V_CC1

Dominant State

TXD Pull-up Resistance

20

40

80

kΩ V_TXD= 0 V

LIN Bus Receiver (LIN Pin)

Receiver Threshold Voltage, V_Bus,rd

Recessive to Dominant Edge

0.4 × 0.45 × –

V

P_11.3.7

P_11.3.8

V_SHS

Receiver Dominant State

V_Bus,dom

–

0.4 ×

V

LIN 2.2/ISO 17987-4

V_SHS

Param 17

Receiver Threshold Voltage, V_Bus,dr

Dominant to Recessive Edge

–

0.55 × 0.60 × V

P_11.3.9

P_11.3.10

P_11.3.11

V_SHS

Receiver Recessive State

Receiver Center Voltage

V_Bus,rec

V_Bus,c

0.6 ×

V_SHS

–

V

LIN 2.2/ISO 17987-4

Param 18

0.475 0.5 × 0.525

× V_SHSV_SHS× V_SHS

LIN 2.2/ISO 17987-4

Param 19

6 V < V_SHS< 18 V

Receiver Hysteresis

V_Bus,hys

0.07 × 0.1 × 0.175

V_SHSV_SHS× V_SHS

V

V_bus,hys= V_bus,dr- V_bus,rd

LIN 2.2/ISO 17987-4

Param 20

P_11.3.12

Wake-up Threshold Voltage V_Bus,wk

0.40 × 0.5 × 0.6 ×

V

–

P_11.3.13

P_11.3.14

V_SHS

2)

Dominant Time for Bus

Wake-up

t_WK,Bus

30

–

150

µs

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

Table 26

Electrical Characteristics (cont’d)

V_SHS= 5.5 V to 18 V, T_j= -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current

flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

LIN Bus Transmitter (LIN Pin)

1)

Bus Serial Diode Voltage

Drop

V_serdiode0.4

0.7

1.0

V

= VCC1;

P_11.3.15

TXD

LIN 2.2/ISO 17987-4

Param 21

Bus Recessive Output

Voltage

V_BUS,ro

0.8 ×

V_SHS

–

V_SHS

V

V_TXD= HIGH Level

P_11.3.16

P_11.3.17

Bus Short Circuit Current

I_BUS,sc

40

100

150

mA V_BUS= 18 V;

LIN 2.2/ISO 17987-4

Param 12

Leakage Current

Loss of Ground

I_BUS,lk1

-1000 -450 20

µA V_SHS= 12 V = GND;

0 V < V_BUS< 18 V;

LIN 2.2/ISO 17987-4

Param 15

P_11.3.18

P_11.3.19

P_11.3.20

P_11.3.21

P_11.3.22

Leakage Current

Loss of Battery

I_BUS,lk2

I_BUS,lk3

I_BUS,lk4

–

20

–

µA V_SHS= 0 V;

V

_BUS= 18 V;

LIN 2.2/ISO 17987-4

Param 16

Leakage Current

Driver Off

-1

–

mA V_SHS= 18 V;

_BUS= 0 V;

V

LIN 2.2/ISO 17987-4

Param 13

Leakage Current

Driver Off

–

20

47

µA V_SHS= 8 V;

V_BUS= 18 V;

LIN 2.2/ISO 17987-4

Param 14

Bus Pull-up Resistance

R_BUS

20

30

kΩ Normal Mode

LIN 2.2/ISO 17987-4

Param 26

1)

LIN Input Capacitance

C_BUS

20

1

25

6

pF

P_11.3.23

P_11.3.24

Receiver propagation delay t_d(L),R

bus dominant to RXD LOW

–

µs V_CC= 3.3 V;

C_RXD= 20 pF;

LIN 2.2/ISO 17987-4

Param 31

Receiver propagation delay t_d(H),R

bus recessive to RXD HIGH

–

1

–

6

2

µs V_CC= 3.3 V;

P_11.3.25

P_11.3.26

C_RXD= 20 pF;

LIN 2.2/ISO 17987-4

Param 31

Receiver delay symmetry

t_sym,R

-2

µs t_sym,R= t_d(L),R- t_d(H),R;

LIN 2.2/ISO 17987-4

Param 32

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

Table 26

Electrical Characteristics (cont’d)

V_SHS= 5.5 V to 18 V, T_j= -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current

flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

LIN Transceiver Enabling

Time

t_LIN,EN

8

13

20

10

–

18

24

14

–

µs ²⁾CSN = HIGH to first valid P_11.3.27

transmitted TXD dominant

1)2)

Bus Dominant Time Out

t_{BUS_LIN}16

ms

µs

P_11.3.28

P_11.3.29

P_11.3.30

_TO

1)2)

TXD Dominant Time Out

t_{TxD_LIN}

16

V

= 0 V

TXD

_TO

1)2)

TXD Dominant Time Out

Recovery Time

t_torec

5

Duty Cycle D1

D1

D2

D3

D4

0.396

³⁾TH_Rec(max) = 0.744 × V_SHS; P_11.3.31

TH_Dom(max) = 0.581 × V_SHS

_SHS= 7.0 … 18 V;

(For worst case at 20 kbit/s)

LIN 2.2/ISO 17987-4 Normal

Slope

;

V

t_bit= 50 µs;

D1 = t_{bus_rec(min)}/2 t_bit

LIN 2.2/ISO 17987-4

Param 27

;

Duty Cycle D2

–

0.581

³⁾TH_Rec(min.) = 0.422 × V_SHS; P_11.3.32

TH_Dom(min.) = 0.284 × V_SHS

_SHS= 7.6 … 18 V;

_bit= 50 µs;

(for worst case at 20 kbit/s)

LIN 2.2/ISO 17987-4 Normal

Slope

;

V

t

D2 = t_{bus_rec(max)}/2 t_bit

LIN 2.2/ISO 17987-4

Param 28

;

Duty Cycle D3

(for worst case at 10.4 kbit/s)

SAE J2602 Low Slope

0.417

–

³⁾TH_Rec(max) = 0.778 × V_SHSP_11.3.33

TH_Dom(max) = 0.616 × V_SHS

;

V_SHS= 7.0 … 18 V;

t

_bit= 96 µs;

D3 = t_{bus_rec(min)}/2 t_bit

LIN 2.2/ISO 17987-4

Param 29

;

Duty Cycle D4

–

0.590

³⁾TH_Rec(min.) = 0.389 × V_SHS; P_11.3.34

(for worst case at 10.4 kbit/s)

SAE J2602 Low Slope

TH_Dom(min.) = 0.251 × V_SHS

V_SHS= 7.6 … 18 V;

;

t

_bit= 96 µs;

D4 = t_{bus_rec(max)}/2 t_bit

LIN 2.2/ISO 17987-4

Param 30

;

1) Not subject to production test, specified by design.

2) Not subject to production test, tolerance defined by internal oscillator tolerance

3) Bus load conditions concerning LIN 2.2/ISO 17987-4 C_LIN, R_LIN= 1 nF, 1 kΩ / 6.8 nF, 660 Ω/ 10 nF, 500 Ω

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

VSHS

TxD

RxD

100 nF

R_LIN

C_RxD

WK

LIN

GND

C_LIN

Figure 41 Simplified Test Circuit for Dynamic Characteristics

Datasheet

105

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OPTIREG™ SBC TLE9263-3BQXV33

LIN Transceiver

t_Bit

TxD

(input to

transmitting node )

t_{Bus _dom (max )}

t_{Bus_rec (min)}

Thresholds of

receiving node 1

TH_{Rec (max)}

TH_{Dom (max)}

V_SUP

(Transceiver supply

of transmitting

node )

Thresholds of

receiving node 2

TH_Rec(min)

TH_Dom(min)

t_{Bus _dom (min)}

t_{Bus_rec(max )}

RxD

(output of receiving

node 1)

t_{d(L),R (1)}

t_d(H),R(1)

RxD

(output of receiving

node 2)

t_(L),R(2)

t_d(H),r(2)

Duty Cycle1 = t_{BUS_rec(min)}/ (2 x t

)

BIT

Duty Cycle2 = t_{BUS_rec(max )}/ (2 x t_BIT

)

Figure 42 Timing Diagram for Dynamic Characteristics

Datasheet

106

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OPTIREG™ SBC TLE9263-3BQXV33

Wake and Voltage Monitoring Inputs

12

Wake and Voltage Monitoring Inputs

12.1

Block Description

Internal Supply

I_{PU_WK}

WKx

+

-

t_WK

I_{PD_WK}

V_Ref

Logic

MONx_Input_Circuit_ext.vsd

Figure 43 Wake Input Block Diagram

Features

•

Three High-Voltage inputs with a 3V (typ.) threshold voltage

Alternate Measurement function for high-voltage sensing via WK1 and WK2

Wake-up capability for power saving modes

Edge sensitive wake feature LOW to HIGH and HIGH to LOW

Pull-up and Pull-down current sources, configurable via SPI

Selectable configuration for static sense or cyclic sense working with TIMER1, TIMER2

In SBC Normal and SBC Stop Mode the level of the WK pin can be read via SPI even if the respective WK is

not enabled as a wake source.

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OPTIREG™ SBC TLE9263-3BQXV33

Wake and Voltage Monitoring Inputs

12.2

Functional Description

The wake input pins are edge-sensitive inputs with a switching threshold of typically 3V. This means that both

transitions, HIGH to LOW and LOW to HIGH, result in a signalization by the SBC. The signalization occurs either

in triggering the interrupt in SBC Normal Mode and SBC Stop Mode or by a wake up of the device in SBC Sleep

and SBC Fail-Safe Mode.

Two different wake detection modes can be selected via SPI:

•

Static sense: WK inputs are always active

Cyclic sense: WK inputs are only active for a certain time period (see Chapter 5.2.1)

Two different filter times of 16µs or 64µs can be selected to avoid a parasitic wake-up due to transients or EMC

disturbances in static sense configuration.

The filter time (t_FWK1, t_FWK2) is triggered by a level change crossing the switching threshold and a wake signal is

recognized if the input level will not cross again the threshold during the selected filter time.

Figure 44 shows a typical wake-up timing and parasitic filter.

V_WK

V_WK,th

t

V_INT

t_WK,f

t_INT

No Wake Event

Wake Event

Figure 44 Wake-up Filter Timing for Static Sense

The wake-up capability for each WK pin can be enabled or disabled via SPI command in the WK_CTRL_2

register.

The wake source for a wake via a WKx pin can always be read in the register WK_STAT_1 at the bits WK1_WU,

WK2_WU, and WK3_WU.

The actual voltage level of the WK pin (LOW or HIGH) can always be read in SBC Normal and SBC Stop Mode in

the register WK_LVL_STAT. During Cyclic Sense, the register show the sampled levels of the respective WK pin.

If FO2...3 are configured as WK inputs in its alternative function (16µs static filter time), then the wake events

will be signalled in the register WK_STAT_2.

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OPTIREG™ SBC TLE9263-3BQXV33

Wake and Voltage Monitoring Inputs

12.2.1

Wake Input Configuration

To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure

integrated current sources via the SPI register WK_PUPD_CTRL. In addition, the wake detection modes

(including the filter time) can be configured via the SPI register WK_FLT_CTRL. An example illustration for the

automatic switching configuration is shown in Figure 45.

Table 27

Pull-Up / Pull-Down Resistor

WKx_PUPD_1 WKx_PUPD_0 Current Sources Note

0

no current

source

WKx input is floating if left open (default setting)

0

1

0

1

pull-down

pull-up

WKx input internally pulled to GND

WKx input internally pulled to internal 5V supply

Automatic

switching

If a high level is detected at the WKx input the pull-up

source is activated, if low level is detected the pull down

is activated.

Note:

If there is no pull-up or pull-down configured on the WK input, then the respective input should be

tied to GND or VS on board to avoid unintended floating of the pin and subsequent wake events.

I_{WKth_min}

I_{WKth_max}

I_WK

V_WKth

Figure 45 Illustration for Pull-Up / Down Current Sources with Automatic Switching Configuration

Table 28

Wake Detection Configuration and Filter Time

WKx_FLT_1 WKx_FLT_0 Filter Time

Description

0

1

0

1

0

Config A

Config B

Config C

static sense, 16µs filter time

static sense, 64µs filter time

Cyclic sense, Timer 1, 16µs filter time. Period, On-time

configurable in register TIMER1_CTRL

1

Config D

Cyclic sense, Timer 2, 16µs filter time. Period, On-time

configurable in register TIMER2_CTRL

Config A and B are intended for static sense with two different filter times.

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OPTIREG™ SBC TLE9263-3BQXV33

Wake and Voltage Monitoring Inputs

Config C or D are intended for cyclic sense configuration. With the filter settings, the respective timer needs to

be assigned to one or more HS output, which supplies an external circuit connected to the WKx pin, e.g. HS1

controlled by Timer 2 (HS1 = 010) and connected to WK3 via an switch circuitry - see also Chapter 5.2.

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OPTIREG™ SBC TLE9263-3BQXV33

Wake and Voltage Monitoring Inputs

12.2.2

Alternate Measurement Function with WK1 and WK2

12.2.2.1 Block Description

This function provides the possibility to measure a voltage, e.g. the unbuffered battery voltage, with the

protected WK1 HV-input. The measured voltage is routed out at WK2. It allows for example a voltage

compensation for LED lighting by changing the duty cycle of the High-Side outputs. A simple voltage divider

needs to be placed externally to provide the correct voltage level to the microcontroller A/D converter input.

The function is available in SBC Normal Mode and it is disabled in all other modes to allow a low-quiescent

current operation.The measurement function can be used instead of the WK1 and WK2 wake and level

signalling capability.

The benefits of the function is that the signal is measured by a HV-input pin and that there is no current flowing

through the resistor divider during low-power modes.

The functionality is shown in a simplified application diagram in Figure 65.

12.2.2.2 Functional Description

This measurement function is by default disabled. In this case, WK1 and WK2 have the regular wake and

voltage level signalization functionality. The switch S1 is open for this configuration (see Figure 65).

The measurement function can be enabled via the SPI bit WK_MEAS.

If WK_MEAS is set to ‘1’, then the measurement function is enabled and switch S1 is closed in SBC Normal

Mode. S1 is open in all other SBC modes. If this function the pull-up and down currents of WK1 and WK2 are

disabled, and the internal WK1 and WK2 signals are gated. In addition, the settings for WK1 and WK2 in the

registers WK_PUPD_CTRL, WK_FLT_CTRL and WK_CTRL_2 are ignored but changing these setting is not

prevented. The registers WK_STAT_1 and WK_LVL_STAT are not updated with respect to the inputs WK1 and

WK2.

However, if only WK1 or WK2 are set as wake sources and a SBC Sleep Mode command is set, then the SPI_FAIL

flag will be set and the SBC will be changed into SBC Restart Mode (see Chapter 5.1 also for wake capability

of WK1 and WK2).

Table 29

Differences between Normal WK Function and Measurement Function

Affected Settings/Modules WK_MEAS = 0

for WK1 and WK2 Inputs

WK_MEAS = 1

S1 configuration

‘open’

‘closed’ in SBC Normal Mode,

‘open’ in all other SBC Modes

Internal WK1 & WK2 signal

processing

Default wake and level signaling

‘WK1...2 inputs are gated internally,

function, WK_STAT_1, WK_STAT_2 WK_STAT_1, WK_STAT_2 are not

are updated accordingly updated

Wake-up via WK1 and WK2 possible if setting the bits is ignored and not

WK1_EN, WK2_EN

bits are set

prevented. If only WK1_EN, WK2_EN

are set while trying to go to SBC Sleep

Mode, then the SPI_FAIL flag will be

set and the SBC will be changed into

SBC Restart Mode.

WK_PUPD_CTRL

WK_FLT_CTRL

normal configuration is possible

no pull-up or pull-down enabled

setting the bits is ignored and not

prevented

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OPTIREG™ SBC TLE9263-3BQXV33

Wake and Voltage Monitoring Inputs

Note:

There is a diode in series to the switch S1 (not shown in the Figure 65), which will influence the

temperature behavior of the switch.

Electrical Characteristics

12.3

Table 30

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

WK1...WK3 Input Pin Characteristics

Max.

Wake-up/monitoring V_WKth

threshold voltage

2

3

4

V

without external

serial resistor R_S(with

R_S:

P_12.3.1

ΔV = I_PD/PU* R_S);

hysteresis included

Threshold hysteresis

V_WKNth,hys0.1

-

0.7

V

without external

serial resistor R_S(with

R_S:

P_12.3.2

ΔV = I_PD/PU* R_S);

WK pin Pull-up Current I_{PU_WK}

-20

3

-10

10

-3

µA

V_{WK_IN}= 4V

V_{WK_IN}= 2V

P_12.3.3

P_12.3.4

WK pin Pull-down

Current

I_{PD_WK}

20

Input leakage current I_LK,l

-2

–

2

µA

0 V < V_{WK_IN}< 40V

P_12.3.5

Drop Voltage across S1 V_Drop,S1

switch

1000

1100

mV ¹⁾Drop Voltage

between WK1 and

WK2 when enabled

for voltage

P_12.3.13

measurement; I_WK1

500µA;

=

T_j= 25°C

Refer to Figure 46

Timing

Wake-up filter time 1 t_FWK1

12

50

16

64

20

80

µs

²⁾SPI Setting

P_12.3.6

P_12.3.7

Wake-up filter time 2 t_FWK2

1) Not subject to production test; specified by design

2) Not subject to production test, tolerance defined by internal oscillator tolerance

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OPTIREG™ SBC TLE9263-3BQXV33

Wake and Voltage Monitoring Inputs

1100

1000

900

800

700

600

500

VS = 13.5V

500 μA

250 μA

100 μA

50 μA

ꢁ50

0

50

100

150

Tjꢀꢀꢀꢁ JUNCTIONꢀTEMPERATUREꢀ(°C)

Figure 46 Typical Drop Voltage Characteristics of S1 (between WK1 & WK2)

Datasheet

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OPTIREG™ SBC TLE9263-3BQXV33

Interrupt Function

13

Interrupt Function

13.1

Block and Functional Description

V_cc1

INT

Time

out

Interrupt logic

Figure 47 Interrupt Block Diagram

The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is

designed as a push/pull output stage as shown in Figure 47. An interrupt is triggered and the INT pin is pulled

low (active low) for t_INTin SBC Normal and Stop Mode and it is released again once t_INTis expired. The minimum

HIGH-time of INT between two consecutive interrupts is t_INTD. An interrupt does not cause a SBC mode change.

Two different interrupt classes could be selected via the SPI bit INT_ GLOBAL:

•

Class 1 (wake interrupt - INT_ GLOBAL=0): all wake-up events stored in the wake status SPI register

(WK_STAT_1 and WK_STAT_2) cause an interrupt (default setting). An interrupt is only triggered if the

respective function is also enabled as a wake source (including GPIOx if configured as a wake input). The

CAN time out signalization CANTO is also considered as a wake source. Therefore, the interrupt mask bit

CANTO_ MASK has higher priority than the bit INT_ GLOBAL, i.e. Integral is not taken into account for

CANTO.

•

Class 2 (global interrupt - INT_ GLOBAL=1): in addition to the wake-up events, all signalled failures stored

in the other status registers cause an interrupt (the register WK_LVL_STAT is not generating interrupts)

Note:

The errors which will cause SBC Restart or SBC Fail-Safe Mode (Vcc1_UV, WD_FAIL, VCC1_SC, TSD2,

FAILURE) are the exceptions of an INT generation on status bits. Also POR and DEV_STAT_x and will

not generate interrupts.

In addition to this behavior, an INT will be triggered when the SBC is sent to SBC Stop Mode and not all bits

were cleared in the WK_STAT_1 and WK_STAT_2register.

The SPI status registers are updated at every falling edge of the INT pulse. All interrupt events are stored in the

respective register (except the register WK_LVL_STAT) until the register is read and cleared via SPI command.

A second SPI read after reading out the respective status register is optional but recommended to verify that

the interrupt event is not present anymore. The interrupt behavior is shown in Figure 48 for class 1 interrupts.

The behavior for class 2 is identical.

The INT pin is also used during SBC Init Mode to select the hardware configuration of the device. See

Chapter 5.1.1 for further information.

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OPTIREG™ SBC TLE9263-3BQXV33

Interrupt Function

WK1

WK2

INT

t_INTD

t_INT

Update of

WK_STAT register

Update of

WK_STAT register

optional

no WK

SPI

Read & Clear

WK_STAT

contents

WK1

no WK

WK2

SPI

Read & Clear

No SPI Read & Clear

Command sent

WK_STAT

contents

WK1 + WK2

no WK

Interrupt_Behavior.vsd

Figure 48 Interrupt Signalization Behavior

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13.2

Electrical Characteristics

Table 31

Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Interrupt Output; Pin INT

1)

INT High Output Voltage V_INT,H

0.8 ×

V_CC1

–

V

I

= -1 mA;

P_13.2.1

P_13.2.2

INT

INT = OFF

1)

INT Low Output Voltage V_INT,L

–

0.2 ×

I

= 1 mA;

INT

V_CC1

INT = ON

2)

INT Pulse Width

t_INT

80

100

120

µs

P_13.2.3

P_13.2.4

INT Pulse Minimum Delay t_INTD

²⁾between

Time

consecutive pulses

Configuration Select; Pin INT

Config Pull-down

Resistance

R_CFG

180

5

250

10

350

14

kΩ

V_INT= 3.3 V

P_13.2.5

P_13.2.6

2)

Config Select Filter Time t_{CFG_F}

µs

1) Output Voltage Value also determines device configuration during SBC Init Mode

2) Not subject to production test, tolerance defined by internal oscillator tolerance.

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Fail Outputs

14

Fail Outputs

14.1

Block and Functional Description

5V_int

T _test

SBC Init

Mode

R_TEST

FO1/2

Failure logic

FO3/TEST

T_{FO_PL}

Failure Logic

Figure 49 Simplified Fail Output Block Diagram for FO1/2 and for FO3/TEST

The fail outputs consist of a failure logic block and three open-drain outputs (FO1, FO2, FO3) with active-low

signalization.

The fail outputs are activated due to following failure conditions:

•

Watchdog trigger failure (For config 3&4 only after the 2nd watchdog trigger failure and for config 1&2 after

1st watchdog trigger failure)

•

Thermal shutdown TSD2

VCC1 short to GND

VCC1 overvoltage (only if the SPI bit VCC1_OV_RST is set)

After 4 consecutive VCC1 undervoltage event (see Chapter 15.6 for details)

At the same time SBC Fail-Safe Mode is entered (exceptions are watchdog trigger failures depending on

selected

configurations - see Chapter 5.1.1).

The fail output activation is signalled in the SPI bit FAILURE of the register DEV_STAT.

For testing purposes only the Fail Outputs can also be activated via SPI by setting the bit FO_ON. This bit is

independent of the FO failure bits. In case that there is no failure condition, the FO outputs can also be turned

off again via SPI, i.e. no successful watchdog trigger is needed.

The entry of SBC Fail-Safe Mode due to a watchdog failure can be configured as described in Chapter 5.1.1.

In order to deactivate the fail outputs in SBC Normal Mode the failure conditions must not be present anymore

(e.g. TSD2, VCC1 short circuit, etc) and the bit FAILURE needs to be cleared via SPI command.

In case of a watchdog failure the correct procedure to deactivate the fail outputs is:

•

a successful WD trigger, i.e. WD_FAIL must be cleared

clearing of the FAILURE bit

WD_FAIL will also be cleared when going to SBC Sleep or SBC Fail-Safe Mode due to another failure (not a WD

failure) or if the watchdog is disabled in SBC Stop Mode

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Note:

The Fail output pin is triggered for any of the above described failures. No FAILURE is caused for the

1st watchdog failure if selected for Config2.

The three fail outputs are activated simultaneously with following output functionalities:

•

FO1: Static fail output

FO2: 1.25Hz, 50% (typ.) duty cycle, e.g. to generate an indicator signal

FO3: 100Hz PWM, 20% (typ.) duty cycle, e.g. to generate a dimmed rear light from a break light.

Note:

The duty cycle for FO3 can be configured via SPI option to 20%, 10%, 5% or 2.5%. Default value is

20%. See the register FO_DC for configuration.

14.1.1

General Purpose I/O Functionality of FO2 and FO3 as Alternate Function

In case that FO2 and FO3 are not used in the application, those pins can also be configured with an alternate

function as high-voltage (VSHS related) General Purpose I/O pins.

VSHS

Config &

Control Logic

FOx/

GPIOx

Figure 50 Simplified General Purpose I/O block diagram for FO2 and FO3/TEST

The pins are by default configured as FO pins. The configuration is done via the SPI register GPIO_CTRL. The

alternate function can be:

•

Wake Inputs: The detection threshold V_GPIOI,this similar as for the WK inputs. The wake-up detection

behavior is the same as for WKx pins. Wake events are stored and reported in WK_STAT_2.

Low-Side Switches: The switch is able to drive currents of up to 10mA (see also V_GPIOL,L1). It is self-protected

with regards to current limitation. No other diagnosis is implemented.

High-Side Switches: The switch is able to drive currents up to 10mA (see also V_GPIOH,H1). It is self-protected

with regards to current limitation. No other diagnosis is implemented.

If configured as GPIO then the respective level at the pin will be shown in WK_LVL_STAT in SBC Normal and

Stop Mode. This is also the case if configured as LS/HS and can serve as a feedback about the respective

state. GPIO2 is shared with the TEST level bit.

Table 32 describes the behavior of the FO/GPIO pins in their different configurations and SBC modes.

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Table 32

FOx

Configuration Mode

FOx (default)

OFF

Fail-Output and GPIO configuration behavior during the respective SBC Modes

SBC Normal

SBC Stop Mode SBC Sleep Mode SBC Restart

Mode

SBC Fail-Safe

Mode

fixed

active / fixed

OFF

active

OFF

configurable

Wake Input

Low-Side

High-Side

wake capable

fixed

wake capable

fixed

wake capable

OFF

fixed

OFF

Explanation of FO/GPIO states:

•

configurable: settings can be changed in this SBC mode

fixed: settings stay as configured in SBC Normal Mode

active: FOx is activated due to a failure leading to SBC Restart or Fail-Safe Mode.

Restart Behavior:

The behavior during SBC Restart and Fail-Safe Mode as well as the transition to SBC Normal Mode is as follows:

•

if configured as Wake Input: it will stay wake capable during SBC Restart Mode and OFF while in SBC Fail-

Safe Mode. It will resume wake capability when leaving SBC Restart Mode (SPI register is not modified)

if configured as Low-Side or High-Side: They will be disabled during SBC Restart and Fail-Safe Mode. After

leaving SBC Restart Mode the previously configured function will be resumed (SPI register is not modified)

if configured as FO and activated due to a failure: FO will stay activated during SBC Restart Mode and when

entering SBC Normal Mode (SPI register is not modified)

Notes

1. In order to avoid unintentional entry of SBC Development Mode care must be taken that the level of FO3/TEST

is HIGH during device power up and SBC Init Mode.

2. The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS

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14.2

Electrical Characteristics

Table 33

Electrical Characteristics

V_SHS= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.¹⁾

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Pin FO1

FO1 low output voltage

(active)

V_FO,L1

–

0

–

1.0

2

V

I_FO= 4mA

P_14.2.1

P_14.2.2

FO1 high output current I_FO,H

µA

V_FO= 28V

(inactive)

Pin FO2

3)

FO2 side indicator

frequency

f_FO2SI

1.00

45

1.25

50

1.50

55

Hz

%

P_14.2.3

P_14.2.4

FO2 side indicator duty

cycle

d_FO2SI

Pin FO3/TEST²⁾

Pull-up Resistance at pin R_TEST

FO3/TEST

2.5

5

10

kΩ

V_TEST=0V;

SBC Init Mode

3)

P_14.2.5

TEST Input Filter Time

t_TEST

50

80

64

80

µs

Hz

P_14.2.6

P_14.2.7

3)

FO3 pulsed

f_FO3PL

100

120

light frequency

FO3 pulsed

d_FO3PL

16

20

24

%

³⁾⁴⁾default setting

P_14.2.8

light duty cycle

Alternate FO2...3

Electrical Characteristics: GPIO

GPIO low-side output

voltage (active)

V_GPIOL,L1

–

1

V

I_GPIO= 10mA

P_14.2.9

5)

GPIO low-side output

voltage (active)

V_GPIOL,L2

–

5

mV

V

I

= 50µA

P_14.2.17

P_14.2.10

P_14.2.18

GPIO

GPIO high-side output

voltage (active)

V_GPIOH,H1VSHS-1

V_GPIOH,H2VSHS-5

–

I_GPO= -10mA

5)

GPIO high-side output

voltage (active)

–

mV

V

I

= -50µA

GPO

GPIO input threshold

voltage

V_GPIOI,th

1.5

2.5

400

3.5

700

⁶⁾hysteresis included P_14.2.11

5)

GPIO input threshold

hysteresis

V_GPIOI,hys100

mV

P_14.2.12

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Fail Outputs

Table 33

Electrical Characteristics (cont’d)

V_SHS= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.¹⁾

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

I_GPIOL,max10

Max.

GPIO low-side current

limitation

30

mA

V_GPIO= 28V

P_14.2.13

P_14.2.14

GPIO high-side current

limitation

I_GPIOH,max-45

–

-10

mA

V_GPIO= 0V

1) The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS

2) The external capacitance on this pin must be limited to less than 10nF to ensure proper detection of SBC

Development Mode and SBC User Mode operation.

3) Not subject to production test, tolerance defined by internal oscillator tolerance.

4) The duty cyclic is adjustable via the SPI bits FO_DC.

5) Not subject to production test, specified by design.

6) Applies also for TEST voltage input level

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Supervision Functions

15

Supervision Functions

15.1

Reset Function

VCC1

RO

Resetlogic

Incl. filter & delay

Figure 51 Reset Block Diagram

15.1.1

Reset Output Description

The reset output pin RO provides a reset information to the microcontroller, for example, in the event that the

output voltage has fallen below the undervoltage threshold V_RT1/2/3/4. In case of a reset event, the reset output

RO is pulled to low after the filter time t_RFand stays low as long as the reset event is present plus a reset delay

time t_RD1. When connecting the SBC to battery voltage, the reset signal remains LOW initially. When the output

voltage V_cc1has reached the reset default threshold V_RT1,r, the reset output RO is released to HIGH after the

reset delay time t_RD1. A reset can also occur due to a watchdog trigger failure. The reset threshold can be

adjusted via SPI, the default reset threshold is V_RT1,f. The RO pin has an integrated pull-up resistor. In case reset

is triggered, it will be pulled low for V_cc1≥ 1V and for VS ≥ V_POR,f(see also Chapter 15.3).

The timings for the RO triggering regarding VCC1 undervoltage and watchdog trigger is shown in Figure 52.

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Supervision Functions

VCC

V_RT1

t < t_RF

The reset threshold can be

configured via SPI in SBC

Normal Mode, default is V_RT1

undervoltage

t

t_CW

t_OW

t_RD1

t_CW

t_LW

t_RD1

t_LW

t_CW

t_OW

SPI

RO

SPI

Init

WD

Trigger

WD

Trigger

SPI

Init

t

t_RF

t_LW= long open window

t_CW= closed window

t_OW= open window

SBC Init

SBC Normal

SBC Restart

SBC Normal

Figure 52 Reset Timing Diagram

15.1.2

Soft Reset Description

In SBC Normal and SBC Stop Mode, it is also possible to trigger a device internal reset via a SPI command in

order to bring the SBC into a defined state in case of failures. In this case the microcontroller must send a SPI

command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid,

the SBC is set back to SBC INIT Mode and all SPI registers are set to their default values (see SPI Chapter 16.5

and Chapter 16.6).

Two different soft reset configurations are possible via the SPI bit SOFT_ RESET_RO:

•

The reset output (RO) is triggered when the soft reset is executed (default setting, the same reset delay

time t_RD1applies)

•

The reset output (RO) is not triggered when the soft reset is executed

Note:

The device must be in SBC Normal Mode or SBC Stop Mode when sending this command.

Otherwise, the command will be ignored.

15.2

Watchdog Function

The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the

microcontroller stops serving the watchdog due to a lock up in the software.

Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN:

•

Time-Out Watchdog (default value)

Window Watchdog

The respective watchdog functions can be selected and programmed in SBC Normal Mode. The configuration

stays unchanged in SBC Stop Mode.

Please refer to Table 34 to match the SBC Modes with the respective watchdog modes.

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Table 34

Watchdog Functionality by SBC Modes

Watchdog Mode

SBC Mode

INIT Mode

Remarks

Starts with Long Open

Window

Watchdog starts with Long Open Window after RO is

released

Normal Mode

WD Programmable

Window Watchdog, Time-Out watchdog or switched

OFF for SBC Stop Mode

Stop Mode

Sleep Mode

Watchdog is fixed or OFF

OFF

SBC will start with Long Open Window when

entering SBC Normal Mode.

Restart Mode

OFF

SBC will start with Long Open Window when

entering SBC Normal Mode.

The watchdog timing is programmed via SPI command. As soon as the watchdog is programmed, the timer

starts with the new setting and the watchdog must be served. The watchdog is triggered by sending a valid

SPI-write command to the watchdog configuration register. The trigger SPI command is executed when the

Chip Select input (CSN) becomes HIGH.

When coming from SBC Init, SBC Restart Mode or in certain cases from SBC Stop Mode, the watchdog timer is

always started with a long open window. The long open window (t_LW= 200ms) allows the microcontroller to

run its initialization sequences and then to trigger the watchdog via SPI.

The watchdog timer period can be selected via the watchdog timing bit field (WD_TIMER) and is in the range

of 10 ms to 1000 ms. This setting is valid for both watchdog types.

The following watchdog timer periods are available:

•

WD Setting 1: 10ms

WD Setting 2: 20ms

WD Setting 3: 50ms

WD Setting 4: 100ms

WD Setting 5: 200ms

WD Setting 6: 500ms

WD Setting 7: 1000ms

In case of a watchdog reset, SBC Restart or SBC Fail-Safe Mode is entered according to the configuration and

the SPI bits WD_FAIL are set. Once the RO goes HIGH again the watchdog immediately starts with a long open

window the SBC enters automatically SBC Normal Mode.

In SBC Development Mode the watchdog is OFF and therefore no reset and interrupt are generated due to a

watchdog failure.

Depending on the configuration, the WD_FAIL bits will be set after a watchdog trigger failure as follows:

•

In case an incorrect WD trigger is received (triggering in the closed watchdog window or when the

watchdog counter expires without a valid trigger) then the WD_FAIL bits will be increased (showing the

number of incorrect WD triggers)

•

For config 2: the bits can have the maximum value of ‘01’

For config 1, 3 and 4: the bits can have the maximum value of ‘10’

The WD_FAIL bits are cleared automatically when following conditions apply:

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•

After a successful watchdog trigger

When the watchdog is OFF: in SBC Stop Mode after successfully disabling it, in SBC Sleep Mode, or in SBC

Fail-Safe Mode (except for a watchdog failure)

15.2.1

Time-Out Watchdog

The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog

trigger can be done at any time within the configured watchdog timer period.

A correct watchdog service immediately results in starting a new watchdog timer period. Taking the

tolerances of the internal oscillator into account leads to the safe trigger area as defined in Figure 53.

If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RO low and

the SBC switches to SBC Restart or SBC Fail-Safe Mode.

Typical timout watchdog trigger period

t

_WDx 1.50

open window

uncertainty

Watchdog Timer Period (WD_TIMER)

t_WDx 1.20

t_WDx 1.80

t / [t_{WD_TIMER}

]

safe trigger area

Wd1_TimeOut_per.vsd

Figure 53 Time-out Watchdog Definition

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Supervision Functions

15.2.2

Window Watchdog

Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer

period is divided between an closed and an open window. The watchdog must be triggered within the open

window.

A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an

open window.

The watchdog timer period is at the same time the typical trigger time and defines the middle of the open

window. Taking the oscillator tolerances into account leads to a safe trigger area of:

t_WDx 0.72 < safe trigger area < t_WDx 1.20.

The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking

the tolerances of the internal oscillator into account leads to the timings as defined in Figure 54.

A correct watchdog service immediately results in starting the next closed window.

Should the trigger signal meet the closed window or should the watchdog timer period elapse, then a

watchdog reset is created by setting the reset output RO low and the SBC switches to SBC Restart or SBC Fail-

Safe Mode.

t_WDx 0.6

t_WDx 0.9

Typ. closed window

Typ. open window

t_WDx 0.48

t_WDx 0.72

t_WDx 1.0

t_WDx 1.20

t_WDx 1.80

closed window

uncertainty

open window

uncertainty

Watchdog Timer Period (WD_TIMER)

t / [t_{WD_TIMER}

]

safe trigger area

Figure 54 Window Watchdog Definition

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Supervision Functions

15.2.3

Watchdog Setting Check Sum

A check sum bit is part of the SPI commend to trigger the watchdog and to set the watchdog setting.

The sum of the 8 data bits in the register WWD_CTRL needs to have even parity (see Equation (15.1)). This is

realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is

ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set.

The checksum is calculated by taking all 8 data bits into account. The written value of the reserved bit 3 of the

WWD_CTRL register is considered (even if read as ‘0’ in the SPI output) for checksum calculation, i.e. if a 1 is

written on the reserved bit position, then a 1 will be used in the checksum calculation.

(15.1)

CHKSUM = Bit15 ⊕ … ⊕ Bit8

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15.2.4

Watchdog during SBC Stop Mode

The watchdog can be disabled for SBC Stop Mode in SBC Normal Mode. For safety reasons, there is a special

sequence to be followed in order to disable the watchdog as described in Figure 55. Two different SPI bits

(WD_STM_ EN_0, WD_STM_ EN_1) in the registers WK_CTRL_1 and WD_CTRL need to be set.

Correct WD disabling

Sequence Errors

sequence

•

Missing to set bit

WD_STM_EN_0 with the

next watchdog trigger after

having set WD_STM_EN_1

Set bit

WD_STM_EN_1 = 1

with next WD Trigger

•

Staying in Normal Mode

instead of going to Stop

Mode with the next trigger

Set bit

WD_STM_EN_0 = 1

Before subsequent WD Trigger

Will enable the WD:

Change to

SBC Stop Mode

•

Switching back to SBC

Normal Mode

•

Triggering the watchdog

WD is switched off

Figure 55 Watchdog disabling sequence in SBC Stop Mode

If a sequence error occurs, then the bit WD_STM_ EN_1 will be cleared and the sequence has to be started

again.

The watchdog can be enabled by triggering the watchdog in SBC Stop Mode or by switching back to SBC

Normal Mode via SPI command. In both cases the watchdog will start with a long open window and the bits

WD_STM_EN_1 and WD_STM_ EN_0 are cleared. After the long open window the watchdog has to be served

as configured in the WD_CTRL register.

Note:

The bit WD_STM_ EN_0 will be cleared automatically when the sequence is started and it was 1

before.

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15.2.5

Watchdog Start in SBC Stop Mode due to Bus Wake

In SBC Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the

watchdog with any BUS wake (CAN or LIN) during SBC Stop Mode. The feature is enabled by setting the bit

WD_EN_ WK_BUS = 1

(= default value after POR). The bit can only be changed in SBC Normal Mode and needs to be programmed

before starting the watchdog disable sequence.

A wake on CAN and LINx will generate an interrupt and the RXD pin for LINx or CAN is pulled to low. By these

signals the microcontroller is informed that the watchdog is startedwith a long open window. After the long

open window the watchdog has to be served as configured in the WD_CTRL register.

To disable the watchdog again, the SBC needs to be switched to Normal Mode and the sequence needs to be

sent again.

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15.3

VS Power On Reset

At power up of the device, the VS Power on Reset is detected when VS > V_POR,rand the SPI bit POR is set to

indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be

kept LOW and will only be released once VCC1 has crossed V_RT1,rand after t_RD1has elapsed.

In case VS < V_POR,f, an device internal reset will be generated and the SBC is switched OFF and will restart in

INIT mode at the next VS rising. This is shown in Figure 56.

VS

V_POR,r

V_POR,f

t

VCC1

V_RT1,r

The reset threshold can be

configured via SPI in SBC

V_RTx,f

Normal Mode, default is V_RT1

RO

SBC Restart Mode is

entered whenever the

Reset is triggered

t

t_RD1

SBC Mode

Re-

start

SBC OFF

SBC INIT MODE

Any SBC MODE

SBC OFF

t

SPI

Command

Figure 56 Ramp up / down example of Supply Voltage

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15.4

Undervoltage VS and VSHS

If the supply voltage VS reaches the undervoltage threshold V_S,UVthen the SBC does the following measures:

•

SPI bit VS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present

anymore,

•

VCC3 is disabled (see Chapter 8.2) unless the control bit VCC3_VS_ UV_OFF is set

The VCC1 short circuit protection becomes inactive (see Chapter 15.7). However, the thermal protection

of the device remains active.

If the undervoltage threshold is exceeded (VS rising) then functions will be automatically enabled again.

If the supply voltage VSHS passes below the undervoltage threshold (V_SHS,UVD) the SBC does the following

measures:

•

HS1...4 are acting accordingly to the SPI setting (see Chapter 9)

LINx: Transmitter and Receiver are disabled during the VSHS undervoltage condition (see Chapter 11.2.7);

SPI bit VSHS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present

anymore,

•

VCC1, VCC2, WKx and CAN are not affected by VSHS undervoltage

15.5

Overvoltage VSHS

If the supply voltage VSHS reaches the overvoltage threshold (V_SHS,OVD) the SBC triggers the following

measures:

•

HS1...4 are acting accordingly to the SPI setting (see Chapter 9)

SPI bit VSHS_OV is set. No other error bits are set. The bit can be cleared once the condition is not present

anymore,

•

VCC1, VCC2, VCC3, WKx, LIN and CAN are not affected by VS overvoltage

15.6

VCC1 Over-/ Undervoltage and Undervoltage Prewarning

VCC1 Undervoltage and Undervoltage Prewarning

15.6.1

A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The

prewarning event is signaled with the bit VCC1_ WARN. No other actions are taken.

As described in Chapter 15.1 and Figure 57, a reset will be triggered (RO pulled ‘low’) when the V_CC1output

voltage falls below the selected undervoltage threshold (V_RTx). The bit VCC1_UV is set and the SBC will enter

SBC Restart Mode.

Note:

The VCC1_ WARN or VCC1_UV bits are not set in Sleep Mode as V_CC1= 0V in this case

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VCC1

V_RTx

t

t_RF

t_RD1

RO

SBC Normal

SBC Restart

SBC Normal

Figure 57 VCC1 Undervoltage Timing Diagram

An additional safety mechanism is implemented to avoid repetitive VCC1 undervoltage resets due to high

dynamic loads on VCC1:

•

A counter is increased for every consecutive VCC1 undervoltage event (regardless on the selected reset

threshold),

•

The counter is active in SBC Init-, Normal-, and Stop Mode,

For VS < V_S,UVthe counter will be stopped in SBC Normal Mode (i.e. the VS UV comparator is always enabled

in SBC Normal Mode),

•

A 4th consecutive VCC1 undervoltage event will lead to SBC Fail-Safe Mode entry and to setting the bit

VCC1_UV _FS

This counter is cleared:

–

when SBC Fail-Safe Mode is entered,

when the bit VCC1_UV is cleared,

when a Soft Reset is triggered.

Note:

It is recommended to clear the VCC1_UV bit once it was set and detected.

15.6.2

VCC1 Overvoltage

For fail-safe reasons a configurable VCC1 overvoltage detection feature is implemented for SBC Init- and

Normal Mode.

In case the V_CC1,OV,rthreshold is crossed, the SBC triggers following measures depending on the configuration:

•

The bit VCC1_ OV is always set;

If the bit VCC1_OV_RST is set and CFGP = ‘1’, then SBC Restart Mode is entered. The FOx outputs are

activated. After the reset delay time (t_RD1), the SBC Restart Mode is left and SBC Normal Mode is resumed

even if the VCC1 overvoltage event is still present (see also Figure 58). The VCC1_OV_RST bit is cleared

automatically;

•

If the bit VCC1_OV_RST is set and CFGP = ‘0’, then SBC Fail-Safe Mode is entered and FOx outputs are

activated.

Note:

Before entering SBC Stop Mode the bit VCC1_OV_RST must be set to ‘0’ to avoid unintentional SBC

Restart or Fail-Safe Mode entry. The status bit VCC1_ OV could be set unintentionally. The reason is

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Supervision Functions

that external noise could be coupled into the VCC1 supply line. Especially, in case the VCC1 output

current in SBC STOP Mode is below the active peak threshold (I_VCC1,Ipeak).

VCC1

V_CC1,OV

t

t_{VCC1,OV_F}

RO

t_RD1

SBC Normal

SBC Restart

SBC Normal

Figure 58 VCC1 Overvoltage Timing Diagram

15.7

VCC1 Short Circuit and VCC3 Diagnostics

The short circuit protection feature for V_CC1is implemented as follows (VS needs to be higher than V_S,UV):

•

If VCC1 is not above the V_RTxwithin t_VCC1,SCafter device power up or after waking from SBC Sleep Mode then

the SPI bit VCC1_SC bit is set, VCC1 is turned OFF, the FOx pins are enabled, FAILURE is set and SBC Fail-

Safe Mode is entered. The SBC can be activated again via wake on CAN, LINx, WKx.

•

The same behavior applies, if V_CC1falls below V_RTxfor longer than t_VCC1,SC

.

VCC3 diagnosis features are implemented as follows:

•

Load Sharing: The external PNP is disabled when VS < V_S,UVif VCC3_VS_ UV_OFF = 0 or when in SBC Stop

Mode if VCC3_LS_ STP_ON = ‘0’. All other diagnostic features are disabled because they are provided via

VCC1.

•

Stand-alone configuration: The external PNP is disabled when VS < V_S,UVif VCC3_VS_ UV_OFF = 0. The

overcurrent limitation is signalled via the bit VCC3_OC according to the selected shunt resistor, VCC3

undervoltage is signalled via the bit VCC3_UV and the regulator is disabled due to VS undervoltage when

V

_S,UVis reached.

Note:

Neither VCC1_SC nor VCC3_UV flags are set during power up of V_CC1or turn on of V_CC3respectively.

15.8

VCC2 Undervoltage and VCAN Undervoltage

An undervoltage warning is implemented for VCC2 and VCAN as follows:

•

V

_CC2undervoltage Detection: In case V_CC2will drop below the V_CC2,UV,fthreshold, then the SPI bit VCC2_UV

is set and can be only cleared via SPI.

_CANundervoltage Detection: In case the voltage on V_CANwill drop below the V_{CAN_UV}threshold, then the SPI

bit VCAN_UV is set and can be only cleared via SPI.

•

V

Note:

The VCC2_UV flag is not set during turn-on or turn-off of V_CC2.

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Supervision Functions

15.9

Thermal Protection

Three independent and different thermal protection features are implemented in the SBC according to the

system impact:

•

Individual thermal shutdown of specific blocks

Temperature prewarning of main microcontroller supply VCC1

SBC thermal shutdown due to VCC1 overtemperature

15.9.1

Individual Thermal Shutdown

As a first-level protection measure the output stages VCC2, CAN, LINx, and HSx are independently switched

OFF if the respective block reaches the temperature threshold T_jTSD1. Then the TSD1 bit is set. This bit can only

be cleared via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the

thermal shutdown protection is only active if the respective block is ON.

The respective modules behave as follows:

•

VCC2: Is switched to OFF and the control bits VCC2_ON are cleared. The status bit VCC2_OT is set. Once

the overtemperature condition is not present anymore, then VCC2 has to be configured again by SPI.

•

VCC3 as a stand-alone regulator: Is switched to OFF and the control bits VCC3_ON are cleared. The status

bit VCC3_OT is set. Once the overtemperature condition is not present anymore VCC3 has to be configured

again by SPI. It is recommended to clear the VCC3_OT bit before enabling the regulator again.

•

VCC3 in load sharing configuration: in case of overtemperature at VCC3 the bit VCC3_OT is set and VCC3 is

switched off. The regulator will be switched on again automatically once the overtemperature event is not

present anymore. Also in this case it is recommended to clear the VCC3_OT bit right away.

CAN: The transmitter is disabled and stays in CAN Normal Mode acting like CAN Receive only mode. The

status bits CAN_FAIL = ‘01’ are set. Once the overtemperature condition is not present anymore, then the

CAN transmitter is automatically switched on.

LINx: The transmitter is disabled and stays in LIN Normal Mode acting like LIN Receive only mode. The

status bits and LIN2_FAIL respectively are set to ‘01’. Once the overtemperature condition is not present

anymore, then the LIN transmitter is automatically switched on.

HSx: If one or more HSx switches reach the TSD1 threshold, then all HSx switches are turned OFF and the

control bits for HSx are cleared (see registers HS_CTRL1 and HS_CTRL2). The status bits HSx_OC_OT are

set (see register HS_OC_OT_STAT). Once the overtemperature condition is not present anymore, then HSx

has to be configured again by SPI.

Note:

The diagnosis bits are not cleared automatically and have to be cleared via SPI once the

overtemperature condition is not present anymore.

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Supervision Functions

15.9.2

Temperature Prewarning

As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1

reaches the thermal prewarning temperature threshold T_jPW. Then the status bit TPW is set. This bit can only

be cleared via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the

thermal prewarning is only active if the VCC1 is ON.

15.9.3

SBC Thermal Shutdown

As a highest level of thermal protection a temperature shutdown of the SBC is implemented if the main supply

VCC1 reaches the thermal shutdown temperature threshold T_jTSD2. Once a TSD2 event is detected SBC Fail-

Safe Mode is entered for t_TSD2to allow the device to cool down. After this time has expired, the SBC will

automatically change via SBC Restart Mode to SBC Normal Mode (see also Chapter 5.1.6).

When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in SBC

Normal Mode once the overtemperature is not present anymore. Independent of the SBC Mode the thermal

shutdown is only active if VCC1 is ON.

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15.10

Electrical Characteristics

Table 35

Electrical Specification

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

VCC1 Monitoring; VCC1 = 3.3V Version

Undervoltage Prewarning

Threshold Voltage PW,f

3.3V option

V_PW,f

V_PW,r

V_RT1,f

V_RT1,r

V_RT2,f

V_RT2,r

V_RT3,f

V_RT3,r

V_RT4,f

V_RT4,r

3.0

3.1

3.2

V

VCC1 falling,

SPI bit is set

P_15.10.36

P_15.10.71

P_15.10.37

P_15.10.38

P_15.10.39

P_15.10.40

P_15.10.41

P_15.10.42

P_15.10.43

P_15.10.44

Undervoltage Prewarning

Threshold Voltage PW,r

3.3V option

3.10

2.95

3.0

3.2

3.28

3.15

3.2

VCC1 rising

Reset Threshold

Voltage RT1,f

3.3V option

3.05

3.1

default setting;

VCC1 falling

Reset Threshold

Voltage RT1,r

3.3V option

default setting;

VCC1 rising

Reset Threshold

Voltage RT2,f

3.3V option

2.5

2.6

2.7

VCC1 falling

VCC1 rising

Reset Threshold

Voltage RT2,r

3.3V option

2.55

2.2

2.65

2.3

2.75

2.4

Reset Threshold

Voltage RT3,f

3.3V option

SPI option;

VS ≥ 4V;

VCC1 falling

Reset Threshold

Voltage RT3,r

3.3V option

2.25

2.0

2.35

2.1

2.45

2.2

VS ≥ 4V;

VCC1 rising

Reset Threshold

Voltage RT4,f

3.3V option

VS ≥ 4V;

VCC1 falling

Reset Threshold

Voltage RT4,r

3.3V option,

2.05

2.15

2.25

VS ≥ 4V;

VCC1 rising,

Reset Threshold Hysteresis V_RT,hys

3.3V option

30

67

–

140

3.7

mV

V

–

P_15.10.45

P_15.10.70

VCC1 Overvoltage Detection V_CC1,OV,r

Threshold Voltage

3.5

rising VCC1

3.3V option

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Supervision Functions

Table 35

Electrical Specification (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

VCC1 Overvoltage Detection V_CC1,OV,f

Threshold Voltage

3.40

3.60

V

falling VCC1

P_15.10.73

3.3V option

2)

VCC1 OV Detection Filter

Time

t_{VCC1,OV_F}

t_VCC1,SC

5

10

4

14

us

P_15.10.51

P_15.10.12

VCC1 Short to GND Filter

Time

3.2

4.8

ms

Reset Generator; Pin RO

Reset Low Output Voltage

V_RO,L

–

0.2

–

0.4

V

I_RO= 1 mA for

P_15.10.14

P_15.10.15

V_CC1≥ 1 V &

V_S≥ V_POR,f

Reset High Output Voltage V_RO,H

0.8 x

V_CC1

+

I_RO= -20 µA

V_CC1

0.3 V

Reset Pull-up Resistor

Reset Filter Time

R_RO

t_RF

10

4

20

10

40

26

kΩ

V_RO= 0 V

P_15.10.16

P_15.10.17

2)

µs

V

< V_RT1x

CC1

to RO = L see also

Chapter 15.3

1) 2)

Reset Delay Time

t_RD1

1.5

2

2.5

ms

P_15.10.18

VCC2 Monitoring

VCC2 Undervoltage

Threshold Voltage (falling)

V_CC2,UV,f

V_CC2,UV,r

4.5

4.6

20

–

4.75

4.9

V

VCC2 falling

VCC2 rising

–

P_15.10.19

P_15.10.77

P_15.10.20

VCC2 Undervoltage

Threshold Voltage (rising)

–

V

V_CC2Undervoltage detection V_{CC2,UV, hys}

100

250

mV

hysteresis

VCC3 Monitoring

V_CC3Undervoltage Detection V_CC3,UV

2.65

2.85

3.00

V

3.3V option or

VCC3_ V_CFG=0

hysteresis

P_15.10.47

included

V_CC3Undervoltage Detection V_CC3,UV

1.45

20

1.52

100

1.65

250

V

VCC3_ V_CFG=1

hysteresis

included

P_15.10.61

P_15.10.22

V_CC3Undervoltage detection V_{CC3,UV, hys}

mV

–

hysteresis

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Supervision Functions

Table 35

Electrical Specification (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

VCAN Monitoring

CAN Supply undervoltage

detection threshold

V_{CAN_UV}

4.45

–

4.85

V

CAN Normal

Mode,

P_15.10.23

hysteresis

included;

Watchdog Generator

Long Open Window

Internal Oscillator

2)3)

t_LW

160

0.8

200

1.0

240

1.2

ms

P_15.10.24

P_15.10.25

f_CLKSBC

MHz

–

Minimum Waiting time during SBC Fail-Safe Mode

Min. waiting time Fail-Safe t_FS,min80 100

Power-on Reset, Over- / Undervoltage Protection

2)4)

120

ms

P_15.10.75

VS Power on reset rising

VS Power on reset falling

V_POR,r

V_POR,f

–

4.7

3

V

VS increasing

VS decreasing

P_15.10.26

P_15.10.27

P_25.10.46

–

VS Undervoltage Detection V_S,UV

Threshold

3.3V option

3.7

–

4.4

Supply UV

threshold for VCC3

and VCC1 SC

detection;

hysteresis

included

VSHS Overvoltage Detection V_SHS,OVD

Threshold

20

22

V

Supply OV

supervision for

HSx;

P_15.10.28

hysteresis

included

5)

VSHS Overvoltage Detection V_SHS,OVD,hys100

hysteresis

500

200

–

mV

V

P_15.10.29

P_15.10.30

VSHS Undervoltage

Detection Threshold

V_SHS,UVD

4.8

5.5

Supply UV

supervision for

LINx, HSx, and HS

of GPIOx;

hysteresis

included

5)

VSHS Undervoltage

Detection hysteresis

V_SHS,UVD,hys50

350

mV

P_15.10.31

Overtemperature Shutdown⁵⁾

Thermal Prewarning

Temperature

T_jPW

125

165

145

185

138

165

200

°C

P_15.10.32

P_15.10.33

Thermal Shutdown TSD1

T_jTSD1

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Supervision Functions

Table 35

Electrical Specification (cont’d)

V_S= 5.5 V to 28 V; T_j= -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

185

Unit Note or

Test Condition

Number

Min.

165

5

Max.

200

25

Thermal Shutdown TSD2

T_jTSD2

°C

P_15.10.34

P_15.10.68

Thermal Shutdown

hysteresis

T_jTSD,hys

15

2)

Deactivation time after

thermal shutdown TSD2

t_TSD2

0.8

1

1.2

s

P_15.10.35

1) The reset delay time will start when VCC1 crosses above the selected Vrtx threshold

2) Not subject to production test, tolerance defined by internal oscillator tolerance.

3) An additional safety factor of 1.5 needs to be applied like shown in Figure 53.

4) This time applies for all failure entries except a device thermal shutdown (TSD2 has a typ. 1s waiting time t_TSD2

)

5) Not subject to production test, specified by design.

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Serial Peripheral Interface

16

Serial Peripheral Interface

16.1

SPI Block Description

The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input

CLK provided by the microcontroller. The output word appears synchronously at the data output SDO (see

Figure 59).

The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After

the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content.

The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for

other use. The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is

shifted out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy chain capable.

CSN high to low: SDO is enabled. Status information transferred to output shift register

CSN

time

CSN low to high: data from shift register is transferred to output functions

CLK

time

Actual data

New data

0 1

+ +

SDI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

time

SDI: will accept data on the falling edge of CLK signal

Actual status

New status

0

1

+

ERR

SDO

ERR

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

-

+

time

SDO: will change state on the rising edge of CLK signal

Figure 59 SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure

compared to the register description)

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Serial Peripheral Interface

16.2

Failure Signalization in the SPI Data Output

When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong

SPI commands are either invalid SBC mode commands or commands which are prohibited by the state

machine to avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set

and the SPI Write command is ignored (mostly no partial interpretation). This bit can be only reset by actively

clearing it via a SPI command.

Invalid SPI Commands leading to SPI_FAIL are listed below:

•

Illegal state transitions: Going from SBC Stop to SBC Sleep Mode. In this case the SBC enters in addition the

SBC Restart Mode;

Trying to go to SBC Stop or SBC Sleep mode from SBC Init Mode. In this case SBC Normal Mode is entered;

•

Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored or the

new watchdog settings are ignored respectively;

In SBC Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration, PWM

settings and HS configuration settings during SBC Stop Mode, etc.;

the SPI command is ignored in this case;

only WD trigger, returning to Normal Mode, triggering a SBC Soft Reset, and Read & Clear status registers

commands are valid SPI commands in SBC Stop Mode;

•

When entering SBC Stop Mode and WK_STAT_1 and WK_STAT_2 are not cleared; SPI_FAIL will not be set

but the INT pin will be triggered;

Changing from SBC Stop to Normal Mode and changing the other bits of the M_S_CTRL register. The other

modifications will be ignored;

SBC Sleep Mode: attempt to go to Sleep Mode when all bits in the BUS_CTRL_1, BUS_CTRL_2 and

WK_CTRL_2 registers are cleared. In this case the SPI_FAIL bit is set and the SBC enters Restart Mode.

Even though the Sleep Mode command is not entered in this case, the rest of the command (e.g modifying

VCC2 or VCC3) is executed and the values stay unchanged during SBC Restart Mode;

Note: At least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode,

i.e. the SBC would not be able to wake up anymore.

If the only wake source is a timer and the timer is OFF then the SBC will wake immediately from Sleep Mode

and enter Restart Mode;

No failure handling is done for the attempt to go to SBC STOP Mode when all bits in the registers

BUS_CTRL_1, BUS_CTRL_2 and WK_CTRL_2 are cleared because the microcontroller can leave this mode

via SPI;

•

If VCC3 load sharing VCC3_LS is enabled and the microcontroller tries to clear the bit, then the rest of the

command executed but VCC3_LS will remain set;

Attempt to enter SBC Sleep Mode if WK_MEAS is set to ‘1’ and only WK1_EN or WK2_EN are set as wake

sources. Also in this case the SPI_FAIL bit is set and the SBC enters Restart Mode;

•

Setting a longer or equal on-time than the timer period of the respective timer;

SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’;

Note:

There is no SPI fail information for unused addresses.

Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 59):

The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set

for following conditions:

•

in case the number of received SPI clocks is not 0 or 16,

in case RO is LOW and SPI frames are being sent at the same time.

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Serial Peripheral Interface

Note:

In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is

not valid if the CLK is high on a falling edge of CSN

The number of received SPI clocks is not 0 or 16:

The number of received input clocks is supervised to be 0- or 16 clock cycles and the input word is discarded

in case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high

during CSN edges. Both errors - 0 bit and 16 bit CLK mismatch or CLK high during CSN edges - are flagged in

the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the

clock is received. The complete SPI command is ignored in this case.

RO is LOW and SPI frames are being sent at the same time:

The ERR flag will be set when the RO pin is triggered (during SBC Restart) and SPI frames are being sent to the

SBC at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below

conditions:

•

if the command begins when RO is HIGH and it ends when RO is LOW,

if a SPI command will be sent while RO is LOW,

If a SPI command begins when RO is LOW and it ends when RO is HIGH.

and the SDO output will behave as follows:

•

always when RO is LOW then SDO will be HIGH,

when a SPI command begins with RO is LOW and ends when RO is HIGH, then the SDO should be ignored

because wrong data will be sent.

Notes

1. It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled low and

SDO is observed - no SPI Clocks are sent in this case

2. The ERR flag could also be set after the SBC has entered SBC Fail-Safe Mode because the SPI communication

is stopped immediately.

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Serial Peripheral Interface

16.3

SPI Programming

For the TLE9263-3BQXV33, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between

Read Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For

the actual configuration and status information, 8 data bits (BIT15...8) are used.

Writing, clearing and reading is done byte wise. The SPI status bits are not cleared automatically and must be

cleared by the microcontroller, e.g. if the TSD2 was set due to overtemperature. The configuration bits will be

partially automatically cleared by the SBC - please refer to the individual registers description for detailed

information. During SBC Restart Mode the SPI communication is ignored by the SBC, i.e. it is not interpreted.

There are two types of SPI registers:

•

Control registers: Those are the registers to configure the SBC, e.g. SBC mode, watchdog trigger, etc

Status registers: Those are the registers where the status of the SBC is signalled, e.g. wake events,

warnings, failures, etc.

For the status registers, the requested information is given in the same SPI command in DO.

For the control registers, also the status of the respective byte is shown in the same SPI command. However,

if the setting is changed this is only shown with the next SPI command (it is only valid after CSN high) of the

same register.

The SBC status information from the SPI status registers, is transmitted in a compressed way with each SPI

response on SDO in the so called Status Information Field register (see also Figure 60). The purpose of this

register is to quickly signal the information to the microcontroller if there was a change in one of the SPI status

registers. In this way, the microcontroller does not need to read constantly all the SPI status registers but only

those registers, which were changed.

Each bit in the Status Information Field represents a SPI status register (see Table 36). As soon as one bit is set

in one of the status registers, then the respective bit in the Status Information Field register will be set. The

register WK_LVL_STAT is not included in the status Information field. This is listed in Table 36.

For Example if bit 0 in the Status Information Field is set to 1, one or more bits of the register 100 0001

(SUP_STAT_1) is set to 1. Then this register needs to be read in a second SPI command. The bit in the Status

Information Field will be set to 0 when all bits in the register 100 0001 are set back to 0.

Table 36

Status Information Field

Corresponding

Bit in Status

Status Register Description

Information Field

Address Bit

100 0001

100 0010

100 0011

0

SUP_STAT_1: Supply Status -VSHS fail, VCCx fail, POR

THERM_STAT: Thermal Protection Status

1

2

DEV_STAT: Device Status - Mode before Wake, WD Fail,

SPI Fail, Failure

3

4

100 0100

100 0110

BUS_STAT: Bus Failure Status: CAN, LINx; BUS_STAT_1

& BUS_STAT_2 are a combinational OR

WK_STAT_1, WK_STAT_2: Wake Source Status;

Status bit is set as combinational OR of both registers

5

6

7

100 0000

101 0100

101 0101

SUP_STAT_2: VCC1_WARN/OV, VCC3 Status

HS_OC_OT_STAT: High-Side Over Load Status

HS_OL_STAT: High-Side Open Load Status

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

LSB

MSB

DI

0

1

2

3

4

5

6

7

8

x

9

x

10 11 12 13 14 15

R/W

Address Bits

Data Bits

x

Register content of

selected address

DO

0

1

2

3

4

5

6

7

8

x

9

x

10 11 12 13 14 15

Data Bits

Status Information Field

x

time

LSB is sent first in SPI message

Figure 60 SPI Operation Mode

Datasheet

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

16.4

SPI Bit Mapping

The following figures show the mapping of the registers and the SPI bits of the respective registers.

The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only

read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after write can be seen

with a new read / write command.

The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if

possible) depending on bit 7. To clear a Data Byte of one of the Status Registers bit 7 must be set to 1. The

registers WK_LVL_STAT, and FAM_PROD_STAT, SWK_OSC_CAL_H_STAT, SWK_OSC_CAL_L_STAT,

SWK_STAT, SWK_ECNT_STAT, SWK_CDR_STAT1, SWK_CDR_STAT2 are an exception as they show the

actual voltage level at the respective WK pin (LOW/HIGH), or a fixed family/ product ID respectively and can

thus not be cleared. It is recommended for proper diagnosis to clear respective status bits for wake events or

failure. However, in general it is possible to enable drivers without clearing the respective failure flags.

When changing to a different SBC Mode, certain configurations bits will be cleared automatically or modified:

•

The SBC Mode bits are updated to the actual status, e.g. when returning to Normal Mode

When changing to a low-power mode (Stop/Sleep), the diagnosis bits of the switches and transceivers are

not cleared. FOx will stay activated if it was triggered before.

•

When changing to SBC Stop Mode, the CAN and LIN control bits will not be modified.

When changing to SBC Sleep Mode, the CAN and LIN control bits will be modified if they were not OFF or

wake capable before.

•

HSx, VCC2 and VCC3 will stay on when going to Sleep-/Stop Mode (configuration can only be done in

Normal Mode). Diagnosis is active (OC, OL, OT). In case of a failure the switch is turned off and no wake-up

is issued

The configuration bits for HSx and VCC2 in stand-alone configuration are cleared in SBC Restart Mode. FOx

will stay activated if it was triggered before. Depending on the respective configuration, CAN/LIN

transceivers will be either OFF, woken or still wake capable.

Note:

The detailed behavior of the respective SPI bits and control functions is described in Chapter 16.5,

Chapter 16.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the SBC

will modify respective control bits.

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

MSB

LSB

15 14 13 12 11 10

8 Data Bits [bits 8...15]

9

8

7

6

5

4

3

2

1

0

Reg.

Type

7 Address Bits [bits 0...6]

for Register Selection

for Configuration & Status Information

M_S_CTRL

rw

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

HW_CTRL

WD_CTRL

BUS_CTRL_1

BUS_CTRL_2

WK_CTRL_1

WK_CTRL_2

WK_PUPD_CTRL

WK_FLT_CTRL

TIMER1_CTRL

TIMER2_CTRL

SW_SD_CTRL

HS_CTRL_1

HS_CTRL_2

GPIO_CTRL

PWM1_CTRL

PWM2_CTRL

PWM_FREQ_CTRL

SYS_STAT_CTRL

SWK_CTRL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SWK_BTL1_CTRL

SWK_BTL2_CTRL

SWK_ID3_CTRL

SWK_ID2_CTRL

SWK_ID1_CTRL

SWK_ID0_CTRL

SWK_MASK_ID3_CTRL

SWK_MASK_ID2_CTRL

SWK_MASK_ID1_CTRL

SWK_MASK_ID0_CTRL

SWK_DLC_CTRL

SWK_DATA7_CTRL

SWK_DATA6_CTRL

SWK_DATA5_CTRL

SWK_DATA4_CTRL

SWK_DATA3_CTRL

SWK_DATA2_CTRL

SWK_DATA1_CTRL

SWK_DATA0_CTRL

SWK_CAN_FD_CTRL

SWK_OSC_TRIM_CTRL

SWK_OPT_CTRL

rw

0

1

0

1

0

1

0

1

0

1

0

1

0

SWK_OSC_CAL_H_STAT

SWK_OSC_CAL_L_STAT

SWK_CDR_CTRL1

r

rw

SWK_CDR_CTRL2

rw

0

1

0

1

0

1

SWK_CDR_LIMIT_H_CTRL

SWK_CDR_LIMIT_L_CTRL

SUP_STAT_2

rw

rc

5

0

1

0

1

SUP_STAT_1

THERM_STAT

DEV_STAT

rc

r

1

2

3

4

-

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

BUS_STAT_1

BUS_STAT_2

WK_STAT_1

WK_STAT_2

WK_LVL_STAT

HS_OC_OT_STAT

HS_OL_STAT

SWK_STAT

rc

r

6

7

SWK_ECNT_STAT

SWK_CDR_STAT1

r

1

0

1

0

SWK_CDR_STAT2

FAM_PROD_STAT

r

1

0

1

0

1

0

Figure 61

SPI Register Mapping including Selective Wake

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

15

14

13

12

Data Bit 15…8

D4

11

10

9

8

7

6...0

Address

A6…A0

Register Short Name

Access

Mode

D7

D6

D5

D3

D2

D1

D0

C O N T R O L R E G I S T E R S

M_S_CTRL

HW_CTRL

MODE_1

VCC3_V_CFG SOFT_RESET_RO

CHECKSUM

LIN_FLASH

reserved

TIMER2_WK_EN TIMER1_WK_EN

INT_GLOBAL

reserved

MODE_0

VCC3_ON

FO_ON

WD_WIN

VCC2_ON_1

VCC3_VS_UV_OFF

WD_EN_WK_BUS

LIN1_1

reserved

WK3_PUPD_0

WK3_FLT_0

TIMER1_ON_0

TIMER2_ON_0

VCC2_ON_0

VCC3_LS

reserved

LIN1_0

reserved

WK2_PUPD_1

WK2_FLT_1

reserved

VCC1_OV_RST

reserved

WD_TIMER_2

CAN_2

reserved

WD_STM_EN_1

WK3_EN

WK2_PUPD_0

WK2_FLT_0

TIMER1_PER_2 TIMER1_PER_1 TIMER1_PER_0

TIMER2_PER_2 TIMER2_PER_1 TIMER2_PER_0

reserved

HS1_2

HS3_2

VCC1_RT_1

VCC3_LS_STP_ON

WD_TIMER_1

CAN_1

LIN2_1

reserved

WK2_EN

WK1_PUPD_1

WK1_FLT_1

VCC1_RT_0

CFG

WD_TIMER_0

CAN_0

LIN2_0

reserved

WK1_EN

WK1_PUPD_0

WK1_FLT_0

read/write

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001100

0001101

0010000

0010100

0010101

0010111

0011000

0011001

0011100

0011110

WD_CTRL

WD_STM_EN_0

LIN_LSM

reserved

BUS_CTRL_1

BUS_CTRL_2

WK_CTRL_1

WK_CTRL_2

WK_PUPD_CTRL

WK_FLT_CTRL

TIMER1_CTRL

TIMER2_CTRL

SW_SD_CTRL

HS_CTRL_1

HS_CTRL_2

GPIO_CTRL

PWM1_CTRL

PWM2_CTRL

PWM_FREQ_CTRL

SYS_STAT_CTRL

LIN_TXD_TO

I_PEAK_TH

reserved

WK_MEAS

WK3_PUPD_1

WK3_FLT_1

TIMER1_ON_1

TIMER2_ON_1

reserved

TIMER1_ON_2

TIMER2_ON_2

HS_OV_SD_EN

HS2_2

reserved

HS_UV_SD_EN HS_OV_UV_REC

HS2_1

HS4_1

reserved

HS1_1

HS3_1

reserved

HS1_0

HS3_0

HS2_0

HS4_0

GPIO2_1

HS4_2

FO_DC_0

FO_DC_1

PWM1_DC_7

PWM2_DC_7

reserved

GPIO2_2

GPIO2_0

GPIO1_2

GPIO1_1

GPIO1_0

PWM1_DC_6

PWM2_DC_6

reserved

PWM1_DC_5

PWM2_DC_5

reserved

PWM1_DC_4

PWM2_DC_4

reserved

PWM1_DC_3

PWM2_DC_3

reserved

PWM1_DC_2

PWM2_DC_2

PWM2_FREQ_0

SYS_STAT_2

PWM1_DC_1

PWM2_DC_1

reserved

PWM1_DC_0

PWM2_DC_0

PWM1_FREQ_0

SYS_STAT_0

SYS_STAT_7

SYS_STAT_6

SYS_STAT_5

SYS_STAT_4

SYS_STAT_3

SYS_STAT_1

S E L E C T I V E W A K E R E G I S T E R S

SWK_CTRL

OSC_CAL

TBIT_7

reserved

ID28

ID20

ID12

reserved

MASK_ID28

MASK_ID20

MASK_ID12

reserved

DATA7_7

DATA6_7

DATA5_7

DATA4_7

DATA3_7

DATA2_7

DATA1_7

DATA0_7

reserved

TRIM_EN_1

TBIT_6

reserved

ID27

ID19

ID11

TRIM_EN_0

TBIT_5

SP_5

ID26

ID18

CANTO_MASK

TBIT_4

reserved

TBIT_3

SP_3

ID24

ID16

reserved

TBIT_2

SP_2

ID23

ID15

reserved

TBIT_1

SP_1

ID22

ID14

CFG_VAL

TBIT_0

SP_0

ID21

ID13

read/write

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

SWK_BTL1_CTRL

SWK_BTL2_CTRL

SWK_ID3_CTRL

SP_4

ID25

ID17

ID9

SWK_ID2_CTRL

SWK_ID1_CTRL

ID10

ID3

ID8

ID1

ID7

ID0

ID6

RTR

ID5

IDE

SWK_ID0_CTRL

ID4

ID2

SWK_MASK_ID3_CTRL

SWK_MASK_ID2_CTRL

SWK_MASK_ID1_CTRL

SWK_MASK_ID0_CTRL

SWK_DLC_CTRL

MASK_ID27

MASK_ID19

MASK_ID11

MASK_ID4

reserved

DATA7_6

DATA6_6

DATA5_6

DATA4_6

DATA3_6

DATA2_6

DATA1_6

DATA0_6

reserved

MASK_ID26

MASK_ID18

MASK_ID10

MASK_ID3

reserved

DATA7_5

DATA6_5

DATA5_5

DATA4_5

DATA3_5

DATA2_5

DATA1_5

DATA0_5

DIS_ERR_CNT

MASK_ID25

MASK_ID17

MASK_ID9

MASK_ID2

reserved

DATA7_4

DATA6_4

DATA5_4

DATA4_4

DATA3_4

DATA2_4

DATA1_4

DATA0_4

RX_FILT_BYP

MASK_ID24

MASK_ID16

MASK_ID8

MASK_ID1

DLC_3

DATA7_3

DATA6_3

DATA5_3

DATA4_3

DATA3_3

DATA2_3

DATA1_3

DATA0_3

FD_FILTER_2

MASK_ID23

MASK_ID15

MASK_ID7

MASK_ID0

DLC_2

DATA7_2

DATA6_2

DATA5_2

DATA4_2

DATA3_2

DATA2_2

DATA1_2

DATA0_2

FD_FILTER_1

MASK_ID22

MASK_ID14

MASK_ID6

reserved

DLC_1

DATA7_1

DATA6_1

DATA5_1

DATA4_1

DATA3_1

DATA2_1

DATA1_1

DATA0_1

FD_FILTER_0

MASK_ID21

MASK_ID13

MASK_ID5

reserved

DLC_0

DATA7_0

DATA6_0

DATA5_0

DATA4_0

DATA3_0

DATA2_0

DATA1_0

DATA0_0

CAN_FD_EN

SWK_DATA7_CTRL

SWK_DATA6_CTRL

SWK_DATA5_CTRL

SWK_DATA4_CTRL

SWK_DATA3_CTRL

SWK_DATA2_CTRL

SWK_DATA1_CTRL

SWK_DATA0_CTRL

SWK_CAN_FD_CTRL

S E L E C T I V E W A K E T R I M & C O N F I G U R A T I O N S R E G I S T E R S

SWK_OSC_TRIM_CTRL

SWK_OPT_CTRL

TRIM_OSC_7

RX_WK_SEL

OSC_CAL_H_7

OSC_CAL_L_7

reserved

CDR_LIM_H_7

CDR_LIM_L_7

TRIM_OSC_6

reserved

OSC_CAL_H_6

OSC_CAL_L_6

reserved

CDR_LIM_H_6

CDR_LIM_L_6

TRIM_OSC_5

reserved

OSC_CAL_H_5

OSC_CAL_L_5

reserved

CDR_LIM_H_5

CDR_LIM_L_5

TRIM_OSC_4

TRIM_OSC_12

OSC_CAL_H_4

OSC_CAL_L_4

reserved

CDR_LIM_H_4

CDR_LIM_L_4

TRIM_OSC_3

TRIM_OSC_11

OSC_CAL_H_3

OSC_CAL_L_3

SELFILT_1

reserved

CDR_LIM_H_3

CDR_LIM_L_3

TRIM_OSC_2

TRIM_OSC_10

OSC_CAL_H_2

OSC_CAL_L_2

SELFILT_0

reserved

CDR_LIM_H_2

CDR_LIM_L_2

TRIM_OSC_1

TRIM_OSC_9

OSC_CAL_H_1

OSC_CAL_L_1

reserved

SEL_OSC_CLK_1 SEL_OSC_CLK_0 read/write

CDR_LIM_H_1

CDR_LIM_L_1

TRIM_OSC_0

TRIM_OSC_8

OSC_CAL_H_0

OSC_CAL_L_0

CDR_EN

read/write

read

read/write

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

SWK_OSC_CAL_H_STAT

SWK_OSC_CAL_L_STAT

SWK_CDR_CTRL1

SWK_CDR_CTRL2

SWK_CDR_LIMIT_HIGH

CDR_LIM_H_0

CDR_LIM_L_0

read/write

SWK_CDR_LIMIT_LOW

S T A T U S R E G I S T E R S

SUP_STAT_2

SUP_STAT_1

THERM_STAT

DEV_STAT

reserved

POR

reserved

DEV_STAT_1

reserved

LIN2_WU

reserved

SBC_DEV_LVL

reserved

VS_UV

VSHS_UV

reserved

DEV_STAT_0

LIN1_FAIL_1

reserved

LIN1_WU

reserved

CFGP

reserved

VSHS_OV

reserved

LIN1_FAIL_0

reserved

CAN_WU

GPIO2_WU

GPIO2_LVL

reserved

VCC3_OC

VCC2_OT

reserved

CANTO

VCC3_UV

VCC2_UV

reserved

WD_FAIL_1

SYSERR

reserved

VCC3_OT

VCC1_SC

TSD2

WD_FAIL_0

CAN_FAIL_1

LIN2_FAIL_1

WK3_WU

reserved

VCC1_OV

VCC1_UV_FS

TSD1

VCC1_WARN

VCC1_UV

TPW

FAILURE

VCAN_UV

reserved

WK1_WU

reserved

WK1_LVL

HS1_OC_OT

HS1_OL

read/clear

read

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1010100

1010101

SPI_FAIL

BUS_STAT_1

BUS_STAT_2

WK_STAT_1

CAN_FAIL_0

LIN2_FAIL_0

WK2_WU

reserved

WK2_LVL

HS2_OC_OT

HS2_OL

reserved

TIMER_WU

GPIO1_WU

GPIO1_LVL

reserved

WK_STAT_2

WK_LVL_STAT

HS_OC_OT_STAT

HS_OL_STAT

WK3_LVL

HS3_OC_OT

HS3_OL

reserved

HS4_OC_OT

HS4_OL

read/clear

S E L E C T I V E W A K E S T A T U S R E G I S T E R S

SWK_STAT

reserved

N_AVG_11

N_AVG_3

SYNC

reserved

N_AVG_10

N_AVG_2

reserved

ECNT_5

N_AVG_9

N_AVG_1

reserved

ECNT_4

N_AVG_8

N_AVG_0

CANSIL

ECNT_3

N_AVG_7

reserved

SWK_SET

ECNT_2

N_AVG_6

reserved

WUP

WUF

read

1110000

1110001

1110010

1110011

SWK_ECNT_STAT

SWK_CDR_STAT1

SWK_CDR_STAT2

ECNT_1

N_AVG_5

reserved

ECNT_0

N_AVG_4

reserved

F A M I LY A N D P R O D U C T R E G I S T E R S

FAM_1 FAM_0 PROD_3

FAM_PROD_STAT

FAM_3

FAM_2

PROD_2

PROD_1

PROD_0

read

1111110

Figure 62

TLE9263-3BQXV33 SPI Bit Mapping including Selective Wake

Datasheet

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

16.5

SPI Control Registers

READ/WRITE Operation (see also Chapter 16.3):

•

The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Reset.

The ‘Restart Value’ defines the register content after SBC Restart, where ‘x’ means the bit is unchanged.

One 16-bit SPI command consist of two bytes:

- the 7-bit address and one additional bit for the register access mode and

- following the data byte

The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to

the SPI bits 8...15 (see also figure before).

•

There are three different bit types:

- ‘r’ = READ: read only bits (or reserved bits)

- ‘rw’ = READ/WRITE: readable and writable bits

- ‘rwh’ = READ/WRITE/Hardware: readable/writable bits, which can also be modified by the SBC hardware

Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be

programmed as “0”.

•

Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only).

Writing to a register is done byte wise by setting the SPI bit 7 to “1”.

SPI control bits are in general not cleared or changed automatically. This must be done by the

microcontroller via SPI programming. Exceptions to this behavior are stated at the respective register

description and the respective bit type is marked with a ‘h’ meaning that the SBC is able to change the

register content.

The registers are addressed wordwise.

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

16.5.1

General Control Registers

M_S_CTRL

Mode- and Supply Control (Address 000 0001_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 00x0 00xx_B

7

6

5

4

3

2

1

0

VCC1_OV_RS

T

MODE_1

MODE_0

VCC3_ON

VCC2_ON_1 VCC2_ON_0

VCC1_RT_1 VCC1_RT_0

r

rwh

rw

Field

Bits

Type

Description

MODE

7:6

rwh

SBC Mode Control

00_B, SBC Normal Mode

01_B, SBC Sleep Mode

10_B, SBC Stop Mode

11_B, SBC Reset: Soft Reset is executed (configuration of RO

triggering in bit SOFT_ RESET_RO)

VCC3_ON

VCC2_ON

5

rwh

VCC3 Mode Control

0_B, VCC3 OFF

1_B, VCC3 is enabled (as independent voltage regulator)

4:3

VCC2 Mode Control

00_B, VCC2 off

01_B, VCC2 on in Normal Mode

10_B, VCC2 on in Normal and Stop Mode

11_B, VCC2 always on (except in SBC Fail-Safe Mode)

VCC1_OV_R

ST

2

rwh

rw

VCC1 Overvoltage leading to Restart / Fail-Safe Mode enable

0_B, VCC1_ OV is set in case of VCC1_OV; no SBC Restart or Fail-

Safe is entered for VCC1_OV

1_B, VCC1_ OV is set in case of VCC1_OV; depending on the

device configuration SBC Restart or SBC Fail-Safe Mode is

entered (see Chapter 5.1.1);

VCC1_RT

1:0

VCC1 Reset Threshold Control

00_B, Vrt1 selected (highest threshold)

01_B, Vrt2 selected

10_B, Vrt3 selected

11_B, Vrt4 selected

Notes

1. It is not possible to change from Stop to Sleep Mode via SPI Command. See also the State Machine Chapter

2. After entering SBC Restart Mode, the MODE bits will be automatically set to SBC Normal Mode. The VCC2_ON

bits will be automatically set to OFF after entering SBC Restart Mode and after OT.

3. The SPI output will always show the previously written state with a Write Command (what has been

programmed before)

Datasheet

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

HW_CTRL

Mode- and Supply Control (Address 000 0010_B)

POR / Soft Reset Value: y000 y000_B;

Restart Value: xx0x x00x_B

7

6

5

4

3

2

1

0

SOFT_RESET

_RO

VCC3_VS_UV

_OFF

VCC3_LS_ST

P_ON

VCC3_V_CFG

FO_ON

VCC3_LS

Reserved

CFG

r

rw

rwh

rw

r

rw

Field

Bits

Type

Description

VCC3_

V_CFG

7

rw

VCC3 Output Voltage Configuration (if configured as

independent voltage regulator)

0_B, VCC3 has same output voltage as VCC1

1_B, VCC3 is configured to either 3.3V or 1.8V (depending on VCC1

derivative)

SOFT_

RESET_RO

6

5

rw

Soft Reset Configuration

0_B, RO will be triggered (pulled low) during a Soft Reset

1_B, No RO triggering during a Soft Reset

FO_ON

rwh

Failure Output Activation (FO1..3)

0_B, FOx not activated by software, FO can be activated by

defined failures (see Chapter 14)

1_B, FOx activated by software (via SPI)

VCC3_VS_

UV_OFF

4

3

rw

VCC3 VS_UV shutdown configuration

0_B, VCC3 will be disabled automatically at VS_UV

1_B, VCC3 will stay enabled even below VS_UV

VCC3_LS

VCC3 Configuration

0_B, VCC3 operating as a stand-alone regulator

1_B, VCC3 in load sharing operation with VCC1

Reserved

2

1

r

Reserved, always reads as 0

VCC3_LS_

STP_ON

rw

VCC3 Load Sharing in SBC Stop Mode configuration

0_B, VCC3 in LS configuration during SBC Stop Mode and high-

power mode: disabled

1_B, VCC3 in LS configuration during SBC Stop Mode and high-

power mode: enabled

CFG

0

rw

Configuration Select (see also Table 5)

0_B, Depending on hardware configuration, SBC Restart or Fail-

Safe Mode is reached after the 2. watchdog trigger failure

(=default) - Config 3/4

1_B, Depending on hardware configuration, SBC Restart or Fail-

Safe Mode is reached after the 1. watchdog trigger failure -

Config 1/2

Notes

1. Clearing the FO_ON bit will not disable the FOx outputs for the case a failure occurred which triggered the FOx

outputs. In this case the FOx outputs have to be disabled by clearing the FAILURE bit.

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If the FO_ON bit is set by the software then it will be cleared by the SBC after SBC Restart Mode was entered

and the FOx outputs will be disabled. See also Chapter 14 for FOx activation and deactivation.

2. After triggering a SBC Soft Reset the bits VCC3_V_CFG and VCC3_LS are not reset if they were set before, i.e. it

stays unchanged, which is stated by the ‘y’ in the POR / Soft Reset Value. POR value: 0000 0000 and Soft Reset

value: xx00 x00x

3. VCC3_LS_STP_ON: Is a combination of load sharing and VCC1 active peak in Stop mode

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WD_CTRL

Watchdog Control (Address 000 0011_B)

POR / Soft Reset Value: 0001 0100_B;

Restart Value: x0xx 0100_B

7

6

5

4

3

2

1

0

WD_STM_

EN_0

WD_EN_

WK_BUS

CHECKSUM

WD_WIN

Reserved WD_TIMER_2 WD_TIMER_1 WD_TIMER_0

r

rw

rwh

rw

r

rwh

Field

Bits

Type

Description

CHECKSUM

7

rw

Watchdog Setting Check Sum Bit

The sum of bits 7:0 needs to have even parity (see Chapter 15.2.3)

0_B, Counts as 0 for checksum calculation

1_B, Counts as 1 for checksum calculation

WD_STM_

EN_0

6

rwh

Watchdog Deactivation during Stop Mode, bit 0

(Chapter 15.2.4)

0_B, Watchdog is active in Stop Mode

1_B, Watchdog is deactivated in Stop Mode

WD_WIN

5

4

rw

Watchdog Type Selection

0_B, Watchdog works as a Time-Out watchdog

1_B, Watchdog works as a Window watchdog

WD_EN_

WK_BUS

Watchdog Enable after Bus (CAN/LIN) Wake in SBC Stop Mode

0_B, Watchdog will not start after a CAN/LINx wake

1_B, Watchdog starts with a long open window after CAN/LINx

Wake

Reserved

3

r

Reserved, always reads as 0

WD_TIMER 2:0

rwh

Watchdog Timer Period

000_B, 10ms

001_B, 20ms

010_B, 50ms

011_B, 100ms

100_B, 200ms

101_B, 500ms

110_B, 1000ms

111_B, reserved

Notes

1. See also Chapter 15.2.4 for more information on disabling the watchdog in SBC Stop Mode.

2. See Chapter 15.2.5 for more information on the effect of the bit WD_EN_WK_BUS.

3. See Chapter 15.2.3 for calculation of checksum.

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BUS_CTRL_1

Bus Control (Address 000 0100_B)

POR / Soft Reset Value: 0010 0000_B; Restart Value: xxxy yyyy_B

7

6

5

4

3

2

1

0

LIN_FLASH

LIN_LSM

LIN_TXD_TO

LIN1_1

LIN1_0

CAN_2

CAN_1

CAN_0

r

rw

rwh

Field

Bits

Type

Description

LIN_FLASH

7

rw

LIN Flash Programming Mode

0_B, Slope control mechanism active

1_B, Deactivation of slope control for baud rates up to 115kBaud

LIN_LSM

6

rw

LIN Low-Slope Mode Selection

0_B, LIN Normal-Mode is activated

1_B, LIN Low-Slope Mode (10.4kBaud) activated

LIN_TXD_

TO

5

rw

LIN TXD Time-Out Control

0_B, TXD Time-Out feature disabled

1_B, TXD Time-Out feature enabled

LIN

4:3

rwh

LIN-Module Modes

00_B, LIN OFF

01_B, LIN is wake capable

10_B, LIN Receive Only Mode

11_B, LIN Normal Mode

CAN

2:0

rwh

HS-CAN Module Modes

000_B, CAN OFF

001_B, CAN is wake capable (no SWK)

010_B, CAN Receive Only Mode (no SWK)

011_B, CAN Normal Mode (no SWK)

100_B, CAN OFF

101_B, CAN is wake capable with SWK

110_B, CAN Receive Only Mode with SWK

111_B, CAN Normal Mode with SWK

Notes

1. Changes in the bits LIN_FLASH and LIN_LSM will be effective immediately once CSN goes to ‘1’.’

2. The reset values for the LIN and CAN transceivers are marked with ‘y’ because they will vary depending on the

cause of change - see below.

3. see Figure 31 and Figure 38 for detailed state changes of LIN and CAN Transceiver for different SBC modes.

4. The bit CAN_2 is not modified by the SBC but can only be changed by the user. Therefore, the access type is

‘rw’ compared to bits CAN_0 and CAN_1.

5. In case SYSERR = 0 and the CAN transceiver is configured to ‘x11’ while going to SBC Sleep Mode, it will be

automatically set to wake capable (‘x01’). The SPI bits will be changed to wake capable. If configured to ‘x10’

and SBC Sleep Mode is entered, then the transceiver is set to wake capable, while it will stay in Receive Only

Mode when it had been configured to ‘x10’ when going to SBC Stop Mode. If it had been configured to wake

capable or OFF then the mode will remain unchanged.The Receive Only Mode has to be selected by the user

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before entering SBC Stop Mode. Please refer to Chapter 5.4.4 for detailed information on the Selective Wake

mode changes.

6. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),

then the wake registers BUS_CTRL_1, BUS_CTRL_2 and WK_CTRL_2 are reset to following values (=wake

sources) ‘xxx0 1001’, ‘0000 0001’ and ‘x0x0 0111’ in order to ensure that the device can be woken again.

BUS_CTRL_2

Bus Control (Address 000 0101_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 00x0 00yy_B

7

6

5

4

3

2

1

0

Reserved

I_PEAK_TH

Reserved

LIN2_1

LIN2_0

r

rw

r

rwh

Field

Bits

Type

r

Description

Reserved

7:6

5

Reserved, always reads as 0

I_PEAK_TH

rw

VCC1 Active Peak Threshold Selection

0_B, low VCC1 active peak threshold selected (ICC1,peak_1)

1_B, higher VCC1 active peak threshold selected (ICC1,peak_2)

Reserved

LIN2

4:2

1:0

r

Reserved, always reads as 0

rwh

LIN2-Module Modes

00_B, LIN2 OFF

01_B, LIN2 is wake capable

10_B, LIN2 Receive Only Mode

11_B, LIN2 Normal Mode

Notes

1. The bit I_PEAK_TH can be modified in SBC Init and Normal Mode. In SBC Stop Mode this bit is Read only but

SPI_FAIL will not be set when trying to modify the bit in SBC STOP Mode and no INT is triggered in case INT_

GLOBAL is set.

2. see Figure 31 and Figure 38 for detailed state changes of LIN and CAN Transceiver for different SBC modes

3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),

then the wake registers BUS_CTRL_1, and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0

1001’, and ‘x0x0 0111’ in order to ensure that the device can be woken again.

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WK_CTRL_1

Internal Wake Input Control (Address 000 0110_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xx00 0000_B

7

6

5

4

3

2

1

0

TIMER2_WK_ TIMER1_WK_

WD_STM_

EN_1

Reserved

EN

r

rw

r

rwh

r

Field

Bits

Type

Description

TIMER2_WK 7

_EN

rw

Timer2 Wake Source Control (for cyclic wake)

0_B, Timer2 wake disabled

1_B, Timer2 is enabled as a wake source

TIMER1_WK 6

_EN

rw

Timer1 Wake Source Control (for cyclic wake)

0_B, Timer1 wake disabled

1_B, Timer1 is enabled as a wake source

Reserved

5:3

r

Reserved, always reads as 0

WD_STM_

EN_1

2

rwh

Watchdog Deactivation during Stop Mode, bit 1

(Chapter 15.2.4)

0_B, Watchdog is active in Stop Mode

1_B, Watchdog is deactivated in Stop Mode

Reserved

1:0

r

Reserved, always reads as 0

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WK_CTRL_2

External Wake Source Control (Address 000 0111_B)

POR / Soft Reset Value: 0000 0111_B;

Restart Value: x0x0 0xxx_B

7

6

5

4

3

2

1

0

INT_GLOBAL Reserved

WK_MEAS

Reserved

WK3_EN

WK2_EN

WK1_EN

w

r

rw

r

rw

r

rw

Field

INT_

GLOBAL

Bits

Type

Description

7

rw

Global Interrupt Configuration (see also Chapter 13.1)

0_B, Only wake sources trigger INT (default)

1_B, All status information register bits will trigger INT (including

all wake sources)

Reserved

WK_MEAS

6

5

r

Reserved, always reads as 0

rw

WK / Measurement selection (see also Chapter 12.2.2)

0_B, WK functionality enabled for WK1 and WK2

1_B, Measurement functionality enabled; WK1 & WK2 are

disabled as wake sources, i.e. bits WK1/2_EN bits are ignored

Reserved

WK3_EN

4:3

2

r

Reserved, always reads as 0

rw

WK3 Wake Source Control

0_B, WK3 wake disabled

1_B, WK3 is enabled as a wake source

WK2_EN

WK1_EN

1

0

rw

WK2 Wake Source Control

0_B, WK2 wake disabled

1_B, WK2 is enabled as a wake source

WK1 Wake Source Control

0_B, WK1 wake disabled

1_B, WK1 is enabled as a wake source

Notes

1. WK_MEAS is by default configured for standard WK functionality (WK1 and WK2). The bits WK1_EN and

WK2_EN are ignored in case WK_MEAS is activated. If the bit is set to ‘1’ then the measurement function is

enabled during Normal Mode & the bits WK1_EN and WK2_EN are ignored. The bits WK1/”_LVL bits need to be

ignored as well.

2. The wake sources LINx and CAN are selected in the register BUS_CTRL_1 and BUS_CTRL_2 by setting the

respective bits to ‘wake capable’

3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),

then the wake registers BUS_CTRL_1, BUS_CTRL_2 and WK_CTRL_2 are reset to following values (=wake

sources) ‘xxx0 1001’, ‘0000 0001’ and ‘x0x0 0111’ in order to ensure that the device can be woken again.

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WK_PUPD_CTRL

Wake Input Level Control (Address 000 1000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00xx xxxx_B

7

6

5

4

3

2

1

0

Reserved

Reserved WK3_PUPD_1 WK3_PUPD_0 WK2_PUPD_1 WK2_PUPD_0 WK1_PUPD_1 WK1_PUPD_0

r

rw

Field

Reserved

Bits

Type

Description

7:6

r

Reserved, always reads as 0

WK3_PUPD 5:4

WK2_PUPD 3:2

WK1_PUPD 1:0

rw

WK3 Pull-Up / Pull-Down Configuration

00_B, No pull-up / pull-down selected

01_B, Pull-down resistor selected

10_B, Pull-up resistor selected

11_B, Automatic switching to pull-up or pull-down

rw

WK2 Pull-Up / Pull-Down Configuration

00_B, No pull-up / pull-down selected

01_B, Pull-down resistor selected

10_B, Pull-up resistor selected

11_B, Automatic switching to pull-up or pull-down

WK1 Pull-Up / Pull-Down Configuration

00_B, No pull-up / pull-down selected

01_B, Pull-down resistor selected

10_B, Pull-up resistor selected

11_B, Automatic switching to pull-up or pull-down

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WK_FLT_CTRL

Wake Input Filter Time Control (Address 000 1001_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00xx xxxx_B

7

6

5

4

3

2

1

0

Reserved

WK3_FLT_1 WK3_FLT_0 WK2_FLT_1 WK2_FLT_0 WK1_FLT_1 WK1_FLT_0

r

rw

Field

Bits

Type

Description

Reserved

WK3_FLT

7:6

5:4

r

Reserved, always reads as 0

rw

WK3 Filter Time Configuration

00_B, Configuration A: Filter with 16µs filter time (static sensing)

01_B, Configuration B: Filter with 64µs filter time (static sensing)

10_B, Configuration C: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer1

11_B, Configuration D: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer2

WK2_FLT

WK1_FLT

3:2

1:0

rw

WK2 Filter Time Configuration

00_B, Configuration A: Filter with 16µs filter time (static sensing)

01_B, Configuration B: Filter with 64µs filter time (static sensing)

10_B, Configuration C: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer1

11_B, Configuration D: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer2

WK1 Filter Time Configuration

00_B, Configuration A: Filter with 16µs filter time (static sensing)

01_B, Configuration B: Filter with 64µs filter time (static sensing)

10_B, Configuration C: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer1

11_B, Configuration D: Filtering at the end of the on-time;

a filter time of 16µs (cyclic sensing) is selected, Timer2

Note:

When selecting a filter time configuration, the user must make sure to also assign the respective

timer to at least one HS switch during cyclic sense operation

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TIMER1_CTRL

Timer1 Control and Selection (Address 000 1100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

TIMER1_

ON_2

TIMER1_

ON_1

TIMER1_

ON_0

TIMER1_

PER_2

TIMER1_

PER_1

TIMER1_

PER_0

Reserved

r

rwh

r

rwh

Field

Bits

Type

Description

Reserved

7

r

Reserved, always reads as 0

TIMER1_

ON

6:4

rwh

Timer1 On-Time Configuration

000_B, OFF / Low (timer not running, HSx output is low)

001_B, 0.1ms on-time

010_B, 0.3ms on-time

011_B, 1.0ms on-time

100_B, 10ms on-time

101_B, 20ms on-time

110_B, OFF / HIGH (timer not running, HSx output is high)

111_B, reserved

Reserved

3

r

Reserved, always reads as 0

TIMER1_

PER

2:0

rwh

Timer1 Period Configuration

000_B, 10ms

001_B, 20ms

010_B, 50ms

011_B, 100ms

100_B, 200ms

101_B, 1s

110_B, 2s

111_B, reserved

Notes

1. A timer must be first assigned and is then automatically activated as soon as the on-time is configured.

2. If cyclic sense is selected and the HS switches are cleared during SBC Restart Mode, then also the timer

settings (period and on-time) are cleared to avoid incorrect switch detection.

3. In case the timer are set as wake sources and cyclic sense is running, then both cyclic sense and cyclic wake

will be active at the same time.

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TIMER2_CTRL

Timer2 Control and selection (Address 000 1101_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

TIMER2_

ON_2

TIMER2_

ON_1

TIMER2_

ON_0

TIMER2_

PER_2

TIMER2_

PER_1

TIMER2_

PER_0

Reserved

r

rwh

r

rwh

Field

Bits

Type

Description

Reserved

7

r

Reserved, always reads as 0

TIMER2_

ON

6:4

rwh

Timer2 On-Time Configuration

000_B, OFF / Low (timer not running, HSx output is low)

001_B, 0.1ms on-time

010_B, 0.3ms on-time

011_B, 1.0ms on-time

100_B, 10ms on-time

101_B, 20ms on-time

110_B, OFF / HIGH (timer not running, HSx output is high)

111_B, reserved

Reserved

3

r

Reserved, always reads as 0

TIMER2_

PER

2:0

rwh

Timer2 Period Configuration

000_B, 10ms

001_B, 20ms

010_B, 50ms

011_B, 100ms

100_B, 200ms

101_B, 1s

110_B, 2s

111_B, reserved

Notes

1. A timer must be first assigned and is then automatically activated as soon as the on-time is configured.

2. If cyclic sense is selected and the HS switches are cleared during SBC Restart Mode, then also the timer

settings (period and on-time) are cleared to avoid incorrect switch detection.

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SW_SD_CTRL

Switch Shutdown Control (Address 001 0000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0xxx 0000_B

7

6

5

4

3

2

1

0

HS_OV_SD_E HS_UV_SD_E HS_OV_UV_R

Reserved

N

EC

r

rw

r

Field

Bits

7

Type

Description

Reserved

r

Reserved, always reads as 0

HS_OV_SD_

EN

6

rw

Shutdown Disabling of HS1...4 in case of VSHS OV

0_B, shutdown enabled in case of VSHS OV

1_B, shutdown disabled in case of VSHS OV

HS_UV_SD_

EN

5

4

rw

Shutdown Disabling of HS1...4 in case of VSHS UV

0_B, shutdown enabled in case of VSHS UV

1_B, shutdown disabled in case of VSHS UV

HS_OV_UV_

REC

Switch Recovery after Removal of VSHS OV/UV for HS1...4

0_B, Switch recovery is disabled

1_B, Previous state before VSHS OV/UV is enabled after OV/UV

condition is removed

Reserved

3:0

r

Reserved, always reads as 0

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HS_CTRL1

High-Side Switch Control 1 (Address 001 0100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

Reserved

HS2_2

HS2_1

HS2_0

Reserved

HS1_2

HS1_1

HS1_0

r

rw

rwh

r

rwh

Field

Bits

Type

Description

Reserved

HS2

7

r

Reserved, always reads as 0

6:4

rwh

HS2 Configuration

000_B, Off

001_B, On

010_B, Controlled by Timer1

011_B, Controlled by Timer2

100_B, Controlled by PWM1

101_B, Controlled by PWM2

110_B, Reserved

111_B, Reserved

Reserved

HS1

3

r

Reserved, always reads as 0

2:0

rwh

HS1 Configuration

000_B, Off

001_B, On

010_B, Controlled by Timer1

011_B, Controlled by Timer2

100_B, Controlled by PWM1

101_B, Controlled by PWM2

110_B, Reserved

111_B, Reserved

Note:

The bits for the switches are also reset in case of overcurrent and overtemperature.

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HS_CTRL2

High-Side Switch Control 2 (Address 001 0101_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

Reserved

HS4_2

HS4_1

HS4_0

Reserved

HS3_2

HS3_1

HS3_0

r

rwh

r

rwh

Field

Bits

Type

Description

Reserved

HS4

7

r

Reserved, always reads as 0

6:4

rwh

HS4 Configuration

000_B, Off

001_B, On

010_B, Controlled by Timer1

011_B, Controlled by Timer2

100_B, Controlled by PWM1

101_B, Controlled by PWM2

110_B, Reserved

111_B, Reserved

Reserved

HS3

3

r

Reserved, always reads as 0

2:0

rwh

HS3 Configuration

000_B, Off

001_B, On

010_B, Controlled by Timer1

011_B, Controlled by Timer2

100_B, Controlled by PWM1

101_B, Controlled by PWM2

110_B, Reserved

111_B, Reserved

Note:

The bits for the switches are also reset in case of overcurrent and overtemperature.

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GPIO_CTRL

GPIO Configuration Control (Address 001 0111_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

FO_DC_1

FO_DC_0

GPIO2_2

GPIO2_1

GPIO2_0

GPIO1_2

GPIO1_1

GPIO1_0

r

rw

Field

Bits

Type

Description

FO_DC

7:6

rw

Duty Cycle Configuration of FO3 (if selected)

00_B, 20%

01_B, 10%

10_B, 5%

11_B, 2.5%

GPIO2

5:3

rw

GPIO2 Configuration

000_B, FO3 selected

001_B, FO3 selected

010_B, FO3 selected

011_B, FO3 selected

100_B, OFF

101_B, Wake input enabled (16µs static filter)

110_B, Low-Side Switch ON

111_B, High-Side Switch ON

GPIO1

2:0

rw

GPIO1 Configuration

000_B, FO2 selected

001_B, FO2 selected

010_B, FO2 selected

011_B, FO2 selected

100_B, OFF

101_B, Wake input enabled (16µs static filter)

110_B, Low-Side Switch ON

111_B, High-Side Switch ON

Note:

When selecting a filter time configuration, the user must make sure to also assign the respective

timer to at least one HS switch during cyclic sense operation

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PWM1_CTRL

PWM1 Configuration Control (Address 001 1000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0

r

rw

Field

Bits

Type

rw

Description

PWM1_DC

7:0

PWM1 Duty Cycle (bit0=LSB; bit7=MSB)

0000 0000_B, 100% OFF

xxxx xxxx _B, ON with DC fraction of 255

1111 1111_B, 100% ON

Note:

The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch,

e.g. the PWM setting ‘000 0001’ could not be realized.

PWM2_CTRL

PWM2 Configuration Control (Address 001 1001_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

PWM2_DC_7 PWM2_DC_6 PWM2_DC_5 PWM2_DC_4 PWM2_DC_3 PWM2_DC_2 PWM2_DC_1 PWM2_DC_0

r

rw

Field

Bits

Type

rw

Description

PWM2_DC

7:0

PWM2 Duty Cycle (bit0=LSB; bit7=MSB)

0000 0000_B, 100% OFF

xxxx xxxx_B, ON with DC fraction of 255

1111 1111_B, 100% ON

Note:

The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch,

e.g. the PWM setting ‘000 0001’ could not be realized.

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Serial Peripheral Interface

PWM_FREQ_CTRL

PWM Frequency Configuration Control (Address 001 1100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0x0x_B

7

6

5

4

3

2

1

0

Reserved

Reserved PWM2_FREQ Reserved PWM1_FREQ

r

rw

r

rw

Field

Bits

Type

Description

Reserved

7:3

2

r

Reserved, always reads as 0

PWM2_

FREQ

rw

PWM2 Frequency Selection

0_B, 200Hz configuration

1_B, 400Hz configuration

Reserved

1

0

r

Reserved, always reads as 0

PWM1_

FREQ

rw

PWM1 Frequency Selection

0_B, 200Hz configuration

1_B, 400Hz configuration

Notes

1. The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g. the

PWM setting ‘000 0001’ could not be realized.

2. The actual PWM frequency correlates with the internal clock tolerance as specified in parameter f_CLKSBC

.

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

SYS_STATUS_CTRL

System Status Control (Address 001 1110_B)

POR Value: 0000 0000_B;

Restart Value/Soft Reset Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

SYS_STAT_7 SYS_STAT_6 SYS_STAT_5 SYS_STAT_4 SYS_STAT_3 SYS_STAT_2 SYS_STAT_1 SYS_STAT_0

r

rw

Field

Bits

Type

rw

Description

SYS_STAT

7:0

System Status Control Byte (bit0=LSB; bit7=MSB)

Dedicated byte for system configuration, access only by

microcontroller. Cleared after power up and Soft Reset

Notes

1. The SYS_STATUS_CTRL register is an exception for the default values, i.e. it will keep its configured value also

after a Soft Reset.

2. This byte is intended for storing system configurations of the ECU by the microcontroller and is only accessible

in SBC Normal Mode. The byte is not accessible by the SBC and is also not cleared after Fail-Safe or SBC

Restart Mode. It allows the microcontroller to quickly store system configuration without loosing the data.

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Serial Peripheral Interface

16.5.2

Selective Wake Control Registers

SWK_CTRL

CAN Selective Wake Control (Address 010 0000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx 0000_B

7

6

5

4

3

2

1

0

CANTO_

MASK

OSC_CAL

TRIM_EN_1 TRIM_EN_0

rw rw

Reserved

CFG_VAL

r

rw

r

rwh

Field

Bits

Type

Description

OSC_CAL

7

rw

Oscillator Calibration Mode

0_B, Oscillator Calibration is disabled

1_B, Oscillator Calibration is enabled

TRIM_EN

6:5

4

rw

(Un)locking mechanism of oscillator recalibration

00_B, locked

01_B, locked

10_B, locked

11_B, unlocked

CANTO_

MASK

rw

CAN Time Out Masking

0_B, CAN time-out is masked - no interrupt (on pin INT) is

triggered

1_B, CAN time-out is signaled on INT

Reserved

CFG_VAL

3:1

0

r

Reserved, always reads as 0

rwh

SWK Configuration valid

0_B, Configuration is not valid (SWK not possible)

1_B, SWK configuration valid, needs to be set to enable SWK

Notes

1. TRIM_EN unlocks the oscillation calibration mode. Only the bit combination ‘11’ is the valid unlock. The pin

TXDCAN is used for oscillator synchronisation (trimming).

2. The microcontroller needs to validate the SWK configuration and set ‘CFG_VAL’ to ‘1’. The SBC will only enable

SWK if CFG_VAL’ to ‘1’. The bit will be cleared automatically by the SBC after a wake up or POR or if a SWK

configuration data is changed by the microcontroller.

3. CANTO bit will only be updated inside BUS_STAT while CAN_2 is set. Therefore, an interrupt is only signaled

upon occurrence of CANTO while CAN_2 (SWK is enabled) is set in SBC Normal and Stop Mode.

4. TRIM_EN also unlocks the writing to the SWK_OPT_CTRL register in order to enable the alternate low-power

Receiver for Selective wake to optimize the quiescent current consumption. Only the bit combination ‘11’

unlocks the calibrations / configurations.

5. In SBC stop-mode, any write command to a CAN or SWK configuration register will lead to CFG_VAL be set to

‘0’ (SWK becomes invalid).

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Serial Peripheral Interface

SWK_BTL1_CTRL

SWK Bit Timing Logic Control1 (Address 010 0001_B)

POR / Soft Reset Value: 1010 0000_B;

Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

TBIT_7

TBIT_6

TBIT_5

TBIT_4

TBIT_3

TBIT_2

TBIT_1

TBIT_0

r

rw

Field

TBIT

Bits

7:0

Type

rw

Description

Number of Time Quanta in a Bit Time

Represents the number of time quanta in a bit time.

Quanta is depending on SEL_OSC_CLK<1:0> from the

SWK_CDR_CTRL2 register.

SWK_BTL2_CTRL

SWK Bit Timing Control2 (Address 010 0010_B)

POR / Soft Reset Value: 0011 0011_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

reserved

SP_5

SP_4

SP_3

SP_2

SP_1

SP_0

r

rw

Field

Bits

Type

Description

Reserved

SP

7:6

5:0

r

Reserved, always reads as 0

rw

Sampling Point Position

Represents the sampling point position (fractional number < 1).

Example: 0011 0011 = 0.796875 (~80%)

SWK_ID3_CTRL

SWK WUF Identifier bits 28...21 (Address 010 0011_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

r

rw

Field

Bits

7:0

Type

rw

Description

ID28_21

WUF Identifier Bits 28...21

Note:

Please note the configuration of the standard identifier and extended identifier. The standard

identifier is configured to the bits ID18...ID28

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OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

SWK_ID2_CTRL

SWK WUF Identifier bits 20...13 (Address 010 0100_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

ID20

ID19

ID18

ID17

ID16

ID15

ID14

ID13

r

rw

Field

ID20_13

Bits

7:0

Type

rw

Description

WUF Identifier Bits 20...13

SWK_ID1_CTRL

SWK WUF Identifier bits 12...5 (Address 010 0101_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

ID12

ID11

ID10

ID9

ID8

ID7

ID6

ID5

r

rw

Field

Bits

7:0

Type

rw

Description

ID12_5

WUF Identifier Bits 12...5

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Serial Peripheral Interface

SWK_ID0_CTRL

SWK WUF Identifier bits 4...0 (Address 010 0110_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 0xxx xxxx_B

7

6

5

4

3

2

1

0

reserved

ID4

ID3

ID2

ID1

ID0

RTR

IDE

r

rw

Field

Bits

7

Type

Description

Reserved

ID4_0

r

Reserved, always reads as 0

WUF Identifier Bits 4..0

6:2

1

rw

RTR

Remote Transmission Request Field (acc. ISO 11898-1)

0_B, Normal Data Frame

1_B, Remote Transmission Request

IDE

0

rw

Identifier Extension Bit

0_B, Standard Identifier Length (11 bit)

1_B, Extended Identifier Length (29 bit)

Note:

The setting RTR = 1 is not allowed for wake-up frames according to the ISO11898-2:2016

SWK_MASK_ID3_CTRL

SWK WUF Identifier Mask bits 28...21 (Address 010 0111_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

MASK_ID28 MASK_ID27 MASK_ID26 MASK_ID25 MASK_ID24 MASK_ID23 MASK_ID22 MASK_ID21

r

rw

Field

Bits

Type

rw

Description

MASK_ID28 7:0

WUF Identifier Mask Bits 28...21

_21

0_B, Unmasked - bit is ignored

1_B, Masked - bit is compared in CAN frame

Note:

Masking WUF bits is done by setting the respective MASK bit to ‘1’

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Serial Peripheral Interface

SWK_MASK_ID2_CTRL

SWK WUF Identifier Mask bits 20...13 (Address 010 1000_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

MASK_ID20 MASK_ID19 MASK_ID18 MASK_ID17 MASK_ID16 MASK_ID15 MASK_ID14 MASK_ID13

r

rw

Field

Bits

Type

rw

Description

MASK_ID20 7:0

WUF Identifier Mask Bits 20...13

_13

0_B, Unmasked - bit is ignored

1_B, Masked - bit is compared in CAN frame

SWK_MASK_ID1_CTRL

SWK WUF Identifier Mask bits 12...5 (Address 010 1001_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

MASK_ID12 MASK_ID11 MASK_ID10 MASK_ID9

MASK_ID8

MASK_ID7

MASK_ID6

MASK_ID5

r

rw

Field

Bits

Type

rw

Description

MASK_ID12 7:0

WUF Identifier Mask Bits 12...5

_5

0_B, Unmasked - bit is ignored

1_B, Masked - bit is compared in CAN frame

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Serial Peripheral Interface

SWK_MASK_ID0_CTRL

SWK WUF Identifier bits 4...0 (Address 010 1010_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 0xxx xx00_B

7

6

5

4

3

2

1

0

Reserved

MASK_ID4

MASK_ID3

MASK_ID2

MASK_ID1

MASK_ID0

Reserved

r

rw

r

Field

Bits

Type

r

Description

Reserved

7

Reserved, always reads as 0

MASK_

ID4_0

6:2

rw

WUF Identifier MASK Bits 4..0

0_B, Unmasked - bit is ignored

1_B, Masked - bit is compared in CAN frame

Reserved

1:0

r

Reserved, always reads as 0

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Serial Peripheral Interface

SWK_DLC_CTRL

SWK Frame Data Length Code Control (Address 010 1011_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 0000 xxxx_B

7

6

5

4

3

2

1

0

Reserved

DLC_3

DLC_2

DLC_1

DLC_0

r

rw

Field

Bits

Type

Description

Reserved

DLC

7:4

3:0

r

Reserved, always reads as 0

rw

Payload length in number of bytes

0000_B, Frame Data Length = 0 or cleared

0001_B, Frame Data Length = 1

0010_B, Frame Data Length = 2

0011_B, Frame Data Length = 3

0100_B, Frame Data Length = 4

0101_B, Frame Data Length = 5

0110_B, Frame Data Length = 6

0111_B, Frame Data Length = 7

from 1000_Bto 1111_BFrame Data Length = 8

Note:

The number of bytes in the data field has to be indicated by the DLC. The DLC consists of four bits.

The admissible number of data bytes for a data frame ranges from zero to eight. DLCs in the range

of zero to seven shall indicate data fields of length of zero to seven bytes. DLCs in the range from

eight to fifteen indicate data fields of length of eight byte. The configured DLC value has to match bit

by bit with the DLC in the received wake-up frame (refer also to Chapter 5.4.2.3).

SWK_DATA7_CTRL

SWK Data7 Register (Address 010 1100_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

DATA7_7

DATA7_6

DATA7_5

DATA7_4

DATA7_3

DATA7_2

DATA7_1

DATA7_0

r

rw

Field

Bits

7:0

Type

rw

Description

DATA7

Data7 byte content(bit0=LSB; bit7=MSB)

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Serial Peripheral Interface

SWK_DATA6_CTRL

SWK Data6 Register (Address 010 1101_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

DATA6_7

DATA6_6

DATA6_5

DATA6_4

DATA6_3

DATA6_2

DATA6_1

DATA6_0

r

rw

Field

DATA6

Bits

7:0

Type

rw

Description

Data6 byte content (bit0=LSB; bit7=MSB)

SWK_DATA5_CTRL

SWK Data5 Register (Address 010 1110_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

DATA5_7

DATA5_6

DATA5_5

DATA5_4

DATA5_3

DATA5_2

DATA5_1

DATA5_0

r

rw

Field

DATA5

Bits

7:0

Type

rw

Description

Data5 byte content (bit0=LSB; bit7=MSB)

SWK_DATA4_CTRL

SWK Data4 Register (Address 010 1111_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

DATA4_7

DATA4_6

DATA4_5

DATA4_4

DATA4_3

DATA4_2

DATA4_1

DATA4_0

r

rw

Field

Bits

7:0

Type

rw

Description

DATA4

Data4 byte content (bit0=LSB; bit7=MSB)

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Serial Peripheral Interface

SWK_DATA3_CTRL

SWK Data3 Register (Address 011 0000_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

DATA3_7

DATA3_6

DATA3_5

DATA3_4

DATA3_3

DATA3_2

DATA3_1

DATA3_0

r

rw

Field

DATA3

Bits

7:0

Type

rw

Description

Data3 byte content (bit0=LSB; bit7=MSB)

SWK_DATA2_CTRL

SWK Data2 Register (Address 011 0001_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

DATA2_7

DATA2_6

DATA2_5

DATA2_4

DATA2_3

DATA2_2

DATA2_1

DATA2_0

r

rw

Field

DATA2

Bits

7:0

Type

rw

Description

Data2 byte content (bit0=LSB; bit7=MSB)

SWK_DATA1_CTRL

SWK Data1 Register (Address 011 0010_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

DATA1_7

DATA1_6

DATA1_5

DATA1_4

DATA1_3

DATA1_2

DATA1_1

DATA1_0

r

rw

Field

Bits

7:0

Type

rw

Description

DATA1

Data1 byte content (bit0=LSB; bit7=MSB)

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Serial Peripheral Interface

SWK_DATA0_CTRL

SWK Data0 Register (Address 011 0011_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

DATA0_7

DATA0_6

DATA0_5

DATA0_4

DATA0_3

DATA0_2

DATA0_1

DATA0_0

r

rw

Field

Bits

7:0

Type

rw

Description

DATA0

Data0 byte content (bit0=LSB; bit7=MSB)

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Serial Peripheral Interface

SWK_CAN_FD_CTRL

CAN FD Configuration Control Register (Address 011 0100_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 00xx xxxx_B

7

6

5

4

3

2

1

0

DIS_ERR_

CNT

Reserved

RX_FILT_BYP FD_FILTER_2 FD_FILTER_1 FD_FILTER_0 CAN_FD_EN

r

rwh

rw

Field

Bits

Type

r

Description

Reserved

7:6

5

Reserved, always reads as 0

DIS_ERR_

CNT

rwh

Error Counter Disable Function

0_B, Error Counter is enabled during SWK

1_B, Error counter is disabled during SWK only if CAN_FD_EN = ‘1’

RX_FILT_

BYP

4

rw

RX Receiver Filter Bypass

0_B, RX Filter not bypassed

1_B, RX Filter bypassed

FD_FILTER 3:1

CAN FD Dominant Filter Time

000_B, 50 ns

001_B, 100 ns

010_B, 150 ns

011_B, 200 ns

100_B, 250 ns

101_B, 300 ns

110_B, 350 ns

111_B, 775 ns

CAN_FD_

EN

0

rw

Enable CAN FD Tolerant Mode

0_B, CAN FD Tolerant Mode disabled

1_B, CAN FD Tolerant Mode enabled

Note:

The bit RX_FILT_ BYP is bypassing the analog filter in the CAN receiver path; The FD_FILTER is not

in the analog path of the CAN receiver and is not bypassed.

DIS_ERR_ CNT is cleared by the SBC at tsilence expiration.

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Serial Peripheral Interface

16.5.3

Selective Wake Trimming and Calibration Control Registers

SWK_OSC_TRIM_CTRL

SWK Oscillator Trimming Register (Address 011 1000_B)

POR / Soft Reset Value: xxxx xxxx_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

TRIM_OSC_7 TRIM_OSC_6 TRIM_OSC_5 TRIM_OSC_4 TRIM_OSC_3 TRIM_OSC_2 TRIM_OSC_1 TRIM_OSC_0

r

rw

Field

Bits

Type

rw

Description

TRIM_OSC 7:0

Oscillator trimming (bit0=LSB; bit7=MSB);

(only writable if TRIM_EN = ‘11’)

Note:

TRIM_OSC[0:4] represent the 32-steps fine trimming range with a monotonous behavior from slower

to faster frequency. The step width is ~0.25MHz.

TRIM_OSC[5:7] are modifying the oscillator temperature coefficient. It is strongly recommended to

not change these values.

Due to CDR functionality, it is not required to change these values.

SWK_OPT_CTRL

Selective Wake Options Register (Address 011 1001_B)

POR / Soft Reset Value: 000x xxxx_B;

Restart Value: x00x xxxx_B

7

6

5

4

3

2

1

0

TRIM_OSC_1 TRIM_OSC_1 TRIM_OSC_1

RX_WK_SEL

Reserved

TRIM_OSC_9 TRIM_OSC_8

2

1

0

r

rw

r

rw

Field

Bits

Type

Description

RX_WK_

SEL

7

rw

SWK Receiver selection (only accessible if TRIM_EN = ‘11’)

0_B, Standard Receiver selected during SWK

1_B, Low-Power Receiver selected during SWK

Reserved

6:5

r

Reserved, always reads as 0

TRIM_OSC 4:0

rw

Oscillator trimming (bit8=LSB; bit12=MSB);

(only writable if TRIM_EN = ‘11’)

Notes

1. The bit RX_WK_SEL is used to select the respective receiver during Selective Wake operation. To reduce the

quiescent current during Frame Detect Mode it is recommended to select the Low-Power Receiver, i.e.

RX_WK_SEL = ‘1’.

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Serial Peripheral Interface

Important: If the RX_WK_SEL bit is changed, then it must be ensured that the values of TRIM_OSC [8:12] bits

remain unchanged to avoid a change of oscillator frequency.

2. TRIM_OSC[8:12] represent the 32-steps coarse trimming range, which is not monotonous.

It is not recommended to change these values.

SWK_OSC_CAL_H_STAT

SWK Oscillator Calibration High Register (Address 011 1010_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

OSC_CAL_

H_7

OSC_CAL_

H_6

OSC_CAL_

H_5

OSC_CAL_

H_4

OSC_CAL_

H_3

OSC_CAL_

H_2

OSC_CAL_

H_1

OSC_CAL_

H_0

r

Field

Bits

Type

Description

OSC_CAL_ 7:0

r

Oscillator Calibration High Register

H

SWK_OSC_CAL_L_STAT

SWK Oscillator Calibration Low Register (Address 011 1011_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

OSC_CAL_

L_7

OSC_CAL_

L_6

OSC_CAL_

L_5

OSC_CAL_

L_4

OSC_CAL_

L_3

OSC_CAL_

L_2

OSC_CAL_

L_1

OSC_CAL_

L_0

r

Field

Bits

Type

Description

OSC_CAL_L 7:0

r

Oscillator Calibration Low Register

SWK_CDR_CTRL1

CDR Control 1 Register (Address 011 1100_B)

POR / Soft Reset Value: 0000 0100_B; Restart Value: 0000 xx0x_B

7

6

5

4

3

2

1

0

Reserved

SEL_FILT_1 SEL_FILT_0

rw rw

Reserved

CDR_EN

r

rw

Field

Bits

7:4

Type

Description

Reserved

r

Reserved, always reads as 0

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Serial Peripheral Interface

Field

Bits

Type

Description

SEL_FILT

3:2

rw

Select Time Constant of Filter

00_B, Time constant 8

01_B, Time constant 16 (default)

10_B, Time constant 32

11_B, adapt

distance between falling edges 2, 3 bit: Time constant 32

distance between f. edges 4, 5, 6, 7, 8 bit: Time constant 16

distance between falling edges 9, 10 bit: Time constant 8

Reserved

CDR_EN

1

0

r

Reserved, always reads as 0

rw

Enable CDR

0_B, CDR disabled

1_B, CDR enabled

SWK_CDR_CTRL2

CDR Control 2Register (Address 011 1101_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 0000 00xx_B

7

6

5

4

3

2

1

0

SEL_OSC_CL SEL_OSC_CL

Reserved

K_1

K_0

r

rw

Field

Reserved

Bits

7:2

Type

Description

r

Reserved, always reads as 0

SEL_OSC_C 1:0

rw

Input Frequency for CDR module

LK

See Table 37 and Table 38.

Table 37

Frequency Settings of Internal Clock for the CDR

SEL_OSC_CLK[1:0]

int. Clock for CDR

80 MHz

00

01

10

11

40 MHz

20 MHz

10 MHz

Table 38

Recommended CDR Settings for Different Baud Rates

Baudrate SWK_BTL1_CTRL Value SWK_CDR_LIMIT_HIGH SWK_CDR_LIMIT_LOW_

SEL_OSC_CLK

[1:0]

_CTRL Value

1010 1000

0101 0100

CTRL Value

1001 1000

0100 1100

00

01

10

500k

1010 0000

0101 0000

CDR Setting not recommended for this baudrate due to insufficient precision

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Table 38

Recommended CDR Settings for Different Baud Rates (cont’d)

Baudrate SWK_BTL1_CTRL Value SWK_CDR_LIMIT_HIGH SWK_CDR_LIMIT_LOW_

_CTRL Value CTRL Value

SEL_OSC_CLK

[1:0]

11

00

01

10

11

00

01

10

11

500k

250k

125k

CDR Setting not recommended for this baudrate due to insufficient precision

CDR Setting not to be used due to excessive time quanta (counter overflow)

1010 0000

0101 0000

1010 1000

0101 0100

1001 1000

0100 1100

CDR Setting not recommended for this baudrate due to insufficient precision

CDR Setting not to be used due to excessive time quanta (counter overflow)

1010 0000

0101 0000

1010 1000

0101 0100

1001 1000

0100 1100

SWK_CDR_LIMIT_HIGH_CTRL

SWK CDR Upper Limit Control (Address 011 1110_B)

POR / Soft Reset Value: 1010 1000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

CDR_LIM_

H_7

CDR_LIM_

H_6

CDR_LIM_

H_5

CDR_LIM_

H_4

CDR_LIM_

H_3

CDR_LIM_

H_2

CDR_LIM_

H_1

CDR_LIM_

H_0

r

rw

Field

Bits

Type

Description

CDR_LIM_H 7:0

rw

Upper Bit Time Detection Range of Clock and Data Recovery

SWK_BTL1_CTRL values > + 5% will be clamped

SWK_CDR_LIMIT_LOW_CTRL

SWK CDR Lower Limit Control (Address 011 1111_B)

POR / Soft Reset Value: 1001 1000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

CDR_LIM_

L_7

CDR_LIM_

L_6

CDR_LIM_

L_5

CDR_LIM_

L_4

CDR_LIM_

L_3

CDR_LIM_

L_2

CDR_LIM_

L_1

CDR_LIM_

L_0

r

rw

Field

Bits

Type

Description

CDR_LIM_L 7:0

rw

Lower Bit Time Detection Range of Clock and Data Recovery

SWK_BTL1_CTRL values < - 5% will be clamped

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16.6

SPI Status Information Registers

READ/CLEAR Operation (see also Chapter 16.3):

•

One 16-bit SPI command consist of two bytes:

- the 7-bit address and one additional bit for the register access mode and

- following the data byte

The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to

the SPI bits 8...15 (see also figure).

•

There are two different bit types:

- ‘r’ = READ: read only bits (or reserved bits)

- ‘rc’ = READ/CLEAR: readable and clearable bits

•

Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only)

Clearing a register is done byte wise by setting the SPI bit 7 to “1”

SPI status registers are in general not cleared or changed automatically (an exception are the WD_FAIL

bits). This must be done by the microcontroller via SPI command

The registers are addressed wordwise.

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16.6.1

General Status Registers

SUP_STAT_2

Supply Voltage Fail Status (Address 100 0000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0x0x xxxx_B

7

6

5

4

3

2

1

0

Reserved

VS_UV

Reserved

VCC3_OC

VCC3_UV

VCC3_OT

VCC1_OV

VCC1_WARN

r

rc

r

rc

Field

Bits

Type

Description

Reserved

VS_UV

7

6

r

Reserved, always reads as 0

rc

VS Undervoltage Detection (V_S,UV)

0_B, No VS undervoltage detected

1_B, VS undervoltage detected

Reserved

VCC3_OC

5

4

r

Reserved, always reads as 0

rc

VCC3 Overcurrent Detection

0_B, No OC

1_B, OC detected

VCC3_UV

VCC3_OT

3

2

1

0

rc

VCC3 Undervoltage Detection

0_B, No VCC3 UV detection

1_B, VCC3 UV Fail detected

VCC3 Overtemperature Detection

0_B, No overtemperature

1_B, VCC3 overtemperature detected

VCC1_

OV

VCC1 Overvoltage Detection (V_CC1,OV,r

0_B, No VCC1 overvoltage warning

1_B, VCC1 overvoltage detected

)

VCC1_

WARN

VCC1 Undervoltage Prewarning (V_PW,f

0_B, No VCC1 undervoltage prewarning

1_B, VCC1 undervoltage prewarning detected

)

Notes

1. The VCC1 undervoltage prewarning threshold V_PW,f/ V_PW,ris a fixed threshold and independent of the VCC1

undervoltage reset thresholds.

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SUP_STAT_1

Supply Voltage Fail Status (Address 100 0001_B)

POR / Soft Reset Value: y000 0000_B;

Restart Value: xxxx xx0x_B

7

6

5

4

3

2

1

0

POR

VSHS_UV

VSHS_OV

VCC2_OT

VCC2_UV

VCC1_SC VCC1_UV_FS VCC1_UV

r

rc

Field

Bits

Type

Description

POR

7

6

5

4

3

2

1

0

rc

Power-On Reset Detection

0_B, No POR

1_B, POR occurred

VSHS_UV

VSHS_OV

VCC2_OT

VCC2_UV

VCC1_SC

VSHS Undervoltage Detection (V_SHS,UVD

0_B, No VSHS-UV

1_B, VSHS-UV detected

)

VSHS Overvoltage Detection (V_SHS,OVD

0_B, No VSHS-OV

1_B, VSHS-OV detected

)

VCC2 Overtemperature Detection

0_B, No overtemperature

1_B, VCC2 overtemperature detected

VCC2 Undervoltage Detection (V_CC2,UV,f

0_B, No VCC2 undervoltage

1_B, VCC2 undervoltage detected

)

VCC1 Short to GND Detection (<Vrtx for t>4ms after switch on)

0_B, No short

1_B, VCC1 short to GND detected

VCC1_UV

_FS

VCC1 UV-Detection (due to Vrtx reset)

0_B, No Fail-Safe Mode entry due to 4th consecutive VCC1_UV

1_B, Fail-Safe Mode entry due to 4th consecutive VCC1_UV

VCC1_UV

VCC1 UV-Detection (due to Vrtx reset)

0_B, No VCC1_UV detection

1_B, VCC1 UV-Fail detected

Notes

1. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on

reset (POR value = 1000 0000). However it will be cleared after a SBC Soft Reset command (Soft Reset value =

0000 0000).

2. During Sleep Mode, the bits VCC1_SC,VCC1_OV and VCC1_UV will not be set when VCC1 is off

3. The VCC1_UV bit is never updated in SBC Restart Mode, in SBC Init Mode it is only updated after RO was

released for the first time, it is always updated in SBC Normal and Stop Mode, and it is always updated in any

SBC modes in a VCC1_SC condition (after VCC1_UV = 1 for >4ms).

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THERM_STAT

Thermal Protection Status (Address 100 0010_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0xxx_B

7

6

5

4

3

2

1

0

Reserved

TSD2

TSD1

TPW

r

rc

Field

Bits

Type

Description

Reserved

TSD2

7:3

2

r

Reserved, always reads as 0

rc

TSD2 Thermal Shut-Down Detection

0_B, No TSD2 event

1_B, TSD2 OT detected - leading to SBC Fail-Safe Mode

TSD1

TPW

1

0

rc

TSD1 Thermal Shut-Down Detection

0_B, No TSD1 fail

1_B, TSD1 OT detected

Thermal Pre Warning

0_B, No Thermal Pre warning

1_B, Thermal Pre warning detected

Note:

TSD1 and TSD2 are not reset automatically, even if the temperature pre warning or TSD1 OT

condition is not present anymore. Also TSD2 is not reset.

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DEV_STAT

Device Information Status (Address 100 0011_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xx00 xxxx_B

7

6

5

4

3

2

1

0

DEV_STAT_1 DEV_STAT_0 Reserved

rc rc

Reserved

WD_FAIL_1 WD_FAIL_0

rh rh

SPI_FAIL

FAILURE

r

rc

Field

Bits

Type

Description

DEV_STAT 7:6

rc

Device Status before Restart Mode

00_B, Cleared (Register must be actively cleared)

01_B, Restart due to failure (WD fail, TSD2, VCC1_UV); also after a

wake from Fail-Safe Mode

10_B, Sleep Mode

11_B, Reserved

Reserved

WD_FAIL

5:4

3:2

r

Reserved, always reads as 0

rh

Number of WD-Failure Events (1/2 WD failures depending on

CFG)

00_B, No WD Fail

01_B, 1x WD Fail, FOx activation - Config 2 selected

10_B, 2x WD Fail, FOx activation - Config 1 / 3 / 4 selected

11_B, Reserved (never reached)

SPI_FAIL

FAILURE

1

0

rc

SPI Fail Information

0_B, No SPI fail

1_B, Invalid SPI command detected

Activation of Fail Output FO

0_B, No Failure

1_B, Failure occurred

Notes

1. The bits DEV_STAT show the status of the device before it went through Restart. Either the device came from

regular Sleep Mode (‘10’) or a failure (‘01’ - SBC Restart or SBC Fail-Safe Mode: WD fail, TSD2 fail, VCC_UV fail

or VCC1_OV if bit VCC1_OV_RST is set) occurred. Failure is also an illegal command from SBC Stop to SBC

Sleep Mode or going to SBC Sleep Mode without activation of any wake source. Coming from SBC Sleep Mode

(‘10’) will also be shown if there was a trial to enter SBC Sleep Mode without having cleared all wake flags

before.

2. The WD_FAIL bits are configured as a counter and are the only status bits, which are cleared automatically

by the SBC. They are cleared after a successful watchdog trigger and when the watchdog is stopped (also in

SBC Sleep and Fail-Safe Mode unless it was reached due to a watchdog failure). See also Chapter 14.1.

3. The SPI_FAIL bit is cleared only by SPI command

4. In case of Config 2/4 the WD_Fail counter is frozen in case of WD trigger failure until a successful WD trigger.

5. If CFG = ‘0’ then a 1st watchdog failure will not trigger the FO outputs or the FAILURE bit but only force the SBC

into SBC Restart Mode.

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BUS_STAT_1

Bus Communication Status (Address 100 0100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0xxx xxxx_B

7

6

5

4

3

2

1

0

Reserved LIN1_FAIL_1 LIN1_FAIL_0

rc rc

CANTO

SYSERR

CAN_FAIL_1 CAN_FAIL_0

VCAN_UV

r

rc

Field

Bits

7

Type

Description

Reserved

LIN1_FAIL

r

Reserved, always reads as 0

6:5

rc

LIN1 Failure Status

00_B, No error

01_B, LIN1 TSD

10_B, LIN1_TXD_DOM: TXD dominant time out for more than 20ms

11_B, LIN1_BUS_DOM: BUS dominant time out for more than

20ms

CANTO

4

rc

CAN Time Out Detection

0_B, Normal operation

1_B, CAN Time Out detected

SYSERR

CAN_FAIL

3

SWK System Error

0_B, Selective Wake Mode is possible

1_B, System Error detected, SWK enabling not possible

2:1

CAN Failure Status

00_B, No error

01_B, CAN TSD shutdown

10_B, CAN_TXD_DOM: TXD dominant time out for longer than

t_{TxD_CAN_TO}

11_B, CAN_BUS_DOM: BUS dominant time out for longer than

t_{TxD_CAN_TO}

VCAN_UV

Notes

0

rc

Undervoltage CAN Bus Supply

0_B, Normal operation

1_B, CAN Supply undervoltage detected. Transmitter disabled

1. CAN and LIN Recovery Conditions:

1.) TXD Time Out: TXD goes HIGH or transmitter is set to wake capable or switched off;

2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.

3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VSHS > VS_UV for LIN and VCAN >

VCAN_UV for CAN

4.)In all cases (also for TSD shutdown): to enable the Bus transmission again, TXD needs to be HIGH for a

certain time (transmitter enable time).

2. The VCAN_UV comparator is enabled if the mode bit CAN_1 = ‘1’, i.e. in CAN Normal or CAN Receive Only Mode.

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3. CANTO will be set only if CAN2 = 1 (=SWK Mode enabled). It will be set as soon as CANSIL was set and will stay

set even in CANSIL it is reset. An interrupt is issued in SBC Stop- and SBC Normal Mode as soon as CANTO is set

and the interrupt is not masked out, i.e. CANTO_MASK must be set to 1.

4. The SYSERR Flag is set in case of a configuration error and in case of an error counter overflow (n>32).

It is only updated if SWK is enabled (CAN_2 = ‘1’). See also Chapter 5.4.3.

5. CANTO is set asynchronously to the INT pulse. In order to prevent undesired clearing of CANTO and thus

possibly missing this interrupt, the bit will be prevented from clearing (i.e. cannot be cleared) until the next

falling edge of INT.

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BUS_STAT_2

Bus Communication Status (Address 100 0101_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0xx0_B

7

6

5

4

3

2

1

0

Reserved

Reserved LIN2_FAIL_1 LIN2_FAIL_0 Reserved

r

rc

r

Field

Bits

Type

Description

Reserved

LIN2_FAIL

7:3

2:1

r

Reserved, always reads as 0

rc

LIN2 Failure Status

00_B, No error

01_B, LIN2 TSD shutdown

10_B, LIN2_TXD_DOM: TXD dominant time out for more than 20ms

11_B, LIN2_BUS_DOM: BUS dominant time out for more than

20ms

Reserved

0

r

Reserved, always reads as 0

Note:

CAN and LINx Recovery Conditions:

1.) TXD Time Out: TXD goes High or transmitter is set to wake capable or switched off;

2.). Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or

switched off.

3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VSHS > VS_UV for LINx and

VCAN > VCAN_UV for CAN

4.) In all cases (also for TSD shutdown): to enable the Bus transmission again, TXD needs to be HIGH

for a certain time (transmitter enable time).

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WK_STAT_1

Wake-up Source and Information Status (Address 100 0110_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx 0xxx_B

7

6

5

4

3

2

1

0

LIN2_WU

LIN1_WU

CAN_WU

TIMER_WU

Reserved

WK3_WU

WK2_WU

WK1_WU

r

rc

r

rc

Field

Bits

Type

Description

LIN2_WU

LIN1_WU

CAN_WU

TIMER_WU

7

6

5

4

rc

Wake up via LIN2 Bus

0_B, No Wake up

1_B, Wake up

Wake up via LIN1 Bus

0_B, No Wake up

1_B, Wake up

Wake up via CAN Bus

0_B, No Wake up

1_B, Wake up

Wake up via TimerX

0_B, No Wake up

1_B, Wake up

Reserved

WK3_WU

3

2

r

Reserved, always reads as 0

rc

Wake up via WK3

0_B, No Wake up

1_B, Wake up

WK2_WU

WK1_WU

1

0

rc

Wake up via WK2

0_B, No Wake up

1_B, Wake up

Wake up via WK1

0_B, No Wake up

1_B, Wake up

Note:

The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode

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WK_STAT_2

Wake-up Source and Information Status (Address 100 0111_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00xx 0000_B

7

6

5

4

3

2

1

0

Reserved

GPIO2_WU GPIO1_WU

Reserved

r

rc

r

Field

Bits

Type

Description

Reserved

7:6

5

r

Reserved, always reads as 0

GPIO2_WU

rc

Wake up via GPIO2

0_B, No Wake up

1_B, Wake up

GPIO1_WU

Reserved

4

rc

r

Wake up via GPIO1

0_B, No Wake up

1_B, Wake up

3:0

Reserved, always reads as 0

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WK_LVL_STAT

WK Input Level (Address 100 1000_B)

POR / Soft Reset Value: xx00 0xxx_B;

Restart Value: xxxx 0xxx_B

7

6

5

4

3

2

1

0

SBC_DEV

_LVL

CFGP

GPIO2_LVL GPIO1_LVL

Reserved

WK3_LVL

WK2_LVL

WK1_LVL

r

Field

Bits

Type

Description

SBC_DEV

_LVL

7

6

5

4

r

Status of SBC Operating Mode at FO3/TEST Pin

0_B, User Mode activated

1_B, SBC Development Mode activated

CFGP

r

Device Configuration Status

0_B, No external pull-up resistor connected on INT (Config 2/4)

1_B, External pull-up resistor connected on INT (Config 1/3)

GPIO2_LVL

GPIO1_LVL

Status of GPIO2 (if selected as GPIO)

0_B, Low Level (=0)

1_B, High Level (=1)

Status of GPIO1 (if selected as GPIO)

0_B, Low Level (=0)

1_B, High Level (=1)

Reserved

WK3_LVL

3

2

r

Reserved, always reads as 0

Status of WK3

0_B, Low Level (=0)

1_B, High Level (=1)

WK2_LVL

WK1_LVL

1

0

r

Status of WK2

0_B, Low Level (=0)

1_B, High Level (=1)

Status of WK1

0_B, Low Level (=0)

1_B, High Level (=1)

Note:

GPIOx_LVL is updated in SBC Normal and Stop Mode if configured as wake input, low-side switch or

high-side switch.

In cyclic sense or wake mode, the registers contain the sampled level, i.e. the registers are updated

after every sampling. The GPIOs are not capable of cyclic sensing.

If selected as GPIO then the respective level is shown even if configured as low-side or high-side.

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HS_OC_OT_STAT

High-Side Switch Overload Status (Address 101 0100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 xxxx_B

7

6

5

4

3

2

1

0

Reserved

HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT

r

rc

Field

Reserved

Bits

7:4

Type

Description

r

Reserved, always reads as 0

HS4_OC_OT 3

HS3_OC_OT 2

HS2_OC_OT 1

HS1_OC_OT 0

rc

Overcurrent & Overtemperature Detection HS4

0_B, No OC or OT

1_B, OC or OT detected

rc

Overcurrent & Overtemperature Detection HS3

0_B, No OC or OT

1_B, OC or OT detected

Overcurrent & Overtemperature Detection HS2

0_B, No OC or OT

1_B, OC or OT detected

Overcurrent & Overtemperature Detection HS1

0_B, No OC or OT

1_B, OC or OT detected

Note:

The OC/OT bit might be set for V_POR,f< VS < 5.5V (see also Chapter 4.2)

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HS_OL_STAT

High-Side Switch Open-Load Status (Address 101 0101_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 xxxx_B

7

6

5

4

3

2

1

0

Reserved

HS4_OL

HS3_OL

HS2_OL

HS1_OL

r

rc

Field

Bits

Type

Description

Reserved

HS4_OL

7:4

3

r

Reserved, always reads as 0

rc

Open-Load Detection HS4

0_B, No OL

1_B, OL detected

HS3_OL

HS2_OL

HS1_OL

2

1

0

rc

Open-Load Detection HS3

0_B, No OL

1_B, OL detected

Open-Load Detection HS2

0_B, No OL

1_B, OL detected

Open-Load Detection HS1

0_B, No OL

1_B, OL detected

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16.6.2

Selective Wake Status Registers

SWK_STAT

Selective Wake Status (Address 111 0000_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 0x00 xxxx_B

7

6

5

4

3

2

1

0

Reserved

SYNC

Reserved

CANSIL

SWK_SET

WUP

WUF

r

Field

Bits

Type

Description

Reserved

SYNC

7

6

r

Reserved, always reads as 0

Synchronisation (at least one CAN frame without fail must have

been received)

0_B, SWK function not working or not synchronous to CAN bus

1_B, Valid CAN frame received, SWK function is synchronous to

CAN bus

Reserved

CANSIL

5:4

3

r

Reserved, always reads as 0

CAN Silent Time during SWK operation

0_B, tsilence not exceeded

1_B, set if tsilence is exceeded.

SWK_SET

WUP

2

1

0

r

Selective Wake Activity

0_B, Selective Wake is not active

1_B, Selective Wake is activated

Wake-up Pattern Detection

0_B, No WUP

1_B, WUP detected

WUF

SWK Wake-up Frame Detection (acc. ISO 11898-2:2016)

0_B, No WUF

1_B, WUF detected

Note:

SWK_SET is set to flag that the selective wake functionality is activated (SYSERR = 0, CFG_VAL = 1,

CAN_2 = 1). The selective wake function is activated via a CAN mode change, except if CAN = ‘100’.

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SWK_ECNT_STAT

SWK Status (Address 111 0001_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 00xx xxxx_B

7

6

5

4

3

2

1

0

Reserved

ECNT_5

ECNT_4

ECNT_3

ECNT_2

ECNT_1

ECNT_0

r

Field

Bits

Type

Description

Reserved

ECNT

7:6

5:0

r

Reserved, always reads as 0

SWK CAN Frame Error Counter

00 0000_B, No Frame Error

01 1111_B, 31 Frame Errors have been counted

10 0000_B, Error counter overflow - SWK function will be disabled

Note:

If a frame has been received that is valid according to ISO 11898-1 and the counter is not zero, then

the counter shall be decremented. If the counter has reached a value of 32, the following actions

shall be performed: Selective Wake function shall be disabled, SYSERR shall be set and CAN wake

capable function shall be enabled, which leads to a wake with the next WUP.

SWK_CDR_STAT1

CDR Status 1 Register (Address 111 0010_B)

POR / Soft Reset Value: 1010 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

N_AVG_11

N_AVG_10

N_AVG_9

N_AVG_8

N_AVG_7

N_AVG_6

N_AVG_5

N_AVG_4

r

Field

Bits

Type

Description

NAVG_SAT 7:0

r

Output Value from Filter Block

N_AVG is representing the integer part of the number of selected

input clock frequency per CAN bus bit.

N_AVG[11:4] e.g.160.75

Datasheet

197

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

SWK_CDR_STAT2

CDR Status 2 Register (Address 111 0011_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

N_AVG_3

N_AVG_2

N_AVG_1

N_AVG_0

reserved

r

Field

Bits

Type

Description

NAVG_SAT 7:4

r

Output Value from Filter Block

N_AVG is representing the fractional part of the number of selected

input clock frequency per CAN bus bit.

N_AVG[3:0] e.g.160.75

Reserved

3:0

r

Reserved, always reads as 0

Datasheet

198

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

16.6.3

Family and Product Information Register

FAM_PROD_STAT

Family and Product Identification Register (Address 111 1110_B)

POR / Soft Reset Value: 0111 yyyy _B; Restart Value: 0111 yyyy_B

7

6

5

4

3

2

1

0

FAM_3

FAM_2

FAM_1

FAM_0

PROD_3

PROD_2

PROD_1

PROD_0

r

Field

Bits

Type

Description

FAM

7:4

r

SBC Family Identifier (bit4=LSB; bit7=MSB)

0 010_B, DC/DC-SBC Family

0 011_B, Mid-Range SBC Family

0 100_B, Multi-CAN SBC Family

0 101_B, Lite-CAN SBC Family

0 111_B, Mid-Range+ SBC Family

x x x x_B, reserved for future products

PROD

Notes

3:0

r

SBC Product Identifier (bit0=LSB; bit3=MSB)

1. The actual default register value after POR, Soft Reset or Restart of PROD will depend on the respective

product. Therefore the value ‘y’ is specified.

2. SWK = Selective Wake feature in CAN Partial Networking standard

Datasheet

199

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

16.7

Electrical Characteristics

Table 39

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

SPI frequency

1)

Maximum SPI frequency

f_SPI,max

–

4.0

MHz

P_16.7.1

SPI Interface; Logic Inputs SDI, CLK and CSN

H-input Voltage Threshold

L-input Voltage Threshold

Hysteresis of input Voltage

V_IH

–

0.7*

V_CC1

V

–

P_16.7.2

P_16.7.3

P_16.7.4

V_IL

0.3*

V_CC1

–

1)

V_IHY

0.08 × 0.12 × 0.5 ×

V_CC1

Pull-up Resistance at pin CSN R_ICSN

20

40

80

kΩ

V_CSN= 0.7 x V_CC1

P_16.7.5

P_16.7.6

Pull-down Resistance at pin R_ICLK/SDI

20

40

80

V_SDI/CLK=

SDI and CLK

0.2 x V_CC1

1)

Input Capacitance at pin

CSN, SDI or CLK

C_I

–

10

–

pF

V

P_16.7.7

P_16.7.8

Logic Output SDO

H-output Voltage Level

V_SDOH

V_CC1

0.4

-

V_CC1

0.2

-

I_DOH= -1.6 mA

I_DOL= 1.6 mA

L-output Voltage Level

Tristate Leakage Current

V_SDOL

I_SDOLK

–

0.2

–

0.4

10

V

P_16.7.9

-10

µA

V_CSN= V_CC1

;

P_16.7.10

0 V < V_DO< V_CC1

1)

Tristate Input Capacitance

Data Input Timing¹⁾

Clock Period

C_SDO

–

10

15

pF

P_16.7.11

t_pCLK

t_CLKH

t_CLKL

t_bef

250

125

250

125

100

50

–

ns

–

P_16.7.12

P_16.7.13

P_16.7.14

P_16.7.15

P_16.7.16

P_16.7.17

P_16.7.18

P_16.7.19

P_16.7.20

P_16.7.21

Clock High Time

–

Clock Low Time

–

Clock Low before CSN Low

CSN Setup Time

–

t_lead

t_lag

–

CLK Setup Time

–

Clock Low after CSN High

SDI Set-up Time

t_beh

–

t_DISU

t_DIHO

–

SDI Hold Time

–

Input Signal Rise Time at pin t_rIN

–

50

SDI, CLK and CSN

Datasheet

200

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Serial Peripheral Interface

Table 39

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V, T_j= -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Input Signal Fall Time at pin t_fIN

–

50

ns

–

P_16.7.22

SDI, CLK and CSN

Delay Time for Mode

Changes²⁾

t_Del,Mode

–

3

–

6

–

µs

includes internal P_16.7.23

oscillator

tolerance

CSN High Time

t_CSN(high)

µs

–

P_16.7.24

Data Output Timing¹⁾

SDO Rise Time

t_rSDO

–

30

–

80

50

ns

C_L= 100 pF

P_16.7.25

P_16.7.26

P_16.7.27

SDO Fall Time

t_fSDO

C_L= 100 pF

SDO Enable Time

SDO Disable Time

SDO Valid Time

t_ENSDO

t_DISSDO

t_VASDO

low impedance

–

high impedance P_16.7.28

–

C_L= 100 pF

P_16.7.29

1) Not subject to production test; specified by design

2) Applies to all mode changes triggered via SPI commands

24

CSN

15

16

17

18

13

14

CLK

SDI

19

20

LSB

MSB

not defined

27

28

29

SDO

Flag

LSB

MSB

Figure 63 SPI Timing Diagram

Note:

Numbers in drawing correlate to the last 2 digits of the Number field in the Electrical Characteristics

table.

Datasheet

201

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Application Information

17

Application Information

17.1

Application Diagram

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

VBAT

T₂

V_CC3

VS

R₁₂

D₁

VBAT

C₁

C₁₃

D₂

C₂

Q1

Q2

Q1

Q2

IC1

V_CC

C₃

C₁₄

GND

R₈

VCC3REF

VCC3SH

V_S

VS

VCC3B

VSHS

V_CC1

VCC1

VCC2

D₃

V_CC2

C₅

C₇

C₄

HS1

HS2

HS3

R₉

C₆

V_S

VSHS

C₁₇

CSN

V_DD

CSN

CLK

SDI

R₇

CLK

SDI

µC

D₄

SDO

C₁₈

C₈

TxD LIN1

RxD LIN1

TxD LIN2

RxD LIN2

TxD CAN

RxD CAN

INT

TxD LIN1

RxD LIN1

TxD LIN2

RxD LIN2

TxD CAN

RxD CAN

INT

Other loads , e.g.

sensor , opamp, ...

LOGIC

State

Machine

VSHS

RO

Reset

Hall1

Q1

Q2

HS4

Hall2

V_SS

VSHS

R₅

R₃

S₃

D₅

R₆

R₄

TLE9263

WK1

WK2

WK3

R₁₃

LIN cell

C₉

LIN1

C₁₅

VBAT

S₂

C₁₀

S₁

V_CC2

R₂

VCAN

CANH

C₁₁

R₁

CANH

CANL

VSHS

D₆

R₁₄

CAN cell

R₁₀

R₁₁

C₁₂

LIN cell

LIN2

C₁₆

V_S

T1

CANL

FOx

GND

LH

Note: The external capacitance on FO3/TEST must be

<=10nF in oder to ensure proper detection of SBC

Development Mode und SBC user mode operation

Application _information

_TLE9263 .vsd

Figure 64 Simplified Application Diagram

Datasheet

202

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Application Information

Note:

Unused outputs are recommended to be left unconnected on the application board. If unused

output pins are routed to an external connector which leaves the ECU, then these pins should have

provision for a zero ohm jumper (depopulated if unused) or ESD protection.

Table 40

Ref.

Bill of Material for Simplified Application Diagram

Typical Value

Purpose / Comment

Capacitances

C1

C2

C3

68µF

100nF

22µF

Buffering capacitor to cut off battery spikes, depending on application

EMC, blocking capacitor

Buffering capacitor to cut off battery spikes from VSHS as separate supply

input; Depending on application, only needed if VSHS is not connected to

VS;

C4

C5

C6

2.2µF low ESR

100nF ceramic

2.2µF low ESR

As required by application, min. 470nF for stability and max. 68µF

recommended

Spike filtering, improve stability of supply for microcontroller;

not needed for SBC

Blocking capacitor, min. 470nF for stability;

if used for CAN supply place a 100nF ceramic capacitor in addition very

close to VCAN pin for optimum EMC behavior

C7

33nF

47pF

10nF

As required by application, mandatory protection for off-board

connections

C8

As required by application, mandatory protection for off-board

connections

C17

C18

C9

Only required in case of off-board connection to optimize EMC behavior,

place close to pin

Only required in case of off-board connection to optimize EMC behavior,

place close to pin

Spike filtering, as required by application, mandatory protection for off-

board connections (see also Simplified Application Diagram with the

Alternate Measurement Function)

C10

C11

10nF

Spike filtering, as required by application, mandatory protection for off-

board connections

Spike filtering, as required by application, mandatory protection for off-

board connections

C12

C13

4.7nF / OEM dependent Split termination stability

10µF low ESR

Stability of VCC3, ceramic capacitor, e.g. Murata 10 µF/10 V

GCM31CR71A106K64L or 2x 4.7 µF/10 V

C14

47nF

Only required in case of off-board connection to optimize EMC behavior,

place close to connector

C15

C16

1nF / OEM dependent

LIN master termination

Resistances

R1

10kΩ

Wetting current of the switch, as required by application

Datasheet

203

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Application Information

Table 40

Ref.

R2

Bill of Material for Simplified Application Diagram (cont’d)

Typical Value

10kΩ

Purpose / Comment

Limit the WK pin current, e.g. for ISO pulses

Wetting current of the switch, as required by application

Limit the WK pin current, e.g. for ISO pulses

Wetting current of the switch, as required by application

Limit the WK pin current, e.g. for ISO pulses

R3

10kΩ

R4

10kΩ

R5

10kΩ

R6

10kΩ

R7

depending on LED config. LED current limitation, as required by application

R8

R9

47kΩ

Selection of hardware configuration 1/3, i.e. in case of WD failure SBC

Restart Mode is entered.

If not connected, then hardware configuration 2/4 is selected

R10

R11

R12

60Ω / OEM dependent

CAN bus termination

1Ω shunt, depending on Sense shunt for ICC3 current limitation (configured to typ. 235mA with 1Ω

required current shunt) for stand-alone configuration;

limitation or load sharing Setting of load sharing ratio (here ICC3/ICC1 = 1) in load sharing

ratio

configuration.

R13

R14

R15

1kΩ / OEM dependent

10kΩ

LIN master termination (if configured as a LIN master)

WK1 pin current limitation, e.g. for ISO pulses, for alternate measurement

function (see also Simplified Application Diagram with the Alternate

Measurement Function)

R16

R17

depending on

application and

microcontroller

Voltage Divider resistor to adjust measurement voltage to

microcontroller ADC input range (see also Simplified Application Diagram

with the Alternate Measurement Function)

depending on

application and

microcontroller

Voltage Divider resistor to adjust measurement voltage to

microcontroller ADC input range (see also Simplified Application Diagram

with the Alternate Measurement Function)

Active Components

D1

D2

e.g. BAS 3010A, Infineon Reverse polarity protection for VS supply pins

e.g. BAS 3010A, Infineon Reverse polarity protection for VSHS supply pin; if separate supplies are

not needed, then connect VSHS to VS pins

D3

D4

D5

D6

T1

T2

LED

As required by application, configure series resistor accordingly

Requested by LIN standard; reverse polarity protection of network

High active FO control

LED

e.g. BAS70

e.g. BCR191W

BCP 52-16, Infineon

Power element of VCC3, current limit or load sharing ratio to be

configured via shunt

MJD 253, ON Semi

e.g. TC2xxx

Alternative power element of VCC3

Microcontroller

µC

Datasheet

204

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Application Information

Note:

This is a simplified example of an application circuit. The function must be verified in the real

application.

VBAT

VS

D₁

C₂

C₁

D₂

e.g.

470uF

VS

V_CC1

VCC1

C₅

C₄

V_S

CSN

CLK

V_DD

CSN

CLK

SDI

SDO

µC

TxD LIN1

SDO

TxD LIN1

RxD LIN1

TxD LIN2

RxD LIN1

TxD LIN2

LOGIC

State

Machine

RxD LIN2

TxD CAN

RxD CAN

RxD LIN2

TxD CAN

RxD CAN

INT

RO

INT

Reset

ADC_x

Vbat_uC

max.

500uA

TLE9263

R₆

WK1

V_SS

≥10k

ISO Pulse

protection

C₉

≥10n

S₁

WK2

Note:

Vbat_uC

R₁₇

Max. WK1 input current shall be

be limited to 500µA to ensure

accuracy and proper operation ;

R₁₆

GND

Figure 65 Simplified Application Diagram with the Alternate Measurement Function via WK1 and WK2

Note:

This is a very simplified example of an application circuit. The function must be verified in the real

application.WK1 must be connected to signal to be measured and WK2 is the output to the

microcontroller supervision function. The maximum current into WK1 must be <500uA. The

minimum current into WK1 should be >5uA to ensure proper operation.

Datasheet

205

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Application Information

5V_int

SBC Init

Mode

T _test

R_TEST

Connector/

Jumper

FO3/

TEST

R_EXT

T _{FO_PL}

Failure Logic

Figure 66 Hint for Increasing the Robustness of pin FO3/TEST during Debugging or Programming

Datasheet

206

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Application Information

17.2

ESD Tests

Note:

Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) has been performed.

The results and test conditions are available in a test report. The target values for the test are listed

in Table 41 below.

Table 41

ESD “Gun Test”

Performed Test

Result

Unit

Remarks

¹⁾²⁾positive pulse

ESD at pin CANH, CANL,

LIN, VS, WK1..3, HSx, VCC2,

VCC3 versus GND

>6

kV

ESD at pin CANH, CANL,

LIN, VS, WK1..3, HSx, VCC2,

VCC3 versus GND

< -6

kV

¹⁾²⁾negative pulse

1) ESD Test “Gun Test” is specified with external components for pins VS, WK1..3, HSx, VCC3 and VCC2. See the

application diagram in Chapter 17.1 for more information.

2) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external

test house (IBEE Zwickau, EMC Test report Nr. 04-01-17)

EMC and ESD susceptibility tests according to SAE J2962-2 (2010) have been performed. Tested by external

test house (UL LLC).

Datasheet

207

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Application Information

17.3

Thermal Behavior of Package

Below figure shows the thermal resistance (R_{th_JA}) of the device vs. the cooling area on the bottom of the PCB

for Ta = 85°C. Every line reflects a different PCB and thermal via design.

Figure 67 Thermal Resistance (R_{th_JA}) vs. Cooling Area

Datasheet

208

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Application Information

Cross Section(JEDEC 2s2p) with Cooling Area

Cross Section(JEDEC 1s0p) with Cooling Area

70µm modelled(traces)

35µm, 90% metalization*

70µm / 5% metalization+ cooling area

*: means percentualCu metalization on each layer

PCB (top view)

PCB (bottom view)

Detail SolderArea

Figure 68 Board Setup

Board setup is defined according to JESD 51-2,-5,-7.

Board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35µm thick), with thermal via array under the exposed

pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm).

Datasheet

209

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Package Outlines

18

Package Outlines

Figure 69 PG-VQFN-48 ¹⁾

The PG-VQFN-48 package is a leadless exposed pad power package featuring Lead Tip Inspection (LTI) to

support Automatic Optical Inspection (AOI).

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

1) Dimensions in mm

Datasheet

210

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Revision History

19

Revision History

Revision Date

Changes

Rev. 1.2 2022-05-04 Datasheet updated:

•

Editorial changes

Updated package outline drawing

P_15.10.26: Updated max value of V_POR,rto 4.7 V

Updated I_peakparameter (P_6.3.13, P_6.3.17, P_6.3.18, P_6.3.19, P_7.3.15,

P_7.3.17)

•

P_4.1.27: parameter V_{CAN_Diff,max}improved to -40V min. and 40V max.

P_4.1.3: parameter V_CC1,max: added Note/Testconditions

Table 4 footnote ⁹⁾: corrected 18µA to 20µA to match with parameter values

Corrected note 2 at CAN wake capable mode: must not -> not need to

Corrected POR/Soft Reset value of FAM_PROD_STAT register. No product

change

•

Added note about clock tolerance at PWM_FREQ_CTRL register description

Pin configuration (Chapter 3): Improved Cooling tab description - connect the

exposed pad to GND

•

Updated CDM specification reference to JS-002

Improved wording of Table 5. No product change.

Corrected Footnote ⁵⁾of CAN FD Tolerance filter parameter to include condition

of used receiver. No product change.

•

Added explaining footnote to parameter t_LW(P_15.10.24). No product change.

Added current consumption for GPIOx in Highside/Lowside switch confguration

in SBC Stop/Sleep mode (P_4.4.37 and P_4.4.38). No product change.

•

Added “not subject to production test” footnote to t_{CFG_F}(P_13.2.6)

Two definitions for VCC1 voltage drop were available. Apply P_6.3.3 to 3.3V

variant only, and P_6.3.4 to 5V variant only. No product change.

Datasheet

211

Rev. 1.2

2022-05-04

OPTIREG™ SBC TLE9263-3BQXV33

Revision History

Revision Date

Changes

Rev. 1.1 2019-09-27 Datasheet updated:

•

Editorial changes

General: added ISO 17987-4 to LIN 2.2

Updated Table 4

–

corrected footnote 9) to match P_4.4.33, i.e changed 525µA to 550µA

•

Chapter 5.1.4 “SBC Sleep Mode”: added condition for CAN mode handling

before SBC Sleep Mode entry

•

Table 9 “CAN Modes ...”: CAN_x bits for CAN Receive Only (no SWK)

Figure 3 “State Diagram ...”: added footnote with condition for CAN mode

handling before SBC Sleep Mode entry

•

Figure 31 “CAN Mode Control Diagram”: added Footnote 2) with condition for

CAN mode handling before SBC Sleep Mode entry

Updated Table 24

–

added P_10.3.57 and P_10.3.58 (no product change)

added P_10.3.59, P_10.3.60, P_10.3.61 and P_10.3.62

tightened P_10.3.16

tightened P_10.3.39 and P_10.3.40 by additional footnote

•

Figure 10.2.4 “CAN Wake Capable Mode”, rearming the transceiver for wake

capability: added condition for CAN mode handling before SBC Sleep Mode

entry

Rev. 1.0 2017-07-31 Initial Release

Datasheet

212

Rev. 1.2

2022-05-04

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2022-05-04

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

a written document signed by

Document reference

Z8F68472363


型号：	TLE9263-3BQX V33
厂家：	Infineon
描述：	The device is designed for various CAN-LIN automot
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