TLE9278BQX V33_技术文档

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

1

Overview

Features

•

SMPS with integrated switches up to 750 mA (DC/DC buck) with 3.3 V

output voltage

DC/DC Boost converter for low V_supsupply voltage with integrated switch

at 6.5 V, 8 V, 10 V and 12 V

Low-Drop Voltage Regulator with external PNP device with configurable 5.0 V, 3.3 V, 1.8 V and 1.2 V output

voltage, protected for off-board usage

•

Very low quiescent current consumption in Stop and Sleep Mode

Four CAN Transceivers compliant to CAN Flexible Data-rate (FD)

ISO 11898-2: 2016 standard up to 5 Mb

One universal High-Voltage Wake Input for voltage level monitoring including wake up capability

Cyclic wake feature via an integrated timer

Reset Output to ensure stable supply to the MCU

Fail Output to activate external load in case of system malfunctions are detected

Output voltage supervision functions in all output supply voltages

Fast Battery Voltage Monitoring Feature

16-bit Serial Perpheral Interface (SPI)

Overtemperature and short circuit protection feature

Wide input voltage and temperature range

Software Compatibility to other SBC family members for the TLE926x and TLE927x families

Green Product (RoHS compliant) & AEC Qualified

7 × 7 mm PG-VQFN-48 package

Potential applications

•

Gateways

Body control modules

Driver assistance

Chasis control

Datasheet

www.infineon.com

Rev. 1.5

2019-09-27

1

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Overview

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100/101.

Description

Infineon’s TLE9278BQX V33 offers the highest level of integration at smallest footprint for automotive

applications requiring multiple channels of CAN transceivers like gateways and high-end Body Control

Modules (BCM). A high-efficient Switch Mode Power Supply (SMPS) buck regulator provides an external 3.3 V

output voltage at up to 750 mA while an additional DC/DC boost converter supports applications or conditions

at low supply input voltages. The device is controlled and monitored via a 16-bit Serial Peripheral Interface

(SPI). Additional features include a time-out/window watchdog circuit with reset, fail output and

undervoltage reset. The device offers low-power modes in order to support applications that are connected

permanently to the battery. A wake-up from the low-power mode is possible via a message on the buses, via

the bi-level sensitive monitoring/wake-up input as well as via the timer. The TLE9278BQX V33 is offered in a

very small footprint, exposed pad PG-VQFN-48 (7 × 7 mm) power package.

Type

Package

Marking

TLE9278BQX V33

PG-VQFN-48

TLE9278BQXV33

Datasheet

2

Rev.1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

3

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

3.2

3.3

4

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1

4.2

4.3

4.4

5

5.1

System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

State Machine Description and SBC Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Device Configuration and SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Supply and Power up configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Watchdog trigger failure configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SBC Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SBC Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SBC Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SBC Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.1

5.1.1.1

5.1.1.2

5.1.1.3

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.2

5.2.1

5.2.2

6

6.1

DC/DC Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Functional Description of the Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Startup Procedure (Soft Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Buck regulator Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Functional Description of the Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Boost Regulator Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Power Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Buck behavior in SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Buck behavior in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1.1

6.1.1.1

6.1.1.2

6.1.1.3

6.1.2

6.1.2.1

6.1.2.2

6.2

6.2.1

6.2.2

Datasheet

3

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

6.2.2.1

6.2.2.2

6.2.2.3

6.2.3

6.2.3.1

6.3

Automatic Transition from PFM to PWM in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Manual Transition from PFM to PWM in SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SBC Stop to Normal Mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Buck behavior in SBC Sleep or Fail Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SBC Sleep/Fail Safe Mode to SBC Normal Mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7

External Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Calculation of R_SHUNT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1

7.2

7.2.1

7.3

7.4

7.5

7.6

8

8.1

8.2

High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

CAN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.3

9

Wake Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.1

9.2

9.2.1

9.3

10

10.1

10.2

Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

11

11.1

11.2

Fail Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

12

12.1

Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Watchdog during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

12.1.1

12.1.2

12.2

12.2.1

12.2.2

12.2.3

12.2.4

Datasheet

4

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

12.2.4.1

12.3

12.4

12.5

12.6

12.7

12.8

12.9

12.10

12.11

12.11.1

12.12

Watchdog Start in SBC Stop Mode due to BUS Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

V_SPower ON Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Measurement Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Fast Battery Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

VBSENSE Boost deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

VIO Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

VIO Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

VIO Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

VEXT Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

13

13.1

13.2

13.3

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

SPI Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

SPI Mapping Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

SPI Mapping Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SPI Status Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Family and Product Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

13.4

13.4.1

13.4.2

13.5

13.5.1

13.6

13.6.1

13.6.2

13.7

14

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

14.1

14.2

14.3

15

16

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Datasheet

5

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Block Diagram

2

Block Diagram

VS

BSTD

V_CC1

Buck

Boost

BCKSW

VCC1

GND

Vint.

VEXTIN

VEXTSH

VEXTB

FO/TEST

Fail Safe

V_ext

PCFG

VIO

VEXTREF

SBC

STATE

MACHINE

SDI

SDO

SPI

CLK

CSN

INTN

Interrupt

Control

VBSENSE

Window Watchdog

RSTN

RESET

GENERATOR

4

WAKE

REGISTER

WK

4

TXDCAN0

RXDCAN0

TXDCAN2

RXDCAN2

CAN

Module 0

CAN

Module 2

CANH0

CANL0

CANH2

CANL2

VCAN

TXDCAN3

RXDCAN3

TXDCAN1

RXDCAN1

CAN

Module 1

CAN

Module 3

CANH3

CANL3

CANH1

CANL1

GND

Figure 1

Block Diagram

Datasheet

6

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

CSN 37

SDO 38

24 RSTN

23 VIO

SDI 39

22 VCC1

CLK 40

GND 41

WK 42

21 RXDCAN3

20 TXDCAN3

19 VCAN

TLE9278

VBSENSE 43

VEXTIN 44

VEXTSH 45

VEXTB 46

VEXTREF 47

FO/TEST 48

18 RXDCAN2

17 TXDCAN2

16 RXDCAN1

15 TXDCAN1

14 RXDCAN0

13 TXDCAN0

PG-VQFN-48

Figure 2

Pin Configuration TLE9278BQX V33

Datasheet

7

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Pin Configuration

3.2

Pin Definitions and Functions

1

Symbol

CANH0

CANL0

GND

Function

CAN High 0 Bus Pin.

2

CAN Low 0 Bus Pin.

3

Ground. CAN0 and CAN1 common ground.

CAN Low 1 Bus Pin.

4

CANL1

CANH1

GND

5

CAN High 1 Bus Pin.

6

Ground. Analog GND.

7

CANH2

CANL2

GND

CAN High 2 Bus Pin.

8

CAN Low 2 Bus Pin.

9

Ground. CAN2 and CAN3 common ground.

CAN Low 3 Bus Pin.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

CANL3

CANH3

PCFG

CAN High 3 Bus Pin.

Configuration pin. For power up hardware configuration (refer to Chapter 5.1.1).

Transmit CAN0.

TXDCAN0

RXDCAN0

TXDCAN1

RXDCAN1

TXDCAN2

RXDCAN2

VCAN

Receive CAN0.

Transmit CAN1.

Receive CAN1.

Transmit CAN2.

Receive CAN2.

Supply Input for internal HS-CAN modules.

Transmit CAN3.

TXDCAN3

RXDCAN3

VCC1

Receive CAN3.

Buck Regulator. Input feedback for Buck Converter.

VIO

I/O voltage supply, reference voltage for over-/undervoltage monitoring

(see Chapter 5.1.1).

24

25

26

27

28

29

RSTN

INTN

GND

BCKSW

n.c.

Reset Output. Active LOW, internal pull-up.

Interrupt Output. Active LOW.

Ground. Buck regulator ground.

Buck regulator switch node output.

not connected. Not bondend internally.

VS

Buck Supply Voltage. Connected to Battery Voltage or Boost output voltage

with reverse protection diode. Use a filter against EMC in case that the Boost is

not used.

30

VS

Buck Supply Voltage. Connected to Battery Voltage or Boost output voltage

with reverse protection diode. Use a filter against EMC in case that the Boost is

not used.

31

32

33

n.c.

not connected. Not bondend internally.

Ground. Boost regulator ground.

GND

Datasheet

8

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Pin Configuration

34

Symbol

n.c.

Function

not connected. Not bondend internally.

35

BSTD

Boost Transistor Drain. Connected between inductor and diode for boost

functionality (refer to Chapter 14.1 for additional information). Connect to

ground if the Boost regulator is not used.

36

BSTD

Boost Transistor Drain. Connected between inductor and diode for boost

functionality (refer to Chapter 14.1 for additional information). Connect to

ground if the Boost regulator is not used.

37

38

39

40

41

42

43

44

CSN

SPI Chip Select Not Input.

SPI Data Output. Out of SBC (=MISO).

SPI Data Input. Into SBC (=MOSI).

SPI Clock Input.

SDO

SDI

CLK

GND

Ground. Common digital ground.

Wake Input.

WK

VBSENSE

VEXTIN

Battery Voltage Monitoring Input.

Input Supply Voltage for VEXT. Connected to Battery Voltage with Reverse

Protection Diode and Filter against EMC.

45

46

47

48

VEXTSH

VEXTB

VEXTSH. Emitter connection for external PNP, shunt connection to VEXTIN.

VEXTB. Base connection for external PNP.

VEXTREF

FO/TEST

VextREF. Collector connection for external PNP, reference input.

Fail Output. active LOW, open-drain;

TEST. Connect to GND to activate SBC Development Mode; Integrated pull-up

resistor. Connect to VS with a pull-up resistor or leave open for normal operation.

Cooling GND

Tab

Cooling Tab - Exposed Die Pad; For cooling purposes only, do not use as an

electrical ground.¹⁾

1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the SBC via the PCB.

The exposed die pad is not connected to any active part of the IC and can be left floating or it can be connected to

GND (recommended) for the best EMC performance.

Note:

All VS pins must be connected to battery potential or insert a reverse polarity diodes where required;

All GND pins as well as the Cooling Tab must be connected to one common GND potential.

Datasheet

9

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Pin Configuration

3.3

Unused Pins

It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that

they are disabled via SPI:

•

CANHx, CANLx, TXDCANx, RXDCANx: leave pins open.

BSTD: connect to GND.

WK: connect to GND and disable WK input via SPI.

RSTN / INTN: leave open.

FO/TEST: connect to GND during power-up to activate SBC Development Mode; connect to VS or leave

open for normal user mode operation.

•

VBSENSE: connect to VS in case that Fast Battery Voltage Monitoring and Boost deactivation features are

not used and keep them disabled.

•

VEXT: See Chapter 7.5.

n.c.: leave open.

Unused pins routed to an external connector which leaves the ECU should feature a zero ohm jumper

(depopulated if unused) or ESD protection.

Datasheet

10

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Voltages

Supply Voltage VS and

VEXTIN pin

V_{S1, max}

V_{S2, max}

-0.3

–

28

40

28

40

V

–

P_4.1.1

P_4.1.2

P_4.1.3

P_4.1.4

Supply Voltage VS and

VEXTIN pin

Load Dump,

max. 400 ms

Boost drain Voltage BSTD

V_{BSTD2, max}-0.3

V_{BCKSW, max}-0.3

–

Boost drain Voltage BSTD

Load Dump,

max. 400 ms

Buck switch BCKSW pin

–

V_S+ 0.3

5.5

V

–

P_4.1.8

P_4.1.9

Buck Regulator feedback,

pin VCC1

V_{CC1, max}

-0.3

External Voltage Regulator V_{EXTREF, max}-0.3

(VEXTREF)

–

28

V

V_EXTREF= 40 V for P_4.1.26

Load Dump,

max. 400 ms

External Voltage Regulator V_{EXTB, max}-0.3

(VEXTB)

V_EXTIN

+ 10

V_EXTB= 40 V for

Load Dump,

max. 400 ms

P_4.1.27

External Voltage Regulator V_{EXTSH, max}V_EXTIN

–

V_EXTIN

+ 0.3

V

–

P_4.1.11

P_4.1.12

(VEXTSH)

- 0.3

Battery Voltage Monitoring V_VBSENSE,-18

40

–

max

Wake Input

V_{WK, max}

V_{HV, max}

-0.3

–

40

5.5

V

–

P_4.1.13

P_4.1.14

P_4.1.15

Fail Pins FO/TEST

Interrupt/Configuration Pin V_{INTN, max}-0.3

INTN

Configuration Pin PCFG

Configuration Pin VIO

CANH, CANL

V_{PCFG, max}-0.3

–

40

V

–

P_4.1.25

P_4.1.28

P_4.1.16

P_4.1.17

P_4.1.18

P_4.1.30

V_{VIO, max}

V_{BUS, max}

-0.3

-40

5.5

40

Digital Input / Output pin’s V_{IO, max}

VCAN Input Voltage

-0.3

5.5

10

V_{VCAN, max}-0.3

Maximum Differential CAN V_{CAN_DIFF,}-5

Bus Voltage

max

Datasheet

11

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

General Product Characteristics

Table 1

Absolute Maximum Ratings¹⁾(cont’d)

T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Temperatures

Junction Temperature

Storage Temperature

ESD Susceptibility

ESD Resistivity to GND

T_j

-40

-55

–

150

°C

–

P_4.1.19

P_4.1.20

T_stg

–

V_ESD

-2

-8

–

2

8

kV

HBM²⁾

HBM²⁾³⁾

P_4.1.21

P_4.1.22

ESD Resistivity to GND,

CANH, CANL

ESD Resistivity to GND

V_ESD

-500

–

500

750

V

CDM⁴⁾

P_4.1.23

P_4.1.24

ESD Resistivity Pin 1,

12,13,24,25,36,37,48 (corner

pins) to GND

V_ESD1,12,13,2-750

4,25,36,37,48

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF).

3) ESD “GUN” Resistivity with ±6 KV (according to IEC61000-4-2 “GUN test” (300 Ω, 150 pF)) it is shown in Application

Information and test will be provided from IBEE institute.

4) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1, usually not tested but rather

ESD SDM.

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

Datasheet

12

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

1)

Supply Voltage

V_S,func

V_POR

28

V

seesection P_4.2.1

POR

Chapter 12.12

CANx Supply Voltage

SPI frequency

V_CAN

f_SPI

4.75

–

5.25

4

V

–

P_4.2.2

P_4.2.3

MHz see

Chapter 13.7 for

f_SPI,max

Junction Temperature

T_j

-40

–

150

°C

–

P_4.2.4

1) Including Power-On Reset, Over- and Undervoltage Protection.

Note:

Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

Device Behavior Outside of Specified Functional Range:

•

28 V < V_S,func< 40 V: Device will still be functional; the specified electrical characteristics might not be

ensured anymore. The absolute maximum ratings are not violated. However, a thermal shutdown might

occur due to high power dissipation.

•

V_CAN< 4.75 V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_0 and the transmitter

will be disabled as long as the UV condition is present.

5.25 V < V_CAN< 5.5 V: CANx transceiver still functional. However, the communication might fail due to out-

of-spec operation.

V

_POR,f< V_S< 5.5 V: Device will be still functional; the specified electrical characteristics might not be ensured

anymore:

–

The voltage regulators will enter the low-drop operation mode.

VIO_UV reset could be triggered depending on the VRTx settings.

Datasheet

13

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

General Product Characteristics

4.3

Thermal Resistance

Table 3

Thermal Resistance¹⁾

Symbol

Parameter

Values

Typ.

7

Unit Note or

Test Condition

Number

Min.

Max.

Junction to Soldering Point R_thJSP

Junction to Ambient R_thJA

–

K/W Exposed Pad

P_4.3.1

P_4.3.2

2)

33

K/W

1) Not subject to production test, specified by design.

2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for 1.5 W. Board: 76.2 × 114.3 × 1.5 mm3

with 2 inner copper layers (35 µm thick), with thermal via array under the exposed pad . Top and bottom layers are

70 µm thick.

4.4

Current Consumption

Table 4

Current Consumption

Current consumption values are specified at T_j= 25°C, V_S= 13.5 V, all outputs open

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

SBC Normal Mode

Normal Mode current

consumption

I_Normal

–

10

16

mA

V_S= 5.5 V to 28 V;

T_j= -40°C to +150°C;

BOOST/VEXT/CANx=

OFF

P_4.4.1

SBC Stop Mode

Stop Mode current

Consumption

I_Stop,25

–

55

70

µA

¹⁾Buck in PFM

P_4.4.2

P_4.4.3

BOOST/VEXT = OFF;

No load on VCC1

VBSENSE_EN = 0_B

CANx/WK not wake

capable

Watchdog = OFF

²⁾T_j= 85°C;

Stop Mode current

I_Stop,85

95

–

µA

Consumption, T_j= 85°C

Buck in PFM

BOOST/VEXT = OFF;

No load on VCC1

VBSENSE_EN = 0_B

CANx/WK not wake

capable

Watchdog = OFF

SBC Sleep Mode

Sleep Mode current

consumption

I_Sleep,25

–

30

50

µA

BOOST/VEXT = OFF; P_4.4.4

VBSENSE_EN = 0_B

CANx/WK not wake

capable

Datasheet

14

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at T_j= 25°C, V_S= 13.5 V, all outputs open

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

65

Unit Note or

Test Condition

Number

Min.

Max.

Sleep Mode current

I_Sleep,85

–

µA

²⁾T_j= 85°C;

P_4.4.5

consumption, T_j= 85°C

BOOST/VEXT = OFF;

VBSENSE_EN = 0_B

CANx/WK not wake

capable

Feature Incremental Current Consumption

Current consumption per

CAN module, recessive state

I_CAN,rec

–

2

3

mA

SBC Normal Mode; P_4.4.6

CAN Normal Mode;

V

_CAN= 5 V;

_TXDCAN= V_IO;

no RL on CANx

²⁾SBC Normal Mode; P_4.4.7

CAN Normal Mode;

Current consumption per

CAN module, dominant

state

I_CAN,dom

–

4.5

V

_CAN= 5 V;

_TXDCAN= GND;

no RL on CANx

Current consumption per

CAN module, Receive Only

Mode, SBC Normal Mode

I_{CAN,RcvOnly,N}

–

0.4

1

0.6

1.4

mA

²⁾CAN Receive Only P_4.4.8

Mode; V_CAN= 5 V;

M

V

_TXDCAN= V_IO;

no RL on CANx

²⁾CAN Receive Only P_4.4.25

Mode; V_CAN= 5 V;

Current consumption per

CAN module, Receive Only

Mode, SBC Stop Mode

I_{CAN,RcvOnly,St}

M

V_TXDCAN= V_IO;

no RL on CANx

Current consumption for WK I_Wake,WK,25

wake capability

–

0.5

2.0

1.5

4.0

µA

³⁾⁴⁾SBC Sleep Mode; P_4.4.11

CANx = OFF

²⁾³⁾⁴⁾SBCSleep Mode; P_4.4.12

T_j= 85°C;

Current consumption for WK I_Wake,WK,85

wake capability T_j= 85°C

CANx = OFF

Current consumption for

CAN wake capability

I_Wake,CAN,25

–

4.5

6

µA

¹⁾³⁾SBC Sleep Mode; P_4.4.13

WK = OFF

t_SILENCEexpired

Current consumption for

CAN wake capability

I_Wake,CAN,85

10

¹⁾²⁾³⁾SBCSleep Mode; P_4.4.14

T_j= 85°C;

WK = OFF

t

_SILENCEexpired

Current consumption for

VEXT in SBC Sleep Mode

I_{Sleep,VEXT,25}

–

45

60

µA

³⁾SBC Sleep Mode;

VEXT = ON (no load);

CANx / WK = OFF

P_4.4.15

Datasheet

15

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at T_j= 25°C, V_S= 13.5 V, all outputs open

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

55

Unit Note or

Test Condition

Number

Min.

Max.

Current consumption for

VEXT in SBC Sleep Mode,

T_j= 85°C

I_{Sleep,VEXT,85}

–

70

µA

²⁾³⁾SBC Sleep Mode; P_4.4.16

T_j= 85°C; VEXT = ON

(no load);

CANx / WK = OFF

Current consumption for

cyclic wake function

I_Stop,C25

I_Stop,C85

–

20

24

26

35

µA

³⁾⁵⁾SBC Stop Mode; P_4.4.17

WD = OFF

²⁾³⁾⁵⁾SBC Stop Mode; P_4.4.18

T_j= 85°C;

Current consumption for

cyclic wake function,

T_j= 85°C

WD = OFF

Current consumption for

watchdog active in Stop

Mode

I_Stop,WD25

I_Stop,WD85

I_Stop,FO

–

20

24

0.5

5

26

35

1.5

–

µA

mA

µA

mA

²⁾SBC Stop Mode;

Watchdog running

P_4.4.19

P_4.4.20

P_4.4.21

Current consumption for

watchdog active in Stop

Mode

²⁾SBC Stop Mode;

T_j= 85°C;

Watchdog running

²⁾All SBC Modes;

T_j= 25°C;

FO = ON (no load);

²⁾SBC Stop Modes; P_4.4.30

VBSENSE_EN = 1_B

T_j= 25°C;

²⁾SBC Normal / Stop P_4.4.31

Modes;

Current consumption for

active fail output (FO)

Current consumption Fast I_Stop,FBM

Battery Monitoring in SBC

Stop Mode

Additional V_Scurrent

consumption with Boost

Module Active

I_BOOST,ON

10

20

V

_BSTx< V_S< V_BST,thx

BOOST_EN = 1_B;

1) Current consumption for CANx transceiver and WK input to be added if set to be wake capable or receiver only.

2) Not subject to production test, specified by design.

3) Current consumption adders of features defined for SBC Sleep Mode also apply for SBC Stop Mode and vice versa

(unless otherwise specified).

4) No pull-up or pull-down configuration selected.

5) Cyclic wake configuration: Timer with 20 ms period.

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Multi-CAN Power+ System Basis Chip

System Features

5

System Features

This chapter describes the system features and behavior of the TLE9278BQX V33:

•

State machine and SBC mode control.

Device configurations.

State of supply and peripherals.

Wake features.

Supervision and diagnosis functions.

The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in

Chapter 13. The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the

TLE9278BQX V33 is compatible to other devices of TLE926x and TLE927x family.

The System Basis Chip (SBC) offers six operating modes:

•

SBC Init Mode: power-up of the device and after soft reset.

SBC Normal Mode: the main operating mode of the device.

SBC Stop Mode: the first-level power saving mode with the main voltage regulator enabled.

SBC Sleep Mode: the second-level power saving mode with Buck regulator disable.

SBC Restart Mode: an intermediate mode after a wake event from SBC Sleep or SBC Fail-Safe Mode or after

a failure (e.g. WD failure in config 1/3) to bring the microcontroller into a defined state via a reset. Once the

failure condition is not present anymore, the device will automatically change to SBC Normal Mode after a

delay time (t_RD1).

•

SBC Fail-Safe Mode: a safe-state mode after critical failures (e.g. TSD2 thermal shutdown) to bring the

system into a safe state and to ensure a proper restart of the system. Buck regulator is disabled.

A special mode called SBC Development Mode is available during software development or debugging of the

system. All of the operating modes mentioned above can be accessed in this mode. However, the watchdog

counter is stopped and does not need to be triggered. This mode can be accessed by setting the TEST pin to

GND during SBC Init Mode.

5.1

State Machine Description and SBC Mode Control

The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register

M_S_CTRL.

The SBC MODE bits are cleared when going trough SBC Restart Mode, so the current SBC mode is always

shown.

Figure 3Figure 4 shows the SBC State Diagram.

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Multi-CAN Power+ System Basis Chip

System Features

First battery connection

SBC Soft Reset

Config.: settings can be configured in

this SBC mode;

SBC Init Mode

*

(Long open window )

Fixed: settings stay as defined in

SBC Normal Mode

VCC1

ON

VEXT

OFF

Boost

OFF

FO

CAN

WD

Cyc.Wake

OFF

inact. OFF ⁽³⁾Config.

*

The SBC Development Mode is a

super set of state machine where the

WD timer is stopped and CANx

Any SPI

command

behavior differs in SBC Init Mode.

Otherwise, there are no differences in

behavior (see also Chapter 5.1.7).

(1) After Fail-Safe Mode entry , the device will stay for at least

typ. 1s in this mode (with RO low) after a TSD2 event and min.

typ. 100ms after other Fail -Safe Events. Only then the device

can leave the mode via a wake-up event. Wake events are

stored during this time.

SBC Normal Mode

VCC1

ON

VEXT

Boost⁽⁶⁾

config.

conf./OFF

(2) according to VEXT configuration

WD trigger

(3) For SBC Development Mode CAN is in Normal Mode in

SBC Init Mode and will stay ON when going from there to SBC

Normal Mode

FO

CAN

WD

Cyc.Wake

config.

act/inact Config.⁽³⁾Config.

(4) See chapter CAN for detailed behavior in SBC Restart Mode

(5) CAN transceiver can be SWK capable , depending on

configuration

Automatic

SPI cmd

§

Reset is released

WD starts with long open window

(6) The Boost regulator activation depends from the VS value.

SPI cmd

SBC Sleep Mode

SBC Stop Mode

VCC1

OFF

VEXT⁽²⁾

Fixed/OFF

Boost

OFF

VCC1

ON

VEXT

fixed

Boost⁽⁶⁾

fixed/OFF

VIO over voltage

Config 1/3 (if VIO_OV_RST set)

CAN ⁽⁵⁾

WD

fixed

FO

fixed

WD

OFF

Cyc.Wake

OFF

FO

fixed

Cyc.Wake

fixed

Wake

cap./OFF

SBC Restart Mode

(RO pin is asserted)

Wake up event

via CANx or WK

Watchdog Failure :

Config 1/3 (MAX_3_RST not set)

& 1st WD failure in Config4

4th consecutive VIO

under voltage event

(if VS > VS_UV_TO)

VCC1

ON

VEXT⁽²⁾

Fixed/OFF

Boost⁽⁶⁾

fixed/OFF

VIO over voltage

Config 2/4 (if VIO_OV_RST set)

VIO Undervoltage

CAN ⁽⁴⁾

FO

active/

fixed

WD

OFF

Cyc.Wake

OFF

Woken /

OFF

TSD2 event

SBC Fail-Safe Mode ⁽¹⁾

1st Watchdog Failure Config 2,

2nd Watchdog Failure , Config 4

VCC1

OFF

VEXT

OFF

Boost

OFF

CAN

VIO Short to GND

FO

fixed

WD

OFF

Cyc.Wake

OFF

Wake

capable

CANx, WK wake-up event

Figure 3

State Diagram showing the SBC Operating Modes

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

System Features

First battery connection

SBC Soft Reset

Config.: settings can be configured in

this SBC mode;

SBC Init Mode

*

(Long open window )

Fixed: settings stay as defined in

SBC Normal Mode

VCC1

ON

VEXT

OFF

Boost

OFF

FO

CAN

WD

Cyc.Wake

OFF

inact. OFF ⁽³⁾Config.

*

The SBC Development Mode is a

super set of state machine where the

WD timer is stopped and CANx

Any SPI

command

behavior differs in SBC Init Mode.

Otherwise, there are no differences in

behavior (see also Chapter 5.1.7).

SBC Normal Mode

(1) After Fail-Safe Mode entry , the device will stay for at least

typ. 1s in this mode (with RO low) after a TSD2 event and min.

typ. 100ms after other Fail -Safe Events. Only then the device

can leave the mode via a wake-up event. Wake events are

stored during this time.

VCC1

ON

VEXT

config.

Boost⁽⁵⁾

conf./OFF

WD trigger

(2) according to VEXT configuration

FO

CAN

WD

Cyc.Wake

config.

act/inact Config.⁽³⁾Config.

(3) For SBC Development Mode CAN is in Normal Mode in

SBC Init Mode and will stay ON when going from there to SBC

Normal Mode

(4) See chapter CAN for detailed behavior in SBC Restart Mode

(5) The Boost regulator activation depends from the VS value.

Automatic

SPI cmd

§

Reset is released

WD starts with long open window

SPI cmd

SBC Sleep Mode

SBC Stop Mode

VCC1

OFF

VEXT⁽²⁾

Fixed/OFF

Boost

OFF

VCC1

ON

VEXT

fixed

Boost⁽⁵⁾

fixed/OFF

VIO over voltage

Config 1/3 (if VIO_OV_RST set)

CAN

FO

fixed

WD

OFF

Cyc.Wake

OFF

FO

fixed

WD

fixed

Cyc.Wake

fixed

CAN

fixed

Wake

cap./OFF

SBC Restart Mode

(RO pin is asserted)

Wake up event

via CANx or WK

Watchdog Failure :

Config 1/3 (MAX_3_RST not set)

& 1st WD failure in Config4

4th consecutive VIO

under voltage event

(if VS > VS_UV_TO)

VCC1

ON

VEXT⁽²⁾

Fixed/OFF

Boost⁽⁵⁾

fixed/OFF

VIO over voltage

Config 2/4 (if VIO_OV_RST set)

VIO Undervoltage

CAN ⁽⁴⁾

FO

active/

fixed

WD

OFF

Cyc.Wake

OFF

Woken /

OFF

TSD2 event

SBC Fail-Safe Mode ⁽¹⁾

1st Watchdog Failure Config 2,

2nd Watchdog Failure , Config 4

VCC1

OFF

VEXT

OFF

Boost

OFF

CAN

VIO Short to GND

FO

fixed

WD

OFF

Cyc.Wake

OFF

Wake

capable

CANx, WK wake-up event

Figure 4

State Diagram showing the SBC Operating Modes

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

System Features

5.1.1

Device Configuration and SBC Init Mode

The SBC Init Mode is the mode where the hardware configuration of the SBC is stored and where the

microcontroller finishes the initialization phase.

The SBC starts up in SBC Init Mode after crossing the power-on reset V_POR,rthreshold (see also Chapter 12.3)

and the watchdog will start with a long open window (t_LWtypical 200ms) after the RSTN is released.

During this power-on phase following configurations are stored in the device:

•

Supply and Power up configurability.

The device behavior regarding a watchdog trigger failure and a VIO overvoltage condition is determined by

the external circuitry on the INTN pin (see below).

•

The selection of the normal device operation or the SBC Development Mode (watchdog disabled for

debugging purposes) will be set depending on the voltage level of the FO/TEST pin (see also

Chapter 5.1.7).

5.1.1.1 Supply and Power up configurability

The pin VIO of TLE9278BQX V33 has to be connected to VCC1. The pin PCFG can be left open or connected to

GND.

The Table 5 shows the only allowed combinations and related behavior.

Table 5

Supply and power up Configurability

PCFG pin VIO Supply µC Supply VEXT

VCC1

VEXT

Supervision

Functions

Output

Voltage

Output voltage Behavior

V

_CC1= 3.3 V Open

VCC1

Configurable via SPI

Supervision

functions on VIO

SPI using

configurable,

VEXT_VCFG

OFF after Power with 3.3 V level;

Up

VREG_UV SPI

status bit active

V_CC1= 3.3 V GND

Configurable via SPI

Supervision

functions on VIO

SPI using

configurable,

VEXT_VCFG

OFF after Power with 3.3 V level;

Up

VREG_UV SPI

status bit active

Note:

VIO can be connected only to VCC1.

5.1.1.2 Watchdog trigger failure configuration

There are four different device configurations (Table 6) available defining the watchdog failure and the VIO

overvoltage behavior. The configurations can be selected via the external connection on the INTN pin and the

SPI bit CFG2 in the HW_CTRL_0 register (see also Chapter 13.4):

•

A watchdog trigger failures leads to SBC Restart Mode (Config 1/3) and depending on CFG2 the Fail Output

(FO) are activated after the 1st or 2nd watchdog trigger failure;

If VIO_OV_RST is set and in Config 1/3, then SBC Restart Mode will be entered in case of VIO_OV and the

FO is activated.

A watchdog trigger failures leads to SBC Fail-Safe Mode (Config 2/4) and depending on CFG2 the Fail

Output (FO) are activated after the 1st or 2nd watchdog trigger failure. The first watchdog trigger failure in

Config 4 will lead to SBC Restart Mode;

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Multi-CAN Power+ System Basis Chip

System Features

If VIO_OV_RST is set and in Config 2/4, then SBC Fail-Safe Mode will be entered in case of VIO_OV and the

FO is activated.

The respective device configuration can be identified by reading the SPI bits CFG2_STATE and CFG1_STATE

in the WK_LVL_STAT register.

Table 6

Watchdog Trigger Failure Configuration

FO Activation SBC Mode Entry

Config Event

SPI Bit CFG2 INTN Pin

(CFG1_STATE)

1

2

3

4

1 × Watchdog Failure after 1st WD Failure SBC Restart Mode

1 × Watchdog Failure after 1st WD Failure SBC Fail-Safe Mode

2 × Watchdog Failure after 2nd WD Failure SBC Restart Mode

2 × Watchdog Failure after 2nd WD Failure SBC Fail-Safe Mode

1

0

External pull-up

No ext. pull-up

External pull-up

No ext. pull-up

The respective configuration will be stored for all conditions and can only be changed by powering down the

device (V_S< V_POR,f).

Table 7 shows the possible SBC hardware configurations.

Table 7

SBC Configuration

Configuration Description

FO/Test

INTN Pin CFG2_STA CFG1_STA

(CFG1_ST TE

ATE)

TE

Config 0

Config 1

SBC Development Mode: no reset is

triggered in case of watchdog trigger

failure. After the Power Up, one

0

-

X

arbitrary SPI command must be sent.

After missing the WD trigger for the first Open or

External

pull-up to

V_IO

1

time, the state of VCC1 remains

unchanged, FO pin is active, SBC in

Restart Mode

>V_TEST,H

Config 2

Config 3

After missing the WD trigger for the first Open or

time,VCC1 turns OFF, FO pin are active, >V_TEST,H

SBC in Fail-Safe mode

Open or

GND

1

0

1

After missing the WD trigger for the

Open or

External

pull-up to

V_IO

second time, the state of VCC1 remains >V_TEST,H

unchanged, FO pin is active, SBC in

Restart Mode

Config 4

After missing the WD trigger for the

second time,VCC1 turns OFF, FO pin is >V_TEST,H

Open or

GND

0

active, SBC in Fail-Safe mode

In case of 3 consecutive resets due to WD fail, it is possible in Config 1 and 3 not to generate additional reset

by setting the MAX_3_RST on WD_CTRL.

Figure 5 shows the timing diagram of the hardware configuration selection. The hardware configuration is

defined during SBC Init Mode. The INTN pin is internally pulled LOW with a weak pull-down resistor during the

reset delay time t_RD1, i.e. after VIO crosses the reset threshold VRT1 and before the RSTN pin goes HIGH. The

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Multi-CAN Power+ System Basis Chip

System Features

INTN pin is monitored during this time and the configuration (depending on the voltage level at INTN) is read

and stored at the rising edge of RSTN (with a filter time of t_{CFG_F}).

VS

V_POR,r

t

VIO

V_RT1,r

t

RSTN

t_{CFG_F}

Config Select filter time

t

t_RD1

Configuration selection monitoring period

Figure 5

Hardware Selection Timing Diagram

Note:

If the POR bit is not cleared then the internal pull-down resistor will be reactivated every time RSTN

is pulled LOW the configuration will be updated at the rising edge of RSTN. Therefore it is

recommended to clear the POR bit right after initialization.

5.1.1.3 SBC Init Mode

In SBC Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. In

the SBC Init Mode any SPI command will bring the SBC to SBC Normal Mode. During the long open window

the watchdog has to be triggered. Thereby the watchdog will be automatically configured. A missing

watchdog trigger during the long open window will cause a watchdog failure and the device will enter SBC

Restart Mode.

Wake events are ignored during SBC Init Mode and will therefore be lost.

Note:

Any SPI command will bring the SBC to SBC Normal Mode even if non-valid (see Chapter 13.2).

For a safe start-up, it is recommended to use the first SPI command to trigger and to configure the

watchdog (see Chapter 12.2).

Note:

At power up, no VIO_UV will be issued nor will FO be triggered as long as VIO is below the V_RT1

threshold and V_Sis below the VIO short circuit detection threshold V_S,UV. The RSTN pin will be kept

low as long as VIO is below the selected V_RT1threshold. As soon as the VIO is higher than V_RT1, the

RSTN is released after t_RD1

.

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Multi-CAN Power+ System Basis Chip

System Features

5.1.2

SBC Normal Mode

The SBC Normal Mode is the standard operating Mode for the SBC. All configurations have to be done in SBC

Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining

the Fail-Safe Mode behavior). A wake-up event on CANx and WK will create an interrupt on pin INTN however,

no change of SBC Mode will occur. The configuration options are listed below:

•

VCC1 is active, Buck in PWM Mode.

VEXT can be switched ON or OFF .

CANx is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart

Mode, see also Chapter 5.1.5).

•

Wake pin level can be monitored and can be selected to be wake capable.

Cyclic wake period can be configured using TIMER_CTRL_0 and enabled by setting TIMER1_WK_ EN.

Watchdog is configurable.

FO is OFF by default.

In SBC Normal Mode, there is the possibility of testing the FO output, i.e. to verify if setting the FO pin to low

will create the intended behavior within the system. The FO output can be enabled and then disabled again

by the microcontroller by setting the FO_ON SPI bit. This feature is only intended for testing purposes.

5.1.3

SBC Stop Mode

The SBC Stop Mode is the first level technique to reduce the overall current consumption. All kind of settings

have to be done before entering SBC Stop Mode. In SBC Stop Mode any kind of SPI write commands are

ignored and the SPI_FAIL bit is set, except for changing to SBC Normal Mode, triggering a SBC Soft Reset,

refreshing the watchdog, changing modulation of the buck. The configuration options are listed below:

•

VCC1 is ON, Buck in PFM Mode if I_VCC1< I_PFM-PWM,TH.

VEXT is fixed ON or OFF in accordance with SPI configuration.

CANx can be selected for ‘Receive Only Mode’, to be wake capable or OFF.

WK pin can be selected to be wake capable, PWM_BY_WK (switch PFM/PWM buck modulation) or OFF.

Wake capability via cyclic wake can be selected.

Watchdog is fixed or OFF (if WD disable sequence was executed).

A wake-up event on CANx and WK will create an interrupt on pin INTN however, no change of SBC Mode will

occur.

In SBC Stop Mode, it is allowed to use the Boost module (enabled before to enter in SBC Stop Mode) in case of

the V_Sis dropping. The Boost works only in PWM and therefore the total amount of current consumption will

increase.

Note:

It is not possible to switch directly from SBC Stop Mode to SBC Sleep Mode. Doing so will also set the

SPI_FAIL flag and will bring the SBC into Normal Mode via SBC Restart Mode.

5.1.4

SBC Sleep Mode

The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum

needed to react on wake-up events.

All settings must be done before entering SBC Sleep Mode. In case that SPI configurations in Sleep Mode have

been sent to the SBC, the commands are ignored and no reactions from the SBC.

The configuration options are listed below:

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Multi-CAN Power+ System Basis Chip

System Features

•

VCC1 is OFF.

VEXT is fixed ON or OFF in accordance with SPI configuration.

CANx can be selected to be wake capable or OFF.

WK pin can be selected to be wake capable or OFF.

A wake-up event on CANx or WK pin will bring the device via SBC Restart Mode into SBC Normal Mode again

and signal the wake event and corresponding sources.

It is not possible to switch off all wake sources in Sleep Mode. This will lead to SBC Normal Mode via SBC

Restart Mode instead.

In order to enter SBC Sleep Mode successfully, all wake source signalization flags from WK_STAT_0 and

WK_STAT_2 need to be cleared. If a failure to do so, will result in an immediate wake-up from SBC Sleep Mode

by going via SBC Restart to Normal Mode.

Note:

As soon as the Sleep Command is sent, the Reset will go low to avoid any undefined behavior

between SBC and microcontroller.

5.1.5

SBC Restart Mode

There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the

microcontroller:

•

From SBC Normal and Stop Mode, it is reached in case of undervoltage on VIO. In case of 4 consecutive

VIO_UV events, SBC Fail-Safe Mode is entered.

•

From SBC Normal and Stop Mode it is reached in case of overvoltage on VIO in config 1/3 if VIO_OV_RST is

set.

•

Incorrect Watchdog triggering (depending of the configuration).

From SBC Sleep and Fail-Safe Mode to ramp up VIO supply after wake event.

From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode, i.e the mode is left automatically

by the SBC without any microcontroller influence once the VIO_UV condition is not present anymore and

when the reset delay time (t_RD1) has expired. The Reset Output (RSTN) is released at the transition.

Entering or leaving the SBC Restart Mode will not result in deactivation of the Fail output.

The following functions are not changed in SBC Restart mode:

•

VEXT is fixed ON or OFF in accordance with SPI configuration.

VCC1 is ON or ramping up.

BOOST is fixed or OFF.

Table 8 contains detailed descriptions of the reason to restart:

Table 8

Reasons for Restart - State of SPI Status Bits after Return to Normal Mode

SBC Mode

Normal

Event

DEV_STAT WD_FAIL

VIO_UV

VIO_OV

Watchdog Failure

VIO undervoltage reset

01

xx

01

x

1

x

1

x

Normal

VIO overvoltage (VIO_OV_RST=1) 01

Sleep Mode

Stop Mode

Wake-up event

10

01

Watchdog Failure

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Multi-CAN Power+ System Basis Chip

System Features

Table 8

Reasons for Restart - State of SPI Status Bits after Return to Normal Mode (cont’d)

SBC Mode

Stop Mode

Fail-Safe

Event

DEV_STAT WD_FAIL

VIO_UV

VIO_OV

VIO undervoltage reset

01

xx

1

x

VIO overvoltage (VIO_OV_RST=1) 01

1

Wake-up event

01

see “Reasons for Fail-Safe, Table 9”

5.1.6

SBC Fail-Safe Mode

The purpose of this mode is to bring the system in a safe status after a failure condition by turning off the VCC1

and VEXT supply and the FO pin is automatically activated. After a wake-up event the system is then able to

restart again.

The Fail-Safe Mode is automatically reached in case of:

•

Overtemperature condition (TSD2).

After 1 or 2 watchdog fails (depending on config setting).

At the 4th consecutive VIO undervoltage event.

From SBC Normal and Stop Mode, in case of overvoltage on VIO in config 2/4, if VIO_OV_RST is set.

VIO is shorted to GND.

VIO is below the VRTx for time longer than t_VIO,SC

.

In this case, the default wake sources are activated, the wake-up events are cleared in the register WK_STAT_0

and WK_STAT_2.

The mode will be maintained for at least t_TSD2in case of TSD2 event and t_FS,minin case of other failure events

to avoid any fast toggling behavior. All wake sources will be masked during this time but the wake-up events

will be stored. Stored wake-up events and wake-up event after this minimum waiting time, will lead to SBC

Restart Mode. Leaving the SBC Fail-Safe Mode will not result in deactivation of the Fail Output pin.

The following functions are influenced during SBC Fail-Safe Mode:

•

FO output is activated.

VCC1 is OFF.

VEXT is OFF.

CANx is wake capable.

WK is wake capable (in case that PWM_BY_WK was set, moving to SBC Fail-Safe Mode will clear the bit).

Cyclic wake is disabled.

Table 9

Mode

Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode

Config Event DEV_STAT TSD2 WD_FAIL VIO_UV VIO_SC VIO_OV

Normal

2

1 × watchdog

01

x

01

x

0

x

failure

Normal

4

2 × watchdog

failure

01

x

10

x

0

x

Normal

1, 2, 3, 4 TSD2

01

1

x

xx

x

1

x

0

1

0

x

1

1, 2, 3, 4 VIO short to GND

2, 4

VIO overvoltage

(VIO_OV_RST=1,

CFG2=1)

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System Features

Table 9

Mode

Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode (cont’d)

Config Event DEV_STAT TSD2 WD_FAIL VIO_UV VIO_SC VIO_OV

Stop Mode

2

1 × watchdog

01

x

01

x

0

x

failure

Stop Mode

4

2 × watchdog

failure

01

x

10

x

0

x

Stop Mode 1, 2, 3, 4 TSD2

01

1

x

xx

x

1

x

0

1

0

x

1

Stop Mode 1, 2, 3, 4 VIO short to GND

Stop Mode 2, 4

VIO overvoltage

(VIO_OV_RST=1,

CFG2=1)

5.1.7

SBC Development Mode

The SBC Development Mode is used during development phase of the application, especially for software

development.

Compared to the default SBC user mode operation, this mode is a super set of the state machine. The device

will start also in SBC Init Mode and it is possible to use all the SBC Modes and functions with following

differences:

•

Watchdog is stopped and does not need to be triggered. Therefore no reset is triggered due to watchdog

failure.

SBC Fail-Safe and Restart Mode are not reached due to watchdog failure but the other reasons to enter

these modes are still valid.

CANx default value in SBC INIT MODE is ON instead of OFF.

The mode is reached by setting the FO/TEST pin to LOW for the entire SBC INIT Mode and by sending an

arbitrary SPI command. The SBC Init Mode is reachable after the power-up or sending a software reset.

SBC Development Mode can only be left by a power-down or by providing a SBC Software Reset using the

MODE bits on M_S_CTRL register regardless the FO/TEST pin level.

When the FO/TEST pin is left open, or connected to V_Sduring the start-up, the SBC starts into normal

operation. The FO/TEST pin has an integrated pull-up resistor (switched ON only during SBC Init Mode) to

prevent the SBC device from starting in SBC Development Mode during normal life of the vehicle. To avoid any

disturbances, the FO/TEST pin is monitored during the SBC Init Mode when the RSTN is HIGH until SBC Init

Mode is left. Only if the FO/TEST pin is LOW for the Init Mode time when the RSTN is HIGH, SBC Development

Mode is reached and stored.

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Multi-CAN Power+ System Basis Chip

System Features

5.2

Wake Features

Following wake sources are implemented in the device:

•

Static Sense: WK input is permanently active (see Chapter 9).

Cyclic Wake: internal wake source controlled via internal timer (see Chapter 5.2.1).

CANx wake: wake-up via CAN message (see Chapter 8).

The wake source must be set before entering in SBC Sleep Mode. In case of critical situation, when the device

will be set into SBC Fail-Safe mode, all default wake sources will be activated. For additional information

about setting, refer to the respective chapters.

5.2.1

Cyclic Wake

The cyclic wake feature is intended to reduce the quiescent current of the device and application.

When the cyclic wake is enabled, a periodic INTN is generated in SBC Normal and Stop Mode based on the

setting of TIMER_CTRL_0.

The correct sequence to configure the cyclic wake is shown in Figure 6. The sequence is as follows:

•

Disable the cyclic wake feature to ensure that there is not unintentional interrupt when activating cyclic

wake (TIMER1_WK_ EN = 0).

•

Configure the cyclic wake timer period in TIMER_CTRL_0 register.

Enable the cyclic wake as a wake-up source in the register WK_CTRL_0 (TIMER1_WK_ EN = 1).

Cyclic Wake Configuration

Reset the TIMER1_WK_EN bit on

To avoid unintentional interrupts

WK_CTRL_0 register

Select Timer Period in

Periods: 10, 20, 50, 100, 200ms, 1s, 2s

TIMER_CTRL_0

No interrupt will be generated,

if the timer is not enabled as a wake source

Set the TIMER1_WK_EN bit on

WK_CTRL_0 register

Cyclic Wake starts / ends by

setting / clearing On-time

INT is pulled low at every rising edge

of On-time except first one

Figure 6

Cyclic Wake: Configuration and Sequence

5.2.2

Internal Timer

The integrated timer is typically used to wake up the microcontroller periodically (cyclic wake).

Following periods can be selected via the register TIMER_CTRL_0:

•

Period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

6

DC/DC Regulator

6.1

Block Description

The SMPS module in the TLE9278BQX V33 is implemented as a cascade of a step-up regulator followed by a

step-down post-regulator. The step-up regulator (DC/DC Boost converter) provides a V_Slevel which permits

the step-down post-regulator (DC/DC Buck converter) to regulate without entering a low-drop condition.

The SMPS module is active in SBC Normal, Stop and Restart Mode. In SBC Sleep and Fail-Safe Mode, the SMPS

module is disabled.

Comparator

VS

D1

L1

D2

Vbat

SPI

VSUP

VS

Boost

Converter

C1

C2

C3

Cf1

BSTD

GND

Feedforward

Buck

Converter

L2

BCKSW

C4

C5

GND

Bandgap

Reference

VCC1

Soft Start

Ramp

Generator

Figure 7

DC/DC Block Diagram

Functional Features

•

3.3 V SMPS (DC/DC) Buck Regulator with integrated high-side and low-side power switching transistor.

SMPS (DC/DC) Boost Regulator for low V_SUPsupply voltage with integrated power transistor.

Adjustable output DC/DC Boost pre-regulator voltage via SPI.

Fixed switching frequency for Buck and Boost Regulator in SBC Normal Mode in PWM (Pulse Width

Modulation).

•

PFM (Pulse Frequency Modulation) for Buck converter in SBC Stop Mode to reduce the quiescent current.

Automatic transition PFM to PWM in SBC Stop Mode.

Soft start-up.

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

•

Edge Shaping for better EMC performances for Buck and Boost regulator.

Undervoltage monitoring via VIO pin with adjustable reset level (refer to Chapter 12.7).

Overvoltage detection via VIO pin activates the FO pin in case that VIO_OV_RST bit is set (refer to

Chapter 12.8).

•

Buck short circuit detection.

Buck 100% Duty Cycle at low V_Soperation.

Buck overcurrent peak detection.

Boost overcurrent peak detection.

6.1.1

Functional Description of the Buck Converter

SPI

Logic

L1

D1

VS

C3

V_SUP

Vbat

Feedforward

C2

C1

Buck

Converter

L2

BCKSW

C5

C6

GND

Bandgap

Reference

VCC1

Soft Start

Ramp

Generator

Figure 8

Buck Block Diagram

The DC/DC Buck converter is intended as post-regulator (VCC1) and it provides a step down converter function

transferring energy from V_Sto a lower output voltage with high efficiency (typically more than 80%). The

output voltage is 3.3 V in a current range up to 750 mA. It is regulated via a digital loop with a precision of ±2%.

It requires an external inductor and capacitor filter on the output switching pin (BCKSW). The Buck regulator

has integrated high-side and low-side power switching transistors. The compensation of the regulation loop

is done internally and no additional external components are needed.

A typical application example and external components proposal is available in Chapter 14.1.

The Buck converter is active in SBC Normal, Stop and Restart Mode and it is disabled in SBC Sleep and Fail-

Safe Mode.

Depending on the SBC Mode, the Buck converter works in two different modes:

•

PWM Mode (Pulse Width Modulation): This mode is available in SBC Normal Mode, SBC Restart Mode and

SBC Stop Mode (only for automatic or manual PFM to PWM transitions. Refer to Chapter 6.2.2). In PWM,

the Buck converter operates with a fixed switching frequency (f_BUK). The duty cycle is calculated internally

based on input voltage, output voltage and output current. The precision is ±2% on input supply and

output current range (refer to Figure 13 for more information). In PWM Mode, the Buck converter is

capable of a 100% duty cycle in case of low V_Sconditions. In order to reduce EMC, the edge shaping feature

has been implemented to control the activation and deactivation of the two power switches.

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

•

PFM Mode (Pulse Frequency Modulation): This mode is activated automatically when the SBC Stop Mode

is entered. The PFM Mode is an asynchronous mode. PFM Mode does not have a controller switching

frequency. The switching frequency depends on conditions of the Buck regulator such as the following:

input supply voltage, output voltage, output current and external components. A typical timing diagram is

shown in Figure 9. The Buck converter in PFM Mode has a tolerance of ±4%. The transition from PFM mode

to PWM mode is described in Chapter 6.2.2.

Tristate

HS

LS

Tristate

Feedback Voltage VCC 1

LVL

UCL

LCL

Coil Current

start biasing

&

oscillator

OFF

ON

OFF

ON

PFM active

Iq

Quiescent Current

Figure 9

Typical PFM timing diagram

6.1.1.1 Startup Procedure (Soft Start)

The Startup Procedure (Soft Start) permits to achieve the Buck regulator output voltage avoiding large

overshoot on the output voltage. This feature is activated during the power-up, from SBC Sleep to Restart

Mode and from SBC Fail-Safe to SBC Restart Mode.

When the Buck regulator is activated, it starts in open loop with a minimum duty cycle which is maintained for

a limited number of switching periods. After this first phase, the duty cycle is linearly increased by a fixed step

and it is maintained for a limited number of switching periods for each duty cycle step. This procedure is

repeated until the target output voltage value of the Buck regulator is reached. As soon as the Buck regulator

output voltage is reached, the regulation loop is closed and it starts to operate normally using PWM Mode

adjusting the duty cycle according to the Buck input and output voltages and the output current.

6.1.1.2 Buck regulator Status register

The register SMPS_STAT contains information about the open or short conditions on BCKSW pin. No SBC

Mode or configuration changes are triggered if one bit on SMPS_STAT register is set.

6.1.1.3 External components

The Buck converter needs one inductor and output capacitor filter. The inductor has a fixed value of 47 µH.

Secondary parameters such as saturation current must be selected based on the maximum current capability

needed in the application.

The output filter capacitors are two parallel 22 µF ceramic capacitor. For additional information, refer to

Chapter 14.1.

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

6.1.2

Functional Description of the Boost Converter

Comparator

VS

D1

L1

D2

Vbat

SPI

VSUP

Boost

Converter

C1

C3

C4

C2

BSTD

GND

VS

Figure 10 Boost Block Diagram

The Boost converter is intended as a pre-regulator and it provides a step up converter function. It transfers

energy from an input supply V_SUP(battery voltage after reverse protection circuit) to a higher output voltage

(V_S) with high efficiency (typically more than 80%).

The regulator integrates the power switching and the sense resistor for overcurrent detection.

The Boost regulator can be enabled in SBC Normal Mode via SPI (register HW_CTRL_0, bit BOOST_EN) and

four output voltage values are selectable via BOOST_V. The Boost regulator can also be active in SBC Stop and

Restart Mode. The selected boost output voltage will automatically define the voltage thresholds where the

boost will be ON (V_BST,TH1, V_BST,TH2, V_BST,TH3and V_BST,TH4). If the Boost regulator is enabled, it switches ON

automatically when V_Sfalls below the selected threshold voltage and switches OFF when crossing this

threshold including hysteresis again. The bit BST_ACT on SMPS_STAT register indicates that the Boost has

been activated.

The Boost output voltage can be changed only if BOOST_EN is set to 0. In case that the boost output voltage

configuration changes with BOOST_EN set to 1, the SPI_FAIL bit is set and the command is ignored.

Figure 11 shows the typical timing for enabling the Boost converter.

VSUP

VS

V_BST,THx

V_BSTx

V_BST,HYSx

0

1

0

BST_ACT

BSTD

Figure 11 Boost converter activation

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

The Boost regulator works in PWM Mode with fixed frequency (f_BST) and a tolerance of ±3%.

If the Boost is enabled in Stop Mode, the quiescent current in the SBC is increased (P_4.4.31).

6.1.2.1 Boost Regulator Status register

The register SMPS_STAT contains information about the open or short conditions on Boost pins including loss

of GND detection. No SBC mode or configuration is triggered if one bit is set on the SMPS_STAT register.

6.1.2.2 External Components

The Boost converter requires a number of external components such as the following: input buffer capacitor

on the battery voltage, inductor, freewheeling diode and filter capacitors.

For recommend external components and corresponding values, refer to Chapter 14.1.

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

6.2

Power Scenarios

The chapter describes the features and performance of the Buck regulator according to SBC modes. The Boost

module works only in SBC Normal or Stop Mode using PWM modulation (refer also to Chapter 6.1.2).

6.2.1

Buck behavior in SBC Normal Mode

In SBC Normal Mode the Buck works is in PWM mode with fixed switching frequency. All supervision functions

for Buck converter are available in SBC Normal Mode and available depending the device configuration

(Chapter 5.1.1). For additional details on the supervision functions, refer to Chapter 12.7, Chapter 12.8,

Chapter 12.9 and Chapter 12.11.

6.2.2

Buck behavior in SBC Stop Mode

The SBC Stop Mode operation is intended to reduce the total amount of quiescent current while still providing

output voltage. In order to achieve this, the Buck regulator changes the modulation from PWM (Pulse Width

Modulation) to PFM (Pulse Frequency Modulation) when entering SBC Stop Mode.

In SBC Stop Mode, the Buck modulation can change as follow:

•

Buck module always in PFM modulation (default setting).

Automatically change from PFM to PWM (setting PWM_AUTO).

Modulation is controlled by the WK pin (setting PWM_BY_WK).

If the PWM_BY_WK and PWM_AUTO are set at the same time, the PWM_AUTO has highest priority and PWM

automatic transition will be used.

If PWM_BY_WK and PWM_AUTO are at the same time set to 0, the buck module remains in PFM in SBC Stop

Mode.

If in SBC Stop Mode the Buck modulation is PWM, the buck output voltage tolerance and output current

capability are like SBC Normal Mode (P_6.5.13 and P_6.5.46).

6.2.2.1 Automatic Transition from PFM to PWM in SBC Stop Mode

If more current is needed, an automatic transition from PFM to PWM mode is implemented. When the Buck

regulator output current exceeds the I_PFM-PWM,THthreshold, the Buck module changes the modulation to PWM

and an INTN event is generated. In addition, the PFM_PWM bit on WK_STAT_0 is set.

In order to set the Buck modulation again in PFM mode, a SBC Stop Mode command has to be write to

M_S_CTRL register. This command has to be sent when the required Buck output current is below the I_PFM-

_PWM,THthreshold.

By default, the feature is disable. To enable the automatic transition from PFM to PWM, the PWM_AUTO bit in

HW_CTRL_0 has to be set before entering SBC Stop Mode.

When entering SBC Stop Mode, the automatic transition from PFM to PWM mode is activated after the

transition time (t_lag), during which the Buck regulator loop changes the modulation technique. Figure 12

shows the timing transition from SBC Normal to Stop Mode.

The transition time t_lagis always implemented in case of transition from PWM to PFM modulation.

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

SPI Commands

Buck modulation

Normal Mode

PWM

Stop Mode

Auto PFM ↔ PWM

PWM

t

t_lag

Figure 12 Transition from SBC Normal to SBC Stop Mode

The t_lagcan be configured via SPI using the PWM_TLAG in HW_CTRL_0 register.

The automatic transition from PFM to PWM can be disabled by setting the PWM_AUTO to 0 in the HW_CTRL_0

register.

6.2.2.2 Manual Transition from PFM to PWM in SBC Stop Mode

The PFM to PWM transition can also be controlled by the microcontroller or an external signal by using the WK

pin as a trigger signal in SBC Stop Mode.

When the PWM_BY_WK bit is set to 1, the Buck regulator can be switched from PFM to PWM using the WK pin.

A LOW level at the WK pin will switch the Buck converter to PFM mode, a HIGH level will switch the Buck

converter to PWM Mode. In this configuration, the transition time t_lagis not taken into account because a

defined signal from microcontroller or external source is expected.

6.2.2.3 SBC Stop to Normal Mode transition

The microcontroller sends an SPI command to switch from SBC Stop Mode to SBC Normal Mode. In this

transition, the Buck regulator changes the modulation from PFM to PWM.

Once the SPI command for the SBC Normal Mode transition is received, the Buck output current is able to rise

above the specified maximum Stop Mode current (I_PFM-PWM,TH).

If the transition from SBC Stop Mode to SBC Normal Mode is carried out when the Boost is enabled and

operating, it will continue to operate without any changes.

6.2.3

Buck behavior in SBC Sleep or Fail Safe Mode

In SBC Sleep or Fail Safe Mode, the Buck and Boost converter are off and not operating. The lowest quiescent

current is achievable.

6.2.3.1 SBC Sleep/Fail Safe Mode to SBC Normal Mode transition

In case of a wake-up event from WK pin or transceivers, the SBC will be set to SBC Restart Mode and as soon

as the reset is released, into SBC Normal Mode.

In SBC Restart Mode, the Buck regulator is activated and ramping-up. The Boost regulator is activated and

ramping-up again (in case the V_Sis below the selected threshold) in according the configuration selected in

SBC Normal Mode. As soon as the Buck output voltage exceeds the reset threshold, the RSTN pin is released.

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

6.3

Electrical Characteristics

Table 10 Electrical Characteristics

T_j= -40°C to +150°C; V_S= 5.5 V to 28 V; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Buck Regulator

Output Voltage PWM including V_CC1,out13.23 3.3

Line and Load regulation

3.37

3.44

3.39

V

SBC Normal Mode

(PWM)

1 mA < I_VCC1< 750 mA

6.5 V < V_S< 28 V

Boost Disable

¹⁾SBC Normal Mode

(PWM)

P_6.5.13

Output Voltage PWM including V_CC1,out13.23 3.3

Line and Load regulation

P_6.5.46

I_VCC1= 400 mA

V_S=4 V

Boost Disable

Output Voltage PFM including V_CC1,out23.16 3.3

Line and Load regulation

SBC Stop Mode (PFM) P_6.5.14

10 µA < I_VCC1< I_PFM-

PWM,TH

6.5 V < V_S< 28 V

Boost Disable

Output Voltage PFM including V_CC1,out33.18 3.3

Line and Load regulation

SBC Stop Mode (PFM) P_6.5.48

10 µA < I_VCC1< 50 mA

6.5 V < V_S< 28 V

Boost Disable

Power Stage on-resistance

High-Side

R_DSON1,HS

R_DSON1,LS

–

1.3

Ω

A

V_S= 6.5 V

_VS= 100 mA

P_6.5.3

P_6.5.20

P_6.5.40

P_6.5.5

P_6.5.6

I

Power Stage on-resistance

Low-Side

I_BCKSW= 100 mA

Overcurrent peak limitation

internal high side

I_{BCK_LIM,TH}0.85 1.05 1.2

V_S> 6.5 V

Buck switching frequency

f_BUK

405 450 495 kHz SBC Normal Mode

(PWM)

Automatic transition PFM to

PWM threshold

80

110 150 mA

¹⁾SBC Stop Mode

(PFM)

I_PFM-

PWM,TH

6.5 V < V_S< 28 V

Transition time from PWM to t_lag

PFM

–

1

–

ms

µs

¹⁾PWM_TLAG=1

(on HW_CTRL_0)

¹⁾PWM_TLAG=0

(on HW_CTRL_0)

P_6.5.15

P_6.5.16

Transition time from PWM to t_lag

PFM

100

Boost Regulator

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

Table 10 Electrical Characteristics (cont’d)

T_j= -40°C to +150°C; V_S= 5.5 V to 28 V; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Boost Voltage 1 including Line V_BST1

and Load regulation

6.5

6.7

6.9

V

²⁾SBC Normal Mode

_SUP= 3 V

_VS= 550 mA

Boost enabled

BOOST_V = 00_B

P_6.5.7

V

I

Boost Voltage 2 including Line V_BST2

and Load regulation

7.76

9.7

8

8.24

10.3

²⁾SBC Normal Mode

P_6.5.8

V

_SUP= 3V

I_VS= 450 mA

Boost enabled

BOOST_V = 01_B

²⁾SBC Normal Mode

Boost Voltage 3 including Line V_BST3

and Load regulation

10

P_6.5.28

P_6.5.31

V

_SUP= 3 V

I_VS= 300 mA

Boost enabled

BOOST_V = 10_B

²⁾SBC Normal Mode

Boost Voltage 4 including Line V_BST4

11.64 12

12.36 V

and Load regulation

V

_SUP= 3 V

I_VS= 250 mA

Boost enabled

BOOST_V = 11_B

Boost Switch ON voltage

V_BST,TH1

6.50

7

7.30

8.90

V

Boost enabled, V_S

falling

BOOST_V = 00_B

P_6.5.9

V_BST,TH2

V_BST,TH3

V_BST,TH4

V_BST,HYS

7.90 8.5

Boost enabled, V_S

falling

BOOST_V = 01_B

P_6.5.18

P_6.5.34

P_6.5.35

9.80 10.5 10.80 V

Boost enabled, V_S

falling

BOOST_V = 10_B

11.7 12.5 13.0

V

Boost enabled, V_S

falling

BOOST_V = 11_B

Boost Switch ON/OFF

hysteresis

0.35 0.5

2.0

0.70

2.3

V

A

Boost enabled

P_6.5.10

P_6.5.11

P_6.5.12

Overcurrent peak limitation

internal switch

I_{BST_LIM,TH}1.7

f_BST

Boost enable

V_SUP≥ 3 V

Boost switching frequency

405 450 495 kHz SBC Normal Mode

(PWM)

1) Not subject to production test, specified by design.

2) Values verified in characterization with Boost converter external components specified in Chapter 14.1. No subject

to production test; specified by design. Refer to Figure 14 for additional information.

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Multi-CAN Power+ System Basis Chip

DC/DC Regulator

800

750

700

650

600

550

500

450

400

VCC1 tolerance +/-2%

4

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

5

5.1 5.2 5.3 5.4 5.5 6.5

8

10 12 18 20 24 28

V_S(V)

Figure 13 Maximum DCDC Buck current capability versus V_S

Note:

Figure 13is based on characterization results overtemperature with external components specified

in Chapter 14.1.

1.8

1.6

1.4

1.2

1

0.8

V_BST1

0.6

V_BST2

V_BST3

V_BST4

11

0.4

0.2

3

4

5

6

7

8

9

10

12

V_SUP(V)

Figure 14 Maximum DCDC Boost current capability versus V_SUP

Note:

Figure 14 is based on simulation results (specified by design), with Boost converter external

components specified in Chapter 14.1.

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Multi-CAN Power+ System Basis Chip

External Voltage Regulator

7

External Voltage Regulator

7.1

Block Description

VEXTIN

VEXTSH

VEXTB

VEXTREF

R_BE

I_EXTbase

V_EXTIN- V_EXTshunt

> V_{shunt_threshold}

+

-

V_REF

State Machine

Figure 15 Functional Block Diagram

Functional Features

•

Low-drop voltage regulator with external PNP transistor (up to 400 mA with 470 mΩ shunt resistor).

Four high voltage pins are used: VEXTIN, VEXTB, VEXTSH, VEXTREF.

Dedicated supply input VEXTIN to supply from V_Sor from VCC1 (Buck regulator output voltage) depending

on the application.

•

Configurable output voltages via SPI: 5.0 V, 3.3 V (default), 1.8 V and 1.2 V.

≥ 4.7 µF ceramic capacitor at output voltage for stability, with ESR < 150 mΩ @ f = 10 kHz to achieve the

voltage regulator control loop stability based on the safe phase margin (bode diagram).

•

Overcurrent limitation can be configured with external shunt resistor.

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Multi-CAN Power+ System Basis Chip

External Voltage Regulator

7.2

General Description

The external voltage regulator is used as an independent voltage regulator. The VEXT_VCFG in HW_CTRL_1

register set the VEXT output voltage. The VEXT_ON in the M_S_CTRL register in SBC Normal Mode activates

the VEXT voltage regulator.

The regulator will act in the respective SBC Mode as described in Table 11.

The maximum current I_{EXT_max}is defined by the shunt used. To protect the VEXT against overtemperature

condition, the base driver has a dedicate temperature sensor. For detailed temperature protection features,

refer to Chapter 12.11.

The status of VEXT is reported in the SUP_STAT_1 register (for detailed protection features refer to

Chapter 12.10).

Table 11 External Voltage Regulator State by SBC Mode

SBC Mode

Voltage Regulator Behavior

INIT Mode

OFF

Normal Mode

Stop Mode

Configurable

Fixed

Sleep Mode

Restart Mode

Fail-Safe Mode

Fixed

OFF

Note:

The configuration of the VEXT voltage regulator behavior must be implemented immediately when

the SBC Normal Mode is reached after power-up of the device. As soon as the bit VEXT_ON is set for

the first time, the configuration for VEXT cannot be changed anymore. The configuration cannot be

changed as long as the device is supplied.

Note:

If the VEXT output voltage is supplying external off-board loads, the application must consider the

series resonance circuit built by cable inductance and decoupling capacitor at load. Sufficient

damping must be provided(e.g. series resistor with capacitor directly at device or 100 Ω Resistor

between PNP collector and VEXTREF with 10 µF cap on collector (see Figure 16).

7.2.1

Functional Description

This regulator offers with VEXT a second supply which could be used as off-board supply e.g. for sensors due

to the integrated HV pins VEXTB, VEXTSH, VEXTREF.

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Multi-CAN Power+ System Basis Chip

External Voltage Regulator

V_{S ,}V_CC1or V_SUP

V_EXT

R_SHUNT

T1

I_EXT

C₂

C₁

R_Lim

100Ω

VEXTIN

VEXTSH

VEXTB

R_BE

VEXTREF

I_EXTbase

V_EXTIN- V_EXTshunt

> V_{shunt_threshold}

+

-

V_REF

State Machine

Figure 16 VEXT Hardware Setup

VEXT can be switched ON or OFF but the output voltage configuration cannot no longer be changed once

activated.

An overcurrent detection function is realized with the external shunt (see Chapter 7.4 for calculating the

desired shunt value) and output current shunt voltage threshold (V_{shunt_threshold}). When this threshold is

reached, IEXT is limited and only the overcurrent detection bit VEXT_OC is set (no other reactions). This bit can

be cleared via SPI once the overcurrent condition is no longer present. If the overcurrent detection feature is

not needed, connect the VEXTSH pin to VEXT supply (VEXTIN pin).

If the VEXT is enabled, an undervoltage event is signaled with the bit VREG_UV in the SUP_STAT_0 register.

7.3

External Components

The characterization is done with the BCP52-16 from Infineon (I_EXT< 200 mA) and with MJD253 from ON

Semi.Other PNP transistors can be used. The functionality must be checked in the application.

Figure 16 shows the hardware set up used.

Table 12 Bill of Materials for VEXT with BCP52-16

Device

C2

Vendor

Murata

–

Reference / Value

10 µF/10V GCM31CR71A106K64L

RSHUNT

T1

1 Ω

Infineon

BCP52-16

Note:

The SBC is not able to ensure a thermal protection of the external PNP transistor. The power

handling capabilities for the application must therefore be chosen according to the selected PNP

device and according to the PCB layout and the properties of the application to prevent thermal

damage.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

External Voltage Regulator

Table 13 Bill of Materials for VEXT with MJD-253

Device

C2

Vendor

Murata

–

Reference / Value

10 µF/10V GCM31CR71A106K64L

470 mΩ

RSHUNT

T1

ON-Semi

MJD253

7.4

Calculation of R_SHUNT

The maximum current I_{EXT_max}where the overcurrent detection bit is set (VEXT_OC = 1 on the SUP_STAT_1

register), is determined by the shunt resistor R_SHUNTand the Output Current Shunt Voltage Threshold

(V_{shunt_threshold}).

The resistor can be calculated as following:

V_{shunt _ threshold}

(7.1)

R_SHUNT

=

I_{EXT _ max}

7.5

Unused Pins

In case the VEXT is not used in the application, connect the unused pins of VEXT as followed:

•

Connect VEXTSH, VEXTIN to V_Sor leave open.

Leave VEXTB open.

Leave VEXTREF open.

Keep VEXT disabled.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

External Voltage Regulator

7.6

Electrical Characteristics

Table 14 Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; SBC Normal Mode; all outputs open; all voltages with respect to ground;

positive current defined flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or Test Condition Number

Min.

Parameters independent from Test Set-up

Max.

External Regulator I_EXTbase

Control Drive

40

60

80

mA

V_EXTbase= 13.5 V

P_7.6.1

Current Capability

Input Current

V_EXTref

I_EXTref

–

1

3

10

µA

mV

V_EXTref= 3.3 V, 5 V, 1.8 V, P_7.6.2

1.2 V

Input Current V_EXTI_EXTshunt

Shunt Pin

3

10

V_EXTshunt= V_S

P_7.6.3

P_7.6.4

1)

Output Current

Shunt Voltage

Threshold

V_{shunt_threshold}180

245

310

Leakage current of I_{EXTbase_lk}

_EXTbasewhen VEXT

disabled

–

5

µA

V_EXTbase= V_S;

T_j= 25°C

P_7.6.7

V

Leakage current of I_{EXTshunt_lk}

V_EXTshuntwhen VEXT

disabled

V_EXTshunt= V_S;

T_j= 25°C

P_7.6.25

Base to emitter

resistor

R_BE

120

–

150

50

185

–

kΩ

V_EXTbase= V_S- 0.3 V;

V_EXTOFF

²⁾Drive current I_{_EXTbase}

I_EXTbaserising

P_7.6.9

Active Peak

Threshold VEXT

(Transition

I_VEXT,Ipeak,r

µA

;

P_7.6.26

V_S=13.5 V;

threshold between

high-power and

low-power mode

regulator)

-40°C < T_j< 150°C

Active Peak

Threshold VEXT

(Transition

I_VEXT,Ipeak,f

–

30

–

µA

²⁾Drive current I__EXTbase

I_EXTbasefalling

V_S= 13.5 V;

;

P_7.6.27

P_7.6.10

threshold between

high-power and

low-power mode

regulator)

-40°C < T_j< 150°C

Parameters dependent on the Test Set-up (with external PNP device MJD-253)

External Regulator V_EXT,out1

Output Voltage

4.9

5

5.1

V

³⁾SBC Normal Mode;

VEXT_VCFG=00_B

including Line and

Load regulation

5.5 V < V_INEXT< 28 V

10 mA < I_EXT< 400 mA;

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

External Voltage Regulator

Table 14 Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; SBC Normal Mode; all outputs open; all voltages with respect to ground;

positive current defined flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

5

Unit Note or Test Condition Number

Min.

Max.

External Regulator V_EXT,out2

Output Voltage

including Line and

Load regulation

4.8

5.2

V

³⁾SBC Stop, Sleep Mode; P_7.6.21

VEXT_VCFG=00_B

5.5 V < V_INEXT< 28 V

10 µA < I_EXT< 20 mA;

External Regulator V_EXT,out3

Output Voltage

including Line and

Load regulation

3.23

3.15

1.75

1.7

3.3V

1.8

3.37

3.45

1.85

1.9

³⁾SBC Normal Mode;

VEXT_VCFG=01_B

P_7.6.11

5.5 V < V_INEXT< 28 V

10 mA < I_EXT< 300 mA;

³⁾SBC Stop, Sleep Mode; P_7.6.12

VEXT_VCFG=01_B

5.5 V < V_INEXT< 28 V

10 µA < I_EXT< 20 mA;

External Regulator V_EXT,out4

Output Voltage

including Line and

Load regulation

External Regulator V_EXT,out5

Output Voltage

including Line and

Load regulation

³⁾SBC Normal Mode;

VEXT_VCFG=10_B

P_7.6.13

5.5 V < V_INEXT< 28 V

10 mA < I_EXT< 300 mA;

³⁾SBC Stop, Sleep Mode; P_7.6.14

VEXT_VCFG=10_B

5.5 V < V_INEXT< 28 V

10 µA < I_EXT< 20 mA;

External Regulator V_EXT,out6

Output Voltage

including Line and

Load regulation

1.8

External Regulator V_EXT,out7

Output Voltage

including Line and

Load regulation

1.16

1.15

1.2

1.24

1.25

³⁾SBC Normal Mode;

VEXT_VCFG=11_B

P_7.2.22

5.5 V < V_INEXT< 28 V

10 mA < I_EXT< 300 mA;

³⁾SBC Stop, Sleep Mode; P_7.6.23

VEXT_VCFG=11_B

External Regulator V_EXT,out8

Output Voltage

1.2

including Line and

Load regulation

5.5 V < V_INEXT< 28 V

10 µA < I_EXT< 20 mA;

1) Threshold at which the current limitation starts to operate.

2) Not subject to production test, specified by design.

3) Tolerance includes load regulation and line regulation.

Datasheet

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

8

High Speed CAN Transceiver

8.1

Block Description

VCAN

V_IO

SPI Mode

Control

R_TD

Driver

CANHx

CANLx

Output

Stage

TXDCANx

Temp.-

Protection

+

timeout

To SPI diagnostic

VCAN

V_IO

RXDCANx

MUX

Receiver

Vs

Wake

Receiver

Figure 17 Functional Block Diagram

8.2

Functional Description

The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode

data transmission (up to 5 Mb) and reception in automotive and industrial applications. It works as an

interface between the CAN protocol controller and the physical bus lines compatible with ISO 11898-2, 11898-

5 as well as SAE J2284.

The CAN transceiver offers low power modes to reduce current consumption. This supports networks with

partially powered down nodes. To support software diagnostic functions, a CAN Receive-only Mode is

implemented.

It is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks,

clamp15/30 applications).

A wake-up from the CAN wake capable mode is possible via a message on the bus. Thus, the microcontroller

can be powered down or idled and will be woken up by the CAN bus activities.

The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support

12 V applications.

The different transceiver modes can be controlled via the SPI CANx bits.

Figure 18 shows the possible transceiver mode transitions when changing the SBC mode.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

SBC Mode

CAN Transceiver Mode

SBC Stop Mode

Receive Only Wake Capable

OFF

SBC Normal Mode

SBC Sleep Mode

SBC Restart Mode

SBC Fail-Safe Mode

Receive Only Wake Capable Normal Mode

Wake Capable

OFF

Woken¹

Wake Capable

¹after a wake event on CAN Bus

Behavior after SBC Restart Mode - not coming from SBC Sleep Mode due to a wake up of the respective transceive:r

If the transceivers had been configured to NormalMode, or Receive Only Mode, then the mode will be changed toWake

Capable. If it was Wake Capable, then it will remainWake Capable. If it had been OFF before SBC Restart Mode, then it

will remain OFF.

Behavior in SBC Development Mode:

CAN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF.

Figure 18 CAN Mode Control Diagram

CAN FD Support

CAN FD stands for ‘CAN with Flexible Data Rate’. It is based on the well established CAN protocol as specified

in ISO 11898-1. CAN FD still uses the CAN bus arbitration method. The benefit is that the bit rate can be

increased by switching to a shorter bit time at the end of the arbitration process and then returning to the

longer bit time at the CRC delimiter before the receivers transmit their acknowledge bits. See also Figure 19.

In addition, the effective data rate is increased by allowing longer data fields. CAN FD allows the transmission

of up to 64 data bytes compared to the 8 data bytes from the standard CAN.

Standard CAN

message

Data phase

(Byte 0 – Byte 7)

CAN Header

CAN Footer

Example:

- 11 bit identifier + 8Byte data

CAN FD with

reduced bit time

Data phase

(Byte 0 – Byte 7)

CAN Header

CAN Footer

- Arbitration Phase

- Data Phase

500kbps

2Mbps

à average bit rate

1.14Mbps

Figure 19 Bit Rate Increase with CAN FD vs. Standard CAN

CAN FD has to be supported by both the physical layer and the CAN controller. If the CAN controller cannot

support CAN FD, then the respective CAN node must at least tolerate CAN FD communication. This CAN FD

tolerant mode is implemented in the physical layer.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

8.2.1

CAN OFF Mode

The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is

intended to completely stop CAN activities or when CAN communication is not needed. The CANH/L bus

interface acts as a high impedance input with a very small leakage current. In CAN OFF Mode, a wake-up event

on the bus will be ignored.

8.2.2

CAN Normal Mode

The CAN Transceiver is enabled via SPI in SBC Normal Mode. CAN Normal Mode is designed for normal data

transmission/reception within the HS-CAN network. The mode is only available in SBC Normal Mode or SBC

Init Mode if the SBC Development Mode is used. The bus biasing is set to VCAN/2.

Transmission

The signal from the microcontroller is applied to the TXDCANx input of the SBC. The bus driver switches the

CANH/L output stages to transfer this input signal to the CAN bus lines.

Enabling sequence

The CAN transceiver requires an enabling time t_CAN,ENbefore a message can be sent on the bus. This means

that the TXDCANx signal can only be pulled LOW after the enabling time. If this is not ensured, then the

TXDCANx needs to be set back to HIGH (=recessive) until the enabling time is completed. Only the next

dominant bit will be transmitted on the bus. Figure 20 shows different scenarios and explanations for CAN

enabling.

V

TXDCAN

t

CAN

Mode

t _CAN,EN

t_CAN,EN

t _CAN,EN

CAN

NORMAL

CAN

OFF

t

V

CANDIFF

Dominant

Recessive

recessive

TXDCAN

level required

recessive TXDCAN

level required before

start of transmission

Correct sequence ,

Bus is enabled after t_CAN,

t_CAN,_ENnot ensured , no

transmission on bus

t_{CAN, EN}not ensured ,

no transmission on bus

EN

Figure 20 CAN Transceiver Enabling Sequence

Reduced Electromagnetic Emission

To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically.

The slope control can be disabled using the CAN_x_Flash bits to achieve bite rate higher than 5 Mb.

Reception

Analog CAN bus signals are converted into digital signals at RXDCANx via the differential input receiver.

8.2.3

CAN Receive Only Mode

In CAN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still operational. This

mode is available in SBC Normal and Stop Mode. The bus biasing is set to VCAN/2.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

8.2.4

CAN Wake Capable Mode

This mode can be used in SBC Stop, Sleep, Restart and Normal Mode and it is used to monitor bus activities. It

is automatically accessed in SBC Fail-Safe Mode. A valid wake-up pattern (WUP) on the bus results in a change

of behavior of the SBC, as described in Table 15. As a signalization to the microcontroller, the RXDCANx pin is

set LOW and will stay LOW until the CANx transceiver is changed to any other mode. After a wake-up event, the

transceiver can be switched to CAN Normal Mode for communication using SPI command.

As shown in Figure 21, a wake-up pattern is signaled on the bus by two consecutive dominant bus levels for

at least t_Wake1(filter time t > t_Wake1), each separated by a recessive bus level of less than t_Wake2

.

Entering low-power mode,

when selective wake-up

function is disabled

or not supported

Bus recessive > tWAKE1

Ini

Wait

Bias off

Bus dominant > tWAKE1

optional:

tWAKE2 expired

1

Bias off

Bus recessive > t^WAKE1

optional:

tWAKE2 expired

2

Bias off

Bus dominant > tWAKE1

Silence expired AND

t

Entering CAN Normal

or CAN Recive Only

Device in low-power mode

3

Bias on

Bus dominant > tWAKE1

Bus recessive > tWAKE1

tSilence expired AND

device in low-power mode

4

Bias on

Figure 21 WUP detection following the definition in ISO 11898-5

Rearming the Transceiver for Wake Capability

After a bus wake-up event, the transceiver is woken. However, the CANx transceiver mode bits will still show

wake capable (=‘01’) so that the RXDCAN signal will be pulled low. There are two possibilities how the CAN

transceiver’s wake capable mode is enabled again after a wake event:

•

The CAN transceiver mode must be toggled, i.e. switched from Wake Capable Mode to CAN Normal Mode,

CAN Receive Only Mode or CAN Off, before switching to CAN Wake Capable Mode again.

•

Rearming is done automatically when the SBC is changed to SBC Stop, Sleep, or SBC Fail-Safe Mode to

ensure wake-up capability.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

Note:

It is not necessary to clear the CAN wake-up bit CAN_x_WU to become wake capable again. It is

sufficient to toggle the CAN mode.

Wake-Up in SBC Stop and Normal Mode

In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INTN output and in the WK_STAT_0,

WK_STAT_2 SPI registers. It is also signaled by RXDCANx pulled to low. The same applies for the SBC Normal

Mode. The microcontroller should set the device from SBC Stop Mode to SBC Normal Mode; there is no

automatic transition to SBC Normal Mode.

For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a bus wake

event in case it was disabled before (if bit WD_EN_WK_ BUS was configured to HIGH before).

Wake-Up in SBC Sleep Mode

Wake-up is possible via a CAN message (filter time t > t_Wake1). The wake-up automatically transfers the SBC into

the SBC Restart Mode and from there to Normal Mode the corresponding RXDCANx pin in set to LOW. The

microcontroller is able to detect the low signal on RXDCANx and to read the wake source out of the

WK_STAT_0 or WK_STAT_2 register via SPI. No interrupt is generated when coming out of SBC Sleep Mode.

The microcontroller can now for example switch the CAN transceiver into CAN Normal Mode via SPI to start

communication.

Table 15 Action due to CAN Bus Wake-Up

SBC Mode

SBC Mode after Wake

Normal Mode

Stop Mode

VCC1

INTN

LOW

HIGH

RXD

LOW

Normal Mode

Stop Mode

ON

Sleep Mode

Restart Mode

Fail-Safe Mode

Restart Mode

Ramping Up

ON

Ramping up

8.2.5

TXD Time-out Feature

If the TXDCANx signal is dominant for a time t > t_{TXD_CAN_TO}, in CAN Normal Mode, the TXD time-out function

deactivates the transmission of the signal at the bus. This is implemented to prevent the bus from being

blocked permanently due to an error. The transmitter is disabled and the transceiver is switched to Receive

Only Mode. The failure is stored in the SPI flag CAN_x_FAIL. The CAN transmitter stage is activated again after

the dominant time-out condition is removed and the transceiver is automatically switched back to CAN

Normal Mode.The transceiver configuration stays unchanged.

8.2.6

Bus Dominant Clamping

If the HS-CAN bus signal is dominant for a time t > t_{BUS_CAN_TO}, regardless of the CAN transceiver mode a bus

dominant clamping is detected and the SPI bit CAN_x_FAIL is set. The transceiver configuration stays

unchanged.

8.2.7

Undervoltage Detection

The voltage at the CAN supply pin is monitored in CAN Normal Mode and CAN Receiver Only Mode . In case of

VCAN undervoltage, the bit VCAN_UV is set and the SBC disables the transmitter stage. If the undervoltage

condition is not present anymore (VCAN > V_{CAN_UV,f}), the transceiver is automatically switched back to CAN

Normal Mode. The transceiver configuration stays unchanged.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

8.3

Electrical Characteristics

Table 16 Electrical Characteristics

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; 4.75 V < V_CAN< 5.25 V; R_L= 60 Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

CAN Supply Voltage

CAN Supply undervoltage

detection threshold

V_{CAN_UV,f}

4.5

–

4.75

V

CAN Normal Mode;

VCAN falling;

P_8.3.1

P_8.3.2

CAN Bus Receiver

Differential Receiver

Threshold Voltage,

recessive to dominant edge

V_{diff,rd_N}

–

0.80

0.90

8.0

–

V_diff= V_CANH- V_CANL;

-12 V ≤ VCM(CAN) ≤

+12 V;

CAN Normal Mode

1)

Dominant state differential V_{diff_D_range}0.9

input voltage range

–

V

= V_CANH- V_CANL

;

P_8.3.60

P_8.3.3

P_8.3.61

P_8.3.4

diff

-12 V ≤ VCM(CAN) ≤

+12 V;

CAN Normal Mode

Differential Receiver

Threshold Voltage,

dominant to recessive edge

V_{diff,dr_N}

0.50

0.60

–

V_diff= V_CANH-V_CANL;

-12 V ≤ VCM(CAN) ≤

+12 V;

CAN Normal Mode

1)

Recessive state differential V_{diff_R_range}-3.0

input voltage range

0.5

V

= V_CANH- V_CANL

diff

;

-12 V ≤ VCM(CAN) ≤

+12 V;

CAN Normal Mode

1)

Common Mode Range

CMR

-12

20

–

12

50

V

CANH, CANL Input

Resistance

R_i

40

kΩ

CAN Normal / Wake P_8.3.5

capable Mode;

-2 V ≤ VCANH/L ≤ +7 V

Recessive state

Differential Input Resistance R_diff

40

80

100

kΩ

CAN Normal / Wake P_8.3.6

capable Mode;

-2 V ≤ VCANH/L ≤ +7 V

Recessive state

Input Resistance Deviation DR_i

between CANH and CANL

-3

–

3

%

¹⁾Recessive state

VCANH = VCANL =5 V

2)

P_8.3.7

P_8.3.8

P_8.3.9

Input Capacitance CANH,

CANL versus GND

C_in

20

10

40

20

pF

V

= 5 V

TXD

2)

Differential Input

Capacitance

C_diff

–

V

= 5 V

TXD

Datasheet

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

Table 16 Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; 4.75 V < V_CAN< 5.25 V; R_L= 60 Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

0.8

Unit Note or

Test Condition

Number

Min.

Max.

Wake-up Receiver

Threshold Voltage,

recessive to dominant edge

V_{diff, rd_W}

–

1.15

V

-12 V ≤ VCM(CAN) ≤

+12 V;

CAN Wake Capable

Mode

¹⁾-12 V ≤ VCM(CAN) ≤ P_8.3.62

+12 V;

P_8.3.10

Wake-up Receiver Dominant V_{diff,D_range_}1.15

state differential input

voltage range

–

8.0

–

W

CAN Wake Capable

Mode

Wake-up Receiver

Threshold Voltage,

dominant to recessive edge

V_{diff, dr_W}

0.4

0.7

–

-12 V ≤ VCM(CAN) ≤

+12 V;

CAN Wake Capable

Mode

P_8.3.11

Wake-up Receiver Recessive V_{diff,R_range_W}-3.0

state differential input

0.4

¹⁾-12 V ≤ VCM(CAN) ≤ P_8.3.63

+12 V;

voltage range

CAN Wake Capable

Mode

CAN Bus Transmitter

CANH/CANL Recessive

Output Voltage

(CAN Normal Mode)

V_{CANL/H_NM}2.0

–

3.0

0.1

50

V

CAN Normal Mode;

_TXD= V_IO;

no load

P_8.3.12

P_8.3.13

P_8.3.14

P_8.3.15

V

CANH/CANL Recessive

Output Voltage

(CAN Wake Capable Mode)

V_{CANL/H_LP}

-0.1

V

CAN Wake Capable

Mode; V_TXD= V_IO;

no load

CANH, CANL Recessive

Output Voltage Difference

V_{diff_r_N}

-500

-100

mV

CAN Normal Mode

V_TXD= V_IO;

no load

V_diff= V_CANH- V_CANL

CANH, CANL Recessive

Output Voltage Difference

V_diff= V_CANH- V_CANL

V_{diff_r_W}

100

CAN Wake Capable

Mode;

V

_TXD= V_IO;

no load

CANL Dominant Output

Voltage

V_CANL

0.5

–

2.25

4.5

V

CAN Normal Mode;

P_8.3.16

P_8.3.17

P_8.3.18

V

_TXD= 0 V;

50 Ω ≤ R_L≤ 65 Ω

CANH Dominant Output

Voltage

V_CANH

2.75

1.5

–

CAN Normal Mode;

V_TXD= 0 V;

50 Ω ≤ R_L≤ 65 Ω

CANH, CANL Dominant

V_{diff_d_N}

2.0

2.5

CAN Normal Mode;

Output Voltage Difference

V

_TXD= 0 V;

V_diff= V_CANH- V_CANL

50 Ω ≤ R_L≤ 65 Ω

Datasheet

50

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

Table 16 Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; 4.75 V < V_CAN< 5.25 V; R_L= 60 Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

CANH, CANL Dominant

V_{diff_d_N}

1.5

5.0

V

¹⁾CAN Normal Mode; P_8.3.58

Output Voltage Difference

V

_TXD= 0 V;

V_diff= V_CANH- V_CANLon

R_L= 2240 Ω

extended bus load range

CANH, CANL output voltage V_{diff_slope_rd}

difference slope, recessive

to dominant

–

70

V/us ¹⁾30% to 70% of

measured

P_8.3.47

P_8.3.48

differential bus

voltage,

C_L= 100 pF, R_L= 60 Ω

CANH, CANL output voltage V_{diff_slope_dr}

difference slope, dominant

to recessive

V/us ¹⁾70% to 30% of

measured

differential bus

voltage,

C_L= 100 pF, R_L= 60 Ω

CANH Short Circuit Current I_CANHsc

CANL Short Circuit Current I_CANLsc

-100

50

–

-80

80

5

-50

100

7.5

mA

µA

CAN Normal Mode;

V_CANHshort= -3 V

P_8.3.20

P_8.3.21

P_8.3.22

CAN Normal Mode

V_CANLshort= 18 V

Leakage Current

I_CANH,lk

I_CANL,lk

V_S= V_CAN= 0 V;

(unpowered device)

0 V < V_CANH,L≤ 5 V;

3)

R

= 0 / 47 kΩ

test

Receiver Output RXD

HIGH level Output Voltage V_RXD,H

0.8 ×

V_IO

–

V

CAN Normal Mode

I_RXD(CAN)= -2 mA;

P_8.3.23

P_8.3.24

LOW Level Output Voltage

V_RXD,L

–

0.2 ×

CAN Normal Mode

V_IO

I_RXD(CAN)= 2 mA;

Transmission Input TXD

HIGH Level Input Voltage

Threshold

V_TXD,H

V_TXD,L

–

0.7 ×

V_IO

V

CAN Normal Mode

recessive state

P_8.3.25

P_8.3.26

P_8.3.27

P_8.3.28

LOW Level Input Voltage

Threshold

0.3 ×

V_IO

–

V

CAN Normal Mode

dominant state

1)

TXD Input Hysteresis

V_TXD,hys

–

0.12 ×

V_IO

mV

TXD Pull-up Resistance

R_TXD

20

8

40

13

80

18

kΩ

–

CAN Transceiver Enabling

Time

t_CAN,EN

µs

⁸⁾CSN = HIGH to first P_8.3.29

valid transmitted

TXD dominant

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

Table 16 Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; 4.75 V < V_CAN< 5.25 V; R_L= 60 Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Dynamic CAN-Transceiver Characteristics

Max.

Driver Symmetry

V_SYM= V_CANH+ V_CANL

V_SYM

4.5

0.5

–

5.5

V

¹⁾⁴⁾CAN Normal

Mode;

P_8.3.19

V

_TXD= 0 V / 5 V;

_CAN= 5 V;

C_SPLIT= 4.7 nF;

50 Ω ≤ R_L≤ 60 Ω

Min. Dominant Time for Bus t_Wake1

Wake-up

1.2

1.8

µs

-12 V ≤ VCM(CAN) ≤

+12 V;

P_8.3.30

CAN Wake capable

Mode

Wake-up Time-out,

Recessive Bus

t_Wake2

0.5

–

10

ms

µs

⁸⁾CAN Wake capable P_8.3.31

Mode

WUP Wake-up

Reaction Time

t_{WU_WUP}

100

⁵⁾⁶⁾⁸⁾Wake-up

reaction time after a

valid WUP on CAN

bus;

P_8.3.32

ISO: Loop Delay (recessive to t_loop,f

dominant)

–

150

255

ns

CAN Normal Mode

C_L= 100 pF;

R_L= 60 Ω;

P_8.3.33

C

_RXD= 15 pF

(see Figure 22)

ISO: Loop Delay (dominant t_loop,r

to recessive)

CAN Normal Mode

C_L= 100 pF;

P_8.3.34

R_L= 60 Ω;

C

_RXD= 15 pF

(see Figure 22)

Propagation Delay

TXD LOW to bus dominant

t_d(L),T

t_d(H),T

t_d(L),R

–

50

–

ns

CAN Normal Mode

C_L= 100 pF;

R_L= 60 Ω;

P_8.3.35

P_8.3.36

P_8.3.37

(see Figure 22)

Propagation Delay

TXD HIGH to bus recessive

50

CAN Normal Mode

C_L= 100 pF;

R_L= 60 Ω;

(see Figure 22)

Propagation Delay

bus dominant to RXD LOW

100

CAN Normal Mode

C_L= 100 pF;

R_L= 60 Ω;

C_RXD= 15 pF

(see Figure 22)

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

Table 16 Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; 4.75 V < V_CAN< 5.25 V; R_L= 60 Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

100

Unit Note or

Test Condition

Number

Min.

Max.

Propagation Delay

bus recessive to RXD HIGH

t_d(H),R

–

ns

CAN Normal Mode

C_L= 100 pF;

R_L= 60 Ω ;

C_RXD= 15 pF

(see Figure 22)

P_8.3.38

Received Recessive bit width t_bit(RXD)

CAN FD up to 2 Mbps

400

435

120

155

–

550

530

220

210

CAN Normal Mode

C_L= 100 pF

P_8.3.45

P_8.3.52

P_8.3.46

P_8.3.53

R_L= 60 Ω

C_RXD= 15 pF

t_bit(TXD)= 500 ns

Parameter definition

in according to

Figure 23.

Transmitted Recessive bit

width

CAN FD up to 2 Mbps

t_bit(BUS)

ns

CAN Normal Mode

C_L= 100 pF

R_L= 60 Ω

C_RXD= 15 pF

t_bit(TXD)= 500 ns

Parameter definition

in according to

Figure 23.

Received Recessive bit width t_bit(RXD)

CAN FD up to 5 Mbps

CAN Normal Mode

C_L= 100 pF

R_L= 60 Ω

C_RXD= 15 pF

t_bit(TXD)= 200 ns

Parameter definition

in according to

Figure 23.

Transmitted Recessive bit

width

t_bit(BUS)

CAN Normal Mode

C_L= 100 pF

CAN FD up to 5 Mbps

R_L= 60 Ω

C

_RXD= 15 pF

t_bit(TXD)= 200ns

Parameter definition

in according to

Figure 23.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

Table 16 Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; 4.75 V < V_CAN< 5.25 V; R_L= 60 Ω; CAN Normal Mode; all voltages with

respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Receiver timing symmetry⁷⁾∆t_Rec

CAN FD up to 2 Mbps

-65

40

ns

⁷⁾CAN Normal Mode P_8.3.39

C_L= 100 pF

R_L= 60 Ω

C_RXD= 15 pF

t_bit(TXD)= 500 ns

Parameter definition

according to

Figure 23.

Receiver timing symmetry

CAN FD up to 5 Mbps

∆t_Rec

-45

–

15

ns

⁷⁾CAN Normal Mode P_8.3.43

C_L= 100 pF

R_L= 60 Ω

C_RXD= 15 pF

t_bit(TXD)= 200 ns

Parameter definition

according to

Figure 23.

TXD Permanent Dominant t_{TXD_CAN_TO}

Time-out

–

2

–

ms

s

⁸⁾CAN Normal Mode P_8.3.40

BUS Permanent Dominant t_{BUS_CAN_TO}

Time-out

–

⁸⁾CAN Normal Mode P_8.3.41

8)

Time-out for bus inactivity t_SILENCE

0.6

1.2

P_8.3.44

1) Not subject to production test, specified by design.

2) Not subject to production test, specified by design, S2P - Method; f = 10 MHz.

3) R_testbetween V_S/V_CANand 0 V (GND).

4)

V

_SYMshall be observed during dominant and recessive state and also during the transition from dominant to recessive

and vice versa while TxD is simulated by a square signal (50% duty cycle) a frequency of 1 MHz.

5) Wake-up is signalized via INTN pin activation in SBC Stop Mode and via VCC1 ramping up with wake from SBC Sleep

Mode.

6) Time starts with end of last dominant phase of WUP.

7) ∆t_Rec= t_bit(RXD)- t_bit(BUS)

8) Not subject to production test, tolerance defined by internal oscillator tolerance.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

High Speed CAN Transceiver

V

TXDCAN

V_IO

GND

t

V_DIFF

t_d(L),T

t_d(H),T

V_{diff, rd_N}

V_{diff, dr_N}

t _d(L),R

t_d(H),R

t

loop,r

V_RXDCAN

V_IO

loop,f

0.8 x V_IO

0.2 x V_IO

GND

t

Figure 22 Timing Diagrams for Dynamic Characteristics

70%

TXDCAN

30%

t_{Loop_f}

5x t_Bit(TXD)

t_Bit(TXD)

V_diff=CANH-CANL

900mV

t_Bit(Bus)

500mV

70%

RXDCAN

30%

t_{Loop_r}

t_Bit(RXD)

Figure 23 From ISO 11898-2: t_Loop, t_Bit(TXD), t_Bit(RXD)Definition

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Wake Input

9

Wake Input

9.1

Features

V_5V,in

I_{PU_WK}

WK

+

-

t_WK

I_{PD_WK}

Logic

Figure 24 Wake Input Block Diagram

Features

•

One HIGH-voltage inputs with V_WKththreshold voltage.

Wake-up capability for power saving modes.

Switch feature for DC/DC Mode (PFM/PWM) in SBC Stop Mode.

Sensitive for level changes LOW to HIGH and HIGH to LOW.

Pull-up and Pull-down current, selectable via SPI.

In SBC Normal and Stop Mode, the WK pin level can be read via SPI.

9.2

Functional Description

The SBC can wake up following a voltage level change at the wake input. The WK input pin is sensitive to level

changes. This means that both transitions, HIGH to LOW and LOW to HIGH, result in SBC signalling (see also

Figure 25). The signal is created in one of the following ways:

•

By triggering the interrupt in SBC Normal and SBC Stop Mode.

By waking up the device in SBC Sleep and SBC Fail-Safe Mode.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Wake Input

WK_LVL_STAT

WK

V_WKth,hys

1

0

V_WKth,min

V_WKth,maxV_WK

Figure 25 Wake Input Threshold Levels and Hysteresis

The wake-up capability, using WK pin, can be enabled or disabled via SPI command.

When the WK is enabled (WK_EN set to 1 on WK_CTRL_1 register), the device wakes up from Sleep Mode with

a HIGH to LOW or LOW to HIGH transition on the WK pin. In SBC Stop and Normal Mode, an Interrupt will be

generated after t_FWK(filter time). In SBC Fail-Safe Mode, the WK is automatically selected as wake-up source

and the device will always go to SBC Restart Mode with a HIGH to LOW or LOW to HIGH transition. The wake

source for WK pin can be read in the register WK_STAT_0 at the bit WK_WU.The state of the WK pin (LOW or

HIGH) can always be read in SBC Normal and Stop Mode at the bit WK on register WK_LVL_STAT.

The WK pin can also be configured as a selection pin for PFM / PWM mode in SBC Stop Mode using the bit

PWM_BY_WK of register HW_CTRL_0. In this case a LOW level at the WK pin will switch the Buck converter to

PFM mode, a HIGH level will switch the Buck converter to PWM Mode maintaining the SBC in SBC Stop Mode.

The filter time is not taken into account because a defined signal is expected (refer to Chapter 6.2.2.2).

In case that the PWM_BY_WK is used, it is still possible to use the WK pin to wake-up from SBC Sleep Mode to

SBC Normal Mode.

Figure 26 shows a typical wake-up timing:

V_WK

V_WKth

t

V_INTN

t_FWK

t_INTN

No Wake Event

Wake Event

Figure 26 Wake-up Filter Timing for Static Sense

9.2.1

Wake Input Configuration

To ensure a defined and stable voltage level at the internal comparator input, it is possible to configure an

integrated current source via the SPI register WK_PUPD_CTRL.

Table 17 shows the possible pull-up and pull-down current configuration.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Wake Input

Table 17 Pull-Up / Pull-Down Resistor

WK_PUPD_1 WK_PUPD_0 Output Current Note

0

no current

source

WK is floating if left open (default setting)

0

1

pull-down

current

WK input internally pulled to GND

1

0

1

pull-up current WK input internally pulled to 5V

automatic

switching

If a HIGH level is detected, the pull-up current is activated

If low level is detected, the pull down current is activated.

Note:

If there is no pull-up or pull-down configured on the WK input, then the respective input should be

tied to GND or V_Son board to avoid unintended floating and waking of the pin.

V_{WKth_min}

V_{WKth_max}

I_WK

V_WKth

Figure 27 Illustration for Pull-Up / Down Current Sources with Automatic Switching Configuration

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Multi-CAN Power+ System Basis Chip

Wake Input

9.3

Electrical Characteristics

Table 18 Electrical Characteristics

T_j= -40°C to +150°CT_j= -40°C to +150°C; V_S= 5.5 V to 28 V; all voltages with respect to ground, positive current

flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Numbe

r

Min.

Max.

WK Input Pin characteristics

Wake-up/monitoringthreshold V_WKth

voltage

2

3

4

V

Falling and rising

edge included

2)

P_9.3.1

Threshold hysteresis

WK pin Pull-up Current

WK pin Pull-down Current

Input leakage current

Timing

V_WKNth,hys0.1

–

0.7

-3

20

2

V

P_9.3.2

P_9.3.3

P_9.3.4

I_{PU_WK}

I_{PD_WK}

I_LK,l

-20

3

-10

10

–

µA

V_{WK_IN}= 4 V

V_{WK_IN}= 2 V

0 V < V_{WK_IN}< V_S+0.3 V¹⁾P_9.3.5

-2

2)

Wake-up filter time

t_FWK

12

16

20

µs

P_9.3.6

1) With pull-up, pull down current disabled.

2) Not subject to production test; specified by design.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Interrupt Function

10

Interrupt Function

10.1

Block and Functional Description

V_IO

INTN

Time

out

Interrupt logic

Figure 28 Interrupt Block Diagram

The interrupt is used to signal wake-up events in real time to the microcontroller. The interrupt block is

designed as a push/pull output stage as shown in Figure 28. An interrupt is triggered and the INTN pin is pulled

low (active low) for t_INTNin SBC Normal and Stop Mode and it is released again once t_INTNis expired. The

minimum HIGH-time of INTN between two consecutive interrupts is t_INTD. An interrupt does not automatically

cause a SBC mode change.

The following wake-up events will be signalized via INTN:

•

All wake-up events stored in the wake status SPI register WK_STAT_0 and WK_STAT_2.

If the bit CANTO_x is set and if it was not masked out.

The VBAT (at pin VBSENSE) monitoring threshold is triggered.

An interrupt is only triggered if the respective function is also enabled as a wake source.

Automatic transition from PFM to PWM mode in SBC Stop Mode.

The register WK_LVL_STAT is not generating interrupt events.

In addition to this behavior, an INTN will be triggered when the SBC is sent to SBC Stop Mode and not all bits

were cleared in the WK_STAT_0 and WK_STAT_2registers.

The SPI status registers are updated at every falling edge of the INTN pulse. All interrupt events are stored in

the respective register (except the register WK_LVL_STAT) until the register is read and cleared via an SPI

command. The interrupt behavior is shown in Figure 29.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Interrupt Function

WK event 1

WK event 2

INTN

t_INTD

t_INT

Update of

WK_STAT register

Update of

WK_STAT register

optional

no WK

SPI

Read & Clear

WK_STAT

contents

WK event 1

no WK

WK event 2

SPI

Read & Clear

No SPI Read & Clear

Command sent

WK event 1 and WK

event 2

WK_STAT

contents

no WK

Figure 29 Interrupt Signaling Behavior

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Interrupt Function

10.2

Electrical Characteristics

Table 19 Interrupt Output

V_S= 6 V to 28 V; T_j= -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Interrupt output; Pin INTN

INTN HIGH Output Voltage V_INTN,H0.8 × V_IO

–

V

I_INTN= -2 mA;

INTN = OFF

P_10.2.1

P_10.2.2

INTN LOW Output Voltage V_INTN,L

–

0.2 × V_IO

I_INTN= 2 mA;

INTN = ON

1)

INTN Pulse Width

t_INTN

t_INTD

80

100

120

µs

P_10.2.3

P_10.2.4

INTN Pulse Minimum

Delay Time

¹⁾Between

consecutive pulses

Configuration Select; Pin INTN

Config Pull-down

Resistance

R_CFG

–

6

250

8

–

kΩ

V_INTN= 5 V

P_10.2.5

P_10.2.6

1)

Config Select Filter Time t_{CFG_F}

10

µs

1) Not subject to production test; specified by design.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Fail Output

11

Fail Output

11.1

Functional Description

5V_int

T_test

SBC Init

Mode

R_TEST

FO/TEST

T_FO

Failure Logic

Figure 30 Fail Output Block Diagram

The Fail Output consists of a failure logic block and one LOW-side switch. In case of a failure, the FO output is

activated and the SPI bit FO_ON_STATE, in the register DEV_STAT, is set.

The Failure Output is activated due to the following failure conditions.

Failure Conditions

•

After one or two Watchdog Trigger failures depending on the configuration.

Thermal Shutdown TSD2.

VIO short to GND.

VIO overvoltage in case that VIO_OV_RST bit is set.

After four consecutive VIO undervoltage detection.

Configurations

Four different configurations can be selected. The selection is done using the pin INTN and the SPI bit CFG2.

Table 20 Reasons for Fail

Config

Event

Fail-Safe Mode Entered SPI CFG2 bit

INTN pin

1

1 × watchdog failure

no

1

External pull-up

2

1 × watchdog failure

yes

1

No ext. pull-up

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Fail Output

Table 20 Reasons for Fail (cont’d)

Config

Event

Fail-Safe Mode Entered SPI CFG2 bit

INTN pin

3

2 × watchdog failure

no

0

External pull-up

4

2 × watchdog failure

yes

0

No ext. pull-up

In order to deactivate the Fail Output, the failure conditions (e.g. TSD2) must not be present anymore and the

bit FO_ON_STATE needs to be cleared via SPI command.

In case of Watchdog fail, the deactivation of the Fail Output is only allowed after a successful WD trigger, i.e.

the FO_ON_STATE bit must be cleared.

Note:

The Fail Output pin is triggered for any of the above described failure and not only for failures

leading to the SBC Fail-Safe Mode.

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Multi-CAN Power+ System Basis Chip

Fail Output

11.2

Electrical Characteristics

Table 21 Interrupt Output

V_S= 6 V to 28 V; T_j= -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Fail Output; Pin FO/TEST

FO LOW output voltage

(active)

V_FO,L

I_FO,H

–

0.6

–

1

V

I_FO= 5 mA

P_11.2.1

P_11.2.2

P_11.2.3

P_11.2.4

P_11.2.6

P_11.2.7

FO HIGH output leakage

current (inactive)

0

2

µA

V

V_FO= 28 V

FO/TEST HIGH-input voltage V_TEST,H

threshold

–

3.5

–

FO/TEST LOW-input voltage V_TEST,L

threshold

1.5

2.5

52

–

V

–

1)

FO/Pull-up Resistance at pin R_TEST

TEST

5

10

81

kΩ

µs

V

= 0 V

TEST

1)

FO/TEST Input Filter Time

t_TEST

64

1) Not subject to production test; specified by design.

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Supervision Functions

12

Supervision Functions

12.1

Reset Function

VIO

RSTN

Resetlogic

Incl. filter & delay

Figure 31 Reset Block Diagram

12.1.1

Reset Output Description

The reset output pin RSTN provides a reset information to the microcontroller, e.g. when the VIO voltage falls

below the undervoltage threshold V_RT1/2/3/4. In case of a reset event due to an undervoltage on V_IO, the reset

output RSTN is pulled to LOW after the filter time t_RFand stays LOW as long as the reset event is present plus

a reset delay time t_RD1. When connecting the SBC to battery voltage, the reset signal remains LOW initially.

When the output voltage V_IOhas reached the default reset threshold V_RT1,f, the reset output RSTN is released

to HIGH after the reset delay time t_RD1. A reset can also occur due to a Watchdog trigger failure. The reset

threshold can be adjusted via SPI; the default reset threshold is V_RT1,f. The RSTN pin has an integrated pull-up

resistor. In case reset is triggered, RSTN will pull LOW for V_S≥ V_POR,f

.

The RSTN trigger timing regarding the VIO undervoltage and watchdog trigger is shown in Figure 32.

VIO

V_RT1

t < t_RF

The reset threshold can be

configured via SPI in SBC

Normal Mode, default is V_RT1

undervoltage

t

t_CW

t_OW

t_RD1

t_CW

t_LW

t_RD1

t_LW

t_CW

t_OW

SPI

Init

WD

Trigger

WD

Trigger

SPI

Init

t_RF

RSTN

t_LW= long open window

t_CW= closed window

t_OW= open window

t

SBC Init

SBC Normal

SBC Restart

SBC Normal

Figure 32 Reset Timing Diagram

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TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Supervision Functions

12.1.2

Soft Reset Description

In SBC Normal and Stop Mode, It is also possible to trigger a Soft Reset via an SPI command in order to bring

the SBC into a defined state in case of failures. In this case the microcontroller must send an SPI command and

set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid, the SBC is set

back to SBC Init Mode and all SPI registers are set to their default values (see SPI Chapter 13.5 and

Chapter 13.6).

As soon as the SBC is in SBC Init Mode due to a software reset, it is possible to change the device configuration

according to the FO/Test, INTN pins and CFG2 bit value. For more information, refer to Chapter 5.1.1.

Two different soft reset configurations are possible via the SPI bit SOFT_RESET_ RSTN:

•

The reset output (RSTN) is triggered when the soft reset is executed (default setting, the same reset delay

time t_RD1applies).

•

The reset output (RSTN) is not triggered when the soft reset is executed.

Note:

The device must be in SBC Normal Mode or SBC Stop Mode when sending this command.

Otherwise, the command will be ignored.

12.2

Watchdog

The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the

microcontroller stops serving the watchdog due to a lock up in the software.

Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN on the

WD_CTRL register:

•

Time-Out Watchdog (default value).

Window Watchdog.

The respective watchdog function can be selected and programmed in SBC Normal Mode. The configuration

remains unchanged in SBC Stop Mode.

Refer to Table 22 to match the SBC Modes with the respective Watchdog Modes.

Table 22 Watchdog Functionality by SBC Modes

SBC Mode

Watchdog Mode

Remarks

INIT Mode

Start with Long Open Window Watchdog starts with Long Open Window after RSTN

is released.

Normal Mode

WD Programmable

Window Watchdog, Time-Out watchdog or switched

OFF for SBC Stop Mode.

Stop Mode

Sleep Mode

Watchdog is fixed or OFF

OFF

SBC will start with Long Open Window when

entering Normal Mode.

Restart Mode

OFF

SBC will start with Long Open Window when

entering Normal Mode.

Fail-Safe Mode

SBC will start with Long Open Window when

entering Normal Mode.

Watchdog timing is programmed via an SPI command. As soon as the Watchdog is programmed, the timer

starts with the new setting and the Watchdog must be served.

The Watchdog is triggered by sending a valid SPI command with write access to WD_CTRL register. The trigger

SPI command is executed when the Chip Select input (CSN) becomes HIGH.

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When coming from SBC Init, Restart or in certain cases Stop Mode, the watchdog timer starts with a long open

window.

The long open window (t_LW) allows the microcontroller to run its initialization sequences and then to trigger

the Watchdog via the SPI.

The watchdog timer period can be selected via the watchdog timing bit field (WD_TIMER on WD_CTRL

register) and it is in the range of 10 ms up to 1000 ms. The timer setting is valid for both watchdog types.

The following Watchdog timer periods are available:

•

WD Setting 1: 10 ms

WD Setting 2: 20 ms

WD Setting 3: 50 ms

WD Setting 4: 100 ms

WD Setting 5: 200 ms (reset value)

WD Setting 6: 500 ms

WD Setting 7: 1000 ms

In case of a watchdog reset, SBC Restart Mode is started or SBC Fail-Safe Mode is entered according to the

configuration and WD_FAIL bits are set.

Once the RSTN goes HIGH again, the watchdog immediately starts with a long open window and the SBC

enters automatically in SBC Normal Mode.

In SBC Development Mode, no reset is generated due to watchdog failure; the watchdog is OFF.

In case of 3 consecutive resets due to WD fail, it is possible in config 1/3 not to generate additional resets by

setting the MAX_3_RST bit on WD_CTRL register.

12.2.1

Time-Out Watchdog

The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog

trigger can become active at any time within the configured watchdog timer period.

A correct watchdog service immediately results in starting a new watchdog timer period. Taking the

tolerances of the internal oscillator into account leads to the safe trigger area defined in Figure 33.

Typical timout watchdog trigger period

t_WDx 1.50

open window

uncertainty

Watchdog Timer Period (WD_TIMER)

t_WDx 1.20

t_WDx 1.80

t / [t_{WD_TIMER}

]

safe trigger area

Figure 33 Time-Out Watchdog Definitions

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If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RSTN LOW

and the SBC switches to SBC Restart or SBC Fails-Safe Mode.

12.2.2

Window Watchdog

Compared to the time-out watchdog, the characteristic of the window watchdog is that the watchdog timer

period is divided between a closed and an open window. The watchdog must be triggered inside the open

window.

A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an

open window.

The watchdog timer period is at the same time the typical trigger time and defines the middle of the open

window.

Taking the oscillator tolerances into account leads to a safe trigger area of:

t_WD× 0.72 < safe trigger area < t_WD× 1.20.

The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking

the tolerances of the internal oscillator into account leads to the timings as defined in Figure 34.

A correct Watchdog service immediately results in starting the next closed window.

Should the trigger signal meet the closed window or should the watchdog timer period elapse, a watchdog

reset is created by setting the reset output RSTN LOW and the SBC switches to SBC Restart or Fail-Safe Mode.

t_WDx 0.6

t_WDx 0.9

Typ. closed window

Typ. open window

t_WDx 0.48

t_WDx 0.72

t_WDx 1.0

t_WDx 1.20

t_WDx 1.80

closed window

uncertainty

open window

uncertainty

Watchdog Timer Period (WD_TIMER)

t / [t_{WD_TIMER}

]

safe trigger area

Figure 34 Window Watchdog Definitions

12.2.3

Checksum

A checksum bit is part of the SPI command to trigger the watchdog and to set the watchdog setting. The sum

of the 8 bits in the register WD_CTRL needs to be even. This is realized by either setting the bit CHECKSUM to

“0” or “1”. If the checksum is wrong, the SPI command is ignored (watchdog not triggered, settings not

changed) and the bit SPI_FAIL is set.

The checksum is calculated by taking all 8 data bits into account.

(12.1)

CHKSUM = Bit15

…

Bit8

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12.2.4

Watchdog during Stop Mode

The watchdog can be disabled via SPI in Stop Mode.

For safety reasons, there is a special sequence to be ensured in order to disable the watchdog as described in

Figure 35. Two dedicated SPI bits (WD_STM_EN_0 and WD_STM_EN_1) in the registers WD_CTRL and

WK_CTRL_0.

If this sequence is not fulfilled, then the bit WD_STM_EN_1 will be cleared and the sequence has to be started

again. As soon as the SBC is set to SBC Normal Mode, then the bits WD_STM_EN_1 and WD_STM_EN_0 are

cleared and this sequence must be followed again to switch OFF the watchdog.

The watchdog can be enabled by triggering the watchdog in SBC Stop Mode or by switching back to SBC

Normal Mode via SPI. In both cases, the watchdog will start with a long open window and the bits

WD_STM_EN_1 and WD_STM_EN_0 are cleared. After the long open window, the watchdog has to be served

as configured in the WD_CTRL register.

Correct WD disabling

Sequence Errors

sequence

•

Missing to set bit

Set bit

WD_STM_EN_1 = 1

WD_STM_EN_0 with the

next watchdog trigger after

having set WD_STM_EN_1

with next WD Trigger

•

Staying in Normal Mode

Set bit

WD_STM_EN_0 = 1

Before subsequent WD Trigger

Will enable the WD :

Change to

SBC Stop Mode

•

Switching back to SBC

Normal Mode

•

Triggering the watchdog

WD is switched off

Figure 35 Watchdog Disabling Sequence

Note:

The bit WD_STM_EN_0 will be cleared automatically when the sequence is started and it was “1”

before.

12.2.4.1 Watchdog Start in SBC Stop Mode due to BUS Wake

In SBC Stop Mode the watchdog can be disabled. In addition a feature can be enabled to start the watchdog

with any BUS wake during Stop Mode. The feature is enabled by setting the bit WD_EN_WK_ BUS. The bit can

only be changed in SBC Normal Mode and needs to be programmed before entering SBC Stop Mode: it is not

reset by the SBC. The sequence described in Chapter 12.2.4 needs to be followed to disable the WD.

With the function enabled, the watchdog will start again with any wake on CANx. The wake on CANx will

generate an interrupt and the RXDCANx is pulled to low. The watchdog starts a with long open window. The

watchdog can be triggered in SBC Stop Mode or the SBC can be switched to SBC Normal Mode. To disable the

watchdog again, the SBC needs to be switched to Normal Mode and the sequence needs to be sent again.

The sequence is shown in Figure 36.

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Correct WD disabling

sequence

Sequence Errors

•

Missing to set bit

Set bit

WD_EN_WK_BUS = 1

WD_STM_EN_0 with the

next watchdog trigger after

having set WD_STM_EN_1

•

Staying in Normal Mode

Set bit

WD_STM_EN_1 = 1

with next WD Trigger

Will enable the WD:

Set bit

WD_STM_EN_0 = 1

•

Switching back to SBC

Normal Mode

Before subsequent WD Trigger

•

Triggering the watchdog

Wake on CANx

Change to

SBC Stop Mode

WD is switched off

Figure 36 Watchdog Disabling Sequence (with wake via BUS)

12.3

V_SPower ON Reset

When powering up, the device detects the V_SPower ON Reset when V_S> V_POR,f, and the POR is set to indicate

that all SPI registers are set to POR default setting. The Buck regulator starts up. The RSTN output is kept LOW

and is only released when VIO has exceeded V_RT1,rand after t_RD1has elapsed.

If V_S<V_POR,f, an internal reset is generated and the SBC is switched OFF. The SBC will restart in SBC INIT Mode

when V_S>V_POR,rrising. Timing behavior is shown in Figure 37.

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VS

V_POR,r

V_POR,f

t

VIO

V_RT1,r

The reset threshold can be

configured via SPI in SBC

Normal Mode, default is V_RT1

V_RTx,f

RSTN

SBC Restart Mode is

entered whenever the

Reset is triggered

t

t_RD1

SBC Mode

Re-

start

SBC OFF

SBC INIT MODE

Any SBC MODE

SBC OFF

t

SPI

Command

Figure 37 Ramp up / down example of Supply Voltage

12.4

Measurement Interface

The measurement interface is sensing the voltage on WK and VBSENSE pin, converting to digital using a 8 bit

SAR high input voltage analog to digital converter and store the value in ADC_STAT.

The input selection (between WK pin or VBSENSE pin) is made by ADC_SEL bit on HW_CTRL_1 register.

The feature is available only in SBC Normal Mode. In SBC Stop, Sleep and Fail Safe Mode, the feature is

automatically disabled to reduce current consumption. Figure 38 shows the block diagram.

WK

8 bit ADC

External Voltage 1

External Voltage 2

ADC_STAT

MUX

VBSENSE

ADC_sel bit

On HW_CTRL_1

Figure 38 Measure Interface: basic concept implementation.

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12.5

Fast Battery Voltage Monitoring

A battery monitoring feature is implemented in the TLE9278BQX V33 in order to provide a fast signalization

path to the microcontroller in case of low battery voltage condition.

The block diagram is shown in Figure 39. The functionality is as follows:

•

The battery voltage is monitored on the dedicated pin VBSENSE (see also the application diagram in

Chapter 14.1).

•

If the voltage falls below the selected threshold, an interrupt is triggered at the INTN pin and the bit

VBAT_UV_ LATCH in the register WK_STAT_2 is set.

•

The bit can be cleared via an SPI if the voltage is above the thresholds again.

The bit VBAT_UV_ STATE in the register WK_LVL_STAT is showing the actual level of the comparator

output, i.e. if the battery voltage is below or above the selected monitoring threshold.

•

The monitoring threshold can be selected via SPI bit with VBSENSE_CFG in the WK_CTRL_0 register. The

feature can be enable in SBC Normal, Stop and Restart Mode using VBSENSE_EN bit on the WK_CTRL_0

register. Four thresholds are available: V_BSENSE0,f...V_BSENSE3,f

.

The Fast Battery voltage monitoring feature is filtered with the time t_{F_VBSENSE}

.

VBSENSE

Vref

State

Machine

INTN

SPI

controlled

GND

Figure 39 Fast Battery Voltage Monitoring Block Diagram

12.6

VBSENSE Boost deactivation

In case of low battery voltage conditions, where the Boost module can operate out of nominal functional

range, it is possible to disable the boost and supply the VS pin only with the output boost capacitor.

The BST_VB_UV_ OFF bit enable this feature.

As soon as the battery voltage is crossing the Boost_OFF,ththreshold, the boost is disabled and VB_UV_BST is

set.

The Boost is automatically enabled when the VBSENSE is crossing Boost_ON,ththreshold.

The VB_UV_BST bit has to be cleared manually.

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12.7

VIO Undervoltage and Undervoltage Prewarning

A first-level voltage detection threshold is implemented as a prewarning for microcontroller. The prewarning

event is signaled with the bit VIO_WARN. No other actions are taken.

As described in Chapter 12.1 and shown in Figure 40, when the VIO voltage reaches the undervoltage

threshold (V_RTx), a reset will be triggered (RSTN pulled ‘LOW’), the bit VIO_UV is set and the SBC will enter SBC

Restart Mode.

Note:

The VIO_WARN and VIO_UV bits are not set in SBC Sleep Mode as VIO = 0 V in this case.

VIO

V_RTx

t

t_RF

t_RD1

RSTN

SBC Normal

Figure 40 VIO Undervoltage Timing Diagram

SBC Restart

SBC Normal

An additional safety mechanism is implemented to avoid repetitive VIO undervoltage resets:

•

A counter is increased for every consecutive VIO undervoltage event.

The counter is active in SBC Init, Normal and Stop Mode and as V_S> V_S,UV

.

A 4th consecutive VIO undervoltage events will lead to SBC Fail-Safe Mode entry and to setting the bit

VIO_UV_FS.

•

The counter is cleared when:

–

SBC Fail-Safe Mode is entered.

The bit VIO_UV is cleared.

A Soft Reset is triggered.

Note:

It is recommended to clear the VIO_UV bit once it was set and detected.

12.8

VIO Overvoltage

For fail safe reasons, a configurable VIO overvoltage detection feature is implemented.

In case the V_IO,OV,rthreshold is crossed, the SBC triggers following measures depending on the configuration:

•

The bit VIO_OV is always set.

If the bit VIO_OV_RST is set in config 1/3, then SBC Restart Mode is entered. The FO output is activated.

After the reset delay time (t_RD1), the SBC Restart Mode is exited and SBC Normal Mode is resumed even if

the VIO overvoltage event is still present (see also Figure 41). The VIO_OV_RST bit is cleared

automatically.

•

If the bit VIO_OV_RST is set in config 2/4, then SBC Fail-Safe Mode is entered and FO output is activated.

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If the VIO_OV_RST bit is not set, one overvoltage event on VIO pin will set the VIO_OV bit but no reset is

generated and FO remains OFF. The SBC doesn’t change the SBC mode.

VIO

V_IO,OV

t

t_{OV_filt}

RSTN

t_RD1

t

SBC Normal

SBC Restart

SBC Normal

Figure 41 VIO Overvoltage Timing Diagram

12.9

VIO Short Circuit

The following protection feature is implemented for VIO:

•

When VIO stays below the undervoltage threshold VRTx for more than t_VIO,SC, the SBC enters SBC Fail-Safe

Mode and turns off VCC1. This feature is available only if V_s> V_S,UV. In addition the SPI status bit VIO_SC is

set. The SBC can exited SBC Fail Safe Mode via a wake-up event on CANx and/or WK pin.

12.10

VEXT Undervoltage

Following protection feature is implemented for VEXT:

If VEXT drops below the V_EXT,UVthreshold, the SPI bit VREG_UV is set and can only be cleared via SPI.

•

Note:

The VREG_UV flag is not set during turn-on or turn-off of VEXT.

12.11

Thermal Protection

The thermal protection mechanism is designed in such a way that the individual modules (VCC1, CANx, Boost

and VEXT) can remain active on as long as possible in case of high temperature. The following thermal

protection features are available and signaled via SPI:

•

Thermal Prewarning T_jPW

Overtemperature Protection:

–

Overtemperature shut down with 2 levels of priority (TSD1 for peripherals and TSD2 for

microcontroller supply).

–

The TSD1 status bit is a combination of CANx, Boost and VEXT thermal shutdown.

The TSD2 status bit is related to VCC1.

If the VEXT base driver sensor detected that T_jTSD1has been reached, it is switched OFF as an initial

protection measure. The control bits (VEXT_ON bits on M_S_CTRL register) are reset and the bits

VEXT_OT and TSD1 are set. The other output stages are not affected if their T_jTSD1threshold is not

reached. When the overtemperature event is not present anymore, the VEXT must be switched ON by

setting the VEXT_ON bit.

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–

If one of the CANx output stages reaches the T_jTSD1temperature threshold, then the transmitter is

switched OFF individually as first-level protection measure. The respective control bits are not reset

and the TSD1 and CAN_x_FAIL bits are set. The CANx drivers are automatically switched on again when

the overtemperature condition is no longer present. The user has to reset the BUS_STAT_0 and

BUS_STAT_2 registers via SPI.

If VCC1 reaches the T_jTSD2temperature threshold, the SBC is sent to SBC Fail-Safe Mode. The SBC stays

in SBC Fail-Safe Mode for at least t_TSD2(typ.1s) after the TSD2 event is not present anymore. The

VCC1_OT is set.The default wake sources CANx and WK are enabled together with the Fail Safe output.

–

Boost Switched OFF in case of TSD1 along with the BOOST_OT bit. The Boost has to activate again

setting the BOOST_EN after the thermal shutdown event.

Once the respective bits (TSD1, TSD2) are set, they can be cleared via SPI if the condition is not present

anymore.

12.11.1 Temperature Prewarning

As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1

reaches the thermal prewarning temperature threshold T_jPW. Then the status bit TPW is set. This bit can only

be cleared via SPI once the overtemperature is not present anymore. The thermal prewarning is only active if

the VCC1 is in PWM mode.

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12.12

Electrical Characteristics

Table 23 Electrical Specification

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Number

Test Condition

Min.

Max.

VIO Monitoring, Reset Generator with VIO = VCC1 = 3.3 V; Pin RSTN

Undervoltage Prewarning

Threshold Voltage

V_PW,f

3.0

3.1

3.2

V

VIO falling,

VIO_WARN bit is

set

P_12.10.57

Undervoltage Prewarning

Threshold Voltage

V_PW,r

V_RT1,f

V_RT1,r

V_RT2,f

V_RT2,r

V_RT3,f

3.10

2.95

3.0

3.2

3.27

3.15

3.2

V

VIO rising

P_12.10.58

P_12.10.34

P_12.10.35

P_12.10.36

P_12.10.37

P_12.10.38

Reset Threshold

Voltage RT1,f

3.05

3.1

Default setting;

VIO falling

Reset Threshold

Voltage RT1,r

Default setting;

VIO rising

Reset Threshold

Voltage RT2,f

2.5

2.6

2.7

SPI option;

VIO falling

Reset Threshold

Voltage RT2,r

2.55

2.2

2.65

2.3

2.75

2.4

SPI option;

VIO rising

Reset Threshold

Voltage RT3,f

SPI option;

V_S≥ 4 V;

VIO falling

Reset Threshold

Voltage RT3,r

V_RT3,r

V_RT34f

V_RT4,r

2.25

2.0

2.35

2.1

2.45

2.2

V

SPI option;

V_S≥ 4 V;

VIO rising

P_12.10.39

P_12.10.55

P_12.10.56

Reset Threshold

Voltage RT4,f

SPI option;

V_S≥ 4 V;

VIO falling

Reset Threshold

Voltage RT4,r

2.05

2.15

2.25

SPI option;

V_S≥ 4 V;

VIO rising

VIO Monitoring, Overvoltage detection

VIO Overvoltage Detection V_IO,OV,r

Threshold

3.5

3.45

12

3.63

3.56

15

3.75

3.7

21

V

¹⁾Rising VIO

PCFG = GND

¹⁾Falling VIO

PCFG = GND

1)

P_12.10.41

P_12.10.45

P_12.10.60

VIO Overvoltage Detection V_IO,OV,f

Threshold

V

VIO Overvoltage filter time t_VIO,OV

µs

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Supervision Functions

Table 23 Electrical Specification (cont’d)

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

VIO Monitoring, Reference Supply Undervoltage detection

VS Undervoltage Detection V_S,UV

3.7

4

4.4

V

Supply UV

P_12.10.43

Threshold

supervision for

VIO PCFG = open;

includesrisingand

falling threshold

1)

VIO Short to GND Filter Time t_VIO,SC

Electrical Characteristics RSTN

Reset LOW Output Voltage V_RSTN,LOW

3.2

–

4

4.8

ms

P_12.10.10

0.2

–

0.4

V

I_RSTN= 1 mA for

V_IO≥ 1 V

P_12.10.12

P_12.10.13

Reset HIGH Output Voltage V_RSTN,HIGH

0.7 ×

V_IO

+

I_RSTN= -20 µA

V_IO

0.3 V

Reset Pull-up Resistor

Reset Filter Time

R_RSTN

t_RF

10

4

20

10

40

kΩ

V_RSTN= 0 V

P_12.10.14

P_12.10.15

1)

26

µs

V < V_RT1×

IO

to RSTN = L

1)2)

Reset Delay Time

t_RD1

1.5

4.5

2

2.5

ms

V

P_12.10.16

P_12.10.17

VEXT Monitoring

V_EXTUndervoltage Detection V_EXT,UV

4.6

4.75

5 V option

VEXT_VCFG=00_B

falling

V_EXTUndervoltage Detection V_EXT,UV

2.65

1.45

0.94

20

2.85

1.52

1.03

100

3.00

1.6

V

3.3 V option

VEXT_VCFG=01_B

falling

P_12.10.46

P_12.10.61

P_12.10.62

P_12.10.63

V

1.8 V option

VEXT_VCFG=10_B

falling

V_EXTUndervoltage Detection V_EXT,UV

1.1

V

1.2 V option

VEXT_VCFG=11_B

falling

1)

V_EXTUndervoltage detection V_{EXT,UV, hys}

250

mV

hysteresis

Watchdog Generator

1)

Long Open Window

Internal Oscillator

t_LW

160

0.8

200

1.0

240

1.2

ms

P_12.10.18

P_12.10.19

f_CLKSBC

MHz

Minimum Waiting Time during SBC Fail-Safe Mode

1)3)

Min. waiting time in Fail-Safe t_FS,min

80

100

120

5

ms

V

P_12.10.20

P_12.10.21

Power-ON Reset, Over-/Undervoltage Protection

V_sPower ON reset rising

V_POR,r

4.5

–

V_sincreasing

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Multi-CAN Power+ System Basis Chip

Supervision Functions

Table 23 Electrical Specification (cont’d)

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; SBC Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

V_sPower ON reset falling

V_POR,f

–

3

V

V_sdecreasing

P_12.10.22

Battery Voltage Monitoring

VBSENSE Monitoring

Threshold 0

V_BSENSE0,f

V_BSENSE1,f

V_BSENSE2,f

V_BSENSE3,f

7.5

5.7

4.2

3.2

8.0

6.0

8.5

6.3

4.8

3.8

200

21

2

V

VBSENSE

decreasing

P_12.10.24

P_12.10.25

P_12.10.26

P_12.10.27

P_12.10.28

P_12.10.48

P_12.10.49

P_12.10.80

VBSENSE Monitoring

Threshold 1

V

VBSENSE

decreasing

VBSENSE Monitoring

Threshold 2

4.5

V

VBSENSE

decreasing

VBSENSE Monitoring

Threshold 3

3.5

V

VBSENSE

decreasing

1)

VBSENSE Monitoring

Threshold Hysteresis

V_BSENSE,hys50

100

16

mV

µs

V

1)

VBSENSE Monitoring Filter t_{F_VBSENSE}

Time

13

VBSENSEBoostdeactivation Boost_OFF,th1.5

threshold

1.75

2.75

VBSENSE falling

VBSENSE rising

VBSENSE Boost activation

threshold

Boost_ON,th2.5

3

V

Overtemperature Shutdown

1)

Thermal Prewarning ON

Temperature

T_jPW

125

145

165

°C

P_12.10.29

1)

Thermal Shutdown TSD1

Thermal Shutdown TSD2

T_jTSD1

T_jTSD2

T_HYS

165

–

185

20

200

–

°C

P_12.10.30

P_12.10.31

P_12.10.81

Thermal Shutdown

Hysteresis

1)

Deactivation time after

thermal shutdown TSD2

t_TSD2

0.8

1

1.2

s

P_12.10.32

Measurement Interface

Resolution

–

8

–

Bits

Input voltage full P_12.10.70

scale = 0V ..39 V

Guarantee offset error

-1

+1

LSB Input voltage full P_12.10.71

scale = 0V ..39 V

Gain error

–

-1.5

–

1.5

%FSR Full scale range

P_12.10.72

Differential non-linearity

(DNL)

LSB Input voltage full P_12.10.73

scale = 0 V..39 V

Integral non-linearity (INL)

–

-1.5

–

1.5

LSB Input voltage full P_12.10.74

scale = 0 V..39 V

1) Not subject to production test; specified by design.

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Supervision Functions

2) The reset delay time will start when VIO crosses above the selected VRTx threshold.

3) This time applies for all failure entries except a device thermal shutdown (TSD2 has a 1 s waiting time t_TSD2).

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13

Serial Peripheral Interface

13.1

SPI Protocol Description

The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input

CLK provided by the microcontroller. The output word appears synchronously at the data output SDO (see

Figure 42).The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW

active. After the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to

the content. The SDO output switches to tristate status (HIGH impedance) at this point, thereby releasing the

SDO bus for other use.The state of SDI is shifted into the input register with every falling edge on CLK. The state

of SDO is shifted out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy-chain

capable.

CSN high to low: SDO is enabled. Status information transferred to output shift register

CSN

time

CSN low to high: data from shift register is transferred to output functions

CLK

time

Actual data

New data

0 1

+ +

SDI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

time

SDI: will accept data on the falling edge of CLK signal

Actual status

New status

0

1

+

ERR

SDO

ERR

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

-

+

time

SDO: will change state on the rising edge of CLK signal

Figure 42 SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure

compared to the register description)

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13.2

Failure Signalization in the SPI Data Output

When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong

SPI commands are either invalid SBC mode commands or commands which are prohibited by the state

machine to avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set

and the SPI Write command is ignored (mostly no partial interpretation). This bit can only be reset by actively

clearing it via a SPI command.

Invalid SPI Commands leading to SPI_FAIL are listed below:

•

Illegal state transitions: going from SBC Stop to SBC Sleep Mode. In this case the SBC additionally enters

the SBC Restart Mode.

Trying to go to SBC Stop or SBC Sleep mode from SBC Init Mode. In this case SBC Normal Mode is entered.

•

Uneven parity in the data bit of the WD_CTRL register. In this case either the watchdog trigger is ignored

or the new watchdog settings are ignored.

In SBC Stop Mode: attempting to change any SPI settings , e.g. changing the watchdog configuration

during SBC Stop Mode.

the SPI command is ignored in this case.

The following are allowed in SBC Stop Mode: WD trigger, returning to SBC Normal Mode , triggering a SBC

Soft Reset, set to SBC Stop Mode (to return from PWM to PFM following an automatic Buck mode

transition) and Read & Clear status register commands are valid SPI commands in SBC Stop Mode.

•

When entering SBC Stop Mode and WK_STAT_0 and WK_STAT_2 are not cleared; SPI_FAIL will not be set

but the INTN pin will be triggered.

When changing from SBC Stop to Normal Mode, any attempt to change the bits on the M_S_CTRL register

will be ignored (SBC remains in SBC Stop Mode). Only VIO_OV_RST and VIO_RT set the SPI_FAIL bit.

SBC Sleep Mode: attempt to go to Sleep Mode when all bits in the BUS_CTRL_0, BUS_CTRL_2,

BUS_CTRL_3 and WK_CTRL_1 registers are cleared (i.e. no wake sources are activated). In this case the

SPI_FAIL bit is set and the SBC enters SBC Restart Mode.

Even though the SBC Sleep Mode command is not entered in this case, the rest of the command (e.g

modifying VEXT) is executed and the values stay unchanged during SBC Restart Mode.

Note: at least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode,

i.e. the SBC would not be able to wake up anymore.

No failure handling occurs for the attempt to go to SBC Stop Mode when all bits in the registers

BUS_CTRL_0, BUS_CTRL_2, BUS_CTRL_3 and WK_CTRL_1 are cleared because the microcontroller can

leave this mode via SPI.

•

After the first VEXT on command, the VEXT_VCFG bits can no longer be changed. if the microcontroller

tries to modify the VEXT_VCFG bits, then the rest of the command is executed but VEXT_VCFG will remain

unchanged.

•

The Boost output voltage can be changed only if BOOST_EN is set to 0. If the Boost output voltage is

changed with BOOST_EN=1, the SPI_FAIL bit is set and the SPI command is ignored.

SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’.

Signalization of the ERR flag in the SPI data output (see Figure 42):

The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set

for the following conditions:

•

In case the number of received SPI clocks is not 0 or 16.

In case RSTN is LOW and SPI frames are being sent at the same time.

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Serial Peripheral Interface

Note:

In order to read the SPI ERR flag property, CLK must be low when CSN is triggered, i.e. the ERR bit is

not valid if the CLK is high on a falling edge of CSN.

The number of received SPI clocks is not 0 or 16:

The number of received input clocks is supervised to be 0 or 16 clock cycles and the input word is discarded in

case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high

during the CSN edges. Both errors, 0 bit and 16 bit CLK mismatch or CLK high during CSN edges are flagged in

the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the

clock is received. The error logic also recognizes if CLK was HIGH during CSN edges. The entire SPI command

is ignored in these cases.

RSTN is LOW and SPI frames are being sent at the same time:

The ERR flag will be set when the RSTN pin is triggered (during SBC Restart Mode) and SPI frames are being

sent to the SBC at the same time. The behavior of the ERR flag signaled at the next SPI command when the

condition below are present:

•

If the command begins when RSTN is HIGH and ends when RSTN is LOW.

If an SPI command is sent while RSTN is LOW.

If an SPI command begins when RSTN is LOW and ends when RSTN is HIGH.

And the SDO output will behave as follows:

•

When RSTN is LOW, SDO is always HIGH.

When SPI command begins with RSTN is LOW and ends when RSTN is HIGH, then the SDO should be

ignored because wrong data will be sent.

Note:

It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled

low and SDO is observed - no SPI clocks are sent in this case.

The ERR flag could also be set after the SBC has entered SBC Fail-Safe Mode because SPI

communication stops immediately.

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Serial Peripheral Interface

13.3

SPI Programming

For TLE9278, 7 bits are used for the address selection (6...0). Bit 7 is used to control the SPI Access, i.e. to decide

between Read Only (if set to ‘0’) and Read_Clear (if set to ‘1’) for the status bits, and between Write (if set to

‘1’) and Read Only (if set to ‘0’) for configuration bits. For the actual configuration and status information, 8

data bits (15...8) are used.

Writing, clearing and reading is done byte wise. SPI configuration and status bits are not cleared automatically

and must be cleared by the microcontroller, e.g. if the TSD2 was set due to overtemperature. The

configuration bits will be partially automatically cleared by the SBC (refer to the description of the individual

registers for detailed information). During SBC Restart, Sleep or Fail-Safe mode, the SPI communication is

ignored by the SBC, i.e. it is not interpreted.

There are two types of SPI registers:

•

Control registers: Those are the registers to configure the SBC, e.g. SBC mode, watchdog trigger, etc.

Status registers: Those are the registers where the status of the SBC is signalled, e.g. wake-up events,

warnings, failures, etc.

For the status registers, the requested information is given in the same SPI command in DO.

For the control registers, also the status of the respective bit is shown in the same SPI command, but if the

setting is changed this is only shown with the next SPI command (it is only valid after CSN HIGH) of the same

register.

The SBC status information from the SPI status registers, is transmitted in a compressed way with each SPI

response on SDO in the so called Status Information Field register (see also Figure 43).

LSB

MSB

DI

0

1

2

3

4

5

6

7

8

x

9

x

10 11 12 13 14 15

R/W

Address Bits

Data Bits

x

Register content of

selected address

DO

0

1

2

3

4

5

6

7

8

x

9

x

10 11 12 13 14 15

Data Bits

Status Information Field

x

time

LSB is sent first in SPI message

Figure 43 SPI Operation Mode

The purpose of this register is to quickly signal the information to the microcontroller if there was a change in

one of the SPI status registers. In this way, the microcontroller does not need to read constantly all the SPI

status registers but only those registers, which were changed. Each bit in the Status Information Field

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Serial Peripheral Interface

represents a SPI status register or a combinational OR of two status registers (see Table 24). As soon as one

bit is set in one of the status registers, the respective bit in the Status Information Field register is set. The

register WK_LVL_STAT is not included in the status information field. This is listed in Table 24:

Table 24 Status Information Field

Status Information Bit Symbol Address Bit

Status Register

0

100 0001

SUP_STAT_0 & SUP_STAT_1 (Combinational OR):

Supply Status (VCC1 and VEXT), POR

1

2

100 0010

100 0011

THERM_STAT: Thermal Protection Status

DEV_STAT: Device Status - Mode before Wake, WD Fail,

SPI Fail, Failure

3

4

100 0100

100 0101

BUS_STAT_0: Bus Failure Status: CAN0, VCAN

BUS_STAT_2 & BUS_STAT_3 (Combinational OR): Bus

Failure Status: CAN1, CAN2 and CAN3

5

6

7

100 0110

100 1001

100 1100

WK_STAT_0: Wake Source Status for CAN0, WK, Timer

and PFM-to-PWM transition

WK_STAT_2: Wake Source Status for CAN1, CAN2,

CAN3, and VBAT_UV

SMPS_STAT: SMPS Status

For example if bit 2 in the Status Information Field is set to 1, one or more bits of the register DEV_STAT is set

to 1. Then this register needs to be read in a second SPI command. The bit in the Status Information Field will

be set to 0 when all bits in the register DEV_STAT are set back to 0.

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13.4

SPI Bit Mapping

13.4.1

SPI Mapping Structure

Figure 44 and Figure 45 show the mapping of the SPI bits and the respective registers.

Depending on bit 7, the bits are only read or also written. The Control Registers ‘000 0001’ to ‘011 1111’ are

READ/WRITE Registers.

The new setting of the bit after write can be seen with the next read / write command. .

The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if

possible) depending on bit 7. To clear a Data Byte of one of the Status Registers, bit 7 must be set to 1. The

register WK_LVL_STAT is an exception as it shows the actual voltage level at the respective pin (LOW/HIGH)

and thus can not be cleared.

When changing to a different SBC Mode, certain configurations and status bits will be modified by the SBC:

•

The SBC Mode bits are updated to the actual status, e.g. when returning to SBC Normal Mode.

In SBC Sleep Mode the CANx control bits will be modified in CANx wake capable if they were ON before.

FO will stay activated if it was triggered before.

•

In general, the configurations is only possible in SBC Normal Mode. Diagnosis are also active in SBC Stop

Mode (e.g. UV, OT). VEXT can be also active in Low power mode (Stop/Sleep).

Depending on the respective configuration, CANx transceivers will be either OFF, woken or still wake

capable.

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13.4.2

SPI Mapping Tables

7

6...0

Register Short Name

banked

Access

Control

Address

A6…A0

C O N T R O L R E G I S T E R S

no

read/write

0000001

0000010

0000011

0000100

0000110

0000111

0001000

0001010

0001011

0001100

0001110

0011110

M_S_CTRL

HW_CTRL_0

WD_CTRL

BUS_CTRL_0

WK_CTRL_0

WK_CTRL_1

WK_PD_CTRL

BUS_CTRL_2

BUS_CTRL_3

TIMER_CTRL

HW_CTRL_1

SYS_STAT_CTRL

S T A T U S R E G I S T E R S

no

read/clear

read

read/clear

1000000

1000001

1000010

1000011

1000100

1000110

1001000

1001001

1001010

1001011

1001100

1011000

SUP_STAT_1

SUP_STAT_0

THERM_STAT

DEV_STAT

BUS_STAT_0

WK_STAT_0

WK_LVL_STAT

WK_STAT_2

BUS_STAT_2

BUS_STAT_3

SMPS_STAT

ADC_STAT

F A M I LY A N D P R O D U C T R E G I S T E R S

no read 1111110

FAM_PROD_STAT

Figure 44 SPI Register Mapping

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15

14

13

12

Data Bit 15…8

D4

11

10

9

8

7

Register Short Name

banked

Read-Only (1)

D7

D6

D5

D3

D2

D1

D0

C O N T R O L R E G I S T E R S

MODE_1

reserved

CHECKSUM

reserved

CAN_2_FLASH

reserved

MODE_0

PWM_TLAG

WD_STM_EN_0

reserved

TIMER_WK_EN VBSENSE_CFG_1 VBSENSE_CFG_0

reserved

CAN_1_FLASH

reserved

SOFT_RESET_RSTNBST_VB_UV_OFF

SYS_STAT_6

VEXT_ON

FO_ON

WD_WIN

reserved

PWM_BY_WK

WD_EN_WK_BUS

reserved

PWM_AUTO

MAX_3_RST

reserved

CAN2_0

CAN_3_FLASH

reserved

BOOST_V_1

SYS_STAT_3

VIO_OV_RST

reserved

WD_TIMER_2

reserved

WD_STM_EN_1

reserved

TIMER_PER_2

BOOST_V_0

SYS_STAT_2

VIO_RT_1

BOOST_EN

WD_TIMER_1

CAN0_1

reserved

WK_PUPD_1

CAN1_1

CAN3_1

TIMER_PER_1

VEXT_VCFG_1

SYS_STAT_1

VIO_RT_0

CFG2

WD_TIMER_0

CAN0_0

VBSENSE_EN

WK_EN

WK_PUPD_0

CAN1_0

no

read/write

M_S_CTRL

HW_CTRL_0

WD_CTRL

BUS_CTRL_0

WK_CTRL_0

WK_CTRL_1

WK_PUPD_CTRL

BUS_CTRL_2

BUS_CTRL_3

TIMER_CTRL_0

HW_CTRL_1

SYS_STAT_CTRL

reserved

CAN2_1

CAN_0_FLASH

reserved

CAN3_0

TIMER_PER_0

VEXT_VCFG_0

SYS_STAT_0

SYS_STAT_7

SYS_STAT_5

SYS_STAT_4

S T A T U S R E G I S T E R S

BVB_UV_BST

POR

reserved

DEV_STAT_1

reserved

PFM_PWM

TEST

VBAT_UV_LATCH

reserved

BST_ACT

VS_UV

reserved

VCC1_OT

DEV_STAT_0

reserved

CFG1_STATE

reserved

BOOST_OT

reserved

VEXT_OC

reserved

TIMER_WU

PCFG_STATE VBAT_UV_STATE

reserved

CAN_2_FAIL_0

reserved

VREG_UV

reserved

WD_FAIL_1

reserved

VEXT_OT

VIO_SC

TSD2

WD_FAIL_0

CAN_0_FAIL_1

reserved

CAN_3_WU

reserved

BCK_SH

VIO_OV

VIO_UV_FS

TSD1

SPI_FAIL

CAN_0_FAIL_0

reserved

VIO_WARN

VIO_UV

TPW

FO_ON_STATE

VCAN_UV

WK_WU

no

read/clear

read

read/clear

SUP_STAT_1

SUP_STAT_0

THERM_STAT

DEV_STAT

BUS_STAT_0

WK_STAT_0

WK_LVL_STAT

WK_STAT_2

BUS_STAT_2

BUS_STAT_3

SMPS_STAT

reserved

CAN_0_WU

CFG2_STATE

reserved

CAN_2_FAIL_1

reserved

WK

reserved

CAN_2_WU

CAN_1_FAIL_1

CAN_3_FAIL_1

BCK_OP

CAN_1_WU

CAN_1_FAIL_0

CAN_3_FAIL_0

reserved

BST_SH

BST_OP

reserved

F A M I LY A N D P R O D U C T R E G I S T E R S

FAM_1 FAM_0 PROD_3 PROD_2

FAM_3

FAM_2

PROD_1

PROD_0

no

read

FAM_PROD_STAT

Figure 45 Detailed SPI Bit Mapping

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Serial Peripheral Interface

13.5

SPI Control Registers

Read / Write Operation (see Chapter 13.3):

•

The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Software Reset.

The ‘Restart Value’ defines the register content after SBC Restart; ‘x’ means the bit is unchanged.

‘y’ in ‘Restart Value’ means the bit can be changed by SBC.

One 16-bit SPI command consist of two bytes:

- the 7-bit address and one additional bit for the register access mode and

- following the data byte

The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to

the SPI bits 8...15.

•

There are three different bit types:

–

‘r’ = READ; read only bits (or reserved bits).

‘rw’ = READ/WRITE; readable and writable bits.

‘rwh’ = READ/WRITE/HARDWARE; as rw with the possibility that the hardware can change the bits.

•

Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only).

Writing to a register is done byte wise by setting the SPI bit 7 to “1”.

SPI control bits are not cleared or changed automatically. This must be done by the microcontroller via SPI

programming.

The registers are addressed wordwise.

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13.5.1

General Control Registers

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Mode- and Supply Control

M_S_CTRL

Mode- and Supply Control (Address 000 0001_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00x0 00xx_B

7

6

5

4

3

2

1

0

MODE

VEXT_ON

Reserved

VIO_OV_RST

VIO_RT

rwh

rw

r

rwh

rw

Field

Bits

Type Description

MODE

7:6

rwh

SBC Mode Control

00_BSBC Normal Mode

01_BSBC Sleep Mode

10_BSBC Stop Mode

11_BSBC Reset: Soft Reset is executed (configuration of RSTN triggering

in bit SOFT_RESET_ RSTN)

VEXT_ON

Reserved

5

rw

VEXT Mode Control

0_BVEXT OFF

1_BVEXT is enabled

4:3

2

r

Reserved, always reads as 0

VIO_OV_RST

rwh

VIO Overvoltage Reset / Fail-Safe enable

0_BVIO_OV is set in case of VIO_OV; no SBC Restart or Fail-Safe is

entered for VIO_OV

1_BVIO_OV is set in case of VIO_OV; depending on the device

configuration SBC Restart or SBC Fail-Safe Mode is entered (see

Chapter 5.1.1);

VIO_RT

Notes

1:0

rw

VIO Reset Threshold Control

00_BVrt1 selected (highest threshold)

01_BVrt2 selected

10_BVrt3 selected

11_BVrt4 selected

1. It is not possible to change from SBC Stop to Sleep Mode via an SPI Command. See also the State Machine

Chapter.

2. After entering SBC Restart Mode, the MODE bits will be automatically set to SBC Normal Mode.

3. The SPI output will always show the previously written state with a Write Command (what has been

programmed before).

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Hardware Control 0

HW_CTRL_0

Hardware Control 0 (Address 000 0010_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0x0x xxxx_B

7

6

5

4

3

2

1

0

Reserved

PWM_TLAG

FO_ON

PWM_BY_WK PWM_AUTO

rwh rw

Reserved

BOOST_EN

CFG2

r

rw

rwh

r

rwh

rw

Field

Bits

7

Type Description

Reserved

r

Reserved, always reads as 0

PWM Lag time

PWM_TLAG

6

rw

This bit permits to set the time between the PWM to PFM transition.

0_B100µs

1_B1ms

FO_ON

5

4

3

rwh

rw

Failure Output activation

This bit is used to activate the Fail Output by software.

0_BFO not activated by software, FO can be activated by defined failure

1_BFO activated by software.

PWM_BY_WK

PWM_AUTO

PWM of Buck converter enabled by WK pin

0_BBuck converter uses PFM in SBC Stop Mode

1_BBuck converter can be switched between PFM and PWM by the WK

pin in SBC Stop Mode.

Automatic transition PFM-PWM in SBC Stop Mode

This bit is used to activate the automatic transition PFM to PWM.

0_BBuck converter always uses PFM in SBC Stop Mode (default)

1_BBuck converter uses automatic transition PFM to PWM in case large

current needed in SBC Stop Mode. To come back in PFM, write a SBC

Stop Mode command to M_S_CTRL.

Reserved

2

1

r

Reserved, always reads as 0

BOOST_EN

rwh

Boost converter enable

0_BBoost Off

1_BBoost enabled, automatic switch ON for LOW V_SVoltage

CFG2

0

rw

Configuration Select 2

0_BFail Output (FO) enabled after 2nd watchdog trigger fail

Config 3/4

1_BFail Output (FO) enabled after 1st watchdog trigger fail

Config 1/2

Notes

1. The FO_ON bit is cleared by the SBC after SBC Restart Mode. Clearing the bit via SPI or via SBC Restart Mode

will not disable the FO output, if the failure condition is still present. See also Chapter 11for FO activation and

deactivation. Setting the FO output via an SPI should be used for testing purposes only.

2. The selection between Config 1/3 respectively Config 2/4 is done by the pin INTN. The INTN pin defines if the

SBC enters to SBC Fail-Safe Mode with VCC1 OFF in case of a watchdog failure.

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Watchdog Control

WD_CTRL

Watchdog Control (Address 000 0011_B)

POR / Soft Reset Value: 0001 0100_B;

Restart Value: x0xx x100_B

7

6

5

4

3

2

1

0

WD_STM_EN

_0

WD_EN_WK_

BUS

CHECKSUM

WD_WIN

MAX_3_RST

WD_TIMER

rw

rwh

rw

rwh

Field

CHECKSUM

Bits

Type Description

7

rw

Watchdog Setting Checksum Bit

The sum of bits 7:0 needs to have even parity

0_BCounts as 0 for checksum calculation

1_BCounts as 1 for checksum calculation

WD_STM_EN_0

WD_WIN

6

5

4

3

rwh

rw

Watchdog Deactivation during SBC Stop Mode, bit 0 (Chapter 12.2.4)

0_BWatchdog is active in Stop Mode

1_BWatchdog is deactivated in Stop Mode

Watchdog Type Selection

0_BWatchdog works as a Time-Out watchdog

1_BWatchdog works as a Window watchdog

WD_EN_WK_

BUS

rw

Watchdog Enable after Bus (CANx) Wake in SBC Stop Mode

0_BWatchdog will not start after a CANx wake

1_BWatchdog starts with a long open window after CANx Wake

MAX_3_RST

rw

Limit number of resets due to a Watchdog failure

0_BAlways generate a reset in case of WD fail

1_BAfter 3 consecutive resets due to WD fail, no further reset is

generated (only valid in config 1/3)

WD_TIMER

2:0

rwh

Watchdog Timer Period

000_B10ms

001_B20ms

010_B50ms

011_B100ms

100_B200ms

101_B500ms

110_B1000ms

111_Breserved

Notes

1. See Chapter 12.2.3 for calculating the checksum.

2. See also Chapter 12.2.4 for more information on disabling the watchdog in SBC Stop Mode.

3. See Chapter 12.2.4 for more information on the effect of the bit WD_EN_WK_BUS.

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Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

Bus Control 0

BUS_CTRL_0

Bus Control 0 (Address 000 0100_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 0000 00yy_B

7

6

5

4

3

2

1

0

Reserved

CAN0

r

rwh

Field

Bits

7:2

Type Description

Reserved

CAN0

r

Reserved, always reads as 0

1:0

rwh

HS-CAN_0 Module Modes

00_BCAN OFF

01_BCAN is wake capable

10_BCAN Receive Only Mode

11_BCAN Normal Mode

Notes

1. See Figure 18 for detailed state changes of the CAN Transceiver for different SBC modes.

2. Failure Handling Mechanism: When the SBC enters SBC Fail-Safe Mode due to a failure (e.g. TSD2, WD-

Failure), then the bus and wake registers are modified by the SBC in order to ensure that the device can be

woken again. Refer to the respective register descriptions.

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Serial Peripheral Interface

Internal Wake Input Control 0

WK_CTRL_0

Internal Wake Input Control 0 (Address 000 0110_B)

POR / Soft Reset Value: 0000 0001_B;

Restart Value: 0xxx 000x_B

7

6

5

4

3

2

1

0

TIMER1_WK_

EN

WD_STM_EN

_1

Reserved

VBSENSE_CFG

Reserved

Reserved VBSENSE_EN

rw

r

rw

r

rwh

r

Field

Bits

7

Type Description

Reserved

r

Reserved, always reads as 0

TIMER1_WK_

EN

6

rw

Wake Source Control (for cyclic wake)

0_BCyclic wake disabled

1_BCyclic wake enabled as a wake source

VBSENSE_CFG 5:4

rw

Battery Voltage Monitoring Threshold Selection

00_BVBSENSE0 threshold selected (highest threshold)

01_BVBSENSE1 threshold selected

10_BVBSENSE2 threshold selected

11_BVBSENSE3 threshold selected

Reserved

3

2

r

Reserved, always reads as 0

WD_STM_EN_1

rwh

Watchdog Deactivation during Stop Mode, bit 1 (Chapter 12.2.4)

0_BWatchdog is active in Stop Mode

1_BWatchdog is deactivated in Stop Mode

Reserved

1

0

r

Reserved, always reads as 0

VBSENSE_EN

rw

Enable the fast battery voltage monitoring

0_BFast Vbatt Monitoring disabled

1_BFast Vbatt Monitoring enabled

Note:

See also Chapter 12.2.4 for more information on disabling the watchdog in SBC Stop Mode.

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Serial Peripheral Interface

External Wake Source Control 1

WK_CTRL_1

External Wake Source Control 1 (Address 000 0111_B)

POR / Soft Reset Value: 0000 0001_B;

Restart Value: 0000 000x_B

7

6

5

4

3

2

1

0

Reserved

WK_EN

r

rwh

Field

Bits

7:1

0

Type Description

Reserved

WK_EN

r

Reserved, always reads as 0

rwh

WK Wake Source Control

0_BWK wake disabled

1_BWK is enabled as a wake source

Notes

1. Failure Handling Mechanism: When the device enters SBC Fail-Safe Mode due to a failure (e.g. TSD2, WD-

Failure), the WK_CTRL_1 is modified to the value ‘0000 0001’ in order to ensure that the device can be woken

again.

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Serial Peripheral Interface

Wake Input Level Control

WK_PUPD_CTRL

Wake Input Level Control (Address 000 1000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 00xx_B

7

6

5

4

3

2

1

0

Reserved

WK_PUPD

r

rw

Field

Bits

7:2

Type Description

Reserved

WK_PUPD

r

Reserved, always reads as 0

1:0

rw

WK Pull-Up / Pull-Down Configuration

00_BNo pull-up / pull-down selected

01_BPull-down resistor selected

10_BPull-up resistor selected

11_BAutomatic switching to pull-up or pull-down

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Bus Control 2

BUS_CTRL_2

Bus Control 2 (Address 000 1010_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: xx0y y0yy_B

7

6

5

4

3

2

1

0

CAN_2_Flash CAN_1_Flash Reserved

CAN2

Reserved

CAN1

rw

r

rwh

r

rwh

Field

Bits

Type Description

CAN_2_Flash

CAN_1_Flash

7

rw

CAN2 Flash Mode activation

0_BFlash Mode disabled: CAN communication up to 5MBaud

1_BFlash Mode enabled: CAN communication for higher than 5MBaud

(higher emission on CAN bus - no slew rate control)

6

rw

CAN1 Flash Mode activation

0_BFlash Mode disabled: CAN communication up to 5MBaud

1_BFlash Mode enabled: CAN communication for higher than 5MBaud

(higher emission on CAN bus - no slew rate control)

Reserved

CAN2

5

r

Reserved, always reads as 0

4:3

rwh

HS-CAN_2 Module Modes

00_BCAN OFF

01_BCAN is wake capable

10_BCAN Receive Only Mode

11_BCAN Normal Mode

Reserved

CAN1

2

r

Reserved, always reads as 0

1:0

rwh

HS-CAN_1 Module Modes

00_BCAN OFF

01_BCAN is wake capable

10_BCAN Receive Only Mode

11_BCAN Normal Mode

Notes

1. See Figure 18 for detailed state changes of the CAN Transceiver for different SBC modes.

2. Failure Handling Mechanism: When the device enters SBC Fail-Safe Mode due to a failure (e.g. TSD2, WD-

Failure), then the bus and wake registers are modified by the SBC in order to ensure that the device can be

woken again. Refer to the respective register descriptions.

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Serial Peripheral Interface

Timer_0 Control and Selection

TIMER_CTRL_0

Timer_0 Control and Selection (Address 000 1100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0000_B

7

6

5

4

3

2

1

0

Reserved

TIMER_0_PER

r

rwh

Field

Reserved

Bits

Type Description

7:3

r

Reserved, always reads as 0

TIMER_0_PER 2:0

rwh

Cyclic Wake Period Configuration

000_B10ms

001_B20ms

010_B50ms

011_B100ms

100_B200ms

101_B1s

110_B2s

111_Breserved

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Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

Hardware Control 1

HW_CTRL_1

Hardware Control 1 (Address 000 1110_B)

POR / Soft Reset Value: 0000 00yy_B; Restart Value: 0x0x xxxx_B

7

6

5

4

3

2

1

0

SOFT_RESET BST_VB_UV_

ADC_SEL

Reserved

BOOST_V

VEXT_VCFG

_RSTN

OFF

rw

r

rw

rwh

Field

Bits

Type Description

ADC_SEL

7

rw

8 bit ADC input channel selector

0_BWK pin is selected

1_BVBSENSE pin is selected

SOFT_RESET_

RSTN

6

5

Soft Reset Configuration

0_BRSTN will be triggered (pulled low) during a Soft Reset (default)

1_BNo RSTN triggering during a Soft Reset

BST_VB_UV_

OFF

Boost switch-off control on VBSENSE low voltage condition

0_BBoost automatic switch-off disable

1_BBoost automatic switch-off enable

Reserved

BOOST_V

4

r

Reserved, always reads as 0

3:2

rw

BOOST Output voltage configuration

00_B6.7V output (default)

01_B8V output

10_B10V output

11_B12V output

VEXT_VCFG

1:0

rwh

VEXT Output voltage configuration

00_B5.0V output

01_B3.3V output (default)

10_B1.8V output

11_B1.2V output

Notes

1. After triggering a SBC Software Reset the bits VEXT_VCFG remain unchanged, as shown by the ‘y’ in the

POR/Soft Reset Value.

2. The VEXT_VCFG can not be accessed if the PCFG pin is connected to GND. Always read ‘01’.

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Serial Peripheral Interface

Bus Control 3

BUS_CTRL_3

Bus Control 3 (Address 000 1011_B)

POR / Soft Reset Value: 0000 0000_B; Restart Value: 000x x0yy_B

7

6

5

4

3

2

1

0

Reserved

CAN_0_Flash CAN_3_Flash Reserved

rw rw

CAN3

r

rwh

Field

Bits

7:5

4

Type Description

Reserved

r

Reserved, always reads as 0

CAN0 Flash Mode activation

CAN_0_Flash

rw

0_BFlash Mode disabled: CAN communication up to 5MBaud

1_BFlash Mode enabled: CAN communication for higher than 5MBaud

(higher emission on CAN bus - no slew rate control)

CAN_3_Flash

3

rw

CAN3 Flash Mode activation

0_BFlash Mode disabled: CAN communication up to 5MBaud

1_BFlash Mode enabled: CAN communication for higher than 5MBaud

(higher emission on CAN bus - no slew rate control)

Reserved

CAN3

2

r

Reserved, always reads as 0

1:0

rwh

HS-CAN_3 Module Modes

00_BCAN OFF

01_BCAN is wake capable

10_BCAN Receive Only Mode

11_BCAN Normal Mode

Notes

1. See Figure 18 for detailed state changes of CAN Transceiver for different SBC modes.

2. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (e.g. TSD2, WD-Failure),

then the bus and wake registers are modified by the SBC in order to ensure that the device can be woken

again. Refer to the respective register descriptions.

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Serial Peripheral Interface

System Status Control

SYS_STATUS_CTRL

System Status Control (Address 001 1110_B)

POR Value: 0000 0000_B;

Restart Value/Soft Reset Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

SYS_STAT

rw

Field

Bits

Type Description

rw System Status Control Byte (bit0=LSB; bit7=MSB)

SYS_STAT

7:0

Dedicated byte for system configuration, access only by

microcontroller

Notes

1. The SYS_STATUS_CTRL register is an exception for the default values, i.e. it will keep its configured value

even after a Software Reset.

2. This byte is intended for storing system configurations of the ECU by the microcontroller and is only accessible

in SBC Normal Mode. The byte is not accessible by the SBC and is also not cleared after SBC Fail-Safe or

Restart Mode. It allows the microcontroller to quickly store the system configuration without losing the data.

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Serial Peripheral Interface

13.6

SPI Status Information Registers

Read/Clear Operation (see Chapter 13.3):

•

One 16-bit SPI command consist of two bytes:

- the 7-bit address and one additional bit for the register access mode and

- following the data byte will be ignored when accessing a status register

The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to

the SPI bits 8...15.

•

There are three different bit types:

- ‘r’ = READ: read only bits (or reserved bits)

- ‘rc’ = READ/CLEAR: readable and clearable bits

- ‘rh’ = READ/HARDWARE: readable and the possibility that the hardware can change the bits

•

Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only)

Clearing a register is done byte wise by setting the SPI bit 7 to “1”

SPI status registers are in general not cleared or changed automatically (an exception are the WD_FAIL

bits). This must be done by the microcontroller via SPI command

The registers are addressed wordwise.

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Serial Peripheral Interface

13.6.1

General Status Registers

Supply Voltage Fail Status 1

SUP_STAT_1

Supply Voltage Fail Status 1 (Address 100 0000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xx0x xxxx_B

7

6

5

4

3

2

1

0

VB_UV_BST

VS_UV

Reserved

VEXT_OC

VREG_UV

VEXT_OT

VIO_OV

VIO_WARN

rc

r

rc

Field

Bits

Type Description

VB_UV_BST

7

rc

VBSENSE low voltage detection

0_BNo VBSENSE low voltage detected

1_BVBSENSE low voltage detected

VS_UV

6

rc

VS Undervoltage Detection (V_S,UV

0_BNo V_Sundervoltage detected

1_BV_Sundervoltage detected

)

Reserved

VEXT_OC

5

4

r

Reserved, always reads as 0

rc

VEXT Overcurrent Detection

0_BNo OC

1_BOC detected

VREG_UV

VEXT_OT

VIO_OV

3

2

1

0

rc

The status is related to VEXT

0_BNo VEXT UV detection

1_BVEXT UV Fail detected

VEXT Overtemperature Detection

0_BNo overtemperature

1_BVEXT overtemperature detected

VIO Overvoltage Detection (V_IO,OV,r

0_BNo VIO overvoltage warning

1_BVIO overvoltage detected

)

VIO_WARN

VIO Undervoltage Prewarning (V_PW,f)

0_BNo VIO undervoltage prewarning

1_BVIO undervoltage prewarning detected

Notes

1. The VIO undervoltage prewarning threshold V_PW,fis a fixed threshold and independent of the VIO

undervoltage reset thresholds.

2. VIO_WARN bit setting: It is never updated in SBC Restart Mode. In SBC Init Mode it is only updated after RSTN

was released for the first time. It is always updated in SBC Normal and Stop Mode. It is never updated in SBC

Sleep Mode and it is always updated in any SBC modes in a VIO_SC condition (after VIO_UV = 1 longer than

t

_VIO,SC).

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Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

Supply Voltage Fail Status 0

SUP_STAT_0

Supply Voltage Fail Status 0 (Address 100 0001_B)

POR / Soft Reset Value: y000 0000_B;

Restart Value: x000 0xxx_B

7

6

5

4

3

2

1

0

POR

Reserved

VIO_SC

VIO_UV_FS

VIO_UV

rc

r

rc

Field

Bits

Type Description

POR

7

rc

Power-On Reset Detection

0_BNo POR

1_BPOR occurred

Reserved

VIO_SC

6:3

2

r

Reserved, always reads as 0

rc

VIO Short to GND Detection

0_BNo short

1_BVIO short to GND detected

VIO_UV_FS

VIO_UV

1

0

rc

VIO UV-Detection (due to VRTx reset)

0_BNo Fail-Safe Mode entry due to 4th consecutive VIO_UV

1_BFail-Safe Mode entry due to 4th consecutive VIO_UV

VIO UV-Detection (due to VRTx reset)

0_BNo VIO_UV detection

1_BVIO UV-Fail detected

Notes

1. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on

reset (POR value = 1000 0000). However it will be cleared after a SBC Software Reset command (Soft Reset

value = 0000 0000).

2. During SBC Sleep Mode, the bits VIO_SC, VIO_OV and VIO_UV will not be set because the regulator suppling

VIO is off.

3. The VIO_UV bit is never updated in SBC Restart Mode. In SBC Init Mode, it is only updated after RSTN was

released for the first time. It is always updated in SBC Normal and Stop Mode, and it is always updated in any

SBC modes in a VIO_SC condition (after VIO_UV = 1 longer than t_VIO,SC).

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Serial Peripheral Interface

Thermal Protection Status

THERM_STAT

Thermal Protection Status (Address 100 0010_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0xx0 0xxx_B

7

6

5

4

3

2

1

0

Reserved

VCC1_OT

BOOST_OT

Reserved

TSD2

TSD1

TPW

r

rc

r

rc

Field

Bits

7

Type Description

Reserved

VCC1_OT

r

Reserved, always reads as 0

6

rc

VCC1 Overtemperature detection

0_BNo VCC1 overtemperature

1_BVCC1 overtemperature detected

BOOST_OT

5

rc

Boost Overtemperature detection

0_BNo Boost overtemperature

1_BBoost overtemperature detected

Reserved

TSD2

4:3

2

r

Reserved, always reads as 0

rc

TSD2 Thermal Shut-Down Detection

0_BNo TSD2 event

1_BTSD2 OT detected - leading to SBC Fail-Safe Mode

TSD1

TPW

1

0

rc

TSD1 Thermal Shut-Down Detection

0_BNo TSD1 fail

1_BTSD1 OT detected

Thermal Pre Warning

0_BNo Thermal Pre warning

1_BThermal Pre warning detected

Note:

TPW, TSD1 and TSD2 are not reset automatically, even if the overtemperature pre warning or TSD1/2

conditions are not longer present.

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Serial Peripheral Interface

Device Information Status

DEV_STAT

Device Information Status (Address 100 0011_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xx00 xxxx_B

7

6

5

4

3

2

1

0

FO_ON_STAT

E

DEV_STAT

Reserved

WD_FAIL

SPI_FAIL

rc

r

rh

rc

Field

Bits

Type Description

DEV_STAT

7:6

rc

Device Status before Restart Mode

00_BCleared (Register must be actively cleared)

01_BRestart due to failure described in Table 8 and Table 9.

10_BSleep Mode

11_BReserved

Reserved

WD_FAIL

5:4

3:2

r

Reserved, always reads as 0

rh

Number of WD-Failure Events (1/2 WD failures depending on INTN)

00_BNo WD Fail

01_B1x WD Fail, FOx activation- Config 1/2

10_B2x WD Fail, FOx activation- Config 3/4

11_BReserved (never reached)

SPI_FAIL

1

0

rc

SPI Fail Information

0_BNo SPI fail

1_BInvalid SPI command detected

FO_ON_STATE

Activation of Fail Output FO

0_BNo Failure

1_BFailure occurred, FO is activated

Notes

1. The WD_FAIL bits are configured as a counter and are the only status bits, which are cleared automatically

by the SBC. They are cleared after a successful watchdog trigger and when the watchdog is stopped (also in

SBC Sleep and Fail-Safe Mode unless it was reached due to a watchdog failure). See also Chapter 11.1.

2. The SPI_FAIL bit is cleared only by SPI command.

3. With Config 2/4, the WD_Fail counter is frozen in case of WD trigger failure until a successful WD trigger occurs.

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Bus Communication Status 0

BUS_STAT_0

Bus Communication Status 0 (Address 100 0100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 0xxx_B

7

6

5

4

3

2

1

0

Reserved

CAN_0_FAIL

VCAN_UV

r

rc

Field

Bits

7:3

Type Description

Reserved

r

Reserved, always reads as 0

CAN_0_FAIL

2:1

rc

CAN_0 Failure Status

00_BNo error

01_BCAN TSD shutdown

10_BCAN_TXD_DOM: TXD dominant time out for more than 2ms

11_BCAN_BUS_DOM: BUS dominant time out for more than 2ms

VCAN_UV

Notes

0

rc

Undervoltage CAN Bus Supply

0_BNormal operation

1_BCAN Supply undervoltage detected. Transmitter disabled

1. CAN0 Recovery Conditions:

1.) TXD Time Out: TXDCAN0 goes HIGH or transmitter is switched off or the transceiver is wake capable.

2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.

3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VCAN > VCAN_UV.

4.) In all cases (also for TSD shutdown): to enable the Bus transmission again, TXDCAN0 needs to be HIGH for

a certain time (transmitter enable time).

2. The VCAN_UV comparator is enabled if the mode bit CANx_1 = ‘1’, i.e. in CAN Normal or CAN Receive Only

Mode.

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Serial Peripheral Interface

Wake-up Source and Information Status 0

WK_STAT_0

Wake-up Source and Information Status 0 (Address 100 0110_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: x0xx 000x_B

7

6

5

4

3

2

1

0

PFM_PWM

Reserved

CAN_0_WU TIMER_0_WU

rc rc

Reserved

WK_WU

rc

r

rc

Field

Bits

Type Description

PFM_PWM

7

rc

PFM_PWM automatic transition detected

0_BNo automatic PFM_PWM transition detected

1_BAutomatic PFM_PWM transition detected

Reserved

6

5

r

Reserved, always reads as 0

CAN_0_WU

rc

Wake up via CAN_0 Bus

0_BNo Wake up

1_BWake up

TIMER_0_WU

4

rc

Wake up via cyclic wake

0_BNo Wake up

1_BWake up

Reserved

WK_WU

3:1

0

r

Reserved, always reads as 0

rc

Wake up via WK

0_BNo Wake up

1_BWake up

Note:

The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode.

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Serial Peripheral Interface

WK Input Level

WK_LVL_STAT

WK Input Level (Address 100 1000_B)

POR / Soft Reset Value: xx0x 000x_B;

Restart Value: xxxx x00x_B

7

6

5

4

3

2

1

0

VBAT_UV_ST

ATE

TEST

CFG1_STATE CFG2_STATE PCFG_STATE

Reserved

WK

r

Field

Bits

Type Description

TEST

7

r

Status of SBC Development Mode

0_BLOW Level (=0), Normal User Operation, SBC Development Mode is

disabled

1_BHIGH Level (=1), SBC Development Mode is enabled, no reset

triggered due to wrong Watchdog trigger

CFG1_STATE

CFG2_STATE

6

5

Status of INTN Pin

This bit shows the level of the INTN pin regarding the device configuration

0_BLOW Level; Fail-Safe Mode entered due to WD failure (1 or 2 failure)

depending on CFG2 bit) Config 2/4

1_BHIGH Level; Fail-Safe Mode not entered, due to WD failure, Config 1/3

Status of CFG2 bit on HW_CTRL_0 register

This bit shows the setting in bit CFG2

0_BLOW Level (=0), Fail Outputs (FOx) are active after 2nd watchdog

trigger fail Config 3/4

1_BHIGH Level (=1); Fail Outputs (FOx) are active after 1st watchdog

trigger fail Config 1/2

PCFG_STATE

4

3

r

Status of PCFG Pin

0_BLOW Level; (connected to GND)

1_BHIGH Level; (left OPEN)

VBAT_UV_

STATE

VBSENSE Undervoltage Detection Status

0_BNo VBSENSE undervoltage detected

1_BVBSENSE undervoltage detected

Reserved

WK

2:1

0

r

Reserved, always reads as 0

Status of WK

0_BLOW Level (=0)

1_BHIGH Level (=1)

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Serial Peripheral Interface

Wake-up Source and Information Status 2

WK_STAT_2

Wake-up Source and Information Status 2 (Address 100 1001_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: x000 0xxx_B

7

6

5

4

3

2

1

0

VBAT_UV_LA

TCH

Reserved

CAN_3_WU CAN_2_WU CAN_1_WU

rc rc rc

rc

r

Field

Bits

Type Description

VBAT_UV_

LATCH

7

rc

VBSENSE Undervoltage Detection

0_BNo VBSENSE undervoltage detected

1_BVBSENSE undervoltage detected (latched status)

Reserved

6:3

2

r

Reserved, always reads as 0

CAN_3_WU

rc

Wake up via CAN_3 Bus

0_BNo wake up

1_BWake up

CAN_2_WU

CAN_1_WU

1

0

rc

Wake up via CAN_2 Bus

0_BNo wake up

1_BWake up

Wake up via CAN_1 Bus

0_BNo wake up

1_BWake up

Note:

The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode.

Datasheet

111

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

Bus Communication Status 2

BUS_STAT_2

Bus Communication Status 2 (Address 100 1010_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 00xx 00xx_B

7

6

5

4

3

2

1

0

Reserved

CAN_2_FAIL

Reserved

CAN_1_FAIL

r

rc

r

rc

Field

Bits

7:6

Type Description

Reserved

r

Reserved, always reads as 0

CAN_2_FAIL

5:4

rc

CAN_2 Failure Status

00_BNo error

01_BCAN TSD shutdown

10_BCAN_TXD_DOM: TXD dominant time out for more than 2ms

11_BCAN_BUS_DOM: BUS dominant time out for more than 2ms

Reserved

3:2

1:0

r

Reserved, always reads as 0

CAN_1_FAIL

rc

CAN_1 Failure Status

00_BNo error

01_BCAN TSD shutdown

10_BCAN_TXD_DOM: TXD dominant time out for more than 2ms

11_BCAN_BUS_DOM: BUS dominant time out for more than 2ms

Notes

1. CAN Recovery Conditions:

1.) TXD Time Out: TXDCANx goes HIGH or transmitter is switched off or the transceiver is wake capable.

2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.

3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VCAN > VCAN_UV.

4.) In all cases (also for TSD shutdown): to enable the Bus transmission again, TXDCANx needs to be HIGH for

a certain time (transmitter enable time).

Datasheet

112

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

Bus Communication Status 3

BUS_STAT_3

Bus Communication Status 3 (Address 100 1011_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: 0000 00xx_B

7

6

5

4

3

2

1

0

Reserved

CAN_3_FAIL

r

rc

Field

Bits

7:2

Type Description

Reserved

r

Reserved, always reads as 0

CAN_3_FAIL

1:0

rc

CAN_3 Failure Status

00_BNo error

01_BCAN TSD shutdown

10_BCAN_TXD_DOM: TXD dominant time out for more than 2ms

11_BCAN_BUS_DOM: BUS dominant time out for more than 2ms

Notes

1. CAN Recovery Conditions:

1.) TXD Time Out: TXDCAN3 goes HIGH or transmitter is switched off or the transceiver is wake capable.

2.) Bus dominant time out: Bus will become recessive or transceiver is set to wake capable or switched off.

3.) Supply undervoltage: as soon as the threshold is crossed again, i.e. VCAN > VCAN_UV.

4.) In all cases (also for TSD shutdown): to enable the Bus transmission again, TXDCAN3 needs to be HIGH for

a certain time (transmitter enable time).

Datasheet

113

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

SMPS state

SMPS_STAT

SMPS state (Address 100 1100_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxx0 0xx0_B

7

6

5

4

3

2

1

0

BST_ACT

BST_SH

BST_OP

Reserved

BCK_SH

BCK_OP

Reserved

rc

r

rc

r

Field

Bits

Type Description

BST_ACT

BST_SH

BST_OP

7

rc

Boost Regulator Active

0_BBoost not active

1_BBoost active

6

5

BSTD short detection

0_BNo short detected on BSTD pin

1_BBSTD short to supply

BSTD open detection

0_BNo open detected on BSTD pin

1_BBSTD loss of diode detected or loss of Boost GND

Reserved

BCK_SH

4:3

2

r

Reserved, always reads as 0

rc

BCKSW pin short detection

0_BNo BCKSW short detected

1_BShort to GND or short to V_Sdetected on BCKSW pin

BCK_OP

1

0

rc

r

BCKSW pin open detection

0_BNo BCKSW open detected

1_BBCKSW loss of freewheeling or BCKSW loss of GND

Reserved

Reserved, always reads as 0

Datasheet

114

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

ADC state

ADC_STAT

ADC state (Address 101 1000_B)

POR / Soft Reset Value: 0000 0000_B;

Restart Value: xxxx xxxx_B

7

6

5

4

3

2

1

0

ADC

rc

Field

ADC

Bits

Type Description

rc ADC output

7:0

Datasheet

115

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

13.6.2

Family and Product Information Register

Family and Product Identification Register

FAM_PROD_STAT

Family and Product Identification Register (Address 111 1110_B)

POR / Soft Reset Value: 0100 yyyy _B; Restart Value: 0100 yyyy_B

7

6

5

4

3

2

1

0

FAM

PROD

r

Field

FAM

Bits

Type Description

7:4

r

SBC Family Identifier (bit4=LSB; bit7=MSB)

0 0 01_BDriver SBC Family

0 0 10_BDC/DC-SBC Family

0 0 11_BMid-Range SBC Family

0 1 00_BMulti-CAN Power+ SBC Family

0 1 01_BLITE SBC Family

0 1 00_BMid-Range+ SBC Family

PROD

Notes

3:0

r

SBC Product Identifier (bit0=LSB; bit3=MSB)

0 0 0 0_BTLE9278-3BQX

0 0 0 1_BTLE9278-3BQX V33

0 0 1 0_BTLE9278BQX

0 0 1 1_BTLE9278BQX V33

1. The actual default register value after POR, Soft Reset or Restart of PROD depends on the respective product.

Therefore the value ‘y’ is specified.

Datasheet

116

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

13.7

Electrical Characteristics

Table 25 Electrical Characteristics: Power Stage

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

SPI frequency

1)

Maximum SPI frequency

f_SPI,max

–

4.0

MHz

P_13.7.1

SPI Interface; Logic Inputs SDI, CLK and CSN

H-input Voltage Threshold V_IH

L-input Voltage Threshold V_IL

Hysteresis of input Voltage V_IHY

–

0.7 ×

V_IO

V

–

P_13.7.2

P_13.7.3

P_13.7.4

P_13.7.5

P_13.7.6

P_13.7.7

0.3 ×

V_IO

–

V

1)

–

0.2 ×

V_IO

–

V

–

Pull-up Resistance at pin

CSN

R_ICSN

20

–

40

10

80

–

kΩ

pF

V_CSN= 0.7 × V_IO

Pull-down Resistance at pin R_ICLK/SDI

SDI and CLK

V_SDI/CLK= 0.2 × V_IO

1)

Input Capacitance at pin

CSN, SDI or CLK

C_I

Logic Output SDO

H-output Voltage Level

L-output Voltage Level

Tri-state Leakage Current

V_SDOH

V_SDOL

I_SDOLK

V_IO- 0.4 V_IO- 0.2 –

V

I_DOH= -1.6 mA

I_DOL= 1.6 mA

P_13.7.8

P_13.7.9

P_13.7.10

–

0.2

–

0.4

10

V

-10

µA

V_CSN= V_IO;

0 V < V_DO< V_IO

1)

‘Tri-state Input Capacitance C_SDO

–

10

15

pF

P_13.7.11

Data Input Timing¹⁾

Clock Period

t_pCLK

t_CLKH

t_CLKL

250

125

250

125

100

50

–

ns

–

P_13.7.12

P_13.7.13

P_13.7.14

P_13.7.15

P_13.7.16

P_13.7.17

P_13.7.18

P_13.7.19

P_13.7.20

P_13.7.21

Clock HIGH Time

Clock LOW Time

–

Clock LOW before CSN LOW t_bef

–

CSN Setup Time

CLK Setup Time

t_lead

t_lag

–

Clock LOW after CSN HIGH t_beh

–

SDI Setup Time

SDI Hold Time

t_DISU

t_DIHO

–

Input Signal Rise Time at pin t_rIN

–

50

SDI, CLK and CSN

Input Signal Fall Time at pin t_fIN

–

50

ns

–

P_13.7.22

SDI, CLK and CSN

Datasheet

117

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Serial Peripheral Interface

Table 25 Electrical Characteristics: Power Stage

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Delay Time for Mode

Changes²⁾

t_Del,Mode

t_CSN(high)

–

5

µs

–

P_13.7.23

P_13.7.24

CSN HIGH Time

Data Output Timing¹⁾

SDO Rise Time

3

–

µs

–

t_rSDO

–

30

–

80

50

ns

C_L= 100 pF

P_13.7.25

P_13.7.26

P_13.7.27

P_13.7.28

P_13.7.29

SDO Fall Time

t_fSDO

C_L= 100 pF

SDO Enable Time

SDO Disable Time

SDO Valid Time

t_ENSDO

t_DISSDO

t_VASDO

LOW impedance

HIGH impedance

C_L= 100 pF

–

1) Not subject to production test; specified by design.

2) Applies to all mode changes triggered via SPI commands.

24

CSN

15

16

17

18

13

14

CLK

SDI

19

20

LSB

MSB

not defined

27

28

29

SDO

Flag

LSB

MSB

Figure 46 SPI Timing Diagram

Note:

Numbers in drawing correlate with the last 2 digits of the Number field in the Electrical

Characteristics table.

Datasheet

118

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Application Information

14

Application Information

14.1

Application Diagram

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

V_ext

T₂

R_SHUNT

C₆

IC1

TDR

TXD

TDR

TXD

V_CC

V_SUP/V_S

C₈

PHY

C₇

RXD

R₂

GND

V_CC1

V_S

Vsup

D₁

C₁

L₁

D₂

L₂

VS

VBAT

BCKSW

VCC1

C₄

C₅

C₂

C₃

C_1fil

BSTD

R₁

VDD

CLK

CSN

SDI

CLK

CSN

SDI

GND

SDO

NRO

RSTN

INTN

PCFG

_NINTµC

V_S

T1

TLE9278x

TXDCAN0

RXDCAN0

TXDCAN1

RXDCAN1

TXDCAN2

RXDCAN2

TXDCAN3

RXDCAN3

TXDCAN0

RXDCAN0

TXDCAN1

RXDCAN1

TXDCAN2

RXDCAN2

TXDCAN3

RXDCAN3

FO

C₉

V_S

FO

WK

S₃

R₄

VSS

R₃

V_CC1

C_VCAN

VCAN

CANH2

CANH0

CANH2

R_CANH

C_CAN

R_CANL

CANL0

CANH1

CANL2

CANH3

CANL0

CANH1

CANL2

CANH3

R_CANH

C_CAN

R_CANL

CANL3

CANL1

CANL3

CANL1

GND

Figure 47 TLE9278BQX V33 Application Diagram

Datasheet

119

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Application Information

Table 26 Bill of Material

Ref.

Typical Value

Purpose / Comment

Capacitances

C1

47 µF ± 20%

Electrolytic

Buffering capacitor to cut off battery spikes, depending on the

application. The voltage rating depends on the application.

C1fil

C2

100 nF ± 20%, 50 V

ceramic

Input filter battery capacitor for optimum EMC behavior.

Output Boost capacitor. ESR ≤ 1Ω over the temperature range.

Input Buck capacitor. Low ESR.

100 µF ± 20%, 50 V,

Electrolytic

C3

1..10 µF ± 20%, 50 V

Ceramic

C4, C5

C₆

22 µF ± 20%, 16V

Ceramic

Output Buck capacitor, for optimum current capability and

dynamic behavior. Low ESR.

1)

10 µF ± 20%, 16 V

ceramic

V

Output capacitor. Low ESR.

EXT

C₇

470 pF ± 20%, 16 V

ceramic

V_EXTFilter capacitor (only needed if used for off-board supply).

V_BSENSEblocking capacitor. Low ESR.

C₈

22 nF ± 20%, 16 V

ceramic

C₉

22 nF ± 20%, 16 V

ceramic

Spikes filtering, as required by application. Mandatory

protection for off-board connection.

C_VCAN

1 µF ± 20%, 16 V

ceramic

Input filter CAN supply. The capacitor must be placed close to

the VCAN pin. For optimum EMC and CAN FD performances, the

capacitor has to be ≥ 4.7 µF

C_CANx

47 nF / OEM dependent

Split termination stability.

Resistances

R_SHUNT

1 Ω ± 1%

Sense shunt for VEXT current limitation (configured to typ.

235 mA with 1 Ω shunt).

R₁

10 kΩ..22 kΩ ± 5%

Selection of hardware configuration 1/3, i.e. in case of WD failure

SBC Restart Mode is entered.

If not connected, then the hardware configuration 2/4 is

selected.

R₂

10 kΩ ± 5% ²⁾

Limit the VBSENSE pin input current.

Wetting current of the switch, as required by application.

Limit the WK pin input current, e.g. for ISO pulses.

CAN bus termination.

R3

10 kΩ ± 5%

R4

10 kΩ ± 5%

R_CANHx

R_CANL

Inductors

L₁

60 Ω / OEM dependent

CAN bus termination.

22 µH..47 µH ± 20%

47 µH ± 20%

³⁾Boost regulator coil. The saturation current depends on the

application.

³⁾Buck regulator coil. The saturation current depends on the

application.

L₂

Active Components

Datasheet

120

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Application Information

Table 26 Bill of Material (cont’d)

Ref.

Typical Value

Purpose / Comment

D1

e.g.SS34HE3/9AT (Vishay) Reverse polarity protection.

or similar

D2

T₂

e.g. SL04-GS08 (Vishay) or Boost regulator power diode. Forward current depends on the

SS34HE3/9AT

application.

BCP 52-16, Infineon

Power element of VEXT, current limit to be configured via shunt

R_SHUNT

.

MJD253, ON Semi

e.g. XC2xxx

Alternative power element of VEXT.

µC

Microcontroller.

1) For optimized EMC performance, one additional filter capacitor ≤ 10 nF ± 20% 16 V ceramic is required.

2) For ISO7637-2 pulse robustness, a higher value might be needed.

3) The saturation current must be define according to the maximum current capability by the application.

5V_int

T_test

SBC Init

Mode

R_TEST

Connector/

FO/TEST Jumper

R_EXT

T_FO

Failure Logic

Figure 48 Hint for Increasing the Robustness of pin FO/TEST during Debugging or Programming

Datasheet

121

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Application Information

14.2

ESD Tests

Tests for ESD robustness according to IEC61000-4-2 “GUN test” (150 pF, 330 Ω) have been performed.

The results and test condition are available in a test report. The values for the tests are listed below.

Table 27 ESD “GUN Test”¹⁾²⁾

Performed Test

Result

Unit

Remarks

ESD at pin VS, VBSENSE,

VEXTIN, VEXTREF, WK,

CANHx, CANLx versus GND

> 6

kV

positive pulse

ESD at pin VS, VBSENSE,

VEXTIN, VEXTREF, WK,

CANHx, CANLx versus GND

< -6

kV

negative pulse

1) ESD susceptibility “ESD GUN” according to EMC 1.3 Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external

test house (IBEE Zwickau, EMC Test report No. 09-12-18).

2) ESD Test “GUN Test” is specified with external components for pins VS, VBSENSE, VEXTIN, VEXTREF and WK. See the

application diagrams in Chapter 14.1 for more information.

EMC and ESD susceptibility tests according to SAE J2962-2 (V. 2014-01-23) have been performed. Tested by

external test house (Jakob Mooser GmbH, Test report No. 434/2016).

Datasheet

122

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Application Information

14.3

Thermal Behavior of Package

The figure below shows the thermal resistance (Rth_JA) of the device vs. the cooling area on the bottom of the

PCB for Ta = 85°C. Every line reflects a different PCB and thermal via design.

70

Tamb=85°C

60

50

40

30

20

10

0

100

200

300

400

500

600

Bottom Cooling area (mm²)

2s2p - 16 vias(standard)

2s0p - 25vias (standard)

2s2p - 25vias (standard)

2s2p - 16vias (35µm)

2s0p - 16vias (standard)

2s2p - 25vias (35µm)

Figure 49 Thermal Resistance (Rth_JA) vs. Cooling Area

Cross Section (JEDEC 2s2p) with Cooling Area

Cross Section (JEDEC 2s0p) with Cooling Area

70µm modelled (traces)

35µm, 90% metalization*

70µm / 5% metalization + cooling area

*: means percentual Cu metalization on each layer

PCB (top view)

PCB (bottom view)

standard solder pads

Figure 50 Board Setup

The Board setup is defined according to JESD 51-2,-5,-7.

Board: 76.2 × 114.3 × 1.5 mm³with 2 inner copper layers (35 µm thick), with thermal via array under the

exposed pad contacting the first inner copper layer and the cooling area on the bottom layer (70 µm).

Datasheet

123

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Package Outlines

15

Package Outlines

0.9 MAX.

(0.65)

11 x 0.5 = 5.5

0.5

±0.1

7

A

±0.03

0.1

6.8

+0.03 ¹⁾

2)

37

B

36

25

24

48x

0.08

48

13

1

12

Index Marking

48x

0.1

0.4 x 45°

±0.05

Index Marking

0.23

M

A B C

(0.2)

0.05 MAX.

(5.2)

(6)

C

1) Vertical burr 0.03 max., all sides

2) These four metal areas have exposed diepad potential

PG-VQFN-48-29, -31-PO V05

Figure 51 PG-VQFN-48¹⁾

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

1) Dimensions in mm

Datasheet

124

Rev. 1.5

2019-09-27

TLE9278BQX V33

Multi-CAN Power+ System Basis Chip

Revision History

16

Revision History

Revision Date

Changes

1.5 2019-09-27 Datasheet updated:

•

General

–

corrected typo “ISO 11989-1” to “11898-1”

changed “SBC Software Development Mode” to “SBC Development Mode”

•

Updated description of the leave procedure in SBC Development Mode (FO/TEST

pin condition)

•

Figure 7 and Figure 10: added dot between VS and Boost Converter

Updated Table 16

–

added P_8.3.47 and P_8.3.48 (no product change)

tightened P_8.3.18

tightened P_8.3.8 and P_8.3.9 by additional footnote

•

Corrected Bit 6 Address (Status Information Field) in Table 24

Added footnote for R₂in Table 26 (Bill of Material)

Added Figure 48

1.4

2019-01-23 Initial Release.

Datasheet

125

Rev. 1.5

2019-09-27

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2019-09-27

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

a written document signed by

Document reference

Z8F68544718


型号：	TLE9278BQX V33
厂家：	Infineon
描述：	A high-efficient switch mode power supply (SMPS) buck regulator provides an external 3.3 V output voltage at up to 750 mA, while an additional DC/DC boost converter supports applications or conditions at low input supply voltages. The device is controlled and monitored via a 16-bit serial peripheral interface (SPI). Additional features include a time-out/window watchdog circuit with reset, fail output and undervoltage reset. The device offers low-power modes in order to support applications that are connected permanently to the battery. A wake-up from the low-power mode is possible via LIN/CAN bus, via the bi-level sensitive monitoring/wake-up input as well as via the timer. The TLE9278BQX V33 is offered in a very small footprint, exposed pad PG-VQFN-48 (7 x 7 mm2) power package.
文件：	总126页 (文件大小：3686K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLE9278BQX V33 [INFINEON]

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