TLE94004EP [INFINEON]
TLE94004EP 是受保护的四倍半桥驱动器，专为汽车运动控制应用而设计，如加热以及通风和空调 (HVAC) 活门直流电机控制。该产品是系列产品中的一款，该系列产品提供半桥驱动器，有 3 个输出到 12 个输出，具有直接接口或 SPI 接口。半桥驱动器设计用于以串联或并联方式驱动直流电机负载。通过直接接口控制正向 (cw)、反向 (ccw)、制动和高阻抗工作模式。它可以提供短路、电源故障和过温检测等诊断功能。结合极低的静态电流，该器件在汽车应用领域极具吸引力。精密小巧的散热焊盘封装 PG-TSDSO-14，提供良好的热性能，节省 PCB 板空间和成本。;
| 型号： | TLE94004EP |
| 厂家： | 
Infineon |
| 描述： | TLE94004EP 是受保护的四倍半桥驱动器，专为汽车运动控制应用而设计，如加热以及通风和空调 (HVAC) 活门直流电机控制。该产品是系列产品中的一款，该系列产品提供半桥驱动器，有 3 个输出到 12 个输出，具有直接接口或 SPI 接口。半桥驱动器设计用于以串联或并联方式驱动直流电机负载。通过直接接口控制正向 (cw)、反向 (ccw)、制动和高阻抗工作模式。它可以提供短路、电源故障和过温检测等诊断功能。结合极低的静态电流，该器件在汽车应用领域极具吸引力。精密小巧的散热焊盘封装 PG-TSDSO-14，提供良好的热性能，节省 PCB 板空间和成本。 空调 PC 电机 驱动 驱动器 |
| 文件： | 总35页 (文件大小：1210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE94004EP
Features
•
•
•
•
•
•
•
•
Four half bridge power outputs
Very low power consumption in sleep mode
3.3V / 5V compatible inputs with hysteresis
All outputs with overload and short circuit protection
Direct interface for control and diagnosis
Overtemperature protection
Over- and Undervoltage lockout
Cross-current protection
Potential applications
•
•
•
•
HVAC Flap DC motors
Monostable and bistable relays
Side mirror x-y adjustment
Voltage controlled bipolar stepper motors
Product validation
Qualified for Automotive Applications. Product Validation according to AEC-Q100
Description
The TLE94004EP is a protected quad half-bridge driver designed especially for automotive motion control
applications such as Heating, Ventilation and Air Conditioning (HVAC) flap DC motor control. It is part of a
larger family offering half-bridge drivers from three outputs to twelve outputs with direct interface or SPI
interface.
The half bridge drivers are designed to drive DC motor loads in sequential or parallel operation. Operation
modes forward (cw), reverse (ccw), brake and high impedance are controlled from a direct interface. It offers
diagnosis features such as short circuit, power supply failure and overtemperature detection. In combination
with its low quiescent current, this device is attractive among others for automotive applications. The small
fine pitch exposed pad package, PG-TSDSO-14, provides good thermal performance and reduces PCB-board
space and costs.
Type
Package
Marking
TLE94004EP
PG-TSDSO-14
TLE94004
Datasheet
www.infineon.com
1
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2017-12-07
TLE94004EP
Table 1
Product Summary
Operating Voltage
Logic Supply Voltage
VS
5.5 ... 20 V
3.0 ... 5.5 V
40 V
VDD
VS(LD)
Maximum Supply Voltage for Load Dump
Protection
Minimum Overcurrent Threshold
ISD
0.9 A
Maximum On-State Path Resistance at Tj = 150°C RDSON(total)_HSx+LSy
1.8 + 1.8 Ω
0.1 µA
Typical Quiescent Current at Tj = 85°C
ISQ
Datasheet
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2017-12-07
TLE94004EP
Table of Contents
1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
1.2
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
4
Characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
5.2
5.2.1
5.2.2
5.3
5.4
6
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Half-Bridge Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Diagnosis Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Short Circuit of Output to Supply or Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Temperature monitoring and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VS Undervoltage Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VS Overvoltage Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
V
DD Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
7.1
7.2
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
9
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Datasheet
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2017-12-07
TLE94004EP
Pin Configuration
1
Pin Configuration
1.1
Pin Assignment
IN 1
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
IN 2
IN 3
EF
EN2
EN1
OUT 4
OUT 2
GND
IN 4
VS
OUT 3
OUT 1
8
Figure 1
Pin Configuration TLE94004EP with direct interface
1.2
Pin Definitions and Functions
Pin
1
Symbol
Function
IN 1
IN 2
IN 3
IN 4
VS
Direct input control for power half-bridge 1
Direct input control for power half-bridge 2
Direct input control for power half-bridge 3
Direct input control for power half-bridge 4
Main supply voltage for power half bridges.
Power half-bridge 3
2
3
4
5
6
OUT 3
OUT 1
GND
OUT 2
OUT 4
EN1
EN2
EF
7
Power half-bridge 1
8
Ground
9
Power half-bridge 2
10
11
12
13
14
EDP
Power half-bridge 4
Enable input for Half-bridges 1/2 with internal pull-down
Enable input for Half-bridges 3/4 with internal pull-down
Error Flag
VDD
-
Logic supply voltage
Exposed Die Pad; For cooling and EMC purposes only - not usable as electrical
ground. Electrical ground must be provided by pins 8. 1)
1) The exposed die pad at the bottom of the package allows better heat dissipation from the device via the PCB. The
exposed pad (EP) must be either left open or connected to GND. It is recommended to connect EP to GND for best
EMC and thermal performance.
Datasheet
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TLE94004EP
Block Diagram
2
Block Diagram
VDD
VS
Quad Half Bridge Driver
Direct Interface
UNDERVOLTAGE
&
OVERVOLTAGE
MONITOR
CHARGE
PUMP
Power stage
BIAS
&
MONITOR
EN1
EN2
Power driver
OUT 1
OUT 2
OUT 3
OUT 4
short to ground
IN1
IN2
IN3
IN4
high-side
driver
detection
LOGIC CONTROL& LATCH
DIRECT INTERFACE
overtemperature
detection
temp
sensor
EF
low-side
driver
short to battery
tection
de
ERROR
DETECTION
overtemperature
detection
GND
Figure 2
Block Diagram TLE94004EP (Direct Interface)
Datasheet
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TLE94004EP
Block Diagram
2.1
Voltage and current definition
Figure 3 shows terms used in this datasheet, with associated convention for positive values.
VS
IS
VS
IDD
IEF
IIN1, IN2, IN3, IN4
VDD
VDD
VEF
VINx
EF
IN1, IN2, IN3, IN4
Direct
Interface
Driver
IOUTx VDSHSx
VDSLSx
OUT x
IEN1 ,IEN2
EN1, EN2
VENx
GND
IGND
Figure 3
Voltage and Current Definition
Datasheet
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TLE94004EP
General Product Characteristics
3
General Product Characteristics
3.1
Absolute Maximum Ratings
Table 2
Absolute Maximum Ratings1)Tj = -40°C to +150°C
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Voltages
Supply voltage
VS
-0.3
–
–
–
40
10
V
P_4.1.1
Supply Voltage Slew Rate
| dVS/dt |
V/µs VS increasing and P_4.2.2
decreasing 1)
Power half-bridge output voltage
Logic supply voltage
VOUT
VDD
-0.3
-0.3
–
–
–
40
V
V
V
0 V < VOUT < VS
0 V < VS < 40 V
P_4.1.2
P_4.1.3
P_4.1.16
5.5
VDD
Logic input voltages
(EN1, EN2, IN1, IN2, IN3, IN4)
V
ENn, VINn -0.3
0 V < VS < 40 V
0 V < VDD < 5.5V
Logic output voltage
(EF)
VEF
-0.3
–
VDD
V
0 V < VS < 40 V
0 V < VDD < 5.5V
P_4.1.17
Currents
Continuous Supply Current for VS
Current per GND pin
Output Currents
IS
0
–
–
–
2.0
2.0
2.0
A
A
A
–
–
–
P_4.1.20
P_4.1.14
P_4.1.15
IGND
IOUT
0
-2.0
Temperatures
Junction temperature
Storage temperature
ESD Susceptibility
Tj
-40
-50
–
–
150
150
°C
°C
–
–
P_4.1.8
P_4.1.9
Tstg
ESD susceptibility OUTn and VS pins VESD
versus GND. All other pins
grounded.
-4
–
4
kV
JEDEC HBM1)2)
P_4.1.10
ESD susceptibility all pins
ESD susceptibility all pins
ESD susceptibility corner pins
VESD
VESD
VESD
-2
–
–
–
2
kV
V
JEDEC HBM1)2)
CDM1)3)
CDM1)3)
P_4.1.11
P_4.1.12
P_4.1.13
-500
500
750
-750
V
1) Not subject to production test, specified by design
2) ESD susceptibility, “JEDEC HBM” according to ANSI/ ESDA/ JEDEC JS001 (1.5 kΩ, 100pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Datasheet
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TLE94004EP
General Product Characteristics
3.2
Functional Range
Table 3
Functional Range
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Supply voltage range for
normal operation
VS(nor)
VDD
5.5
–
–
–
–
20
V
–
P_4.2.1
P_4.2.3
P_4.2.6
P_4.2.5
Logic supply voltage range for
normal operation
3.0
5.5
5.5
150
V
–
–
Logic input voltages
(EN1, EN2, IN1, IN2, IN3, IN4)
VINn, VENn -0.3
Tj -40
V
Junction temperature
°C
Note:
Within the normal functional range the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the related electrical
characteristics table.
Datasheet
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TLE94004EP
General Product Characteristics
3.3
Thermal Resistance
Table 4
Thermal Resistance TLE94004EP
Symbol
Parameter
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
1)
Junction to Case, TA = -40°C
Junction to Case, TA = 85°C
RthjC_cold
RthjC_hot
–
14
–
–
–
K/W
K/W
K/W
1)
–
–
17
1) 2)
Junction to ambient, TA = -40°C RthjA_cold_
126
(1s0p, minimal footprint)
min
1) 2)
1) 3)
1) 3)
1) 4)
1) 4)
1) 5)
1) 5)
Junction to ambient, TA = 85°C RthjA_hot_m
(1s0p, minimal footprint)
–
–
–
–
–
–
–
134
69
81
67
79
53
67
–
–
–
–
–
–
–
K/W
K/W
K/W
K/W
K/W
K/W
K/W
in
Junction to ambient, TA = -40°C RthjA_cold_3
(1s0p, 300mm2 Cu)
00
Junction to ambient, TA = 85°C RthjA_hot_30
(1s0p, 300mm2 Cu)
0
Junction to ambient, TA = -40°C RthjA_cold_6
(1s0p, 600mm2 Cu)
00
Junction to ambient, TA = 85°C RthjA_hot_60
(1s0p, 600mm2 Cu)
0
Junction to ambient, TA = -40°C RthjA_cold_2
(2s2p)
s2p
Junction to ambient, TA = 85°C RthjA_hot_2s
(2s2p)
2p
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip
+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with minimal footprint copper area and 35µm thickness.
Ta = -40°C, each channel dissipates 0.2W. Ta = 85°C, each channel dissipates 0.135W.
3) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip
+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with additional cooling of 300mm2 copper area and 35µm
thickness. Ta = -40°C, each channel dissipates 0.2W. Ta = 85°C, each channel dissipates 0.135W.
4) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip
+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with additional cooling of 600mm2 copper area and 35µm
thickness. Ta = -40°C, each channel dissipates 0.2W. Ta = 85°C, each channel dissipates 0.135W.
5) Specified RthJA value is according to JEDEC JESD51-2, -3 at natural convection on FR4 2s2p board; The product (chip
+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with two inner copper layers ( 4 x 35µm Cu). Ta = -40°C,
each channel dissipates 0.2W. Ta = 85°C, each channel dissipates 0.135W.
Datasheet
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TLE94004EP
General Product Characteristics
3.4
Electrical Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 20 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN1= HIGH
and EN2= HIGH, IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless
otherwise specified; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Current Consumption, EN1 = EN2 = GND
Supply Quiescent current ISQ
Logic supply quiescent current IDD_Q
–
–
–
0.1
0.1
0.6
2
1
3
µA
µA
µA
-40°C ≤ Tj ≤ 85°C
-40°C ≤ Tj ≤ 85°C
-40°C ≤ Tj ≤ 85°C
P_4.4.1
P_4.4.2
P_4.4.3
Total quiescent current
ISQ + IDD_Q
Current Consumption, EN=HIGH
Supply current
IS_HSON
IDD
–
–
1.5
0.6
3
mA
mA
All high-sides ON1)2) P_4.4.101
P_4.4.5
Logic supply current
2.5
Over- and Undervoltage Lockout
Undervoltage Switch ON
voltage threshold
VUV ON
VUV OFF
VUV HY
4.4
4
4.90 5.3
4.50 4.9
V
V
V
V
V
V
VS increasing
VS decreasing
VUV ON - VUV OFF
VS increasing
VS decreasing
VOV OFF - VOV ON
P_4.4.8
Undervoltage Switch OFF
voltage threshold
P_4.4.9
2)
Undervoltage Switch ON/OFF
hysteresis
–
0.40
23
22
1
–
P_4.4.10
P_4.4.11
P_4.4.12
P_4.4.13
Overvoltage Switch OFF voltage VOV OFF
threshold
21
20
–
25
24
–
Overvoltage Switch ON voltage VOV ON
threshold
2)
Overvoltage Switch ON/OFF
hysteresis
VOV HY
VDD Power-On-Reset
VDD POR
2.40
2.35
–
2.63 2.90
2.57 2.85
V
V
V
VDD increasing
VDD decreasing
VDD POR - VDD POffR
P_4.4.14
P_4.4.15
P_4.4.98
VDD Power-Off-Reset
VDD POffR
VDD POR HY
2)
VDD Power ON/OFF hysteresis
0.06
–
Static Drain-source ON-Resistance (High-Side or Low-Side)
High-Side or Low-Side RDSON
(all outputs)
RDSON_HB_25C
–
825 1200 mΩ
IOUT = ±0.5 A;
Tj = 25 °C
P_4.4.16
P_4.4.17
High-Side or Low-Side RDSON
(all outputs)
RDSON_HB_150
–
1350 1800 mΩ
IOUT = ±0.5 A;
Tj = 150 °C
C
Output Protection and Diagnosis of high-side (HS) channels of half-bridge output
HS Overcurrent Shutdown
Threshold
ISD_HS
-1.5
-1.2 -0.9
A
See Figure 6
P_4.4.20
P_4.4.21
Difference between shutdown ILIM_HS
and limit current
-
-1.2
-0.6
0
A
2) |ILIM_HS| ≥ |ISD_HS|
See Figure 6
ISD_HS
Datasheet
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1.0
2017-12-07
TLE94004EP
General Product Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 20 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN1= HIGH
and EN2= HIGH, IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless
otherwise specified; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified) (cont’d)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
2)
Overcurrent Shutdown filter
time
tdSD_HS
15
19
23
µs
P_4.4.22
Output Protection and Diagnosis of low-side (LS) channels of half-bridge output
LS Overcurrent Shutdown
Threshold
ISD_LS
0.9
1.2
0.6
19
1.5
1.2
23
A
See Figure 7
P_4.4.27
P_4.4.28
P_4.4.29
2)
Difference between shutdown ILIM_LS
and limit current
-
0
A
I
≥ ISD_LS
LIM_LS
ISD_LS
Figure 7
2)
Overcurrent Shutdown filter
time
tdSD_LS
15
µs
Outputs OUT(1...n) leakage current
HS leakage current in off state IQLHn_NOR
-2
-0.5
–
µA
VOUTn = 0V ; OUT1/2: P_4.4.32
EN1=GND,
EN2=High; OUT3/4:
EN1=High,EN2=GN
D
HS leakage current in off state IQLHn_SLE
LS Leakage current in off state IQLLn_NOR
-2
–
-0.5
0.5
–
2
µA
µA
VOUTn = 0V; EN1 =
EN2 =GND
P_4.4.33
VOUTn = VS ; OUT1/2: P_4.4.34
EN1=GND,
EN2=High; OUT3/4:
EN1=High,EN2=GN
D
LS Leakage current in off state IQLLn_SLE
–
0.5
2
µA
VOUTn = VS ; EN1 =
P_4.4.35
EN2 =GND
Output Switching Times. See Figure 8 and Figure 9.
Slew rate of high-side and low- dVOUT/ dt
side outputs
0.1
0.45 0.75
V/µs Resistive load =
P_4.4.36
P_4.4.37
P_4.4.38
P_4.4.39
P_4.4.40
P_4.4.41
P_4.4.42
3)
100Ω; VS=13.5V
Output delay time high side
driver on
tdONH
tdOFFH
tdONL
tdOFFL
5
20
45
20
45
35
75
35
75
µs
µs
µs
µs
µs
µs
Resistive load =
100Ω to GND
Output delay time high side
driver off
15
5
Resistive load =
100Ω to GND
Output delay time low side
driver on
Resistive load =
100Ω to VS
Output delay time low side
driver off
15
100
100
Resistive load =
100Ω to VS
Cross current protection time, tDHL
high to low
130 160
130 160
Resistive load =
100Ω2)
Cross current protection time, tDLH
low to high
Resistive load =
100Ω2)
Datasheet
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TLE94004EP
General Product Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 20 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN1= HIGH
and EN2= HIGH, IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless
otherwise specified; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified) (cont’d)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Input Interface: Logic Inputs EN1, EN2
Set up time after sleep mode
High-input voltage
tSET_DI
VENH
–
–
–
150
µs
V
2) See Figure 5
P_4.4.49
P_4.4.43
0.7 *
VDD
–
VDD
Low-input voltage
VENL
0
–
0.3 *
V
–
P_4.4.44
VDD
2)
Hysteresis of input voltage
Pull down resistor
EF reset time
VENHY
–
500
40
–
–
mV
kΩ
ns
P_4.4.45
P_4.4.46
RPD_EN
tEF_RESET
20
250
70
–
VEN1/2 = 0.2 x VDD
2) Set ENx to Low for P_4.4.121
t
EF_RESET to reset EF
Input Interface: Logic Inputs IN1, IN2, IN3, IN4
High input voltage threshold
VINnH
0.7 *
VDD
–
–
VDD
V
V
–
–
P_4.4.90
P_4.4.91
Low input voltage threshold
VINnL
0
0.3 *
VDD
2)
Hysteresis of input voltage
Pull-down resistor
VINnHY
RPD
–
500
40
–
mV
P_4.4.92
P_4.4.94
20
70
kΩ
–
Output Interface: Logic Output EF
High output voltage level
VEFH
VDD
-
VDD - VDD
V
IEFH = -1.6 mA
P_4.4.88
0.4
0.2
Low output voltage level
Leakage current
VEFL
IEFLK
0
0.2
–
0.4
1
V
IEFL = 1.6 mA
P_4.4.95
P_4.4.96
-1
µA
0V < VEF < 5.5V
Thermal Shutdown
Thermal shutdown junction
temperature
TjSD
160
–
175 190
°C
°C
See Figure 102)
P_4.4.81
P_4.4.82
2)
Thermal comparator hysteresis TjHYS
1) IS_HSON does not include the load current
4
–
2) Not subject to production test, specified by design
3) Measured for 20% - 80% of VS.
Datasheet
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TLE94004EP
Characterization results
4
Characterization results
Performed on 5 devices, over operating temperature and nominal/extended supply range.
Typical performance characteristics
Supply quiescent current
Supply current
P_4.4.1
P_4.4.4
2.9
0.3
0.25
0.2
2.4
1.9
1.4
0.9
0.4
0.15
0.1
0.05
0
-0.1
-50 -30 -10 10 30 50 70 90 110 130 150
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
Junction Temperature [°C]
VS=5.5V
VS=13.5V
VS=18V
VS=20
VS=22V
VS=13.5V
VS=18V
VS=20V
VS=22V
Logic supply quiescent current
Logic supply current
P_4.4.2
P_4.4.5
0.7
0.7
0.65
0.6
0.6
0.5
0.4
0.3
0.2
0.1
0
0.55
0.5
-0.1
-50 -30 -10 10 30 50 70 90 110 130 150
-50
0
50
100
150
Junction Temperature [°C]
Junction Temperature [°C]
VS=5.5V
VS=13.5V
VS=18V
VS=20V
VS=22V
VS=5.5V
VS=13.5V VS=18V VS=20V
VS=22V
Datasheet
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TLE94004EP
Characterization results
HS static Drain-source ON-resistance
LS static Drain-source ON-resistance
P_4.4.16/P_4.4.17
P_4.4.16/P_4.4.17
1500
1600
1500
1400
1300
1200
1100
1000
900
1400
1300
1200
1100
1000
900
800
800
700
700
600
600
-50 -30 -10 10 30 50 70 90 110 130 150
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
Junction Temperature [°C]
VS=5.5V
VS=13.5V
VS=18V
VS=20V
VS=22V
VS=5.5V
VS=13.5V
VS=18V
VS=20V
VS=22V
HS static drain-source ON-resistance
VS = 13.5V and VDD = 5V
LS static drain-source ON-resistance
VS = 13.5V and VDD = 5V
P_4.4.16/P_4.4.17
LS Static Drain-source ON-Resistance
P_4.4.16/P_4.4.17
1500
1500
1400
1300
1200
1100
1000
900
1400
1300
1200
1100
1000
900
800
800
700
700
600
600
-50 -30 -10 10 30 50 70 90 110 130 150
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
Junction Temperature [°C]
OUT1
OUT2
OUT3
OUT1
OUT2
OUT3
Datasheet
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TLE94004EP
Characterization results
Slew rate ON of high-side outputs
Slew rate ON of low-side outputs
P_4.4.36
P_4.4.36
0.60
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.20
-50 -30 -10 10 30 50 70 90 110 130 150
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
Junction Temperature [°C]
VS=5.5V
VS=13.5V
VS=18V
VS=20V
VS=22
VS=5.5V
VS=13.5V
VS=18V
VS=20V
VS=22V
Slew rate OFF of high-side outputs
Slew rate OFF of low-side outputs
P_4.4.36
P_4.4.36
0.55
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.50
0.45
0.40
0.35
0.30
0.25
0.20
-50 -30 -10 10 30 50 70 90 110 130 150
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
Junction Temperature [°C]
VS=5.5V
VS=13V5
VS=18V
VS=20V
VS=22V
VS=5.5V
VS=13.5V
VS=18V
VS=20V
VS=22V
Datasheet
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TLE94004EP
Characterization results
HS overcurrent shutdown threshold
LS overcurrent shutdown threshold
P_4.4.20
P_4.4.27
-1120
1240
1220
1200
1180
1160
1140
1120
-1140
-1160
-1180
-1200
-1220
-1240
1100
-50 -30 -10 10 30 50 70 90 110 130 150
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
Junction Temperature [°C]
VS=5.5V
VS=13.5V
VS=18V
VS=20V
VS=22V
VS=5.5V
VS=13.5
VS=18V
VS=20V
VS=22V
Undervoltage switch ON voltage threshold
Undervoltage switch OFF voltage threshold
P_4.4.8
P_4.4.9
5.05
4.64
4.62
4.6
5
4.95
4.9
4.58
4.56
4.54
4.52
4.85
4.5
-50 -30 -10 10 30 50 70 90 110 130 150
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
Junction Temperature [°C]
VDD=3V
VDD=5V
VDD=5.5V
VDD=3V
VDD=5V
VDD=5.5V
Datasheet
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TLE94004EP
Characterization results
Overvoltage switch ON voltage threshold
Overvoltage switch OFF voltage threshold
P_4.4.12
P_4.4.11
22.8
23.6
22.7
22.6
22.5
22.4
22.3
22.2
22.1
22.0
23.5
23.4
23.3
23.2
23.1
23
22.9
22.8
21.9
22.7
-50 -30 -10 10 30 50 70 90 110 130 150
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
Junction Temperature [°C]
VDD=3V
VDD=5V
VDD=5.5V
VDD=3V
VDD=5V
VDD=5.5V
VDD Power-on-reset and VDD Power-off-reset
P_4.4.14/P_4.4.15
2.68
2.66
2.64
2.62
2.60
2.58
2.56
2.54
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature [°C]
VDD POR
VDD POffR
Datasheet
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TLE94004EP
General Description
5
General Description
5.1
Power Supply
The TLE94004EP has two power supply inputs, VS and VDD. The half bridge outputs are supplied by VS, which is
connected to the 12V automotive supply rail. VDD is used to supply the I/O buffers and internal voltage
regulator of the device.
VS and VDD supplies are separated so that information stored in the logic block remains intact in the event of
voltage drop outs or disturbances on VS. The system can therefore continue to operate once VS has recovered,
without having to resend commands to the device.
A rising edge on VDD crossing VDD POR triggers an internal Power-On Reset (POR) to initialize the IC at power-on.
All data stored internally is deleted, and the outputs are switched off (high impedance).
An electrolytic and 100nF ceramic capacitors are recommended to be placed as close as possible to the VS
supply pin of the device for improved EMC performance in the high and low frequency band. The electrolytic
capacitor must be dimensioned to prevent the VS voltage from exceeding the absolute maximum rating. In
addition, decoupling capacitors are recommended on the VDD supply pin.
5.2
Operation modes
5.2.1
Normal mode
The TLE94004EP enters normal mode by setting EN1 or EN2 to High. In normal mode, the charge pump is
active and all output transistors can be activated or deactivated according to Chapter 6.1.
5.2.2
Sleep mode
The TLE94004EP enters sleep mode by setting the EN1 and EN2 pins to Low. The EN1 and EN2 inputs have an
internal pull-down resistor.
In sleep mode, all output transistors are turned off and the logic content is reset. The current consumption is
reduced to ISQ + IDD_Q
.
5.3
Reset Behaviour
The following reset triggers have been implemented in the TLE94004EP:
DD Undervoltage Reset:
V
The digital block will be deactivated, the logic contents cleared and the output stages are switched off if VDD is
below the undervoltage threshold, VDD POffR. The digital block is initialized once VDD voltage levels is above the
undervoltage threshold, VDD POR
.
Reset on EN1/2 pins:
If the EN1/2 pins are pulled Low, the logic content is reset and the device enters sleep mode.
5.4
Reverse Polarity Protection
The TLE94004EP requires an external reverse polarity protection. During reverse polarity, the free-wheeling
diodes across the half bridge output will begin to conduct, causing an undesired current flow (IRB) from ground
potential to battery and excessive power dissipation across the diodes. As such, a reverse polarity protection
diode is recommended (see Figure 4).
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TLE94004EP
General Description
b)
VBAT
a)
GND
D
RP
CS2
C
S
HSx
HSx
OUTx
OUTx
LSx
LSx
I
RB
VBAT
GND
Figure 4
Reverse Polarity Protection
Datasheet
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TLE94004EP
Half-Bridge Outputs
6
Half-Bridge Outputs
The half-bridge outputs of the TLE94004EP are intended to drive motor loads. They consist of a total of four
DMOS half-bridges, which can be driven either continuously or in PWM via INx pins. The output stages
integrated circuits protect the outputs against overcurrent and overtemperature.
6.1
Output Stages
EN1 and EN2 inputs control the state of the device according to Table 6.
•
When EN1 = 0 and EN2 = 0, the device enters sleep mode with low power consumption and all outputs are
OFF (high impedance).
•
•
When EN1=1, HB1 and HB2 are enabled
When EN2=1, HB3 and HB4 are enabled
Table 6
Device states
EN1
EN2
HB1/2
OFF
HB 3/4
OFF
Device state
0
0
1
1
0
1
0
1
Sleep mode, all outputs are OFF
Device is in normal mode
Device is in normal mode
Device is in normal mode
OFF
Enabled
OFF
Enabled
Enabled
Enabled
Note:
After the transition from sleep mode to normal mode, the outputs are OFF for a duration tSET_DI .See
Figure 5
EN1 and/or EN2 = High
VENx
Normal mode
H
EN1 =EN2 = Low
Sleep mode
L
Time
OUTx
tSE T _DI
Active
High-Z
Time
OUTx is active if the
corresponding ENx = High
Figure 5
Output setup time after a transition from standby to normal mode
The control inputs consist of CMOS-compatible schmitt-triggers with hysteresis. There are altogether four
control inputs, i.e. IN1, IN2 , IN3 and IN4 with internal pull-down resistors.
If EN1 = 0, HB1 and HB2 are OFF. If EN1 = 1, HB1 and HB2 are controlled according toTable 7
Table 7
Functional Truth Table for HB1 and HB2
EN1
0
IN1
X
IN2
X
HB1
OFF
L
HB2
OFF
L
Mode
HB1 and HB2 are OFF
Brake Low
1
0
0
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TLE94004EP
Half-Bridge Outputs
Table 7
Functional Truth Table for HB1 and HB2
EN1
IN1
0
IN2
1
HB1
L
HB2
H
Mode
1
1
1
Motor counter-clockwise
Motor clockwise
Brake High
1
0
H
L
1
1
H
H
If EN2 = 0, HB3 and HB4 are OFF. If EN2 =1, HB3 and HB4 are controlled according to Table 8
Table 8
Functional Truth table for HB3 and HB4
EN2
IN3
X
IN4
X
HB3
OFF
L
HB4
OFF
L
Mode
0
1
1
1
1
HB3 and HB4 are OFF
Brake Low
0
0
0
1
L
H
Motor counter-clockwise
Motor clockwise
Brake High
1
0
H
L
1
1
H
H
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TLE94004EP
Half-Bridge Outputs
6.2
Diagnosis Monitoring
The EF pin (push-pull output) reports the following error conditions:
•
•
•
Overcurrent (OC)
Overtemperature (OT)
VS overvoltage and VS undervoltage
EF reports an overcurrent event on HB1/2 only if EN1 = 1. Likewise, EF reports an overcurrent on HB3/4 only if
EN2 = 1.
After an overcurrent event is detected on HB1/2, EF is latched to 1, until EN1 = 0.Likewise, after an overcurrent
event detected on HB3/4, EF is latched to 1 until EN2 = 0.
EF reports overtemperature or VS overvoltage/undervoltage events if the device is in normal mode (EN1 = 1 or
EN2 = 1). The error flag is latched to 1 for these fault conditions until EN1 = 0 and EN2 = 0
Table 9
Error reporting by EF pin
EN1
EN2
Error reported by EF pin
0
1
0
1
0
0
1
1
Not applicable, the device is in sleep mode
OC on HB1/2, OT, VS under/overvoltage
OC on HB3/4, OT, VS under/overvoltage
OC on HB1/2, OC on HB3/4, OT, VS under/overvoltage
The table below depicts the EF behaviour:
Table 10
Error flag behaviour and reset conditions
Fault condition
No fault
EF
Reset conditions
0
–
Overcurrent on HB1 or HB2 1 (latched)
Overcurrent on HB3 or HB4 1 (latched)
Set EN1 pin to 0 for tEF_RESET
Set EN2 pin to 0 for tEF_RESET
VS < VOV ON, EN1 = 0 and EN2 = 0 for tEF_RESET
VS > VUV ON, EN1 = 0 and EN2 = 0 for tEF_RESET
EN1 = 0 and EN2 = 0 for tEF_RESET
VS overvoltage
VS undervoltage
Overtemperature
1 (latched)
1 (latched)
1 (latched)
6.3
Protection
This device has embedded protective functions which are designed to prevent the destruction of the device
under fault conditions described in this section. Fault conditions are treated as “outside” normal operating
range. Protection functions are not designed for continuous repetitive operation.
6.3.1
Short Circuit of Output to Supply or Ground
The high-side switches are protected against short circuits to ground whereas the low-side switches are
protected against short circuits to supply.
The high-side and low-side switches will enter into an over-current condition if the current within the switch
exceeds the overcurrent shutdown detection threshold, ISD. Upon detection of the ISD threshold, an
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TLE94004EP
Half-Bridge Outputs
overcurrent shutdown filter, tdSD is begun. As the current rises beyond the threshold ISD, it will be limited by the
current limit threshold, ILIM. Upon expiry of the overcurrent shutdown filter time, the affected power switch is
latched off (see Figure 6 and Figure 7) and the EF is set to 1 and latched.
The faulty power switch remains deactivated and EF is latched as long as the corresponding ENx =1.
To resume normal functionality of the power switch (in the event the overcurrent condition disappears or to
verify if the failure still exists) the microcontroller shall:
1. clear the error flag by setting the corresponding ENx to 0 (see Table 10)
2. set the corresponding ENx to 1 in order to re-enable the corresponding half-bridges
VS
| IHS |
I ILIM_HS I
ON
I ILIM_HS - ISD_HS
I
I ISD_HS
I
OUTn
Short to GND
t
tdSD_ HS
Short condition on High-Side Switch
Figure 6
High-Side Switch - Short Circuit and Overcurrent Protection
VS
ILS
VS
ILIM_ LS
ILIM_ LS - ISD_LS
Short to Supply
ISD_LS
OUTn
ON
t
tdSD_LS
Short condition on Low-Side Switch
Figure 7
Low-Side Switch - Short Circuit and Overcurrent Protection
6.3.2
Cross-current protection
In bridge configurations the high-side and low-side power transistors are ensured never to be simultaneously
“ON” to avoid cross currents. This is achieved by integrating delays in the driver stage of the power outputs to
create a dead-time between switching off of one power transistor and switching on of the adjacent power
transistor within the half-bridge. The dead times, tDHL and tDLH, as shown in Figure 8 case 3 and Figure 9 case
3, have been specified to ensure that the switching slopes do not overlap with each other. This prevents a cross
conduction event.
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TLE94004EP
Half-Bridge Outputs
If x = 1 or 2, then y = 1 and z =2
Otherwisey = 2 and z =1
Case 1: Delay TimeHigh SideDriver OFF
INx
t
Previous State Æ New State
ENy
HS ON
Æ
HS OFF
t
ENz
LS OFF
Æ
LS OFF
t
VOUT_HSx [V]
VS
80%
1)
tdOFFH
20%
GND
t
1)
Delay time HS OFF
Case 2: Delay Time Low Side Driver ON
INx
t
ENy
Previous StateÆ New State
HS OFF
Æ
HS OFF
t
ENz
LS OFF
Æ
LS ON
t
VOUT_LSx [V]
VS
80%
2)
tdONL
20%
2) Delay time LS ON without dead time ; HS previously OFF
GND
t
Case 3: Delay Time Low Side Driver ON with tDHL dead time
INx
Previous State Æ New State
t
t
HS ON
Æ
HS OFF
ENy
LS OFF
Æ
LS ON
VOUT_LSx [V]
VS
80%
Low-Side
ON
3)
tdONL +tDHL
delay time
20%
3) Delay time LS ON with dead time ; HS previously ON
GND
t
Figure 8
Half bridge outputs switching times - high-side to low-side transition
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TLE94004EP
Half-Bridge Outputs
If x = 1 or 2, then y = 1 and z =2
Otherwisey = 2 and z =1
Case 1: Delay Time High Side Driver OFF
INx
t
t
Previous State Æ New State
ENy
HS OFF
Æ
HS OFF
ENz
LS ON
Æ
LS OFF
t
VOUT_LSx [V]
VS
80%
1)
tdOFFL
20%
GND
t
1)
Delay time LS OFF
Case 2: Delay Time High Side Driver ON
INx
t
Previous State Æ New State
ENy
ENz
HS OFF
Æ
HS ON
t
LS OFF
Æ
LS OFF
t
VOUT_HSx [V]
VS
80%
2)
tdONH
20%
2) Delay time HS ON without dead time ; LS previously OFF
GND
t
Case 3: Delay Time High Side Driver ON with tDLH dead time
INx
Previous State ÆNew State
HS OFF
Æ
HS ON
t
ENy
LS ON
Æ
LS OFF
t
VOUT_HSx [V]
VS
80%
High-Side
ON
3)
tdONH + tDLH
delay time
20%
3) HS ON delay time with dead time ; LS previously ON
GND
t
Figure 9
Half bridge outputs switching times- low-side to high-side transition
6.3.3
Temperature monitoring and shutdown
Temperature sensors are integrated in the power stages. The temperature monitoring circuit compares the
measured temperature to the shutdown threshold.
Datasheet
25
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TLE94004EP
Half-Bridge Outputs
If one or more temperature sensors reach the shut-down temperature threshold, all outputs are latched off.
All outputs remain deactivated as long as EN1 = 1 or EN2 = 1.
To resume normal functionality of the power switch (in the event the overtemperature condition disappears
or to verify if the failure still exists) the microcontroller shall:
1. clear the error flag by setting EN1 and EN2 to 0 (see Table 10)
2. set EN1 or EN2 to 1 in order to send the device from sleep mode back to normal mode
Tj
TjSD
t
VOUTx
ON
High Z
t
Overtemperature error
no error
VEF
H
Error Flag
L
t
Figure 10 Overtemperature Behaviour
Datasheet
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2017-12-07
TLE94004EP
Half-Bridge Outputs
6.3.4
VS Undervoltage Behaviour
If the supply voltage decreases to the undervoltage switch-off threshold, VUV OFF, then all output switches are
switched off, and the error flag EF is set to High (error detection). If VS rises again and reaches the undervoltage
switch-on threshold, VUV ON, the power-stages are automatically reactivated according to ENx and INx. Refer to
Figure 11
VS
VUV HY
VUV ON
VUV OFF
Time
Time
EN1 =EN2= 0
EN1=1
Sleep mode and/or EN2=1
VOUTx
ON
OFF (High-Z)
VS undervoltage
Error Flag
t
SE T _DI
VEF
H
Hi-Z
L
Time
EF actively set of Low
Figure 11 Undervoltage behaviour
Datasheet
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2017-12-07
TLE94004EP
Half-Bridge Outputs
6.3.5
VS Overvoltage Behaviour
If the supply voltage increases beyond the overvoltage switch threshold, VOV OFF, then all output switches are
switched off and EF is set High, indicating an overvoltage condition. If VS decreases again and reaches the
overvoltage switch-on threshold, VOV ON, then the power-stages are automatically reactivated according to
ENx and INx. Refer to Figure 12.
VS
VOV HY
VOV OFF
VOV ON
Time
EN1= EN2 = 0
Sleep mode
EN1=1
and/or EN2=1
VOUTx
ON
OFF (High-Z)
VS overvoltage
Time
Error Flag
tSE T_ DI
VEF
H
Hi-Z
L
Time
EF actively set of Low
Figure 12 Overvoltage behaviour
6.3.6
VDD Undervoltage
In the event the VDD logic supply decreases below the undervoltage threshold, VDD_POFFR, the TLE94004EP will
enter reset. EF is set to high impedance during a VDD undervoltage event.
The digital block will be initialized and the output stages are switched off to High impedance. The
undervoltage reset is released once VDD voltage levels are above the undervoltage threshold, VDD POR
.
Datasheet
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2017-12-07
TLE94004EP
Application Information
7
Application Information
Note:
The following simplified application examples are given as a hint for the implementation of the
device only and shall not be regarded as a description or warranty of a certain functionality,
condition or quality of the device. The function of the described circuits must be verified in the real
application.
7.1
Application Diagram
CD
RWA
100nF
VBAT
100 kΩ
Reset
Adjust
D
GND
3-5, 10-12
Watchdog In
8
1
6
7
13
Watchdog Out
Watchdog Adjust
Input
DRP
Reset Out
Q
VReg
TLE4678G
14
9
2
CI
100 nF
CQ
22μF
WDO WDI
R
µC
GND
VCC
100 nF
VS
VDD
OUT1
EN1
EN2
M1
M1
M2
M3
EF
OUT2
Series resistors are
recommended if the VS of
the TLE94004 EP is protected
by an active reverse polarity
protection
M1
IN1
IN2
IN3
IN4
OUT3
OUT4
Landing pads for ceramic
capacitors at OUTx
M2
GND
2 motors
in non-
cascaded
configuration
3 motors in
cascaded
configuration
Single motor,
higher current
a
b
c
Figure 13 Application Example for DC-motor loads
Datasheet
29
1.0
2017-12-07
TLE94004EP
Application Information
C
D
R
WA
100nF
VBAT
100 kΩ
Reset
Adjust
D
GND
3-5, 10-12
Watchdog In
8
1
6
7
13
Watchdog Out
Watchdog Adjust
Input
D
RP
Reset Out
Q
VReg
TLE4678G
14
9
2
C
I
100 nF
C
Q
22μF
WDO
WDI
R
VCC
100 nF
VS
VDD
OUT
1
2
EN1
EN2
M1
M1
M2
M3
EF
OUT
OUT
Series resistors are
recommended if the VS of
µC
M1
IN
IN
IN
IN
1
the TLE94004 EP is protected
by an active reverse polarity
protection
2
3
3
4
Landing pads for ceramic
capacitors at OUTx
M2
OUT
4
GND
2 motors
in non-
cascaded
3 motors in
cascaded
configuration
Single motor,
higher current
GND
configuration
a
b
c
VDD
VDD
V
S
VS
OUT
OUT
1
2
EN1
EN2
M1
M1
M2
M3
EF
M1
IN
IN
IN
IN
1
2
3
OUT
OUT
3
4
4
M2
GND
2 motors
in non-
cascaded
configuration
3 motors in
cascaded
configuration
Single motor,
higher current
a
b
c
Figure 14 Application Example with two TLE94004EP
Datasheet
30
1.0
2017-12-07
TLE94004EP
Application Information
V
BAT
DRP
VReg
Q
VCC
VS
VDD
OUT
1
EN1
EN2
OUT
OUT
2
3
EF
µC
IN1
IN2
IN3
IN4
Series resistors are
recommended if the VS of
the TLE94004EP is protected
by an active reverse polarity
protection
M
Landing pads for ceramic
capacitors at OUTx
OUT
4
GND
GND
Figure 15 Application Example with TLE94004EP driving a bipolar transistor in voltage mode control
Notes on the application example
1. Series resistors between the microcontroller and the signal pins of the TLE94004EP are recommended if an
active reverse polarity protection (MOSFET) is used to protect the VS pin. These resistors limit the current
between the microcontroller and the device during negative transients on VBAT (e.g. ISO/TR 7637 pulse 1)
2. Landing pads for ceramic capacitors at the outputs of the TLE94004EP as close as possible to the connectors
are recommended (the ceramic capacitors are not populated if unused). These ceramic capacitors can be
mounted if a higher performance in term of ESD capability is required.
3. The electrolytic capacitor at the VS pin should be dimensioned in order to prevent the VS voltage from
exceeding the absolute maximum rating. PWM operation with a too low capacitance can lead to a VS voltage
overshoot, which results in a VS overvoltage detection.
4. Unused outputs are recommended to be left unconnected (open) in the application. If unused output pins are
routed to an external connector which leaves the PCB, then these outputs should have provision for a zero
ohm jumper (depopulated if unused) or ESD protection. In other words, unused pins should be treated like
used pins.
5. Place bypass ceramic capacitors as close as possible to the VS pins, with shortest connections the GND pins
and GND layer, for best EMC performance
Datasheet
31
1.0
2017-12-07
TLE94004EP
Application Information
7.2
Thermal application information
Ta = -40°C, Ch1 to Ch4 are dissipating a total of 0.8W (0.2W each).
Ta = 85°C, Ch1 to Ch4 are dissipating a total of 0.54W (0.135W each).
Zth-ja for TLE 94004EP
150
1s0p / 600mm² / -40°C
1s0p / 600mm² / +85°C
120
1s0p / 300mm² / -40°C
1s0p / 300mm² / +85°C
1s0p / footprint / -40°C
90
1s0p / footprint / +85°C
2s2p / -40°C
2s2p / +85°C
60
30
0
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
10000
time [sec]
Figure 16 ZthJA Curve for different PCB setups
Zth-jc for TLE 94004EP
18
16
14
12
10
8
Tamb = -40°C
Tamb = +85°C
6
4
2
0
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
time [sec]
Figure 17 ZthJC Curve
Datasheet
32
1.0
2017-12-07
TLE94004EP
Package Outlines
8
Package Outlines
Figure 18 PG-TSDSO-14 (Plastic Green - Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e lead-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Datasheet
33
1.0
2017-12-07
TLE94004EP
Revision History
9
Revision History
Revision Date
Changes
1.0
2017-12-07 Initial release
Datasheet
34
1.0
2017-12-07
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
The information given in this document shall in no For further information on technology, delivery terms
Edition 2017-12-07
Published by
Infineon Technologies AG
81726 Munich, Germany
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest
characteristics ("Beschaffenheitsgarantie").
Infineon Technologies Office (www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2017 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or any
consequences of the use thereof can reasonably be
expected to result in personal injury.
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