V23832-T2531-M101 [INFINEON]
PAROLI 2 Tx AC, 1.25 Gbit/s; 帕罗利2的Tx交流， 1.25 Gbit / s的
| 型号： | V23832-T2531-M101 |
| 厂家： | 
Infineon |
| 描述： | PAROLI 2 Tx AC, 1.25 Gbit/s |
| 文件： | 总33页 (文件大小：690K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fiber Optics
Parallel Optical Link Transmitter:
PAROLI® 2 Tx AC, 1.25 Gbit/s
V23832-T2531-M101
V23832-R511-M101
Parallel Optical Link Receiver:
PAROLI® 2 Rx AC, 1.25 Gbit/s
Design Benefits
• Relieve system bandwidth bottle necks
• Simplifies system design
• Enables system upgrades in field
• Low power consumption at increased board density
• Flat package for height critical application
Features
File: 3104
• Infineon’s highly reliable 850 nm VCSEL technology
• Power supply 3.3 V
• Transmitter with multistandard electrical interface
• Receiver with Infineon’s adjustable CML output
• 12 electrical data channels
• Asynchronous, AC-coupled optical link
• 12 optical data channels
• Internal power monitoring for constant power budget
• Transmission data rate of up to 1250 Mbit/s per channel,
total link data rate up to 15 Gbit/s
• PIN diode array technology
• Optimized for 62.5 µm multimode graded index fiber
• MT based optical port (MPO connector)
• Plug-in module with ultra low profile
• IEC Class 1M laser eye safety compliant
• OIF1) compliant
• GBE mask compliant modules available
• EMI-shielding for front panel access
• Standard link length compliant
• Unused transmitter channels can be switched off
• DC or AC coupling of input data
• Telcordia compliant
1)
OIF-VSR4-01.0 Implementation Agreement (VSR OC-192/STM-64).
PAROLI® is a registered trademark of Infineon Technologies AG
Data Sheet
1
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Applications
Optical Port
• Designed for the industry standard 12 fiber MT Connector (MPO)
• Alignment pins fixed in module port
• Integrated mechanical keying
• Module is provided with a dust cover
Features of MT Connector (MPO)
(as part of optional PAROLI fiber optic cables)
• Uses standardized MT ferrule
• MT compatible fiber spacing (250 µm) and alignment pin spacing (4600 µm)
• Push-pull mechanism
• Ferrule bearing spring loaded
Features of the PAROLI 2 Electrical Connector
• Pluggable version using BGA socket
• 100 pin positions (10x10)
• 4 mm stack height in mated conditions
• Plug and receptacle are provided with protective cap
• Standard BGA process for socket assembly
• Contact area plating made out of gold over nickel
• Module side: FCI-MEG-Array® -Plug (part no. 84512-202)
• PCB side: FCI-MEG-Array® -Receptacle (part no. 84513-201)
Applications
• Switches, routers, transport equipment
• Mass storage devices
• Access network
• Rack-to-rack/board-to-board interconnect
• Optical backplane interconnect
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Pin Configuration
Pin Configuration
Pin A1
Pin A10
Bottom view
File: 3331
Figure 1
Pin Information Transmitter
Numbering Conventions Transmitter (bottom view)
J
I
H
G
F
E
D
C
B
A
VEE
DI05N
DI05P
DI06N
DI06P
DI07N
DI07P
DI08N
DI08P
VEE
1
2
3
4
5
6
7
8
9
10
DI04P
DI04N
DI01P
DI01N
DI02P
DI02N
DI03P
DI03N
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
DI09N
DI09P
DI12N
DI12P
DI11N
DI11P
DI10N
DI10P
VEE
Reserved Reserved t.b.l.o.
Reserved Reserved t.b.l.o.
t.b.l.o.
t.b.l.o.
t.b.l.o.
–LE
Reserved Reserved VEE
Reserved Reserved VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
t.b.l.o.
t.b.l.o.
LCU
VIN
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
LE
–RESET VEE
VCC
VCC
VCC
VEE
VEE
VCC
This edge towards MPO connector
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Pin Configuration
Pin Description Transmitter
Symbol
VCC
Level/Logic Description
Power supply voltage of laser driver
VIN
CML: VIN = Reference supply (e.g. VCC)
LVDS, LVPECL: VIN = VEE
VEE
Ground
LCU
LVCMOS
Out
Laser Controller Up.
High = normal operation.
Low = laser fault or RESETlow.
DIxxN
Signal In
Signal In
Data Input #xx, inverted
DIxxP
Data Input #xx, non-inverted
–RESET
LVCMOS In High = laser diode array is active.
Low = switches laser diode array off.
This input has an internal pull-down to ensure laser eye
safety switch off in case of unconnected RESETinput.
LVCMOS In Laser ENABLE. High active.
LE
High = laser array is on if LE is also active.
Low = laser array is off. This input has an internal pull-up,
therefore can be left open.
–LE
LVCMOS In Laser ENABLE. Low active.
Low = laser array is on if LE is also active. This input has
an internal pull-down, therefore can be left open.
t.b.l.o.
to be left open
Reserved
Reserved for future use
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Pin Configuration
Pin A1
Pin A10
Bottom view
File: 3332
Figure 2
Pin Information Receiver
Numbering Conventions Receiver (bottom view)
J
I
H
G
F
E
D
C
B
A
VEE
DO05P DO05N DO06P DO06N DO07P DO07N DO08P DO08N VEE
1
2
3
4
5
6
7
8
9
10
DO04N VEE
DO04P VEE
DO01N VEE
DO01P VEE
DO02N VEE
DO02P VEE
DO03N VEE
DO03P VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
DO09P
DO09N
DO12P
DO12N
DO11P
DO11N
DO10P
DO10N
VEE
Reserved Reserved t.b.l.o.
Reserved Reserved OEN
t.b.l.o.
ENSD
–SD12
Reserved Reserved VEE
Reserved Reserved VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
SD01
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
Reserved REFR
VCCO
VCCO
VCC
VCCO
VCCO
VCC
VEE
VEE
VCC
VCC
This edge towards MPO connector
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Pin Configuration
Pin Description Receiver
Symbol
VCC
Level/Logic Description
Power supply voltage of pre amplifier and analog circuitry
Power supply voltage of output stages
VCCO
REFR
Adjustment of output current by connecting external
resistor to VEE
VEE
Ground
OEN
LVCMOS In Output Enable High = normal operation.
Low = sets all Data Outputs to low.
This input has an internal pull-up which pulls to high level
when this input is left open.
ENSD
LVCMOS In High = SD1 and –SD12 function enabled.
Low = SD1 and –SD12 are set to permanent active.
This input has an internal pull-up which pulls to high level
when this input is left open.
SD1
LVCMOS
Out
Signal Detect on fiber #1.
High = signal of sufficient AC power is present on fiber #1.
Low = signal on fiber #1 is insufficient.
–SD12
LVCMOS
Out
low active
Signal Detect on fiber #12.
Low = signal of sufficient AC power is present on fiber #12.
High = signal on fiber #12 is insufficient.
DOxxP
DOxxN
t.b.l.o.
CML Out
CML Out
Data Output #xx, non-inverted
Data Output #xx, inverted
to be left open
Reserved
Reserved for future use
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Description
Description
PAROLI is a parallel optical link for high-speed data transmission. A complete PAROLI
link consists of a transmitter module, a 12-channel fiber optic cable, and a receiver
module. The transmitter supports LVDS, CML and LVPECL differential signals. Two
different receiver modules are available. Module V23832-R521-M101 is for LVDS
electrical output only. This specification (V23832-R511-M101) describes a receiver for
Infineon’s adjustable CML output.
Transmitter
DC-balanced
data stream
Receiver
12 parallel
channels
12
12
PAROLI Link
File: 3509
Figure 3
Example of a PAROLI Link
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Description
Transmitter V23832-T2531-M101
The transmitter module converts parallel electrical input signals via a laser driver and a
Vertical Cavity Surface Emitting Laser (VCSEL) diode array into parallel optical output
signals. All input data signals are Multistandard Differential Signals (LVDS compatible;
LVPECL and CML is also supported because of the wide common input range). The
electrical interface (LVDS, LVPECL or CML) is selected by the supply inputs VIN. The
data rate is up to 1250 Mbit/s for each channel. The transmitter module’s min. data rate
of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with
a lower disparity. The transmitter features active feedback of optical output power and
extinction ratio, which guarantees a constant power budget.
Unused channels can be forced to a quiescent state by applying e.g. a constant high
level to the input stage of these channels. The integrated alerter circuit (see “Laser Eye
Safety Design Considerations” on Page 12) will switch off the corresponding
transmitter output, which results also in a reduced power consumption. Unused
transmitter input channels can also be left open. The integrated swing detection circuit
will assure a quiescent output state for these channels.
A logic low level at –RESET switches all laser outputs off. During power-up –RESET
must be used as a power-on reset which disables the laser driver and laser control until
the power supply has reached a 3.135 V level.
The Laser Controller Up (LCU) output is low if a laser fault is detected or –RESET is
forced to low.
All non data signals have LVCMOS levels.
Transmission delay of the PAROLI system is ≤ 1 ns for the transmitter, ≤ 1 ns for the
receiver and approximately 5 ns per meter for the fiber optic cable.
Electrical
Input
LE −LE Laser Enable
Optical
Output
12
12
12
12
Laser
Driver
Laser
Diode
Array
Data In
Data
Input
Stage
Laser
Control
Laser Controller
Up (LCU)
VIN
−RESET
File: 3317
Figure 4
Transmitter Block Diagram
1)
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,
ITU-T recommendation G.957 sec. II.
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Description
Receiver V23832-R511-M101
The PAROLI receiver module converts parallel optical input signals into parallel electrical
output signals. The optical signals received are converted into voltage signals by PIN
diodes, trans impedance amplifiers, and gain amplifiers. The differential data outputs are
Infineon’s adjustable CML signals. A separate module (V23832-R521-M101) with LVDS
output is also available. The output differential voltage (swing) is adjusted by an external
resistor connected to the REFR module input, the output average is adjustable by
external pull-up resistors.
The data rate is up to 1250 Mbit/s for each channel. The receiver module’s min. data rate
of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern
with a lower disparity.
Additional Signal Detect outputs (SD1 active high / –SD12 active low) show whether an
optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can
be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently
generate an active level at Signal Detect outputs, even if there is insufficient signal input.
This could be used for test purposes.
A logic low at Output Enable sets all data outputs to logic low. SD outputs will not be
effected.
All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is
≤ 1 ns for the transmitter, ≤ 1 ns for the receiver and approximately 5 ns per meter for
the fiber optic cable.
Optical
Input
REFR
Electrical
Output
12
12
12
12
Gain
Amplifier
CML
Output
Stage
Data Out
Data
Pin
Diode
Array
Amplifier
Signal
Detect
Circuit
SD1
−SD12
ENSD Output Enable (OEN)
File: 3323
Figure 5
Receiver Block Diagram
1)
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,
ITU-T recommendation G.957 sec. II.
Data Sheet
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2003-11-19
V23832-T2531-M101
V23832-R511-M101
Description
Regulatory Compliance
The following table shows industry standard test methods and results obtained from the
indicated test methods. (The overall system design will affect the electromagnetic
interference (EMI), electrostatic discharge (ESD) and immunity).
Feature
Standard
Comments
ESD:
JEDEC Human Body
Class 1C
Electrostatic Discharge Model (HBM) Test
to the Electrical Pins
(HBM)
Method
EIA/JESD22-A114-B
(MIL-STD 883D
method 3015.7)
Immunity:
EN 61000-4-2
IEC 61000-4-2
Discharges ranging from ±2 kV to
±15 kV on the front end/face-plate/
receptacle cause no damage to
module (under recommended
mounting conditions).
Against Electrostatic
Discharge (ESD) to the
Module Receptacle
Immunity:
Against Radio
Frequency
EN 61000-4-3
IEC 61000-4-3
With a field strength of 3 V/m, noise
frequency ranges from 10 MHz to
2 GHz1). No effect on module
performance between the
Electromagnetic Field
specification limits.
Emission:
FCC 47 CFR Part 15, Noise frequency range:
Electromagnetic
Interference (EMI)
Class B
EN 55022 Class B
CISPR 22
30 MHz to 18 GHz;
Radiated Emission does not exceed
specified limits when measured
inside a shielding enclosure with
recommended cutout dimensions.
Typically pass with > 11 dB margin
to the limit (under recommended
mounting conditions).
1)
This test covers high frequency bands of mobile phones.
EMI Recommendations
EMI behavior of each PAROLI module revision is evaluated and measured - in order to
ensure a good and sufficient EMI performance of all PAROLI modules. As the total EMI
performance will also depend on system design and to avoid electromagnetic radiation
exceeding the required limits set by the standards, please take note of the following
recommendations.
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Description
When Gigabit switching components are found on a PCB (e.g. multiplexer, serializer-
deserializer, clock data recovery, etc.), any opening of the chassis may leak radiation;
this may also occur at chassis slots other than that of the device itself. Thus every
mechanical opening or aperture should be as small as feasible and its length carefully
considered.
On the board itself, every data connection should be an impedance matched line (e.g.
micro strip, strip line or coplanar strip line). Data (D) and Data-not (Dn) should be routed
symmetrically. Vias should be avoided. Where internal termination inside an IC or a
PAROLI module is not present, a line terminating resistor must be provided.
The decision of how best to establish a ground depends on many boundary conditions.
This decision may turn out to be critical for achieving lowest EMI performance. At RF
frequencies the ground plane will always carry some amount of RF noise. Thus the
ground and VCC planes are often major radiators inside an enclosure.
As a general rule, for small systems such as PCI cards placed inside poorly shielded
enclosures, the common ground scheme has often proven to be most effective in
reducing RF emissions. In a common ground scheme, the PCI card becomes more
equipotential with the chassis ground. As a result, the overall radiation will decrease. In
a common ground scheme, it is strongly recommended to provide a proper contact
between signal ground and chassis ground at every location where possible. This
concept is designed to avoid hotspots which are places of highest radiation, caused
when only a few connections between chassis and signal grounds exist. Compensation
currents would concentrate at these connections, causing radiation.
However, as signal ground may be the main cause for parasitic radiation, connecting
chassis ground and signal ground at the wrong place may result in enhanced RF
emissions. For example, connecting chassis ground and signal ground at a front panel/
bezel/chassis by means of a fiber optic module may result in a large amount of radiation
especially where combined with an inadequate number of grounding points between
signal ground and chassis ground. Thus the fiber optic module becomes a single contact
point increasing radiation emissions. Even a capacitive coupling between signal ground
and chassis ground may be harmful if it is too close to an opening or an aperture. For a
number of systems, enforcing a strict separation of signal ground from chassis ground
may be advantageous, providing the housing does not present any slots or other
discontinuities. This separate ground concept seems to be more suitable in huge
systems.
The return path of RF current must also be considered. Thus a split ground plane
between Tx and Rx paths may result in severe EMI problems.
The bezel opening for a transceiver should be sized so that all contact springs of the
transceiver cage make good electrical contact with the face plate.
Please consider that the PCB may behave like a dielectric waveguide. With a dielectric
constant of 4, the wavelength of the harmonics inside the PCB will be half of that in free
space. Thus even the smallest PCBs may have unexpected resonances.
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Laser Eye Safety
Laser Eye Safety
The transmitter of the AC coupled Parallel Optical Link (PAROLI) is an IEC 60825-1
Amend. 2 Class 1M laser product. It complies with FDA performance standards (21 CFR
1040.10 and 1040.11) for laser products except for deviations pursuant to Laser Notice
No. 50, dated July 26, 2001. To avoid possible exposure to hazardous levels of invisible
laser radiation, do not exceed maximum ratings.
The PAROLI module must be operated under the specified operating conditions (supply
voltage can be adjusted between 3.0 V and 3.6 V) under any circumstances to ensure
laser eye safety.
Class 1M Laser Product
Attention: Invisible laser radiation. Do not view directly with optical instruments.
Note: Any modification of the module will be considered an act of “manufacturing”, and will
require, under law, recertification of the product under FDA (21 CFR 1040.10 (i)).
Laser aperture
and beam
File: 3506
Figure 6
Laser Emission
Laser Eye Safety Design Considerations
To ensure laser eye safety for all input data patterns each channel is controlled internally
and will be switched off if the laser eye safety limits are exceeded. A channel alerter
switches the respective data channel output off if the input duty cycle permanently
exceeds 57% (switching range 57 % min. - 65 % max.). The alerter will not disable the
channel below an input duty cycle of 57% under all circumstances.
The minimum alerter response time is 1 µs with a constant high input, i.e. in the input
pattern the time interval of excessive high input (e.g. ’1’s in excess of a 57% duty cycle,
consecutive or non-consecutive) must not exceed 1 µs, otherwise the respective channel
will be switched off. The alerter switches the respective channel from off to on without
the need of resetting the module if the input duty cycle is no longer violated.
All of the channel alerters operate independently, i.e. an alert within a channel does not
affect the other channels. To decrease the power consumption of the module unused
channel inputs can be tied to high input level. In this way a portion of the supply current
in this channel is triggered to shut down by the corresponding alerter.
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Laser Eye Safety
Laser Eye Safety Measurement Conditions
Laser Data
Symbol
Values
typ.
Unit
Condition
min.
max.
Center wavelength λC
830
850
860
nm
Tcase 0...80°C
Array size
12
channels
°/rad
Divergence angle/ Θ/NA
Numerical
44/0.22
Θ full /
NA half angle
Aperture
IEC class 1M
Accessible
Emission Limit
AEL
6.36
dBm
7 mm aperture
@ 100 mm
distance
Applying penalties ∆Popt
4.2
dB
(safety margin)
Test limit
2.16
dBm
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Technical Data
Technical Data
Absolute Maximum Ratings
Stress beyond the values stated below may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods of time may affect
device reliability. Performance between absolute maximum ratings and recommended
operating conditions is not guaranteed.
Parameter
Symbol
Limit Values
Unit
min.
max.
4.5
Supply Voltage
VCC–VEE –0.3
V
Data/Control Input Levels1)
Data Input Differential Voltage2)
Operating Case Temperature3)
Storage Ambient Temperature
Relative Humidity (non condensing)
VIN
–0.5
VCC+0.5
2.0
V
|VID|
Tcase
Tstg
V
0
90
°C
°C
%
kV
–40
5
100
95
ESD Resistance
1
(all pins to VEE, human body model)4)
(see table “Regulatory Compliance” on
Page 10)
1)
At Data and LVCMOS inputs.
2)
|VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|.
Measured at case temperature reference point (see Figure 18 on Page 31).
To avoid electrostatic damage, handling cautions similar to those used for MOS devices must be observed.
3)
4)
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Technical Data
Recommended Operating Conditions1)
Parameter
Symbol
Values
Unit
min.
typ.
max.
Transmitter
Operating Case Temperature
Power Supply Voltage
Noise on Power Supply2)
Tcase
VCC
0
45
80
°C
V
3.135
3.3
3.6
200
VCC
NPS
mV
mV
Data Input Voltage Range
(DC-coupled)3), 4)
VDATAI
500
80
Data Input Differential Voltage
(DC- or AC-coupled)4), 5)
|VID|
1000
mV
Data Input Skew6)
tSPN
0.5 x tR-DI, ps
tF-DI
Data Input Rise/Fall Time7)
LVCMOS Input High Voltage
LVCMOS Input Low Voltage
t
R-DI, tF-DI 50
360
VCC
0.8
20
ps
V
VLVCMOSIH 2.0
VLVCMOSIL VEE
V
LVCMOS Input Rise/Fall Time8) tR-LVCMOSI
,
ns
tF-LVCMOSI
Receiver
Power Supply Voltages
Noise on Power Supply2)
Output Current9)
VCC, VCCO 3.0
3.3
3.6
200
9
V
NPS
mV
mA
Iout
3
Output Voltage (DC-coupled)10) Vout
V
CCO–1.8
V
CCO+0.5 V
Output Differential Voltage
(DC- or AC-coupled)10), 11)
|VOD|
80
800
mV
Output Load RC Time Constant tRC
150
VCC
0.8
20
ps
V
LVCMOS Input High Voltage
VLVCMOSIH 2.0
LVCMOS Input Low Voltage
VLVCMOSIL VEE
V
LVCMOS Input Rise/Fall Time8) tR-LVCMOSI
,
ns
tF-LVCMOSI
Optical Input Rise/Fall Time12)
Input Extinction Ratio
t
R-OI, tF-OI
400
860
ps
ER
6.0
dB
nm
Input Center Wavelength
λC
830
Voltages refer to VEE = 0 V.
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Technical Data
1)
2)
Recommended range of input parameters for specified module functional performance.
Noise frequency is 1 kHz to fmax, where fmax is equal to the maximum data rate in units of MHz. E.g. for a
maximum data rate of 2700 Mbit/s, fmax = 2700 MHz. Power supply noise is defined with the recommended
filter in place at the supply side of the filtering circuit (see Figure 9 on Page 17).
The input stage can also be AC-coupled.
3)
4)
Input level diagram: see Figure 7 on Page 16.
5)
|VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|.
Skew between positive and negative inputs measured at 50% level.
20% - 80% level.
6)
7)
8)
Measured between 0.8 V and 2.0 V.
9)
I
out ≈ 10*1.15 V/Rexternal. Resistor Rexternal to be connected externally between REFR and VEE.
10)
11)
Output level diagram: see Figure 8 on Page 16.
|VOD| = Iout*(300 Ω || RLOAD). The output current range of 3 mA to 9 mA corresponds to |VOD| = 130 mV to 385 mV
for RLOAD = 50 Ω.
|VOD| = |(output voltage of non-inverted output minus output voltage of inverted output)|.
20% - 80% level. Non filtered values.
12)
mV
V
CC
|V
|
ID
500
Time
File: 3318
Figure 7
Input Level Diagram, DC-coupling
mV
V
+0.5
CCO
|V
|
OD
V
−1.8
CCO
Time
File: 3319
Figure 8
Output Level Diagram, DC-coupling
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Technical Data
Recommended Power Supply Filtering
A power supply filtering is recommended for the transmitter and the receiver module. A
possible filtering scheme is shown in Figure 9. The module signal and chassis ground
refer to a common ground plane, which can be contacted to the PCB ground by the
mounting screws (see Figure 17 “PCB Layout” on Page 28).
VCC
L1
VCC to PAROLI Tx or Rx Module
1 µH
C1
22 µF
C3
100 nF
C2
100 nF
File: 3330
Board Ground Plane
Figure 9
Filtering Scheme
Transmitter Module
VCC
Data In P
internal P
internal N
Rin/2
Rin/2
Data In N
VIN
> 6 kΩ
1.95 V
File: 3320
Figure 10
Transmitter - Input Stage
Data Sheet
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2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
Receiver Module
Out P
Out N
600 Ω
internal logic signal
Iout: 3 mA...9 mA
Iout
(adjust-
able)
max. high level = VCCO+0.5 V
min. low level = VCCO−1.8 V
VCCO: Paroli module supply
BGR
1.15 V
for output stage
Iout /10
~
REFR module pin
Rexternal (one setting applies to all outputs)
File: 3324
Figure 11
Receiver - CML Output Stage
Data Sheet
18
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
The electro-optical characteristics described in the following tables are valid only for use
under the recommended operating conditions.
Transmitter Electrical Characteristics
Parameter
Symbol
Values
typ.
Unit
min.
max.
450
1.6
Supply Current1)
Power Consumption1)
ICC
P
400
1.3
mA
W
Data Rate per Channel
DR
5002)
1250
0.4
Mbit/s
V
LVCMOS Output Voltage Low VLVCMOSOL
LVCMOS Output Voltage High VLVCMOSOH 2.5
V
LVCMOS Input Current
High/Low
ILVCMOSI
–100
100
µA
LVCMOS Output Current High3) ILVCMOSOH
LVCMOS Output Current Low4) ILVCMOSOL
0.5
4.0
120
mA
mA
Ω
Data Differential
RIN
80
100
Input Impedance5)
1)
Measured at the recommended case temperature of Tcase = 45°C. For Tcase = 0°C a decrease of approximately
10% and for Tcase = 80°C an increase of approximately 15% can be expected.
Specified for CID worst case pattern (disparity 72) or any pattern with a smaller disparity. The minimum data
2)
rate depends on the disparity of the used data pattern. For example, a regular clock signal (1-0 sequence) can
be transmitted down to a data rate as low as 1 Mbit/s.
Source current.
Sink current.
3)
4)
5)
Data input stage.
Data Sheet
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2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
Transmitter Electro-Optical Characteristics
Parameter
Symbol
Values
Unit
min.
typ.
max.
200
Optical Rise Time1)
tR
ps
Optical Fall Time1)
tF
200
ps
Total Jitter2), 3)
TJ
0.284
0.1
UI
Deterministic Jitter3), 4)
Channel-to-channel skew5)
Launched Average Power6)
Launched Power Shutdown
Center Wavelength7)
Spectral Width (rms)8)
Relative Intensity Noise9)
Extinction Ratio (dynamic)
DJ
UI
tCSK
PAVG
PSD
λC
100
ps
–8.0
830
–5.0
–3.0
–30.0
860
dBm
dBm
nm
nm
dB/Hz
dB
850
∆λ
0.35
0.65
–117
RIN
ER
OMA
6.0
0.1912)
Optical Modulation
Amplitude10), 11)
0.4613)
mW
Eye mask compliance
GBE
Electro-optical parameters valid for each channel and measured at the highest specified data rate.
All optical parameters are measured with a 62.5 µm multimode fiber.
1)
20% - 80% level, non filtered values.
2)
The Total Jitter (TJ) is composed of Random Jitter (RJ) and Deterministic Jitter (DJ) according to:
TJ = RJ (14 Sigma value) + DJ.
The TJ is specified at a BER of 10–12 from TP1 to TP2 according to IEEE 802.3, sec. 38.5.
The RJ is measured at the 50% level of the optical signal as the mean of the rising and falling edge
measurement value.
UI (Unit Interval) is equal to the length of one bit. For example, 2.72 Gbit/s corresponds to 368 ps.
The DJ consists of Duty Cycle Distortion and Data Dependent Jitter and is measured according to IEEE 802.3
using a K28.5 pattern.
With input channel-to-channel skew 0 ps and a maximum data channel-to-channel average deviation and
swing deviation of 5%.
The specified output power is compliant with IEC 60825-1, Amendment 2, Class 1M Accessible Emission
Limits (AEL).
3)
4)
5)
6)
7)
Wavelength is measured according to IEEE 802.3, sec. 38.6.1.
Spectral width is measured according to IEEE 802.3, sec. 38.6.1.
RIN is measured according to IEEE 802.3, sec. 38.6.4.
8)
9)
10)
11)
Peak to peak values.
OMA is defined as the difference of the optical high state (’1’) and the optical low state (’0’):
OMA = Popt(’1’) – Popt(’0’).
Corresponds to a minimum extinction ratio of 6 dB.
12)
13)
Corresponds to a typical extinction ratio of 8 dB.
Data Sheet
20
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
3.6 V
3.135 V
V
CC
2.0 V
0.8 V
−RESET
t
3
data valid
data invalid
Data
t
t
2
1
File: 3321
Figure 12
Timing Diagram
Parameter
Symbol
Values
typ.
Unit
min.
max.
50
–RESET on delay time
–RESET off delay time
–RESET low duration1)
t1
t2
t3
15
ms
ns
µs
100
500
10
1)
Only when not used as power on reset. At any failure recovery, –RESET must be brought to low level for at
least t3.
Data Sheet
21
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
Receiver Electrical Characteristics
Parameter
Symbol
Values
Unit
min.
typ.
max.
Supply Current1)
ICC
P
170
+15 Iout
200
+15 Iout
mA
Power Consumption1), 2)
0.7
0.9
W
Data Output Rise/Fall Time3)
tR-DO
,
250
ps
tF-DO
LVCMOS Output Voltage Low VLVCMOSOL
LVCMOS Output Voltage High VLVCMOSOH 2500
400
100
mV
mV
µA
LVCMOS Input Current
High/Low
ILVCMOSI
–100
LVCMOS OutputCurrent High4) ILVCMOSOH
LVCMOS OutputCurrent Low5) ILVCMOSOL
0.5
mA
mA
UI
4.0
Total Jitter6), 7), 8), 9), 10)
TJ
0.33
0.08
100
Deterministic Jitter6), 9), 11)
Channel-to-channel skew12)
DJ
tCSK
UI
ps
1)
Typical value is measured at Tcase = 45°C and 3.3 V, maximum value is measured at Tcase = 80°C and 3.6 V.
Calculated for Iout = 3 mA.
Measured between 20% and 80% level. Maximum value is related to a maximum RC load time constant of
2)
3)
t
RC = 150 ps.
4)
5)
6)
7)
8)
9)
10)
Source current.
Sink current.
With no optical input jitter.
Measured with an optical input power of 3 dB above minimum receiver sensitivity.
Unused channels shall be terminated by 50 Ω.
UI (Unit Interval) is equal to the length of one bit. For example, 2.72 Gbit/s corresponds to 368 ps.
The Total Jitter (TJ) is the sum from Random Jitter (RJ) and Deterministic Jitter (DJ) according to:
TJ = RJ (14 Sigma value) + DJ.
The TJ is specified at a BER of 10–12 from TP3 to TP4 according to IEEE 802.3, sec. 38.5.
The RJ is measured at the 50% level of the optical signal as the mean of the rising and falling edge RJ
measurement value.
11)
12)
The DJ consists of Duty Cycle Distortion and Data Dependent Jitter and is measured according to IEEE 802.3
using a K28.5 pattern.
With input channel-to-channel skew 0 ps.
Data Sheet
22
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
Receiver Electro-Optical Characteristics
Parameter
Symbol
Values
max.
Unit
min.
Data Rate Per Channel
DR
5001)
1250
Mbit/s
dBm
mW
Sensitivity (Average Power)2)
Optical Modulation Amplitude3)
Saturation (Average Power)5)
Signal Detect Assert Level6)
Signal Detect Deassert Level6)
Signal Detect Hysteresis6)
PIN
–16.0
OMA
PSAT
PSDA
PSDD
0.0304)
–2.0
dBm
dBm
dBm
dB
–17.0
4.0
–27.0
1.0
PSDA
–PSDD
Return Loss of Receiver 7)
ORL
12
dB
Electro-optical parameters valid for each channel and measured at the highest specified data rate.
All optical parameters are measured with a 62.5 µm multimode fiber.
1)
Specified for CID worst case pattern (disparity 72) or any pattern with a smaller disparity. The minimum data
rate depends on the disparity of the used data pattern. For example, a regular clock signal (1-0 sequence) can
be received down to a data rate as low as 6 Mbit/s.
Sensitivity is measured for BER = 10–12 with a Pseudo Random Bit sequence of length 223–1 (PRBS23) and a
test pattern source with RIN of –117 dB/Hz or better. Sensitivity is specified for the worst case extinction ratio
and maximum cross talk possibility. The maximum crosstalk possibility is defined as the “victim” receiver
channel operating at its sensitivity limit and the neighboring channels operating at 6 dB higher incident optical
power.
2)
3)
4)
5)
6)
Peak to peak value.
Corresponds to a maximum sensitivity (average power) of –16 dBm at an extinction ratio of 6 dB.
Saturation is specified with a Pseudo Random Bit sequence of length 223–1 (PRBS23) and ER ≥ 6 dB.
P
P
SDA: Average optical power when SD switches from inactive to active.
SDD: Average optical power when SD switches from active to inactive.
7)
Return loss is specified as the ration of the received optical power to the reflected optical power back into the
link fiber.
Data Sheet
23
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
Data Out 1, 12
Signal Detect 1
t2
t1
Signal Detect 12
File: 3325
2.0 V
Output Enable OEN
0.8 V
data valid
data valid
data Low
Data Out
t3
t4
File: 3326
Figure 13
Timing Diagrams
Parameter
Symbol
Values
Unit
min.
typ.
3
max.
10
Signal Detect Deassert Time
Signal Detect Assert Time
Output Enable off Delay Time
Output Enable on Delay Time
t1
t2
t3
t4
µs
µs
µs
µs
2
10
14
18
20
20
Data Sheet
24
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
VCC
2 x 50 Ω
Receiver Module
Out P
Out N
In P
In N
600 Ω
internal logic signal
Iout
(adjust-
able)
BGR
Iout /10
REFR module pin
Rexternal (one setting applies to all outputs)
File: 3327
Figure 14
Interfacing to CML
Data Sheet
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2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
VCC
2 x 300 Ω
In P
Receiver Module
Out P
Out N
100 Ω
In N
600 Ω
internal logic signal
Iout
(adjust-
able)
BGR
Iout /10
REFR module pin
Rexternal (one setting applies to all outputs)
File: 3328
VCC
2 x 75 Ω
Receiver Module
Out P
In P
In N
600 Ω
Out N
2 x 150 Ω
internal logic signal
Iout
(adjust-
able)
BGR
Iout /10
REFR module pin
Rexternal (one setting applies to all outputs)
File: 3329
Figure 15
Interfacing to LVPECL
Data Sheet
26
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
Host Face-Plate Layout for Panel Accessed Modules
F1
F2
F6
F3
F4
F9
F10
F11
F7
F12
F8
F5
File: 3507
Figure 16
Key
Values
typ.
Unit
Comments
min.
max.
F1
F2
F3
F4
18.42 20
mm
mm
mm
mm
Cutout center spacing
Cutout width
16.7
9.1
16.8
16.9
9.3
9.2
Cutout height
4.42
4.52
4.62
Center of cutout and center of receptacle to
top of PCB
F5
44.5
46
1
mm
mm
mm
mm
mm
mm
Face-plate placement
F6
Radius
F7
4.25
16.8
Opt. reference plane to top of PCB
Limitation for PCB length
Length of receptacle
F8
38
F9
F10
F11
F12
15.3
7.6
Including shield, without spring contacts
Including shield, without spring contacts
1.7
mm
See Package Outlines Figure 18 on
Page 31
Data Sheet
27
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
Dimensions in mm
File: 3508
Figure 17
PCB Layout
1. Figure 17 describes the recommended customer board layout for the PAROLI 2
modules.
2. The holes for the screwing leads and ground plates must be tied to signal ground.
3. Modules must be screwed on the 4 indicated positions (tightening torque should be
typically 10 cNm).
4. Screw size for PCB or heat sink mounting = M1.6.
5. Screw length (PCB mounting) = PCB thickness + 5.2–0.5 mm.
6. Screw length (heat sink mounting) = heat sink thickness + 3.1–0.5 mm.
7. Modules can be mounted directly side by side.
8. The dashed lines in Figure 17 indicate the typical keep out area for straight MPO
connectors as well as for the module MPO receptacle in case of central board
placement of the module.
Data Sheet
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2003-11-19
V23832-T2531-M101
V23832-R511-M101
Technical Data
Thermal Characteristics
The thermal behaviour of PAROLI modules (transmitter and receiver) depends on the
operating conditions for different applications.
The following table gives a guideline for system designers.
Tcase – Tambient
The thermal resistance Rth (Rth = ------------------------------------------ ; Pel = electrical power consumption)
Pel
can be used for calculating the module case temperature under different operating
conditions and is displayed for two different module options:
a) Baseplate module without heat sink.
b) Baseplate module with customer designed heat sink
(e.g. height = 9 mm, length = 41 mm, width = 18 mm, no. of cooling fins = 9).
Air Velocity1)
0 m/s
23.3
1.5 m/s
10.3
3 m/s
8.6
4 m/s
7.5
Unit
K/W
K/W
Rth - Option a)
Rth - Option b)
20.0
5.2
4.2
4.0
1)
The air velocity is applied along the shortest side of the module in parallel to the direction of the heat sinks.
Link Length
The link length calculations are based on the most conservative assumption of PAROLI
modules working on their worst case specification limits. Multimode fibers of different
types (modal bandwidth at 850 nm) are shown. The stated link length is valid under all
specified operating conditions and includes 2 dB of additional connector loss.
Fiber Type Diameter Modal Bandwidth Link Distance
Link Distance
at 1.25 Gbit/s
[m]
Core/Cladding
at 0.5 Gbit/s
[µm]
[MHz*km]
200
[m]
62.5 / 125
62.5 / 125
850
360
640
400
1300
Data Sheet
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V23832-T2531-M101
V23832-R511-M101
Technical Data
Channel Description
Transmitter Module
(front view as looking into the MPO connector receptacle of the module)
Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1
Host PCB below
Receiver Module
(front view as looking into the MPO connector receptacle of the module)
Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1
Host PCB below
The MPO connector provides a keying functionality, which requires a 180 degree twist
of fiber cable, if used as a direct connection between transmitter and receiver module.
(For example the transmitter channel 1 is directly connected to the receiver cannel 1).
Handling Instructions
Washing Process
The PAROLI mating BGA connector can be handled according to standard industry
wave solder, hand solder and washing processes.
The PAROLI modules shall not be washed, due to possible influence on module
performance.
Dust Cover
The optical connector is provided with a dust cover, which protects the optical interface
from potential damage and contamination from dust during handling. The dust cover
should always remain in the module, when no connector is used.
Data Sheet
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2003-11-19
V23832-T2531-M101
V23832-R511-M101
Package Outlines
Package Outlines
PAROLI 2 Tx
Temperature Reference Point
on top of the module
PAROLI 2 Rx
Temperature Reference Point
on top of the module
Typical module mass approximately 10.4 grams
The front collar EMI shield is electrically separated from module signal ground
Dimensions in mm
File: 3203
Figure 18
Data Sheet
31
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Ordering Information
Ordering Information
Part Number
Description
V23832-T2531-M101
PAROLI Transmitter, 12 x 1.25 Gbit/s,
multistandard electrical interface
V23832-T2131-M101
V23832-T2431-M101
V23832-T2331-M101
V23832-R521-M101
V23832-R121-M101
V23832-R421-M101
V23832-R321-M101
V23832-R511-M101
V23832-R111-M101
V23832-R411-M101
V23832-R311-M101
PAROLI Transmitter, 12 x 1.6 Gbit/s,
multistandard electrical interface
PAROLI Transmitter, 12 x 2.7 Gbit/s,
multistandard electrical interface
PAROLI Transmitter, 12 x 3.125 Gbit/s,
multistandard electrical interface
PAROLI Receiver, 12 x 1.25 Gbit/s,
LVDS electrical interface
PAROLI Receiver, 12 x 1.6 Gbit/s,
LVDS electrical interface
PAROLI Receiver, 12 x 2.7 Gbit/s,
LVDS electrical interface
PAROLI Receiver, 12 x 3.125 Gbit/s,
LVDS electrical interface
PAROLI Receiver, 12 x 1.25 Gbit/s,
CML electrical interface
PAROLI Receiver, 12 x 1.6 Gbit/s,
CML electrical interface
PAROLI Receiver, 12 x 2.7 Gbit/s,
CML electrical interface
PAROLI Receiver, 12 x 3.125 Gbit/s,
CML electrical interface
Data Sheet
32
2003-11-19
V23832-T2531-M101
V23832-R511-M101
Revision History:
2003-11-19
DS2
Previous Version:
2003-05-21
Page
Subjects (major changes since last revision)
Document completely revised
Edition 2003-11-19
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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