XMC7100-F144K4160AA_技术文档

XMC7100

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

General description

XMC7100 is a family of XMC7000 microcontrollers targeted at industrial applications. XMC7100 has one or two

Arm® Cortex®-M7 CPUs for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and security

processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data

rate (CAN FD) and Ethernet. XMC7000 devices are manufactured on an advanced 40-nm process. XMC7100

incorporates Infineon's low-power flash memory, multiple high-performance analog and digital peripherals, and

enables the creation of a secure computing platform.

Features

• CPU subsystem

- One or two^[1]250-MHz 32-bit Arm® Cortex®-M7 CPUs, each with

• Single-cycle multiply

• Single/double-precision floating point unit (FPU)

• 16-KB data cache, 16-KB instruction cache

• Memory Protection Unit (MPU)

• 16-KB instruction and 16-KB data Tightly-Coupled Memories (TCM)

- 100-MHz 32-bit Arm® Cortex® M0+ CPU with

• Single-cycle multiply

• MPU

- Inter-processor communication in hardware

- Three DMA controllers

• Peripheral DMA controller #0 (P-DMA0, DW0) with 100 channels

• Peripheral DMA controller #1 (P-DMA1, DW1) with 58 channels

• Memory DMA controller (M-DMA0, DMAC0) with 8 channels

• Integrated memories

- Up to 4160 KB of code-flash with an additional up to 256 KB of work-flash

• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it

• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

• Flash programming through SWD/JTAG interface

- Up to 768 KB of SRAM with selectable retention granularity

• Cryptography engine

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

• Using digital signature verification

• Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES: 64-bit blocks, 64-bit key

- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve

(ECC)

- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

Note

1. For more information, refer to Ordering information.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Features

• Safety for application

- Memory Protection Unit (MPU)

- Shared Memory Protection Unit (SMPU)

- Peripheral Protection Unit (PPU)

- Watchdog Timer (WDT)

- Multi-Counter Watchdog Timer (MCWDT)

- Low-Voltage Detector (LVD)

- Brown-Out Detection (BOD)

- Overvoltage Detection (OVD)

- Clock Supervisor (CSV)

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)

• Low-power 2.7-V to 5.5-V operation

- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power

management

- Configurable options for robust BOD

• Two threshold levels (2.7 V and 3.0 V) for BOD on V_DDDand V_DDA

• One threshold level (1.1 V) for BOD on V_CCD

• Wakeup

- Up to two pins to wake from Hibernate mode

- Up to 220 GPIO pins to wake from Sleep modes

- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes

• Clocks

- Internal Main Oscillator (IMO)

- Internal Low-Speed Oscillator (ILO)

- External Crystal Oscillator (ECO)

- Watch Crystal Oscillator (WCO)

- Phase-Locked Loop (PLL)

- Frequency-Locked Loop (FLL)

• Communication interfaces

- Up to eight CAN FD channels

• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and

transceivers

• Compliant with ISO 11898-1:2015

• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD

• ISO 16845:2015 certificate available

- Up to 11 runtime-reconfigurable serial communication block (SCB) channels, each configurable as I²C, SPI,

or UART

- One 10/100 Mbps Ethernet MAC interface conforming to IEEE-802.3bw

• Supports the following PHY interfaces:

Media-independent interface (MII)

Reduced media-independent interface (RMII)

• Compliant with IEEE-802.1BA Audio Video Bridging (AVB)

• Compliant with IEEE-1588 Precision Time Protocol (PTP)

• External memory interface

- One SPI (Single, Dual, Quad, or Octal) or HYPERBUS™ interface

- On-the-fly encryption and decryption

- Execute-In-Place (XIP) from external memory

Datasheet

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Features

• SDHC interface

- One Secure Digital High Capacity (SDHC) interface supporting embedded MultiMediaCard (eMMC), Secure

Digital (SD), or Secure Digital Input Output (SDIO)

• Compliant with eMMC 5.1, SD 6.0, and SDIO 4.10 specifications

- Data rates up to SD High Speed 50 MHz, or eMMC 52-MHz DDR

• Audio interface

- Three Inter-IC Sound (I²S) Interface for connecting digital audio devices

- I²S, left justified, or Time Division Multiplexed (TDM) audio formats

- Independent transmit or receive operation, each in master or slave mode

• Timers

- Up to 75 16-bit and eight 32-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks

• Up to 12 16-bit counters for motor control

• Up to 63 16-bit counters and eight 32-bit counters for regular operations

• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time

(PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes

- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,

and so on)

• Real time clock (RTC)

- Year/Month/Date, Day-of-week, Hour:Minute:Second fields

- 12- and 24-hour formats

- Automatic leap-year correction

• I/O

- Up to 220 programmable I/Os

- Three I/O types

• GPIO Standard (GPIO_STD)

• GPIO Enhanced (GPIO_ENH)

• High-Speed I/O Standard (HSIO_STD)

• Regulators

- Generate a 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply

- Three regulators:

• DeepSleep

• Core internal

• Core external

• Programmable analog

- Three SAR A/D converters with up to 75 external channels (72 I/Os + 3 I/Os for motor control)

• ADC0 supports 32 logical channels, with 32 + 1 physical connections

• ADC1 supports 32 logical channels, with 32 + 1 physical connections

• ADC2 supports 8 logical channels, with 8 + 1 physical connections

• Any external channel can be connected to any logical channel in the respective SAR

- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps

- Each ADC also supports six internal analog inputs like

• Bandgap reference to establish absolute voltage levels

• Calibrated diode for junction temperature calculations

• Two AMUXBUS inputs and two direct connections to monitor supply levels

- Each ADC supports addressing of external multiplexers

- Each ADC has a sequencer supporting autonomous scanning of configured channels

- Synchronized sampling of all ADCs for motor-sense applications

Datasheet

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Features

• Smart I/O

- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os

- Up to 36 I/Os (GPIO_STD) supported

• Debug interface

- JTAG controller and interface compliant to IEEE-1149.1-2001

- Arm® Serial Wire Debug (SWD) port

- Supports Arm® Embedded Trace Macrocell (ETM) Trace

• Data trace using SWD

• Instruction and data trace using JTAG

• Industry advanced development tools

- Infineon IDE ModusToolbox™ software for code development and debugging

• Packages

- 100-TEQFP, 14 × 14 × 1.6 mm (max), 0.5-mm lead pitch

- 144-TEQFP, 20 × 20 × 1.6 mm (max), 0.5-mm lead pitch

- 176-TEQFP, 24 × 24 × 1.6 mm (max), 0.5-mm lead pitch

- 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch

Datasheet

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Table of contents

General description ...........................................................................................................................1

Features ...........................................................................................................................................1

Table of contents...............................................................................................................................5

Features list..................................................................................................................................... 6

Communication peripheral instance list.................................................................................................................... 8

Blocks and functionality ................................................................................................................... 9

Architecture block diagram......................................................................................................................................... 9

Functional description.................................................................................................................... 10

CPU subsystem .......................................................................................................................................................... 10

System resources....................................................................................................................................................... 11

Peripherals................................................................................................................................................................. 15

I/Os ............................................................................................................................................................................. 18

XMC7100 address map .................................................................................................................... 21

Flash base address map .................................................................................................................. 23

Peripheral I/O map ......................................................................................................................... 25

XMC7100 clock diagram .................................................................................................................. 27

XMC7100 CPU start-up sequence ..................................................................................................... 28

Pin assignment .............................................................................................................................. 29

High-speed I/O matrix connections .................................................................................................. 36

Package pin list and alternate functions........................................................................................... 37

Power pin assignments................................................................................................................... 45

Alternate function pin assignments ................................................................................................. 46

Pin function description............................................................................................................................................ 54

Interrupts and wake-up assignments............................................................................................... 57

Core interrupt types ....................................................................................................................... 67

Trigger multiplexer ........................................................................................................................ 68

Triggers group inputs ..................................................................................................................... 70

Triggers group outputs ................................................................................................................... 74

Triggers one-to-one........................................................................................................................ 75

Peripheral clocks............................................................................................................................ 79

Faults............................................................................................................................................ 82

Peripheral protection unit fixed structure pairs................................................................................ 85

Bus masters ................................................................................................................................... 98

Miscellaneous configuration ........................................................................................................... 99

Development support................................................................................................................... 101

Documentation........................................................................................................................................................ 101

Tools......................................................................................................................................................................... 101

Electrical specifications ................................................................................................................ 102

Absolute maximum ratings ..................................................................................................................................... 102

Device-level specifications...................................................................................................................................... 108

Smoothing capacitor recommendations ............................................................................................................... 109

DC specifications ..................................................................................................................................................... 110

Reset specifications................................................................................................................................................. 115

I/O ............................................................................................................................................................................. 116

Analog peripherals................................................................................................................................................... 122

26.8 AC specifications...............................................................................................................................................128

Digital peripherals ................................................................................................................................................... 129

Memory .................................................................................................................................................................... 139

System resources..................................................................................................................................................... 141

Clock specifications................................................................................................................................................. 154

Clock timing diagrams........................................................................................................................................... 160

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Table of contents

Ethernet specifications............................................................................................................................................ 162

SDHC specifications................................................................................................................................................. 165

Audio subsystem specifications.............................................................................................................................. 170

Serial memory interface specifications.................................................................................................................. 175

Ordering information ................................................................................................................... 182

Part number nomenclature .................................................................................................................................... 182

Packaging.................................................................................................................................... 183

Appendix ..................................................................................................................................... 188

Bootloading or end-of-line (EoL) programming .................................................................................................... 188

External IP revisions ................................................................................................................................................ 189

Acronyms .................................................................................................................................... 190

Errata.......................................................................................................................................... 192

Revision History ............................................................................................................................ 195

Datasheet

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Features list

1

Features list

Table 1-1

XMC7100 feature list for all packages

Packages

144-TEQFP 176-TEQFP

Features

100-TEQFP

272-BGA

CPU

Core

One or two 32-bit Arm® Cortex®-M7 CPUs and a 32-bit Arm® Cortex® M0+ CPU

2.7 V to 5.5 V

Operating voltage

Operating voltage for HSIO_STD

Core voltage

Not supported

1.05 V to 1.15 V

2.7 V to 3.6 V

Arm® Cortex®-M7 250 MHz (max for each) and Arm® Cortex®-M0+ 100 MHz

Operating frequency

(max)

MPU, PPU

FPU

DSP-MUL/DIV/MAC

TCM

Supported

Supports both single (32-bit) and double (64-bit) precision

Supported by Arm® Cortex®-M7 CPUs

16-KB instruction and 16-KB data for each Cortex®-M7 CPU

Memory

1088 KB (960 KB + 128 KB) / 2112 KB (1984 KB + 128 KB) / 4160 KB (4032 KB +

128 KB)^[2]

Code-flash

Work-flash

SRAM (configurable for retention)

ROM

128 KB (96 KB + 32 KB) / 256 KB (192 KB + 64 KB)^[2]

192 KB / 384 KB / 768 KB^[2]

64 KB

Communication Interfaces

CAN0 (CAN-FD: Up to 8 Mbps)

CAN1 (CAN-FD: Up to 8 Mbps)

CAN RAM

4 ch

4^[3]/3^[4]ch

4 ch

32 KB per instance (CAN0/1), 64 KB in total

Serial Communication Block

9 ch

9^[5]/8^[6]ch

8 ch

10 ch

11 ch

(SCB/UART)

Serial Communication Block

(SCB/I²C)

Serial Communication Block

10 ch

(SCB/SPI)

Ethernet MAC

1 ch × 10/100 (ETH0, MII/RMII on GPIO_STD)

Memory Interfaces

1 ch

(HSIO_STD at

50 MHz,

1 ch (GPIO_STD at 32 MHz)

eMMC/SD

GPIO_STD at

32 MHz)

1 ch

(HSIO_STD at

100 MHz,

Single SPI / Dual SPI / Quad SPI /

Octal SPI / HYPERBUS™

GPIO_STD at

32 MHz)

Timers

RTC

1 ch

12 ch

63 ch

8 ch

TCPWM (16-bit) (Motor Control)

TCPWM (16-bit)

TCPWM (32-bit)

External Interrupts

72

116

148

220

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XMC7000 microcontroller

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Features list

Table 1-1

Analog

XMC7100 feature list for all packages ^(continued)

Packages

144-TEQFP 176-TEQFP

Features

100-TEQFP

272-BGA

3 Units (SAR0/32, SAR1/32, SAR2/8 logical channels)

37 external

52 external

64 external

72 external

channels(SAR0/14 channels(SAR0/21 channels(SAR0/24

channels

12-bit, 1 Msps SAR ADC

ch,

(SAR0/32 ch,

SAR1/32 ch,

SAR2/8 ch)

SAR1/15 ch,

SAR2/8 ch)

SAR1/23 ch,

SAR1/32 ch,

SAR2/8 ch)

18 ch (6 per ADC) Internal sampling

Motor control input

Security

3 ch (synchronous sampling of one channel on each of the 3 ADCs)

Supported

Flash Security (program/work

read protection)

Flash chip erase enable

eSHE / HSM

Audio

Configurable

By separate firmware^[7]

I²S / TDM

Tx 2 ch, Rx 2 ch

Tx 3 ch, Rx 3 ch

System

P-DMA0 with 100 channels (16 general-purpose), P-DMA1 with 58 channels

(8 general-purpose), and M-DMA0 with 8 channels

DMA Controller

Internal main oscillator

8 MHz

Internal low speed oscillator

32.768 kHz (nominal)

PLL

FLL

Input: 3.988 to 33.34 MHz, PLL output: up to 250 MHz

Input: 0.25 to 80 MHz, FLL output: up to 100 MHz

Watchdog Timer and

Supported

Multi-counter Watchdog Timer

Clock Supervisor

Cyclic wakeup from DeepSleep

GPIO_STD

GPIO_ENH

HSIO_STD

Supported

68

112

144

203

13

4

Not supported

3 blocks, mapped 5 blocks, mapped

Smart I/O (Blocks)

5 blocks, mapped through 36 I/Os

through 15 I/Os through 27 I/Os

Low-voltage detect

Maximum Ambient Temperature

Debug Interface

Two, 26 selectable levels

125 °C

SWD/JTAG

Debug Trace

Arm® Cortex®-M7 ETB size of 8 KB, Arm® Cortex® M0+ MTB size of 4 KB

Notes

2. For more information, refer to Ordering Information.

3. Function EXT_PS_CTL0 on P22.1 is not used.

4. Function EXT_PS_CTL0 on P22.1 is used.

5. Functions EXT_PS_CTL0 on P21.1 and EXT_PS_CTL1 on P21.2 are not used.

6. Function EXT_PS_CTL0 on P21.1 or EXT_PS_CTL1 on P21.2 is used.

7. Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.

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XMC7000 microcontroller

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Features list

1.1

Communication peripheral instance list

The following table lists the instances supported under each package for communication peripherals, based on

the minimum pins needed for the functionality.

Table 1-2

Communication peripheral instance list

Module

CAN0

CAN1

100-TEQFP

144-TEQFP

0/1/2/3

176-TEQFP

0/1/2/3

272-BGA

0/1/2/3

Minimum pin functions

TX, RX

0/1/2/3

0/1/2/3^[3]or

0/2/3^[4]

SCB/UAR

T

SCB/I2C

0 to 8

0 to 9

0 to 10

TX, RX

0 to 8^[5]or

SCL, SDA

0/1/2/3/4/5/7/8^[6]

SCB/SPI

0/1/2/3/4/5/7/8

MISO, MOSI, SCK, SELECT0

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Blocks and functionality

2

Blocks and functionality

2.1

Architecture block diagram

ITCM

16 KB

DTCM

16 KB

DTCM

CPU Subsystem

ITCM

16 KB

SWJ/ETM/ITM/CTI

XMC7100

MXS40-HT

16 KB

SWJ/MTB/CTI

Cortex M7

350 MHz

SRAM0

Up to

512KB

SRAM1

Up to

256KB

eCT Flash

Crypto

Arm Cortex M7

ROM

64KB

Arm

Cortex M0+

100 MHz

Up to 4160 KB Code-Flash

+ Up to 256 KB Work-Flash

AES,SHA,CRC,

TRNG,RSA,ECC

250 MHz

D$

I$

FPU

(SP/DP)

16KB

AHBS

16KB

_ND_VI$_{C, MPU, AX}I_I$

16KB

FPU

AHBP

(SP/DP)

SRAM

Controller

SRAM

Controller

8 KB $

Flash Controller

System Resources

Initiator/MMIO

ROM Controller

NVIC, MPU, AXI

AHBP

AHBS

MUL, NVIC, MPU

Power

Sleep Control

POR

OVD

BOD

LVD

System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU)

Peripheral Interconnect (MMIO,PPU)

REF

PWRSYS-HT

LDO

PCLK

Clock

Clock Control

3x MCWDT

Prog.

Analog

2xILO

IMO

WDT

ECO

CSV

FLL

SAR

ADC

(12-bit)

4xPLL

Reset

Reset Control

XRES

Test

TestMode Entry

Digital DFT

x3

Analog DFT

SARMUX

72 ch

WCO

RTC

Power Modes

High Speed I/O Matrix, Smart I/O, Boundary Scan

5x Smart I/O

Active/Sleep

LowePowerActive/Sleep

Up to 203x GPIO_STD, 4x GPIO_ENH, Up to 13x HSIO_STD

DeepSleep

Hibernate

IO Subsystem

The Architecture block diagram shows a simplified view of the interconnection between subsystems and

blocks. XMC7100 has four major subsystems: CPU, system resources, peripherals, and I/O^{[8, 9, 10]}. The

color-coding shows the lowest power mode where the particular block is still functional.

XMC7100 provides extensive support for programming, testing, debugging, and tracing of both hardware and

firmware.

Debug-on-chip functionality enables in-system debugging using the production device. It does not require

special interfaces, debugging pods, simulators, or emulators.

The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet and J-Link.

The debug circuits are enabled by default.

XMC7100 provides a high level of security with robust flash protection and the ability to disable features such as

debug.

Additionally, each device interface can be permanently disabled for applications concerned with phishing

attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash

programming sequences. All programming, debug, and test interfaces are disabled when maximum device

security is enabled.

Notes

8. GPIO_STD supports 2.7 V to 5.5 V V_DDIOrange.

9. GPIO_ENH supports 2.7 V to 5.5 V V_DDIOrange with higher currents at lower voltages.

10.HSIO_STD supports 2.7 V to 3.6 V V_DDIOrange with high-speed signalling and programmable drive strength.

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32-bit Arm® Cortex®-M7

Functional description

3

Functional description

3.1

CPU subsystem

3.1.1

CPU

The XMC7100 CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and one or two 32-bit

Arm® Cortex®-M7 CPUs, each with MPU, single/double-precision FPU, and 16-KB data and instruction caches. This

subsystem also includes P-/M-DMA controllers, a cryptographic accelerator, up to 4160 KB of code-flash, up to

256 KB of work-flash, up to 768 KB of SRAM, and 64 KB of ROM.

The Cortex-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following

completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,

SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by

an inter-processor communication (IPC) mechanism using hardware semaphores.

Each Cortex-M7 CPU has 16 KB of instruction and 16 KB of data TCM with programmable read wait states. Each

TCM is clocked by the associated Cortex-M7 CPU clock.

3.1.2

DMA controllers

XMC7100 has three DMA controllers: P-DMA0 with 16 general-purpose and 84 dedicated channels, P-DMA1 with 8

general-purpose and 50 dedicated channels, and M-DMA0 with eight channels. P-DMA is used for

peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of

channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.

General-purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables

demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)

to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high

memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each

channel. They support independent accesses to peripherals using the AHB multi-layer bus.

3.1.3

Flash

XMC7100 has 1088 KB (960 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size), 2112 KB (1984 KB

with a 32-KB sector size, and 128 KB with an 8-KB sector size) or 4160 KB (4032 KB with a 32-KB sector size, and

128 KB with an 8-KB sector size) of code-flash with an additional work-flash of 128 KB (96 KB with a 2-KB sector

size, and 32 KB with a 128-B sector size) or 256 KB (192 KB with a 2-KB sector size, and 64 KB with a 128-B sector

size). Work-flash is optimized for reprogramming many more times than code-flash. Code-flash supports

Read-While-Write (RWW) operation allowing flash to be updated while the CPU is active. Both the code-flash and

work-flash areas support dual-bank operation for over-the-air (OTA) programming.

3.1.4

SRAM

XMC7100 has up to 768 KB of SRAM with two independent controllers. SRAM0 provides DeepSleep retention in

32-KB increments while SRAM1 is selectable between fully retained and not retained.

3.1.5

ROM

XMC7100 has 64 KB of ROM that contains boot and configuration routines. This ROM enables secure boot and

authentication of user flash to guarantee a secure system.

3.1.6

Cryptography accelerator for security

The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy

check, pseudo random number generation, true random number generation, galois/counter mode, and a vector

unit to support asymmetric key cryptography such as RSA and ECC.

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Functional description

3.2

System resources

Power system

3.2.1

The power system ensures that the supply voltage levels meet the requirements of each power mode, and

provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip

reset during the initial power ramp.

Three BOD circuits monitor the external supply voltages (V_DDD, V_DDA, V_CCD). The BOD on V_DDDand V_CCDis initially

enabled and cannot be disabled. The BOD on V_DDAis initially disabled and can be enabled by the user. For the

external supplies V_DDDand V_DDA, BOD circuits are software-configurable with two settings; a 2.7-V minimum

voltage that is robust for all internal signaling, and a 3.0-V minimum voltage, which is also robust for all I/O

specifications (which are guaranteed at 2.7 V). The BOD on V_CCDis provided as a safety measure and is not a

robust detector.

Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (V_DDD, V_DDA, V_CCD), and

overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on V_DDDand

V_DDAare configurable with two settings; a 5.0-V and 5.5-V maximum voltage.

Two voltage detection circuits are provided to monitor the external supply voltage (V_DDD) for falling and rising

levels, each configurable for one of the 26 selectable levels.

All BOD, OVD, and OCD circuits on V_DDDand V_CCDgenerate a reset, because these protect the CPUs and fault logic.

The BOD and OVD circuits on V_DDAcan be configured to generate either a reset, or a fault.

3.2.2

Regulators

XMC7100 contains three regulators that provide power to the low-voltage core transistors: DeepSleep, core

internal, and core external. These regulators accept a 2.7-V to 5.5-V V_DDDsupply and provide a low-noise 1.1-V

supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and

firmware when switching between power modes. The core internal and core external regulators operate in Active

mode, and provide power to the CPU subsystem and associated peripherals.

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Functional description

3.2.2.1

DeepSleep

The DeepSleep regulator is used to maintain power in a small number of blocks when in DeepSleep mode.

These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other

configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal

regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is

disabled.

3.2.2.2

Core internal

The core internal regulator supports load currents up to 280 mA, and is operational during device start-up

(boot process), and in Active/Sleep modes.

3.2.2.3

Core external^[11]

To support worst-case loading, with both M7 CPUs and the M0+ CPU at their maximum clock frequency and all

integrated peripherals operating, a core external regulator is required, capable of load currents up to 600 mA.

While the control and monitor circuits for the core external regulator are internal to XMC7100, the power

regulating element (NPN pass transistor, PMIC, or LDO) is external. This reduces the overall power dissipation

within the XMC7100 package, while maintaining a well-regulated core supply.

The core external regulator may be implemented with either an external NPN pass transistor, PMIC, or linear

regulator (LDO). Each implementation requires different external components on the PCB, and different

connections to XMC7100 for both regulation and control.

Vpwr

(2.7-5.5V)

10 uF

XMC7000

V_DDD

NPN transistor

Emitter Follower

ZXT849K

etc

DRV_VOUT

EXT_PS_CTL0

0.1Ω

1/4W

1%

EXT_PS_CTL1

Core supply rail

V_CCD

C_S1

Figure 3-4

Sample core external regulator with NPN transistor

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Functional description

2.7V – 5.5V Power rail

V_DDD

Vin

Core supply rail

Switching node

V_CCD

XMC7000

External

PMIC

C_S1

R1

R2

Enable

(EN)

Feedback

(FB)

DRV_VOUT

V_DDDor

EXT_PS_CTL1

Power Good

(PG)

EXT_PS_CTL0

EXT_PS_CTL1

- PMIC EN pin polarity is HIGH for enable. PMIC PG pin polarity is HIGH for power good.

- If EN pin of PMIC does not have the internal pull-down resistor, an external pull-down resistor must be placed to keep the PMIC disabled during power-on reset.

- See the Traveo II device datasheet for C_S1

.

- Output voltage setting resistors (R1, R2) are needed according to the selected PMIC.

Figure 3-5

Sample core external regulator with PMIC/LDO

Both the core internal and core external regulators require an external bulk storage capacitor connected to the

VCCD pin. This capacitor provides charge under the dynamic loads of the low-voltage core transistors.

3.2.3

Clock system

The XMC7100 clock system provides clocks to all subsystems that require them, and glitch-free switching

between different clock sources. In addition, the clock system ensures that no metastable conditions occur.

The clock system for XMC7100 consists of the 8-MHz IMO, two ILOs, four watchdog timers, four PLLs, an FLL, five

clock supervisors (CSV), a 8- to 33.34-MHz ECO, and a 32.768-kHz WCO.

The clock system supports three main clock domains: CLK_HF, CLK_SLOW, and CLK_LF.

• CLK_HFx are the Active mode clocks. Each can use any of the high-frequency clock sources including IMO,

EXT_CLK, ECO, FLL, or PLL

• CLK_SLOW provides a reference clock for the Cortex-CM0+ CPU, Crypto, P-/M-DMA, and other slow infrastructure

blocks of CPU subsystem

• CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The

reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO.

Note

11.When XMC7100 is in Hibernate mode, the GPIO used to control the core external regulator are High-Z. This may

require an external pull-up or pull-down resistor to disable the external regulator and configure it for minimum

operating current.

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Functional description

Table 3-1

CLK_HF destinations

Description

CPUSS (Memories, CLK_SLOW, Peripherals)

CPUSS (Cortex-M7 CPU 0, 1)

CAN FD, TCPWM, SCB, SAR

Event Generator

Ethernet

Audio Subsystem (I²S)

SDHC Interface, SMIF

Name

CLK_HF0

CLK_HF1

CLK_HF2

CLK_HF3

CLK_HF4

CLK_HF5

CLK_HF6

3.2.3.6

IMO clock source

The IMO is the frequency reference in XMC7100 when no external reference is available or enabled. The IMO

operates at a frequency of around 8 MHz.

3.2.3.7

ILO clock source

An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in

DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven

counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-

vision.

3.2.3.8

PLL and FLL

A PLL (one of the two 200 MHz and two 400 MHz) or FLL may be used to generate high-speed clocks from the IMO,

ECO, or an EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of 45 µs) in exchange for a

small amount (±2%) of frequency error^[12]. A 400-MHz PLL supports spread spectrum clock generation (SSCG)

with down spreading.

3.2.3.9

Clock supervisor

Each clock supervisor (CSV) allows one clock (reference) to supervise the behavior of another clock (monitored).

Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the

frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the

frequency-range comparator detects a stopped clock or a clock outside the specified frequency range, an

abnormal state is signaled and either a reset or an interrupt is generated.

3.2.3.10

EXT_CLK

One of the three GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be

used as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.

3.2.3.11

ECO

The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.

It supports fundamental mode (non-overtone) quartz crystals, in the range of 8 to 33.34 MHz. When used in

conjunction with the PLL, it generates CPU and peripheral clocks up to the device’s maximum frequency. ECO

accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the

available I/O functions.

Note

12.Operation of reference-timed peripherals (such as a UART) with an FLL-based reference is not recommended

due the allowed frequency error.

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Functional description

3.2.3.12

WCO

The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external

32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock

reference for CLK_LF, which is the clock source for the MCWDT and RTC.

3.2.4

Reset

XMC7100 can be reset from a variety of sources, including software. Most reset events are asynchronous and

guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT,

software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and

allows software to determine the cause of the reset. An XRES_L pin is available for external reset.

3.2.5

Watchdog timer

XMC7100 has one watchdog timer (WDT) and three multi-counter watchdog timers (MCWDT).

The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from

Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT

timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause

register.

An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are

only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used

separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.

3.2.6

Power modes

XMC7100 has six power modes.

• Active – all peripherals are available

• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are

available, but with limited capability

• Sleep – all peripherals except the CPUs are available

• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are

available, but with limited capability

• DeepSleep – only peripherals which work with CLK_LF are available

• Hibernate – the device and I/Os are frozen, the device resets on wakeup

3.3

Peripherals

3.3.1

Peripheral clock dividers

Integer and fractional clock dividers are provided for peripheral and timing purposes.

Table 3-1 Clock Dividers - CPUSS Group (Nr. 0)

Divider Type

Instances

Description

div_8

div_16

3

1

Integer divider, 8 bits

Integer divider, 16 bits

Table 3-2

Clock Dividers - COMM Group (Nr. 1)

Divider Type

Instances

Description

div_8

div_16

div_24_5

16

17

16

Integer divider, 8 bits

Integer divider, 16 bits

Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Functional description

3.3.2

Peripheral protection unit

The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU,

P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the

bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address

range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).

3.3.3

12-bit SAR ADC

XMC7100 contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit

result in 26 clock cycles. The references for all three SAR ADCs come from a dedicated pair of inputs: VREFH and

VREFL^[13]

.

XMC7100 supports up to 93 logical ADC channels, and external inputs from up to 75 I/Os. Each ADC also supports

six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC and

package type) are listed in Table 1-1.

Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with

zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1

Msps whether it is for a single channel or distributed over several channels). The sequencer switching is

controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the

appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates

subsequent conversions for repetitive or group conversions without CPU intervention.

Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32

GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal

signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports

synchronous sampling of one motor-sense channel on each of the three ADCs.

XMC7100 has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be

sampled by one ADC at a time. Software post-processing is required to convert the temperature sensor reading

into kelvin or Celsius values.

To accommodate signals with varying source impedances and frequencies, it is possible to have different sample

times programmed for each channel. Each ADC also supports range comparison, which allows fast detection of

out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate

the measurement for out-of-range values. The ADCs are not usable in DeepSleep and Hibernate modes as they

require a high-speed clock. The ADC input reference voltage VREFH range is 2.7 V to V_DDAand VREFL is V_SSA

.

3.3.4

Timer/counter/PWM block (TCPWM)

The TCPWM block consists of 16-bit (75 channels) and 32-bit (8 channels) counters with user-programmable

period. Twelve of the 16-bit counters are optimized for motor-control operations. Each TCPWM counter contains

a capture register to record the count at the time of an event, a period register (used to either stop or auto-reload

the counter when its count is equal to the period register), and compare registers to generate signals that are

used as PWM duty-cycle outputs.

Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,

PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.

In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with

features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead

times for PWM output signals.

The TCPWM block also provides true and complement outputs, with programmable offset between them, to

allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the

PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems

when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time

for software intervention).

Note

13.VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when

properly connected, reduces or removes the impact of IR drops in the VSSIO and VSSA paths from measure-

ments.

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Functional description

3.3.5

Serial communication blocks (SCB)

XMC7100 contains up to 11 serial communication blocks, each configurable to support I²C, UART, or SPI.

3.3.5.1

I²C interface

An SCB can be configured to implement a full I²C master (capable of multi-master arbitration) or slave

interface. Each SCB configured for I²C can operate at speeds of up to 1 Mbps (Fast-mode Plus) and has flexible

buffering options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO

buffering for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the

need for clock stretching. The I²C interface is compatible with Standard, Fast-mode, and Fast-mode Plus

devices as specified in the NXP I²C-bus specification and user manual (UM10204). The I²C-bus I/O is

implemented with GPIO in open-drain modes^{[14, 15]}

.

3.3.5.2

UART interface

When configured as a UART, each SCB provides a full-featured UART with maximum signalling rate determined

by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and

SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit

multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines.

Common UART functions such as parity, number of stop bits, break detect, and frame error are supported.

FIFO buffering of transmit and receive data allows greater CPU service latencies to be tolerated.

3.3.5.3

SPI interface

The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start

pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The

SPI interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports

EZSPI^[16]mode.

SCB0 supports the following additional features:

• Operable as a slave in DeepSleep mode

• I²C slave EZ (EZI²C^[17]) mode with up to 256-B data buffer for multi-byte communication without CPU

intervention

• I²C slave externally-clocked operations

• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention

3.3.6

CAN FD

XMC7100 contains two CAN FD controller blocks, each supporting four CAN FD channel. All CAN FD controllers are

compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the

time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in

hardware. All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx

handler manages message acceptance filtering, transfer of received messages from the CAN core to a message

RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages

from the message RAM to the CAN core, and provides transmit-message status.

3.3.7

Ethernet MAC

XMC7100 supports one Ethernet channel with transfer rates of 10, or 100 Mbps. The input/output frames and flow

control are complaint to the Ethernet/IEEE 802.3bw standard and also IEEE-1588 precision-time protocol (PTP).

XMC7100 supports half/full-duplex data transport using external PHY devices. The MAC supports glue-free

connection to PHYs through IEEE standard MII, and RMII interfaces. The device also supports Audio-Video

Bridging (AVB). The MAC supports standard 6-byte programmable addresses.

Notes

14.This is not 100% compliant with the I²C-bus specification; I/Os are not over-voltage tolerant, do not support the 20-mA sink requirement

of Fast-mode Plus, and violate the leakage specification when no power is applied.

15.Only Port 0 with the slew rate control enabled meets the minimum fall time requirement.

16.The Easy SPI (EZSPI) protocol is based on the Motorola SPI protocol operating in any mode (0, 1, 2, or 3). It allows communication

between master and slave while reducing the need for CPU intervention.

17.The Easy I²C (EZI2C) protocol is a unique communication scheme built on top of the I²C protocol by Infineon. It uses a meta protocol

around the standard I²C protocol to communicate to an I²C slave using indexed memory transfers. This reduces the need for CPU

intervention.

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Functional description

3.3.8

External memory interface

In addition to the internal flash memory, XMC7100 supports direct connection to as much as 128 MB of external

flash or RAM memory. This connection is made through either a HYPERBUS™ or serial peripheral interface (SPI).

HYPERBUS™ allows connection to HYPERFLASH™ and HYPERRAM™ devices, while SPI (single, dual, quad, or octal

SPI at up to 90 MHz) can connect with serial flash memory. Code stored in memory connected through this

interface allows execute-in-place (XIP) operation, which does not require the instructions to be first copied to

internal memory, and on-the-fly encryption and decryption for environments requiring secure external data and

code.

3.3.9

SDHC interface

XMC7100 supports one Secure Digital High Capacity (SDHC) interface, which conforms to Secure Digital (SD) 6.0,

Secure Digital Input Output (SDIO) 4.10, and Embedded Multimedia Card (eMMC) 5.1 specifications, along with

Host Control Interface (HCI) 4.2 specification. The interface supports System DMA (SDMA), Advance DMA (ADMA2,

ADMA3), and command queuing (CQ) features. This interface supports data rates of SD DS (Default Speed, 4-bits

at 25 MHz), SD HS (High Speed, 4-bits at 50 MHz, and eMMC 52-MHz DDR (8-bits at 52-MHz card clock).

3.3.10

Audio interface

XMC7100 supports three instances of Inter-IC Sound Bus (I²S) interface to connect to digital audio devices:

Supports I2S, Left Justified (LJ), and eight-channel Time Division Multiplexed (TDM) digital audio interface

formats in both master and slave modes with independent operations in receive and transmit directions.

3.3.11

One-time-programmable (OTP) eFuse

XMC7100 contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable

identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing,

programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available

for user purposes.

3.3.12

Event generator

The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep

mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a

SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide

CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing

overall power consumption and processing overhead.

3.3.13

Trigger multiplexer

XMC7100 supports connection of various peripherals using trigger signals. Triggers are used to inform a

peripheral of the occurrence of an event or change of state. These triggers are used to affect or initiate some

action in other peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a

destination. Triggers provide active logic functionality and are typically supported in Active mode.

3.4

I/Os

XMC7100 has up to 220 programmable I/Os.

The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on and

reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.

Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service

routine (ISR) associated with it.

I/O port power source mapping is listed in Table 3-1. The associated supply determines the V_OH, V_OL, V_IH, and V_IL

levels when configured for CMOS and Industrial thresholds.

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32-bit Arm® Cortex®-M7

Functional description

Table 3-1

I/O port power source

Supply pins

Ports

VDDD

P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23, P28, P29, P30, P31

VDDIO_1

VDDIO_2

VDDIO_3

P6, P7, P8, P9, P32

P10, P11, P12, P13, P14, P15, P26, P27

P24, P25

3.4.1

Port nomenclature

Px.y describes a particular bit “y” available within an I/O port “x.”

For example, P4.2 reads “port 4, bit 2”.

Each I/O implements the following:

• Programmable drive mode

- High impedance

- Resistive pull-up

- Resistive pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up or pull-down

- Weak pull-up or pull-down

XMC7100 has three types of programmable I/Os: GPIO Standard, GPIO Enhanced, and HSIO Standard.

3.4.2

GPIO Standard (GPIO_STD)

Supports standard industrial signaling across the 2.7-V to 5.5-V V_DDIOrange. GPIO Standard I/Os have multiple

configurable drive levels, drive modes, and selectable input levels.

3.4.3

GPIO Enhanced (GPIO_ENH)

Supports extended functionality industrial signalling across the 2.7-V to 5.5-V V_DDIOrange with higher currents at

lower voltages (full I²C timing support, slew-rate control).

Both GPIO_STD and GPIO_ENH implement the following:

• Configurable input threshold (CMOS, TTL, or industrial)

• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)

• Analog input mode (input and output buffers disabled)

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32-bit Arm® Cortex®-M7

Functional description

3.4.4

HSIO Standard (HSIO_STD)

These I/Os are optimized exclusively for high-speed signaling and do not support slew-rate control, DeepSleep

operation, POR mode control, analog connections, or non-CMOS signaling levels. HSIO_STD supports high-speed

peripherals such as QSPI, HYPERBUS™, Ethernet, and SDHC controller. HSIO_STD also supports programmable

drive strength. These I/Os are available only in Active mode and retain state in DeepSleep mode.

3.4.5

Smart I/O

Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals

coming into the chip. XMC7100 has five Smart I/O blocks. Operation can be synchronous or asynchronous and

the blocks operate in all device power modes except for Hibernate.

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32-bit Arm® Cortex®-M7

XMC7100 address map

4

XMC7100 address map

The XMC7100 microcontroller supports the memory spaces shown in Figure 4-1.

• 1088 KB (960 KB + 128 KB), 2112 KB (1984 KB + 128 KB), or 4160 KB (4032 KB + 128 KB) of code-flash, used in

the single- or dual-bank mode based on the associated bit in the flash control register

- Single-bank mode: 1088 KB, 2112 KB, or 4160 KB

- Dual-bank mode: 544 KB, 1056 KB, or 2080 KB per bank

• 128 KB (96 KB + 32 KB) or 256 KB (192 KB + 64 KB) of work-flash, used in the single- or dual-bank mode based

on the associated bit in the flash control register

- Single-bank mode: 128 KB or 256 KB

- Dual-bank mode: 64 KB or 128 KB per bank

• 64 KB of secure ROM

• 192 KB, 384 KB, or 768 KB of SRAM (First 2 KB is reserved for internal usage)

• 16 KB of Instruction TCM for each Cortex-M7 CPU

• 16 KB of Data TCM for each Cortex-M7 CPU

• 128 MB SMIF XIP

0xFFFF FFFF

Arm System

CPU & Debug Registers

Space

0xE000 0000

Reserved

0xA011 3FFF

16 KB

Reserved

16 KB

Reserved

16 KB

Reserved

16 KB

Core CM7_1 Data TCM

CM7_1 DTCM

CM7_1 ITCM

0xA011 0000

0xA010 3FFF

0xA010 0000

Core CM7_1 Instruction TCM

0xA001 3FFF

0xA001 0000

CM7_0 DTCM

CM7_0 ITCM

Core CM7_0 Data TCM

0xA000 3FFF

0xA000 0000

Core CM7_0 Instruction TCM

Reserved

0x67FF FFFF

Serial Memory Interface XIP

128 MB

SMIF_XIP

0x6000 0000

0x43FF FFFF

Reserved

Peripheral

Mainly used for on-chip peripherals;

e.g., AHB or APB peripherals

Interconnect or

Memory map

0x4000 0000

Reserved

General purpose RAM,

mainly used for data

See “XMC7100 Address

Map 2” for the memory

size details

SRAM

0x2800 0800

0x2800 0000

2

KB

Reserved

16 KB

Reserved

32 KB

Reserved

32 KB

CM7 internal address map for its

Data TCM

0x2000 3FFF

0x2000 0000

CM7 DTCM

0x1780 7FFF

0x1780 0000

Alternate Flash

Supervisory

Used to store manufacture specific

data like flash protection settings, trim

settings, device addresses, serial numbers,

calibration data, etc.

0x1700 7FFF

0x1700 0000

Flash Supervisory

Work flash

Reserved

See “XMC7100 Address

Map 2” for the memory

size details

Work flash used for long

term data retention

0x1400 0000

Reserved

See “XMC7100 Address

Map 2” for the memory

size details

Mainly used for user program code

Code flash

ROM Mirror

0x1000 0000

Reserved

Secured Boot ROM to set user specified

protection levels, trim and configuration

data, code authentication, jump to user mode, etc.

0x0100 FFFF

0x0100 0000

64 KB

Reserved

64 KB

0x0000 FFFF

ROM

0x0000 0000

CM7 internal address map for its instruction TCM.

The address overlaps with portion of ROM region.

0x0000 3FFF

16 KB

CM7 ITCM

0x0000 0000

Figure 4-1

XMC7100 address map 1^{[18, 19]}

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32-bit Arm® Cortex®-M7

XMC7100 address map

XMC7100/XMC7100D-

F100K/F144K/F176K/E272K

XMC7100/XMC7100D-

F100K/F144K

2112

XMC7100-

F100K

1088

4160

0x4000 0000

Reserved

0x280B FFFF

SRAM1 256 KB

0x2808 0000

0x2807 FFFF

0x2805 FFFF

SRAM

768 KB

SRAM1 128 KB

SRAM0 256 KB

0x2802 FFFF

0x2804 0000

0x2803 FFFF

SRAM1 64 KB

SRAM0 128 KB

SRAM

384 KB

SRAM0 512 KB

SRAM

192 KB

0x2802 0000

0x2802 FFFF

0x2800 0000

Reserved

0x1403 FFFF

64 KB

(128 B Small Sectors)

Work

Flash

0x1403 0000

0x1402 FFFF

0x1401 FFFF

32 KB

(128 B Small Sectors)

32 KB

(128 B Small Sectors)

Work

Flash

128 KB

Work

Flash

128 KB

256 KB

192 KB

(2 KB Large Sectors)

0x1401 8000

0x1401 7FFF

0x1401 8000

0x1401 7FFF

96 KB

(2 KB Large Sectors)

96 KB

(2 KB Large Sectors)

0x1400 0000

Reserved

0x1040 FFFF

128 KB

Reserved

(8 KB Small Sectors)

0x103F 0000

0x103E FFFF

Reserved

Code

Flash

4160 KB

0x1020 FFFF

128 KB

(8 KB Small Sectors)

4032 KB

(32 KB Large Sectors)

0x101F 0000

0x101E FFFF

Code

Flash

2112 KB

0x1010 FFFF

128 KB

(8 KB Small Sectors)

1984 KB

(32 KB Large Sectors)

0x100F 0000

0x100E FFFF

Code

Flash

1088 KB

960 KB

(32 KB Large Sectors)

0x1000 0000

Figure 4-2

XMC7100 address map 2^[18]

Notes

18.The size representation is not up to scale.

19.First 2KB of SRAM is reserved, not available for users. User must keep the power of first 32KB block of SRAM0 in enabled or retained

in all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.

Datasheet

23

002-33896 Rev. *A

2022-10-20

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Flash base address map

5

Flash base address map

Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions

along with their respective base addresses.

Table 5-1

Code-flash address mapping in single-bank mode

Code-flash Size

Large Sectors Small Sectors

Large Sector Base Address Small Sector Base Address

(KB)

(LS)

(SS)

4160

2112

1088

32 KB × 126

32 KB x 62

32 KB x 30

8 KB × 16

8 KB x 16

0x1000 0000

0x103F 0000

0x101F 0000

0x100F 0000

Table 5-2

Work-flash address mapping in single-bank mode

Work-flash Size

(KB)

Large Sectors Small Sectors Large Sector Base Address Small Sector Base Address

256

128

2 KB × 96

2 KB x 48

128 B × 512

128 B x 256

0x1400 0000

0x1403 0000

0x1401 8000

Table 5-3

Code-flas

Code-flash address mapping in dual-bank mode (Mapping A)

Second

Half SS

Base

First Half First Half

First

Second

Half LS

Second

Half SS

Half

LS Base

Address

SS Base

Address

h Size (KB) Half LS

Half SS

LS Base

Address

4160

2112

1088

32 KB × 63 8 KB × 8 32 KB × 63 8 KB × 8

32 KB x 31 8 KB x 8 32 KB x 31 8 KB x 8

32 KB x 15 8 KB x 8 32 KB x 15 8 KB x 8

0x1000

0000

0x1000

0000

0x1000

0000

0x101F

8000

0x100F

8000

0x1007

8000

0x1200

0000

0x1200

0000

0x1200

0000

0x121F

8000

0x120F

8000

0x1207

8000

Table 5-4

Code-flas

Code-flash address mapping in dual-bank mode (Mapping B)

First Half First Half

Second

Half

Second

Half SS

Base

First

Second

Half LS

Second

Half SS

LS Base

Address

SS Base

Address

h Size (KB) Half LS

Half SS

LS Base

Address

4160

2112

1088

32 KB × 63 8 KB × 8 32 KB × 63 8 KB × 8

32 KB x 31 8 KB x 8 32 KB x 31 8 KB x 8

32 KB x 15 8 KB x 8 32 KB x 15 8 KB x 8

0x1200

0000

0x1200

0000

0x1200

0000

0x121F

8000

0x120F

8000

0x1207

8000

0x1000

0000

0x1000

0000

0x1000

0000

0x101F

8000

0x100F

8000

0x1007

8000

Datasheet

24

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2022-10-20

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Flash base address map

Table 5-5

Work-flas

Work-flash address mapping in dual-bank mode (Mapping A)

Second

Half

Second

Half SS

Base

First Half First Half

First

Second

Half LS

Second

Half SS

LS Base

Address

SS Base

Address

h Size (KB) Half LS

Half SS

LS Base

Address

256

128

2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1400 0x1401 8000 0x1500 0x1501 8000

0000

2 KB x 24 128 B x 128 2 KB x 24 128 B x 128 0x1400

0000

0x1400

C000

0x1500 0x1500 C000

0000

Table 5-6

Work-flas

Work-flash address mapping in dual-bank mode (Mapping B)

Second

Half

Second

Half SS

Base

First Half First Half

First

Second

Half LS

Second

Half SS

LS Base

Address

SS Base

Address

h Size (KB) Half LS

Half SS

LS Base

Address

256

128

2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1500

0000

2 KB x 24 128 B x 128 2 KB x 24 128 B x 128 0x1500

0000

0x1501

8000

0x1500

C000

0x1400

0000

0x1400

0000

0x1401

8000

0x1400

C000

Datasheet

25

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2022-10-20

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Peripheral I/O map

6

Peripheral I/O map

Table 6-1

XMC7100 peripheral I/O map

Instanc-

es

Instance

Size

Section

Description

Base Address

Group Slave

Peripheral interconnect

Peripheral group (0, 1, 2, 3, 4, 5, 6, 8, 9)

Peripheral trigger group

Peripheral 1:1 trigger group

Peripheral interconnect, master interface

PERI Programmable PPU

0x4000 0000

0x4000 4000

0x4000 8000

0x4000 C000

0x4002 0000

0x4002 0800

0x4004 0000

0x4010 0000

0x4020 0000

0x4021 0000

0x4022 0000

0x4022 1000

0x4023 0000

9

11

0x40

0x400

PERI

0

PERI_MS

10^[20]

700

2

0x40

0x2000

0

1

PERI Fixed PPU

PERI_PCLK Peripheral Clock Groups

0

1

2

0

CRYPTO

CPUSS

Cryptography component

CPU subsystem (CPUSS)

Fault structure subsystem

Fault structures

Inter process communication

IPC structures

FAULT

2

1

4

0x100

IPC

8

0x20

2

IPC interrupt structures

Protection

PROT

Shared memory protection unit structures 0x4023 2000

16

0x40

0x400

2

3

4

Memory protection unit structures

Flash controller

0x4023 4000

0x4024 0000

FLASHC

System Resources Sub-System Core

Registers

0x4026 0000

Clock Supervision High Frequency

Clock Supervision Reference Frequency

Clock Supervision Low Frequency

0x4026 1400

0x4026 1710

0x4026 1720

8

1

2

3

1

0x10

SRSS

2

5

Clock Supervision Internal Low Frequency 0x4026 1730

Clock PLL 400 MHz

Multi Counter WDT

Free Running WDT

SRSS Backup Domain/RTC

Backup Register

P-DMA0 Controller

P-DMA0 channel structures

P-DMA1 Controller

0x4026 1900

0x4026 8000

0x4026 C000

0x4027 0000

0x4027 1000

0x4028 0000

0x4028 8000

0x4029 0000

0x4029 8000

0x402A 0000

0x402A 1000

0x10

0x100

BACKUP

P-DMA

2

6

7

8

9

4

100

58

8

0x04

0x40

0x100

P-DMA1 channel structures

M-DMA0 Controller

M-DMA0 channels

M-DMA

Note

20.These Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the

device-specific TRM to know more about the configuration of these programmable PPUs.

Datasheet

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XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Peripheral I/O map

Table 6-1

Section

XMC7100 peripheral I/O map ^(continued)

Instanc-

es

Instance

Size

Description

Base Address

Group Slave

eFUSE

HSIOM

GPIO

eFUSE Customer Data (192 bits)

High-Speed I/O Matrix (HSIOM)

GPIO port control/configuration

Programmable I/O configuration

SMARTIO port configuration

Event generator 0 (EVTGEN0)

Event generator 0 comparator structures

Serial Memory Interface 0 (SMIF0)

SMIF0 Devices

Secure Digital High Capacity 0 (SDHC0)

SDHC0 Wrap

SDHC0 Core

Ethernet 0 (ETH0)

CAN0 controller

Message RAM CAN0

CAN1 controller

Message RAM CAN1

Timer/Counter/PWM 0 (TCPWM0)

TCPWM0 Group #0 (16-bit)

TCPWM0 Group #1 (16-bit, Motor control)

TCPWM0 Group #2 (32-bit)

0x402C 0868

0x4030 0000

0x4031 0000

0x4032 0000

0x4032 0C00

0x403F 0000

0x403F 0800

0x4042 0000

0x4042 0800

0x4046 0000

0x4046 1000

0x4048 0000

0x4052 0000

0x4053 0000

0x4054 0000

0x4055 0000

0x4038 0000

0x4038 8000

0x4039 0000

6

33

0x04

0x10

0x80

2

3

10

0

1

SMARTIO

EVTGEN

SMIF

3

4

2

3

0

5

16

1

0x100

0x20

0x80

SDHC

ETH

4

1

4

0x10000

0x200

0x7FFF

0x200

4

5

2

1

TTCANFD

TCPWM

4

5

2

3

0x7FFF

63

12

8

0x80

Serial Communications Block

SCB

I²S

0x4060 0000

0x4080 0000

11

3

0x10000

0x1000

6

8

0-10

0-2

(SPI/UART/I²C)

I²S Audio Subsystem

Programmable Analog Subsystem (PASS0) 0x4090 0000

SAR0 channel controller

SAR1 channel controller

SAR PASS SAR2 channel controller

SAR0 channel structures

0x4090 0000

0x4090 1000

0x4090 2000

0x4090 0800

0x4090 1800

0x4090 2800

9

0

32

8

0x40

SAR1 channel structures

SAR2 channel structures

Datasheet

27

002-33896 Rev. *A

2022-10-20

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

XMC7100 clock diagram

7

XMC7100 clock diagram

IMO

EXT_CLK

ECO

WCO

LS

ILO0

LS

ILO1

LS

ECO

Prescaler

LS

MUX

FLL

MUX

PLL400#0

MUX

PLL400#1

CLK_

MUX

PLL#2

MUX

PLL#3

MUX

LS

CLK_ILO0

CLK_

PATH0

CLK_

PATH1

CLK_

PATH3

CLK_

PATH4

CLK_

PATH5

CLK_REF_HF

PATH2

WDT

MUX

CLK_BAK

CLK_LF

RTC

CSV

CLK_ILO0

MCWDT

MUX

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

CLK_HF0

CLK_HF1

CLK_HF2

CLK_HF3

CLK_HF4

CLK_HF5

CLK_HF6

CLK_HF7

CSV

CLK_ILO0

CLK_LF

CLK_REF_HF

SDHC

AUDIOSS

I2S External Clock

Ethernet

Tx _CLK,Rx_CLK and REF_CLK to Ethernet PHY

Event Generator

CAN FD

CLK_GR

5

Divider

(1- 256)

TCPWM[0]

CLK_GR

6

Divider

(1- 256)

SCB[*]

SCB[0]

Serial Interface Clock

CLK_GR

9

Divider

(1- 256)

SAR ADC

PCLK_CANFD [x] _CLOCK_CAN[y]

PCLK_TCPWM0 _CLOCKS[x]

PCLK_SCB [x] _CLOCK

Peripheral

Clock Dividers #1

PCLK_PASS_CLOCK_SAR[x]

CLK_FAST_0

CLK_FAST_1

Divider

(1-256)

CM7_0

CM7_1

Divider

(1-256)

SMIF

CLK_MEM

Divider

(1- 256)

ROM/SRAM/FLASH

CPUSS FastI nfrastructure

CLK_SLOW

Divider

(1-256)

CM0+

LEGEND 1:

LEGEND 2:

Active Domain

CPUSSSlow I nfrastructure

DeepSleep Domain

Hibernate Domain

P- DMA / M-DMA

CRYPTO

PERI

CLK_PERI

CLK_GR3

CLK_GR4

CLK_GR8

Divider

(1-256)

Divider

(1- 256)

Relationship of Monitored Clock and

Reference Clock

Monitored Clock

Divider

(1- 256)

SRSS

Reference Clock

CSV

Divider

(1- 256)

EFUSE

LEGEND 3:

One Clock Line

MultipleC lockL ines

IOSS

Peripheral

Clock Dividers #0

CPUSS(DEBUG)

TCK/SWDCLK from a Debugger

CLK_ TRC_DBG

Divider

(1-256)

PCLK_SMARTIO[x] _CLOCK

PCLK_CPUSS_CLOCK_TRACE_IN

Figure 7-1

XMC7100 clock diagram

Datasheet

28

002-33896 Rev. *A

2022-10-20

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

XMC7100 CPU start-up sequence

8

XMC7100 CPU start-up sequence

The start-up sequence is described in the following steps:

1. System Reset (@0x0000 0000)

2. CM0+ executes ROM boot (@0x0000 0004)

i. Applies trims

ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory

flash

iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it

3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)

i. Debug pins are configured based on the SWD/JTAG spec^[21]

ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash

(@0x1000 0000)

iii.CM0+ branches to its Reset handler

4. CM0+ starts execution of application

i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)

i. Sets clocks for CM7_0 (CLK_HF1) and CM7_1 (CLK_HF2)

ii. Sets CM7_0 (CM7_0_VECTOR_TABLE_BASE @0x4020 0200) and CM7_1 (CM7_1_VECTOR_TABLE_BASE

@0x4020 0600) vector tables to the respective locations, also and mentioned in flash (specified in the linker

definition file)

iii.Enables the power for both the CPU cores CM7_0 and CM7_1

iv.Disables CPU_WAIT to allow accesses from the debugger

v. Releases CM7_0 and/or CM7_1 from reset

vi.Continues execution of CM0+ user application

5. CM7_0 and/or CM7_1 executes directly from either code-flash or SRAM

i. CM7_0/CM7_1 branches to its Reset handler

ii. Continues execution of the user application

Note

21.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer

to Table 11-1 for pin assignments.

Datasheet

29

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2022-10-20

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Pin assignment

9

Pin assignment

Note: For all TEQFP packages, the thermal pad needs to be connected to VSSD.

VSSD

P0.0

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDDD

P18.7

P18.6

P18.5

P18.4

P18.3

P18.2

P18.1

P18.0

VSSD

VCCD

VDDD

P14.1

P14.0

P13.7

P13.6

P13.5

P13.4

P13.3

P13.2

P13.1

P13.0

VSSD

2

P0.1

3

P0.2

4

P0.3

5

P2.0

6

P2.1

7

P2.2

8

P2.3

9

P3.0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P3.1

VDDD

VSSD

P5.0

100-TEQFP

P5.1

P5.2

P5.3

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

VDDD

VDDIO_1

Figure 9-1

100-TEQFP pin assignment

Datasheet

30

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2022-10-20

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Pin assignment

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDDD

VSSD

1

2

3

4

P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/ETH0_TXD_3/PWM_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_7

P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/ETH0_TXD_2/PWM_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_6

P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/ETH0_TXD_1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5

P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/ETH0_TXD_0/PWM_H_2/SCB1_SEL1/SCB3_SEL0/TRACE_DATA_0/ADC[2]_4

P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/ETH0_TX_CLK/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/SCB3_CLK/TRACE_CLOCK/ADC[2]_3

P18.2 PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/ETH0_TX_ER/PWM_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/SCB3_MOSI/ADC[2]_2

P18.1 PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/ETH0_TX_CTL/PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/SCB3_MISO/FAULT_OUT_1/ADC[2]_1

P18.0 PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/ETH0_REF_CLK/PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0

VSSD

PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA/SCB0_MISO P0.0

PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL/SCB0_MOSI P0.1

PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/SCB4_MISO/CAN0_1_TX P0.2

PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/SCB4_MOSI/CAN0_1_RX P0.3

PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/TC_H_4_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0

PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/TC_H_5_TR0/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/CAN0_0_RX/TRIG_IN[3] P2.1

PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/ETH0_RX_ER/TC_H_6_TR0/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/TRIG_IN[4] P2.2

PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL/TC_H_7_TR0/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3

PWM_1/PWM_2_N/TC_1_TR0/TC_2_TR1/ETH0_MDIO/PWM_H_6_N/SCB6_RX/SCB6_MISO/CAN0_3_TX/TRIG_DBG[0] P3.0

PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/ETH0_MDC/PWM_H_7_N/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN0_3_RX/TRIG_DBG[1] P3.1

VDDD

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VCCD

VSSD

100-TEQFP

VDDD

PWM_9/PWM_8_N/TC_9_TR0/TC_8_TR1/SCB5_SEL2 P5.0

P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/AUDIOSS2_TX_SCK/PWM_H_6_N/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_0_RX/ADC[1]_21

P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/AUDIOSS2_MCLK/PWM_H_6/SCB2_MISO/SCB2_RX/CAN1_0_TX/ADC[1]_20

P13.7 PWM_47/PWM_M_11_N/TC_47_TR0/TC_M_11_TR1/AUDIOSS1_RX_SDI/PWM_H_5_N/TRIG_IN[23]/ADC[1]_19

P13.6 PWM_M_11/PWM_46_N/TC_M_11_TR0/TC_46_TR1/AUDIOSS1_RX_WS/PWM_H_5/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18

P13.5 PWM_46/PWM_M_10_N/TC_46_TR0/TC_M_10_TR1/AUDIOSS1_RX_SCK/PWM_H_4_N/SCB3_SEL2/ADC[1]_17

P13.4 PWM_M_10/PWM_45_N/TC_M_10_TR0/TC_45_TR1/AUDIOSS1_CLK_I2S_IF/PWM_H_4/SCB3_SEL1/ADC[1]_16

P13.3 PWM_45/PWM_M_9_N/TC_45_TR0/TC_M_9_TR1/AUDIOSS1_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15

P13.2 PWM_M_9/PWM_44_N/TC_M_9_TR0/TC_44_TR1/AUDIOSS1_TX_WS/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14

P13.1 PWM_44/PWM_M_8_N/TC_44_TR0/TC_M_8_TR1/AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13

P13.0 PWM_M_8/PWM_43_N/TC_M_8_TR0/TC_43_TR1/AUDIOSS1_MCLK/EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12

VSSD

PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1/SCB9_SEL3 P5.1

PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1 P5.2

PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1 P5.3

PWM_M_0/PWM_14_N/TC_M_0_TR0/TC_14_TR1/SCB4_RX/SCB4_MISO/ADC[0]_0 P6.0

PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/ADC[0]_1 P6.1

PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SDHC_CARD_MECH_WRITE_PROT/SCB4_RTS/SCB4_SCL/SCB4_CLK/CAN0_2_TX/ADC[0]_2 P6.2

PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SPIHB_CLK/SDHC_CARD_CMD/SCB4_CTS/SCB4_SEL0/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3

PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SPIHB_RWDS/SDHC_CLK_CARD/SCB4_SEL1/ADC[0]_4 P6.4

PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SPIHB_SEL0/SDHC_CARD_DETECT_N/SCB4_SEL2/ADC[0]_5 P6.5

VDDD

VDDIO_1

Figure 9-2

100-TEQFP pin assignment with alternate functions

Datasheet

31

002-33896 Rev. *A

2022-10-20

XMC7000 microcontroller

32-bit Arm® Cortex®-M7

Pin assignment

VSSD

P0.0

P0.1

P0.2

P0.3

P1.0

P1.1

P2.0

P2.1

P2.2

P2.3

P2.4

P3.0

P3.1

P3.2

P3.3

P3.4

VDDD

VSSD

P4.0

P4.1

P5.0

P5.1

P5.2

P5.3

P5.4

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

VDDD

VDDIO_1

1

108

107

106

105

104

103

102

101

100

99

VDDD

P18.7

P18.6

P18.5

P18.4

P18.3

P18.2

P18.1

P18.0

P17.4

P17.3

P17.2

P17.1

P17.0

VSSD

VCCD

VDDD

P15.3

P15.2

P15.1

P15.0

P14.5

P14.4

P14.1

P14.0

P13.7

P13.6

P13.5

P13.4

P13.3

P13.2

P13.1

P13.0

VSSD

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

98

97

96

95

94

93

92

91

144-TEQFP

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

Figure 9-3

144-TEQFP pin assignment