IZ74LV04 [INTEGRAL]
HEX INVERTER; 六反相器
INTEGRAL CORP. 
IN74LV04
HEX INVERTER
The IN74LV04 is a low-voltage Si-gate CMOS device that is pin
and function compatible with 74HC/HCT04A.
The IN74LV04 provides six inverting buffers.
• Wide Operating Voltage: 1.0÷5.5 V
• Optimized for Low Voltage applications: 1.0÷3.6 V
• Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V
• Low Input Current
ORDERING INFORMATION
IN74LV04N
IN74LV04D
IZ74LV04
Plastic
SOIC
Chip
TA = -40° ÷ 125° C for all
packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Input
Output
PIN 14 =VCC
PIN 7 = GND
A
L
Y
H
L
H
1
IN74LV04
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 ÷ +7.0
±20
Unit
V
mA
mA
mA
VCC
IIK*1
IOK*2
Io*3
DC supply voltage (Referenced to GND)
DC input diode current
DC output diode current
±50
DC
output
source
or
for
for
sink
types
types
current
with
±25
-bus driver outputs
DC GND current
- bus driver outputs
DC VCC current
IGND
ICC
mA
mA
mW
±50
±50
with
- bus driver outputs
PD
Power dissipation per package, plastic DIP+
750
500
SOIC
package+
Tstg
TL
Storage temperature
-65 ÷ +150
°C
°C
Lead temperature, 1.5 mm from Case for 10
seconds
260
(Plastic DIP ), 0.3 mm (SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SOIC Package: : - 8 mW/°C from 70° to 125°C
*1: VI < -0.5V or VI > VCC+0.5V
*2: Vo < -0.5V or Vo > VCC+0.5V
*3: -0.5V < Vo < VCC+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
1.0
0
Max
5.5
Unit
V
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to
GND)
VCC
V
TA
tr, tf
Operating Temperature, All Package Types
Input Rise and Fall Time
-40
+125
°C
ns
VCC
VCC
VCC
=1.2
=2.0
=3.0
V
V
V
0
0
0
0
1000
700
500
400
V
CC =3.6 V
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
V
OUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.
2
IN74LV04
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Test
VCC,
V
25°C
-40°C ÷
85°C
-40°C ÷
125°C
Symbol Parameter
Unit
V
Conditions
min max min max min max
VIH
VIL
High-Level Input
1.2 0.9
2.0 1.4
3.0 2.1
3.6 2.5
-
0.9
1.4
2.1
2.5
-
-
0.9
1.4
2.1
2.5
-
-
Voltage
-
-
-
-
-
-
-
-
-
Low-Level Input
Voltage
1.2
2.0
3.0
3.6
-
-
-
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
-
V
V
-
-
-
-
-
-
VOH
High-Level Output VI = VIL
1.2 1.1
2.0 1.92
1.0
1.9
2.9
2.34
1.0
1.9
2.9
2.20
Voltage
-
-
-
IO = -50 µA
*
*
2.92
2.48
-
-
-
VI = VIL
IO = -6.0 µA
-
-
-
V
V
VOL
Low-Level Output VI = VIH
1.2
2.0
-
-
-
-
0.09
0.09
0.09
0.33
-
-
-
-
0.1
0.1
0.1
0.4
-
-
-
-
0.1
0.1
0.1
0.5
Voltage
IO = 50 µA
VI = VIH or VIL 3.0
V
IO = 6.0 mА
IIL
IIН
Low-Level Input
Leakage Current
-
-
-
-0.1
0.1
2.0
-
-
-
-1.0
1.0
20
-
-
-
-1.0
1.0
40
µA
µA
µA
High-Level Input VI = VCC
Leakage Current
*
*
IСС
Quiescent Supply VI = 0 В or
Current
VCC
IO = 0 µA
(per Package)
* : VCC= (3.3±0.3) V
3
IN74LV04
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns, VIL=0V, VIH=VCC, RL=1 kΩ)
VCC
V
Guaranteed Limit
25°C
-40°C ÷ 85°C
-40°C ÷
125°C
Symbol
Parameter
Unit
ns
min max min max min max
tTHL, (tTLH) Output Transition 1.2
Time, Any Output 2.0
-
-
70
16
10
90
23
14
-
-
-
-
-
-
85
20
-
-
-
-
-
-
100
24
(Figure 1)
*
1.2
13
15
tPHL, (tPLH) Propagation
-
-
-
120
28
150
34
Delay, Input A to 2.0
Output Y (Figure
1)
*
18
21
CI
Input Capacitance 3.0
-
-
3.5
-
3.5
pF
pF
-
CPD
Power Dissipation Capacitance (Per
Inverter)
ТА=25°С, VI=0V÷VCC
42
Used
to
determine
the
no-load
dynamic
power
consumption:
PD = CPDVCC2fI+ ∑(CLVCC2fo), fI - input frequency, fo - output frequency (MHz)
∑(CLVCC2fo) – sum of the outputs
tHL
tLH
VCC
0.9
0.9
V1
Input А
V1
0.1
GND
0.1
tPHL
tPLH
0.9
0.9
VCC
V1
Output Y
V1
0.1
0.1
GND
V1 = 0.5 VCC
tTHL
tTLH
Figure 1. Switching Waveforms
VCC
VI
VO
Termination resistance RT
–
should be equal to ZOUT of pulse
generators
DEVICE
UNDER
PULSE
GENERATOR
TEST
RT
RL
CL
Figure 2. Test Circuit
4
IN74LV04
CHIP PAD DIAGRAM IZ74LV04
12
02
10
11
09
05
13
08
Chip marking
25LV04
14
(x=0.127; y=0.580
)
07
06
01
04
03
1.35
±
0.03
Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)
Thickness of chip 0.46 ± 0,02 mm
PAD LOCATION
Pad No
01
Symbol
А1
X
Y
0.111
0.333
0.600
0.770
1.006
1.138
1.138
1.138
1.006
0.771
0.600
0.332
0.111
0.111
0.228
0.111
0.111
0.111
0.111
0.293
0.477
0.786
0.970
0.970
0.970
0.970
0.855
0.619
02
Y1
03
A2
04
Y2
05
A3
06
Y3
07
GND
Y4
08
09
A4
10
Y5
11
A5
12
Y6
13
A6
14
Vcc
5
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