DA28F320J5A-120 [INTEL]
5 Volt Intel StrataFlash® Memory; 5伏英特尔的StrataFlash ？内存
| 型号： | DA28F320J5A-120 |
| 厂家： | 
INTEL |
| 描述： | 5 Volt Intel StrataFlash® Memory |
| 文件： | 总51页 (文件大小：620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 Volt Intel StrataFlash® Memory
28F320J5 and 28F640J5 (x8/x16)
Datasheet
Product Features
■ High-Density Symmetrically-Blocked
■ Cross-Compatible Command Support
Architecture
—Intel Basic Command Set
—Common Flash Interface
—Scalable Command Set
■ 32-Byte Write Buffer
—64 128-Kbyte Erase Blocks (64 M)
—32 128-Kbyte Erase Blocks (32 M)
■ 4.5 V–5.5 V VCC Operation
—2.7 V–3.6 V and 4.5 V–5.5 V I/O
Capable
—6 µs per Byte Effective Programming
Time
■ 120 ns Read Access Time (32 M)
■ 6,400,000 Total Erase Cycles (64 M)
150 ns Read Access Time (64 M)
3,200,000 Total Erase Cycles (32 M)
■ Enhanced Data Protection Features
—100,000 Erase Cycles per Block
■ Automation Suspend Options
—Block Erase Suspend to Read
—Block Erase Suspend to Program
■ System Performance Enhancements
—STS Status Output
—Absolute Protection with
VPEN = GND
—Flexible Block Locking
—Block Erase/Program Lockout during
Power Transitions
■ Industry-Standard Packaging
■ Operating Temperature –20 °C to + 85 °C
(–40 °C to +85 °C on .25 micron ETOXVI)
process technology parts)
—SSOP Package (32, 64 M)
TSOP Package (32 M)
Capitalizing on two-bit-per-cell technology, 5 Volt Intel StrataFlash® memory products provide 2Xthe bits
in 1Xthe space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory
devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result,
Intel StrataFlash components are ideal for code or data applications where high density and low cost are
required. Examples include networking, telecommunications, audio recording, and digital imaging.
Intel StrataFlash memory components deliver a new generation of forward-compatible software support.
By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel’s 0.4 micron ETOX™ V process technology and Intel’s 0.25 micron ETOX VI
process technology, 5 Volt Intel StrataFlash memory provides the highest levels of quality and reliability.
Notice: This document contains information on products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizinga design.
Order Number: 290606-015
April 2002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relatingto sale and/or use of Intel products includingliability or warranties rel atingto
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arisingfrom future changes to them.
The 28F320J5 and 28F640J5 may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placingyour product order.
Copies of documents which have an orderingnumber and are referenced in this document, or other Intel literature may be obtained by calling1-800-
548-4725 or by visitingIntel's website at http://www.intel.com.
Copyright © Intel Corporation 1997–2002.
*Other names and brands may be claimed as the property of others.
2
Datasheet
28F320J5 and 28F640J5
Contents
1.0
2.0
Product Overview.......................................................................................................7
Principles of Operation..........................................................................................11
2.1
Data Protection....................................................................................................11
3.0
Bus Operation............................................................................................................12
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Read....................................................................................................................13
Output Disable.....................................................................................................13
Standby ...............................................................................................................13
Reset/Power-Down .............................................................................................13
Read Query.........................................................................................................14
Read Identifier Codes..........................................................................................14
Write....................................................................................................................16
4.0
Command Definitions.............................................................................................17
4.1
4.2
Read Array Command.........................................................................................18
Read Query Mode Command .............................................................................18
4.2.1 Query Structure Output ..........................................................................19
4.2.2 Query Structure Overview ......................................................................20
4.2.3 Block Status Register.............................................................................21
4.2.4 CFI Query Identification String...............................................................21
4.2.5 System Interface Information .................................................................22
4.2.6 Device Geometry Definition....................................................................23
4.2.7 Primary-Vendor Specific Extended Query Table....................................23
Read Identifier Codes Command........................................................................24
Read Status Register Command.........................................................................25
Clear Status Register Command.........................................................................25
Block Erase Command........................................................................................26
Block Erase Suspend Command ........................................................................26
Write to Buffer Command....................................................................................27
Byte/Word Program Commands .........................................................................27
Configuration Command .....................................................................................28
Set Block and Master Lock-Bit Commands.........................................................28
Clear Block Lock-Bits Command.........................................................................29
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
5.0
Design Considerations ..........................................................................................38
5.1
5.2
5.3
5.4
Three-Line Output Control...................................................................................38
STS and Block Erase, Program, and Lock-Bit Configuration Polling ..................38
Power Supply Decoupling...................................................................................38
Input Signal Transitions – Reducing Overshoots and Undershoots When Using
Buffers/Transceivers ...........................................................................................39
VCC, VPEN, RP# Transitions................................................................................39
Power-Up/Down Protection.................................................................................39
Power Dissipation................................................................................................40
5.5
5.6
5.7
6.0
Electrical Specifications........................................................................................40
6.1
Absolute Maximum Ratings.................................................................................40
Datasheet
3
28F320J5 and 28F640J5
6.2
6.3
6.4
6.5
6.6
6.7
OperatingConditions .......................................................................................... 40
Capacitance ........................................................................................................ 41
DC Characteristics .............................................................................................. 41
AC Characteristics—Read-Only Operations .......................................................44
AC Characteristics— Write Operations............................................................... 46
Block Erase, Program, and Lock-Bit Configuration Performance .......................49
7.0
8.0
Ordering Information.............................................................................................. 50
Additional Information ........................................................................................... 51
4
Datasheet
28F320J5 and 28F640J5
Revision History
Date of
Version
Revision
Description
09/01/97
09/17/97
12/01/97
-001
-002
-003
Original version
Modifications made to cover sheet
/GND Pins Converted to No Connects Specification Change added
V
CC
I
, I
, I
and I
Specification Change added
CCE
CCS CCD CCW
Order Codes Specification Change added
01/31/98
03/23/98
-004
-005
The µBGA* chip-scale package in Figure 2 was changed to a 52-ball package
and appropriate documentation added. The 64-Mb µBGA package dimensions
were changed in Figure 2. Changed Figure 4 to read SSOP instead of TSOP.
32-Mbit Intel StrataFlash memory read access time added. The number of
block erase cycles was changed. The write buffer program time was changed.
The operatingtemperature was changed. A read parameter was added. Sev-
eral program, erase, and lock-bit specifications were changed. Minor docu-
mentation changes were made as well. Datasheet designation changed from
Advance Information to Preliminary.
07/13/98
12/01/98
-006
-007
Intel StrataFlash memory 32-Mbit µBGA package removed. t
read specifi-
EHEL
cation reduced. Table 4 was modified. The Ordering Information was updated.
Removed 32 Mbit, 100 ns references and orderinginformation for same. Pro-
vided clearer V
specifications. Provided maximum program/erase specifica-
OH
tion. Added Input Signal Transitions—Reducing Overshoots and Undershoots
When Using Buffers/Transceivers to Design Considerations section.
Name of document changed from Intel® StrataFlash™ Memory Technology 32
and 64 Mbit.
05/04/99
09/16/99
-008
-009
Updated CFI Tables, Section 4.2.1—Section 4.2.7.
OperatingTemperature Range Specification was increased to –20 °C to
+85° C. The 32-Mbit Read Access at +85 °C was changed (Section 6.5, AC
Characteristics-Read Only Operations).
10/20/99
-010
Modified Write Pulse Width definition
Added lock-bit default status (Section 4.11)
Added order code information for –20 °C to +85 °C
11/08/99
12/16/99
-011
-012
Modified Chip Enable Truth Table
Corrected error in command table
Removed erase queuingoption from Figure 9, Block Erase Flowchart
06/26/00
-013
Add reference to 0.25 micron process on cover page
Corrected error in Table 10, Maximum buffer write time.
Updated section 6.7 program/erase times.
Corrected error in table 19 maximum temperature range
03/28/01
04/23/02
-014
-015
Changed Clear Block-Lock Bit Time in Section 6.7.
Added .25 micron ETOXVI process technology ordering information
Removed µBGA CSP information
Datasheet
5
28F320J5 and 28F640J5
6
Datasheet
28F320J5 and 28F640J5
1.0
Product Overview
The Intel StrataFlash® memory family contains high-density memories organized as 8 Mbytes or 4
Mwords (64-Mbit) and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or
16-bit words. The 64-Mbit device is organized as sixty-four 128-Kbyte (131,072 bytes) erase
blocks while the 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks are
selectively and individually lockable and unlockable in-system. See the memory map in Figure 4
on page 12.
A Common Flash Interface (CFI) permits software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-
compatible software support for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work
with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes device and system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor and
internal operation of the device. A valid command sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase, program, and lock-bit configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second—
independent of other blocks. Each block can be independently erased 100,000 times. Block erase
suspend mode allows system software to suspend block erase to read or program data from any
other block.
Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming
performance. By using the Write Buffer, data is programmed in buffer increments. This feature can
improve system program performance by up to 20 times over non-Write Buffer writes.
Individual block locking uses a combination of bits, block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase and program operations while the master lock-
bit gates block lock-bit modification. Three lock-bit configuration operations set and clear lock-bits
(Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands).
The status register indicates when the WSM’s block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional indicator of WSM activity by providing both a
hardware signal of status (versus software polling) and status masking (interrupt masking for
background block erase, for example). Status indication using STS minimizes both CPU overhead
and system power consumption. When configured in level mode (default mode), it acts as a RY/
BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit
configuration. STS-high indicates that the WSM is ready for a new command, block erase is
suspended (and programming is inactive), or the device is in reset/power-down mode.
Additionally, the configuration command allows the STS pin to be configured to pulse on
completion of programming and/or block erases.
Datasheet
7
28F320J5 and 28F640J5
Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2,
“Chip Enable Truth Table” on page 12) reduces decoder logic typically required for multi-chip
designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip
miniature card or SIMM module.
The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit
mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16-bit
operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A
device block diagram is shown in Figure 1.
When the device is disabled (see Table 2 on page 12) and the RP# pin is at VCC, the standby mode
is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (tPHQV) is required
from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHWL
)
from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the
status register is cleared.
The Intel StrataFlash memory devices are available in several package types. The 64-Mbit is
available in 56-lead SSOP (Shrink Small Outline Package) and µBGA* package (micro Ball Grid
Array). The 32-Mbit is available in 56-lead TSOP (Thin Small Outline Package) and 56-lead
SSOP. Figures 2, 3, and 4 show the pinouts.
Figure 1. Intel StrataFlash® Memory Block Diagram
DQ0 - DQ15
VCCQ
Output Buffer
Input Buffer
VCC
BYTE#
Query
I/O Logic
CE0
CE1
CE2
WE#
OE#
RP#
Identifier
Register
CE
Logic
Command
User
Interface
Status
Register
Multiplexer
Data
Comparator
Y-Decoder
X-Decoder
Y-Gating
STS
32-Mbit: A0- A21
64-Mbit: A0 - A22
Input Buffer
Write State
Machine
VPEN
Program/Erase
Voltage Switch
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Kbyte Blocks
Address
Latch
VCC
GND
Address
Counter
8
Datasheet
28F320J5 and 28F640J5
Table 1. Lead Descriptions
Symbol
Type
Name and Function
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.
A
INPUT
This address is latched duringa x8 program cycle. Not used in x16 mode (i.e., the A input buffer
0
0
is turned off when BYTE# is high).
ADDRESS INPUTS: Inputs for addresses duringread and program operations. Addresses are
internally latched duringa program cycle.
A –A
INPUT
1
22
32-Mbit: A –A
0
21
22
64-Mbit: A –A
0
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs
commands duringCommand User Interface (CUI) writes. Outputs array, query, identifier, or status
data in the appropriate read mode. Floated when the chip is de-selected or the outputs are
INPUT/
OUTPUT
DQ –DQ
0
7
disabled. Outputs DQ –DQ are also floated when the Write State Machine (WSM) is busy. Check
6
0
SR.7 (status register bit 7) to determine WSM status.
HIGH-BYTE DATA BUS: Inputs data duringx16 buffer writes and programmingoperations.
Outputs array, query, or identifier data in the appropriate read mode; not used for status register
reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy.
INPUT/
OUTPUT
DQ –DQ
8
15
CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. When the device is de-selected (see Table 2 on pag e 12, power reduces to standby
levels.
CE ,
0
CE ,
INPUT
INPUT
1
2
All timingspecifications are the same for these three signals. Device selection occurs with the first
CE
edge of CE , CE , or CE that enables the device. Device deselection occurs with the first edge of
0
1
2
CE , CE , or CE that disables the device (see Table 2).
0
1
2
RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode.
RP#-high enables normal operation. Exit from reset sets the device to read array mode. When
driven low, RP# inhibits write operations which provides data protection duringpower transitions.
RP#
RP# at V enables master lock-bit settingand block lock-bits configuration when the master
HH
lock-bit is set. RP# = V overrides block lock-bits thereby enablingblock erase and
programming operations to locked memory blocks. Do not permanently connect RP# to V
HH
.
HH
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
OE#
WE#
INPUT
INPUT
WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array
blocks. WE# is active low. Addresses and data are latched on the risingedge of the WE# pulse.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the STATUS pin, see
OPEN
DRAIN
OUTPUT
STS
the Configurations command. Tie STS to V
with a pull-up resistor.
CCQ
BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on
DQ –DQ , while DQ –DQ float. Address A selects between the high and low byte. BYTE# high
0
7
8
15
0
BYTE#
INPUT
places the device in x16 mode, and turns off the A input buffer. Address A then becomes the
0
1
lowest order address.
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasingarray blocks, programmingdata, or
configuring lock-bits.
V
INPUT
PEN
With V
≤ V
, memory contents cannot be altered.
PENLK
PEN
V
V
SUPPLY
DEVICE POWER SUPPLY: With V ≤ V
, all write attempts to the flash memory are inhibited.
LKO
CC
CC
OUTPUT
BUFFER
SUPPLY
OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output voltages. To
obtain output voltages compatible with system data bus voltages, connect V
supply voltage.
to the system
CCQ
CCQ
GND
NC
SUPPLY
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
Datasheet
9
28F320J5 and 28F640J5
Figure 2. TSOP Lead Configuration (32 Mbit)
28F016SV
28F016SA
28F016SV
28F016SA
28F160S5
28F032SA 28F320J5
28F320J5 28F032SA
28F160S5
WP#
WE#
OE#
RY/BY#
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ3
DQ10
DQ2
VCC
WP#
WE#
OE#
WP#
WE#
OE#
NC
NC
CE1
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
3/5#
CE1
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
3/5#
CE1
CE2
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
NC
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WE#
OE#
STS
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCCQ
GND
DQ11
DQ3
DQ10
DQ2
VCC
RY/BY# STS
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Intel StrataFlash® Memory
56-Lead TSOP
Standard Pinout
14 mm x 20 mm
Top View
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC
NC
NC
CE2
Highlights pinout changes
NOTES:
1. V (Pin 37) and GND (Pin 48) are not internally connected. For future device revisions, it is recommended
CC
that these pins be connected to their respected power supplies (i.e., Pin 37 = V and Pin 48 = GND).
CC
2. For compatibility with future generations of Intel StrataFlash® memory, this NC (pin 56) should be connected
to GND.
Figure 3. SSOP Lead Configuration (64 Mbit and 32 Mbit)
28F016SA
28F016SV
28F016SA
28F016SV
28F160S5 28F320S5 28F640J5 28F320J5
28F320J5 28F640J5 28F320S5 28F160S5
CE0#
A12
CE0#
A12
CE0#
A12
CE0
A12
A13
CE0
A12
A13
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VPEN
RP#
A11
A10
A9
A1
VPEN
RP#
A11
A10
A9
A1
VPP
RP#
A11
A10
A9
A1
VPP
RP#
A11
A10
A9
A1
VPP
RP#
A11
A10
A9
A1
A13
A13
A13
3
A14
A14
A14
A14
A14
4
A15
A15
A15
A15
A15
5
3/5#
CE1#
NC
A20
A19
A18
A17
A16
VCC
GND
DQ6
DQ14
DQ7
DQ15
RY/BY#
OE#
WE#
WP#
DQ13
DQ5
DQ12
DQ4
VCC
NC
CE1#
NC
A20
A19
A18
A17
A16
VCC
GND
DQ6
DQ14
DQ7
DQ15
RY/BY#
OE#
WE#
WP#
DQ13
DQ5
DQ12
DQ4
VCC
NC
CE1#
A21
A20
A19
A18
A17
A16
VCC
GND
DQ6
DQ14
DQ7
DQ15
RY/BY#
OE#
WE#
WP#
DQ13
DQ5
DQ12
DQ4
VCC
A22
CE1
A21
A20
A19
A18
A17
A16
NC
CE1
A21
A20
A19
A18
A17
A16
6
7
A2
A2
A2
A2
A2
8
A3
A3
A3
A3
A3
9
A4
A4
A4
A4
A4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A5
A5
A5
A5
A5
Intel
A6
A6
A6
A6
A6
StrataFlash® Memory
56-Lead SSOP
A7
A7
A7
A7
A7
GND
A8
GND
A8
GND
A8
GND
A8
GND
A8
Standard Pinout
VCC
VCC
GND
DQ6
DQ14
DQ7
DQ15
STS
OE#
WE#
NC
GND
DQ6
DQ14
DQ7
DQ15
STS
OE#
WE#
NC
VCC
DQ9
DQ1
DQ8
DQ0
A0
VCC
DQ9
DQ1
DQ8
DQ0
A0
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC
DQ2
DQ10
DQ3
DQ11
GND
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC
DQ2
DQ10
DQ3
DQ11
GND
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC
DQ2
DQ10
DQ3
DQ11
GND
16 mm x 23.7 mm
Top View
BYTE#
NC
BYTE#
NC
CE2
DQ2
DQ10
DQ3
DQ11
GND
CE2
DQ2
DQ10
DQ3
DQ11
GND
DQ13
DQ5
DQ12
DQ4
VCCQ
DQ13
DQ5
DQ12
DQ4
VCCQ
Highlights pinout changes.
NOTES:
1. V (Pin 42) and GND (Pin 15) are not internally connected. For future device revisions, it is recommended
CC
that these pins be connected to their respected power supplies (i.e., Pin 42 = V and Pin 15 = GND).
CC
2. For compatibility with future generations of Intel StrataFlash® memory, this NC (pin 23) should be connected
to GND.
10
Datasheet
28F320J5 and 28F640J5
2.0
Principles of Operation
The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program,
and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power
supplies during block erasure, program, lock-bit configuration, and minimal processor overhead
with RAM-like interface timings.
After initial device power-up or return from reset/power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of external memory control pins allows array
read, standby, and output disable operations.
Read array, status register, query, and identifier codes can be accessed through the CUI (Command
User Interface) independent of the VPEN voltage. VPENH on VPEN enables successful block
erasure, programming, and lock-bit configuration. All functions associated with altering memory
contents—block erase, program, lock-bit configuration—are accessed via the CUI and verified
through the status register.
Commands are written using standard micro-processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase, program, and lock-bit configuration. The
internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and
margining of data. Addresses and data are internally latched during program cycles.
Interface software that initiates and polls progress of block erase, program, and lock-bit
configuration can be stored in any block. This code is copied to and executed from system RAM
during flash memory updates. After successful completion, reads are again possible via the Read
Array command. Block erase suspend allows system software to suspend a block erase to read or
program data from/to any other block.
2.1
Data Protection
Depending on the application, the system designer may choose to make the VPEN switchable
(available only when memory block erases, programs, or lock-bit configurations are required) or
hardwired to VPENH. The device accommodates either design practice and encourages
optimization of the processor-memory interface.
When VPEN ≤ VPENLK, memory contents cannot be altered. The CUI’s two-step block erase, byte/
word program, and lock-bit configuration command sequences provide protection from unwanted
operations even when VPENH is applied to VPEN. All program functions are disabled when VCC is
below the write lockout voltage VLKO or when RP# is VIL. The device’s block locking capability
provides additional protection from inadvertent code or data alteration by gating erase and program
operations.
Datasheet
11
28F320J5 and 28F640J5
3.0
Bus Operation
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus cycles.
Figure 4. Memory Map
A [22-0]: 64-Mbit
A [21-0]: 32-Mbit
A [22-1]: 64-Mbit
A [21-1]: 32-Mbit
3FFFFF
7FFFFF
128-Kbyte Block
128-Kbyte Block
64-Kword Block
64-Kword Block
63
31
63
31
7E0000
3F0000
3FFFFF
3E0000
1FFFFF
1F0000
03FFFF
01FFFF
128-Kbyte Block
128-Kbyte Block
64-Kword Block
64-Kword Block
1
0
1
0
020000
01FFFF
010000
00FFFF
000000
000000
Byte-Wide (x8) Mode
Word Wide (x16) Mode
Table 2. Chip Enable Truth Table
CE
CE
CE
0
DEVICE
2
1
V
V
V
V
V
V
V
IL
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
IL
IL
V
IH
IL
IL
IL
IH
IH
V
V
V
IL
V
IL
IH
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
V
IH
V
V
IH
IH
IL
V
V
IH
NOTES:
1. See Application Note, AP-647 5 Volt Intel StrataFlash® Memory Design Guide for typical CE configurations.
2. For single-chip applications CE and CE can be strapped to GND.
2
1
12
Datasheet
28F320J5 and 28F640J5
3.1
Read
Information can be read from any block, query, identifier codes, or status register independent of
the VPEN voltage. RP# can be at either VIH or VHH
.
Upon initial device power-up or after exit from reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read
Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control pins dictate the data
flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be
enabled (see Table 2), and OE# must be driven active to obtain data at the outputs. CE0, CE1, and
CE2 are the device selection controls and, when enabled (see Table 2), select the memory device.
OE# is the data output (DQ0–DQ15) control and, when active, drives the selected memory data
onto the I/O bus. WE# must be at VIH.
3.2
3.3
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
Standby
CE0, CE1, and CE2 can disable the device (see Table 2) and place it in standby mode which
substantially reduces device power consumption. DQ0–DQ15 outputs are placed in a high-
impedance state independent of OE#. If deselected during block erase, program, or lock-bit
configuration, the WSM continues functioning, and consuming active power until the operation
completes.
3.4
Reset/Power-Down
RP# at VIL initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and status register is
set to 80H.
During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In
default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the
reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during block erase, program, or lock-bit configuration modes. If
a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
Datasheet
13
28F320J5 and 28F640J5
flash memory may be providing status information instead of array data. Intel® Flash memories
allow proper initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.5
3.6
Read Query
The read query operation outputs block status information, CFI (Common Flash Interface) ID
string, system interface information, device geometry information, and Intel-specific extended
query information.
Read Identifier Codes
The read identifier codes operation outputs the manufacturer code, device code, block lock
configuration codes for each block, and the master lock configuration code (see Figure 5). Using
the manufacturer and device codes, the system CPU can automatically match the device with its
proper algorithms. The block lock and master lock configuration codes identify locked and
unlocked blocks and master lock-bit setting.
14
Datasheet
28F320J5 and 28F640J5
Figure 5. Device Identifier Code Memory Map
Word
Address
A[22-1]: 64 Mbit
A[21-1]: 32 Mbit
3FFFFF
Block 63
Reserved for Future
Implementation
3F0003
3F0002
Block 63 Lock Configuration
Reserved for Future
Implementation
3F0000
3EFFFF
(Blocks 32 through 62)
Block 31
Reserved for Future
Implementation
1F0003
1F0002
Block 31 Lock Configuration
Reserved for Future
Implementation
1F0000
1EFFFF
(Blocks 2 through 30)
01FFFF
Block 1
Reserved for Future
Implementation
010003
010002
Block 1 Lock Configuration
Reserved for Future
Implementation
010000
00FFFF
Block 0
Reserved for Future
Implementation
000004
000003
000002
000001
000000
Master Lock Configuration
Block 0 Lock Configuration
Device Code
Manufacturer Code
NOTE: A is not used in either x8 or x16 modes when obtainingthese identifier codes. Data is always given on
0
the low byte in x16 mode (upper byte contains 00h).
Datasheet
15
28F320J5 and 28F640J5
3.7
Write
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection
and clearing of the status register, and, when VPEN = VPENH, block erasure, program, and lock-bit
configuration.
The Block Erase command requires appropriate command data and an address within the block to
be erased. The Byte/Word Program command requires the command and address of the location to
be written. Set Master and Block Lock-Bit commands require the command and address within the
device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-
Bits command requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 2 on
page 12). Standard microprocessor write timings are used.
Table 3. Bus Operations
STS
(default
mode)
(1)
Mode
Notes
RP#
CE
OE#(2) WE#(2) Address
V
DQ(3)
0,1,2
PEN
Read Array
Output Disable
Standby
4,5,6
V
V
V
or V
or V
or V
Enabled
Enabled
Disabled
V
V
V
X
X
X
X
X
X
D
High Z(7)
IH
IH
IH
HH
HH
HH
IL
IH
OUT
V
Hig
h Z
X
IH
IH
X
X
High Z
X
Reset/Power-
Down Mode
(7)
V
X
X
X
X
X
X
X
X
Hig h Z
Note 8
Note 9
Hig h Z
IL
Read Identifier
Codes
See
Figure 5
(7)
V
V
V
or V
or V
or V
Enabled
Enabled
Enabled
V
V
Hig h Z
IH
IH
IH
HH
HH
HH
IL
IL
IL
IH
IH
IH
See
Table 7
(7)
Read Query
V
V
V
V
Hig h Z
Read Status
(WSM off)
X
D
OUT
DQ = D
7
OUT
Read Status
(WSM on)
V
V
or V
or V
Enabled
Enabled
V
V
X
X
V
DQ
DQ
= Hig h Z
= Hig h Z
IH
IH
HH
HH
IL
IH
PENH
15–8
6–0
Write
6,10,11
V
V
X
D
IN
X
IH
IL
NOTES:
1. See Table 2 for valid CE configurations.
2. OE# and WE# should never be enabled simultaneously.
3. DQ refers to DQ –DQ if BYTE# is low and DQ –DQ if BYTE# is high.
0
7
0
15
4. Refer to DC Characteristics. When V
≤ V
, memory contents can be read, but not altered.
PEN
PENLK
5. X can be V or V for control and address pins, and V
or V
for V
. See DC Characteristics for
IL
and V
IH
PENLK
PENH
PEN
V
voltages.
PENLK
PENH
6. In default mode, STS is V when the WSM is executinginternal block erase, program, or lock-bit
OL
configuration algorithms. It is V when the WSM is not busy, in block erase suspend mode (with
programming inactive), or reset/power-down mode.
OH
7. High Z will be V with an external pull-up resistor.
OH
8. See Read Identifier Codes Command section for read identifier code data.
9. See Read Query Mode Command section for read query data.
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when V
=
PEN
V
and V is within specification. Block erase, program, or lock-bit configuration with V < RP# < V
PENH
CC IH HH
produce spurious results and should not be attempted.
11.Refer to Table 4 for valid D duringa write operation.
IN
16
Datasheet
28F320J5 and 28F640J5
4.0
Command Definitions
When the VPEN voltage ≤ VPENLK, only read operations from the status register, query, identifier
codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program,
and lock-bit configuration operations.
Device operations are selected by writing specific commands into the CUI. Table 4 defines these
commands.
Table 4. Intel StrataFlash® Memory Command Set Definitions(1,2)
Scaleable
Bus
or Basic
Command
Cycles
Req’d.
Notes
First Bus Cycle
Second Bus Cycle
Command
Set(2)
Oper(3)
Addr(4)
Data(5,6)
Oper(3)
Addr(4)
Data(5,6)
Read Array
SCS/BCS
SCS/BCS
SCS
1
Write
X
FFH
Read Identifier
Codes
≥ 2
≥ 2
2
7
8
Write
Write
Write
X
X
X
90H
98H
70H
Read
Read
Read
IA
QA
X
ID
Read Query
QD
Read Status
Register
SCS/BCS
SRD
Clear Status
Register
SCS/BCS
SCS/BCS
1
Write
Write
X
50H
E8H
9, 10,
11
Write to Buffer
> 2
BA
Write
BA
N
40H
or
10H
Word/Byte
Program
SCS/BCS
SCS/BCS
SCS/BCS
2
2
1
12,13
11,12
12,14
Write
Write
Write
X
X
X
Write
Write
PA
BA
PD
Block Erase
20H
D0H
Block Erase,
Program
B0H
Suspend
Block Erase,
Program
Resume
SCS/BCS
SCS
1
12
Write
X
D0H
Configuration
2
2
Write
Write
X
X
B8H
60H
Write
Write
X
CC
Set Read
Configuration
RCD
03H
Set Block Lock-
Bit
SCS
SCS
2
2
2
Write
Write
Write
X
X
X
60H
60H
C0H
Write
Write
Write
BA
X
01H
D0H
PD
Clear Block
Lock-Bits
15
Protection
Program
PA
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
2. If the WSM is running, only DQ is valid; DQ –DQ and DQ –DQ float, which places them in a hig h-
7
15
8
6
0
impedance state.
Datasheet
17
28F320J5 and 28F640J5
3. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command
Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
4. Bus operations are defined in Table 3.
5. X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see Figure 5 and Table 13.
QA = Query database Address.
PA = Address of memory location to be programmed.
6. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register. See Table 16 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code.
7. The upper byte of the data bus (DQ –DQ ) duringcommand writes is a “Don’t Care” in x16 operation.
8
15
8. Followingthe Read Identifier Codes command, read operations access manufacturer, device, block lock, and
master lock codes. See Read Identifier Codes Command section for read identifier code data.
9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument.
Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =
000FH. The third and consecutive bus cycles, as determined by N, are for writingdata into the Write Buffer.
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in
the sequence aborts the write to buffer operation. Please see Fig ure 6, “Write to Buffer Flowchart” on
page 32, for additional information.
11.Programmingthe write buffer to flash or initiatingthe erase operation does not begin until a confirm
command (D0h) is issued.
12.If the block is locked, RP# must be at V to enable block erase or program operations. Attempts to issue a
HH
block erase or program to a locked block while RP# is V will fail.
IH
13.Either 40H or 10H are recognized by the WSM as the byte/word program setup.
14.If the master lock-bit is set, RP# must be at V to set a block lock-bit. RP# must be at V to set the master
HH
HH
lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is V
.
IH
15.If the master lock-bit is set, RP# must be at V to clear block lock-bits. The clear block lock-bits operation
HH
simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command
can be done while RP# is V
.
IH
4.1
4.2
Read Array Command
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to
read array mode. This operation is also initiated by writing the Read Array command. The device
remains enabled for reads until another command is written. Once the internal WSM has started a
block erase, program, or lock-bit configuration, the device will not recognize the Read Array
command until the WSM completes its operation unless the WSM is suspended via an Erase
Suspend command. The Read Array command functions independently of the VPEN voltage and
RP# can be VIH or VHH
.
Read Query Mode Command
This section defines the data structure or “database” returned by the Common Flash Interface (CFI)
Query command. System software should parse this structure to gain critical information such as
block size, density, x8/x16, and electrical specifications. Once this information has been obtained,
the software will know which command sets to use to enable flash writes, block erases, and
otherwise control the flash component. The Query is part of an overall specification for multiple
command set and control interface descriptions called Common Flash Interface, or CFI.
18
Datasheet
28F320J5 and 28F640J5
4.2.1
Query Structure Output
The Query “database” allows system software to gain information for controlling the flash
component. This section describes the device’s CFI-compliant interface that allows the host system
to access Query data.
Query data are always presented on the lowest-order data outputs (DQ0–DQ7) only. The numerical
offset value is the address relative to the maximum bus width supported by the device. On this
family of devices, the Query table device starting address is a 10h, which is a word address for x16
devices.
For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H
data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ0–DQ7) and 00h in
the high byte (DQ8–DQ15).
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 5. Summary of Query Structure Output as a Function of Device and Mode
Device
Type/
Mode
Query start location in
maximum device bus
width addresses
Query data w ith maximum
device bus width addressing
Query data w ith byte
addressing
Hex
Offset
Hex
Code
ASCII
Value
Hex
Offset
Hex
Code
ASCII
Value
x16 device
x16 mode
10h
10:
11:
12:
0051
0052
0059
“Q”
“R”
“Y”
20:
21:
22:
20:
21:
22:
51
00
52
51
51
52
“Q”
“Null”
“R”
“Q”
“Q”
x16 device
x8 mode
N/A(1)
N/A(1
“R”
NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is
configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the
system, is "Not Applicable" for x8-configured devices.
Datasheet
19
28F320J5 and 28F640J5
Table 6. Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing
Hex Code
Byte Addressing
Hex Code
Offset
–A
Value
Offset
Value
A
D
–D
A –A
D –D
7 0
15
0
15
0
7
0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
0051
0052
0059
“Q”
“R”
“Y”
20h
21h
22h
23h
24h
25h
26h
27h
28h
...
51
51
52
52
59
59
P_ID
P_ID
P_ID
...
“Q”
“Q”
“R”
“R”
“Y”
P_ID
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
LO
P_ID
HI
P
“Y”
LO
P
PrVendor
ID #
ID #
...
HI
LO
LO
A_ID
LO
A_ID
...
HI
HI
...
4.2.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” See AP-646 Common Flash Interface (CFI) and Command Sets
(order number 292204) for a full description of CFI.
The following sections describe the Query structure sub-sections in detail.
Table 7. Query Structure(1)
Offset
Sub-Section Name
Description
00h
01h
Manufacturer Code
Device Code
(BA+2)h(2)
04-0Fh
10h
Block Status Register
Reserved
Block-Specific Information
Reserved for Vendor-Specific Information
CFI Query Identification StringReserved for Vendor-Specific Information
1Bh
System Interface Information
Device Geometry Definition
Command Set ID and Vendor Data Offset
Flash Device Layout
27h
Primary Intel-Specific
Extended Query Table
Vendor-Defined Additional Information Specific to the Primary
Vendor Algorithm
P(3)
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is
128 Kbyte).
3. Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table.
20
Datasheet
28F320J5 and 28F640J5
4.2.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations.
Block Erase Status (BSR.1) allows system software to determine the success of the last block erase
operation. BSR.1 can be used just after power-up to verify that the VCC supply was not
accidentally removed during an erase operation. This bit is only reset by issuing another erase
operation to the block. The Block Status Register is accessed from word address 02h within each
block.
Table 8. Block Status Register
Offset
(BA+2)h(1)
Length
Description
Block Lock Status Register
Address
Value
1
BA+2:
--00 or --01
BSR.0 Block Lock Status
0 = Unlocked
BA+2:
(bit 0): 0 or 1
1 = Locked
BSR.1 Block Erase Status
0 = Last erase operation completed successfully
1 = Last erase operation did not complete successfully
BA+2:
BA+2:
(bit 1): 0 or 1
(bit 2–7): 0
BSR 2–7: Reserved for Future Use
NOTE:
1. BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64-KB block) beginning location
in word mode).
4.2.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s).
Table 9. CFI Identification
Hex
Code
Offset Length
Description
Query-unique ASCII string“QRY”
Add.
Value
10h
3
10
--51
--52
--59
--01
--00
--31
--00
--00
--00
--00
--00
“Q”
“R”
“Y”
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
13h
15h
17h
19h
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
Datasheet
21
28F320J5 and 28F640J5
4.2.5
System Interface Information
The following device information can optimize system interface software.
Table 10. System Interface Information
Hex
Code
Offset Length
Description
Add.
Value
V
V
V
V
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1Bh
1Ch
1Dh
1Eh
1
1
1
1
1B:
--45
--55
--00
--00
4.5 V
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1C:
1D:
1E:
5.5 V
0.0 V
0.0 V
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
1Fh
20h
21h
22h
1
1
1
1
“n” such that typical single word program time-out = 2n µs
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
“n” such that typical full chip erase time-out = 2n ms
1F:
20:
21:
22:
--07
--07
--0A
--00
128 µs
128 µs
1 s
NA
“n” such that maximum word program time-out = 2n times
typical
23h
1
23:
--04
2 ms
24h
25h
26h
1
1
1
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
24:
25:
26:
--04
--04
--00
2 ms
16 s
NA
22
Datasheet
28F320J5 and 28F640J5
4.2.6
Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 11. Device Geometry Definition
Code See Table
Below
Offset Length
27h
28h
Description
“n” such that device size = 2n in number of bytes
1
27:
x8/
x16
2
Flash device interface: x8 async x16 async x8/x16 async
28:
--02
28:00,29:00 28:01,29:00 28:02,29:00
29:
2A:
2B:
--00
--05
--00
2Ah
2
“n” such that maximum number of bytes in write buffer = 2n
32
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions with one or
more contiguous same-size erase blocks
3. Symmetrically blocked partitions have one blockingregion
4. Partition size = (total blocks) x (individual block size)
2Ch
2Dh
1
4
2C:
--01
1
Erase Block Region 1 Information
2D:
2E:
2F:
30:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Table 12. Device Geometry Definition
128 Mbit
(Info Only
Address
32 Mbit
64 Mbit
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
--16
--02
--00
--05
--00
--01
--1F
--00
--00
--02
--17
--02
--00
--05
--00
--01
--3F
--00
--00
--02
--18
--02
--00
--05
--00
--01
--7F
--00
--00
--02
4.2.7
Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query
table specifies this and other similar information.
Datasheet
23
28F320J5 and 28F640J5
Table 13. Primary Vendor-Specific Extended Query
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
Primary extended query table
Unique ASCII string“PRI”
31:
32:
33:
34:
35:
36:
37:
38:
39:
bit 0 = 0
bit 1 = 1
bit 2 = 0
bit 3 = 1
bit 4 = 0
--50
--52
--49
--31
--31
--0A
--00
--00
--00
No
“P”
“R”
“I”
“1”
“1”
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 9–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of optional features follows at
the end of the bit-30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
Yes
No
Yes
No
Supported functions after suspend: read Array, Status,
Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
(P+9)h
1
2
3A:
--01
bit 0 = 1
3B:
3C:
bit 0 = 1
bit 1 = 0
Yes
--01
--00
Yes
No
(P+A)h
(P+B)h
V
logic supply highest performance program/erase
CC
voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
optimum program/erase supply voltage
(P+C)h
1
1
3D:
--50
--00
5.0 V
0.0 V
V
PP
(P+D)h
(P+E)h
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Reserved for Future Use
3E:
3F:
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.
4.3
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following
the command write, read cycles from addresses shown in Figure 5 retrieve the manufacturer,
device, block lock configuration and master lock configuration codes (see Table 13 for identifier
code values). To terminate the operation, write another valid command. Like the Read Array
command, the Read Identifier Codes command functions independently of the VPEN voltage and
RP# can be VIH or VHH. This command is valid only when the WSM is off or the device is
suspended. Following the Read Identifier Codes command, the following information can be read:
24
Datasheet
28F320J5 and 28F640J5
Table 14. Identifier Codes
Code
Address(1)
Data
Manufacture Code
Device Code
00000
00001
(00) 89
(00) 14
32-Mbit
64-Mbit
00001
(00) 15
Block Lock Configuration
• Block Is Unlocked
X0002(2)
DQ = 0
0
• Block Is Locked
DQ = 1
0
• Reserved for Future Use
Master Lock Configuration
• Device Is Unlocked
• Device Is Locked
DQ
1–7
00003
DQ = 0
0
DQ = 1
0
• Reserved for Future Use
DQ
1–7
NOTES:
1. A is not used in either x8 or x16 modes when obtainingthe identifier codes. The lowest order address line is
0
A . Data is always presented on the low byte in x16 mode (upper byte contains 00h).
1
2. X selects the specific block’s lock configuration code. See Figure 5 for the device identifier code memory
map.
4.4
Read Status Register Command
The status register may be read to determine when a block erase, program, or lock-bit configuration
is complete and whether the operation completed successfully. It may be read at any time by
writing the Read Status Register command. After writing this command, all subsequent read
operations output data from the status register until another valid command is written. The status
register contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that
enables the device (see Table 2). OE# must toggle to VIH or the device must be disabled (Table 2)
before further reads to update the status register latch. The Read Status Register command
functions independently of the VPEN voltage. RP# can be VIH or VHH
.
During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid
until the WSM completes or suspends the operation. Device I/O pins DQ0–DQ6 and DQ8–DQ15
are placed in a high-impedance state. When the operation completes or suspends (check status
register bit 7), all contents of the status register are valid when read.
4.5
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits indicate various failure conditions (see Table 16).
By allowing system software to reset these bits, several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in sequence) may be performed. The status register
may be polled to determine if an error occurred during the sequence.
To clear the status register, the Clear Status Register command (50H) is written. It functions
independently of the applied VPEN voltage. RP# can be VIH or VHH. The Clear Status Register
command is only valid when the WSM is off or the device is suspended.
Datasheet
25
28F320J5 and 28F640J5
4.6
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
first written, followed by an block erase confirm. This command sequence requires an appropriate
address within the block to be erased (erase changes all block data to FFH). Block preconditioning,
erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle
block erase sequence is written, the device automatically outputs status register data when read (see
Figure 8, “Block Erase Flowchart” on page 34). The CPU can detect block erase completion by
analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE0, CE1, or CE2 to
update the status register.
When the block erase is complete, status register bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared before system software attempts corrective actions.
The CUI remains in read status register mode until a new command is issued.
This two-step command sequence of set-up followed by execution ensures that block contents are
not accidentally erased. An invalid Block Erase command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when VCC
is valid and VPEN = VPENH. If block erase is attempted while VPEN ≤ VPENLK, SR.3 and SR.5 will
be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared or, if
set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and
RP# = VIH, SR.1 and SR.5 will be set to “1.” Block erase operations with VIH < RP# < VHH
produce spurious results and should not be attempted.
4.7
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or program data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs status register data when read after the Block Erase Suspend
command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase
operation has been suspended (both will be set to “1”). In default mode, STS will also transition to
VOH. Specification tWHRH defines the block erase suspend latency.
At this point, a Read Array command can be written to read data from blocks other than that which
is suspended. A program command sequence can also be issued during erase suspend to program
data in other blocks. During a program operation with block erase suspended, status register bit
SR.7 will return to “0” and the STS output (in default mode) will transition to VOL
.
The only other valid commands while block erase is suspended are Read Query, Read Status
Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to VOL
.
After the Erase Resume command is written, the device automatically outputs status register data
when read (see Figure 9, “Block Erase Suspend/Resume Flowchart” on page 35). VPEN must
remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. RP#
must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot
resume until program operations initiated during block erase suspend have completed.
26
Datasheet
28F320J5 and 28F640J5
4.8
Write to Buffer Command
To program the flash device, a Write to Buffer command sequence is initiated. A variable number
of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the
Write to Buffer setup command is issued along with the Block Address (see Figure 6, “Write to
Buffer Flowchart” on page 32). At this point, the eXtended Status Register (XSR, see Table 17,
“Status Register Definition” on page 31) information is loaded and XSR.7 reverts to “buffer
available” status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring
XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1.
When XSR.7 transitions to a “1,” the buffer is ready for loading.
Now a word/byte count is given to the part with the Block Address. On the next write, a device
start address is given along with the write buffer data. Subsequent writes provide additional device
addresses and data, depending on the count. All subsequent addresses must lie within the start
address plus the count.
Internally, this device programs many flash cells in parallel. Because of this parallel programming,
maximum programming performance and lower power are obtained by aligning the start address at
the beginning of a write buffer boundary (i.e., A4–A0 of the start address = 0).
After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM
(Write State Machine) to begin copying the buffer data to the flash array. If a command other than
Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated
and status register bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue
another Write to Buffer setup command and check XSR.7.
If an error occurs while writing, the device will stop writing, and status register bit SR.4 will be set
to a “1” to indicate a program failure. The internal WSM verify only detects errors for “1”s that do
not successfully program to “0”s. If a program error is detected, the status register should be
cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an
erase), the device will not accept any more Write to Buffer commands. Additionally, if the user
attempts to program past an erase block boundary with a Write to Buffer command, the device will
abort the write to buffer operation. This will generate an “Invalid Command/Sequence” error and
status register bits SR.5 and SR.4 will be set to a “1.”
Reliable buffered writes can only occur when VPEN = VPENH. If a buffered write is attempted
while VPEN ≤ VPENLK, status register bits SR.4 and SR.3 will be set to “1.” Buffered write attempts
with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally,
successful programming requires that the corresponding Block Lock-Bit be reset or, if set, that RP#
= VHH. If a buffered write is attempted when the corresponding Block Lock-Bit is set and RP# =
VIH, SR.1 and SR.4 will be set to “1.” Buffered write operations with VIH < RP# < VHH produce
spurious results and should not be attempted.
4.9
Byte/Word Program Commands
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup
(standard 40H or alternate 10H) is written followed by a second write that specifies the address and
data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and
program verify algorithms internally. After the program sequence is written, the device
automatically outputs status register data when read (see Figure 7, “Byte/Word Program
Flowchart” on page 33). The CPU can detect the completion of the program event by analyzing the
STS pin or status register bit SR.7.
Datasheet
27
28F320J5 and 28F640J5
When program is complete, status register bit SR.4 should be checked. If a program error is
detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s
that do not successfully program to “0”s. The CUI remains in read status register mode until it
receives another command.
Reliable byte/word programs can only occur when VCC and VPEN are valid. If a byte/word
program is attempted while VPEN ≤ VPENLK, status register bits SR.4 and SR.3 will be set to “1.”
Successful byte/word programs require that the corresponding block lock-bit be cleared or, if set,
that RP# = VHH. If a byte/word program is attempted when the corresponding block lock-bit is set
and RP# = VIH, SR.1 and SR.4 will be set to “1.” Byte/word program operations with VIH < RP# <
VHH produce spurious results and should not be attempted.
4.10
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once
the STS pin has been configured, it remains in that configuration until another configuration
command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation
where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state
machine is ready for a new operation or suspended. Table 15, “Write Protection Alternatives” on
page 30 displays the possible STS configurations.
To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed
by the desired configuration code. The three alternate configurations are all pulse mode for use as a
system interrupt as described below. For these configurations, bit 0 controls Erase Complete
interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h
configuration code with the Configuration command resets the STS pin to the default RY/BY#
level mode. The possible configurations and their usage are described in Table 15. The
Configuration command may only be given when the device is not busy or suspended. Check SR.7
for device status. An invalid configuration code will result in both status register bits SR.4 and
SR.5 being set to “1.” When configured in one of the pulse modes, the STS pin pulses low with a
typical pulse width of 250 ns.
4.11
Set Block and Master Lock-Bit Commands
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and
a master lock-bit. Out of the factory, the block lock-bits and the master lock-bit are unlocked. The
block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit
modification. With the master lock-bit not set, individual block lock-bits can be set using the Set
Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = VHH
sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits
requires both the Set Block Lock-Bit command and VHH on the RP# pin. These commands are
,
invalid while the WSM is running or the device is suspended. See Table 14, “Identifier Codes” on
page 25 for a summary of hardware and software write protection options.
Set block lock-bit and master lock-bit commands are executed by a two-cycle sequence. The set
block or master lock-bit setup along with appropriate block or device address is written followed
by either the set block lock-bit confirm (and an address within the block to be locked) or the set
master lock-bit confirm (and any device address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device automatically outputs status register data when
read (see Figure 10, “Set Block Lock-Bit Flowchart” on page 36). The CPU can detect the
completion of the set lock-bit event by analyzing the STS pin output or status register bit SR.7.
28
Datasheet
28F320J5 and 28F640J5
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared. The CUI will remain in read status register mode
until a new command is issued.
This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and
SR.5 being set to “1.” Also, reliable operations occur only when VCC and VPEN are valid. With
V
PEN ≤ VPENLK, lock-bit contents are protected against alteration.
A successful set block lock-bit operation requires that the master lock-bit be zero or, if the master
lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1
and SR.4 will be set to “1” and the operation will fail. Set block lock-bit operations while VIH
<
RP# < VHH produce spurious results and should not be attempted. A successful set master lock-bit
operation requires that RP# = VHH. If it is attempted with RP# = VIH, SR.1 and SR.4 will be set to
“1” and the operation will fail. Set master lock-bit operations with VIH < RP# < VHH produce
spurious results and should not be attempted.
4.12
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the
master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits
command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-
Bits command and VHH on the RP# pin. This command is invalid while the WSM is running or the
device is suspended. See Table 14, “Identifier Codes” on page 25 for a summary of hardware and
software write protection options.
Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup
is first written. The device automatically outputs status register data when read (see Figure 11,
“Clear Block Lock-Bit Flowchart” on page 37). The CPU can detect completion of the clear block
lock-bits event by analyzing the STS pin output or status register bit SR.7.
When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a reliable clear block lock-bits operation can
only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while
V
PEN ≤ VPENLK, SR.3 and SR.5 will be set to “1.” A successful clear block lock-bits operation
requires that the master lock-bit is not set or, if the master lock-bit is set, that RP# = VHH. If it is
attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to “1” and the
operation will fail. A clear block lock-bits operation with VIH < RP# < VHH produce spurious
results and should not be attempted.
If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range or
RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear
block lock-bits is required to initialize block lock-bit contents to known values. Once the master
lock-bit is set, it cannot be cleared.
Datasheet
29
28F320J5 and 28F640J5
Table 15. Write Protection Alternatives
Master
Lock-Bit
Block
Lock-Bit
Operation
RP#
or
Effect
V
IH
Block Erase or Program
0
1
Block Erase and Program Enabled
V
HH
X
V
Block is Locked. Block Erase and Program Disabled
IH
Block Lock-Bit Override. Block Erase and Program
Enabled
V
HH
V
V
or
HH
IH
Set or Clear Block Lock-Bits
0
1
X
X
Set or Clear Block Lock-Bit Enabled
Master Lock-Bit Is Set. Set or Clear Block Lock-Bit
Disabled
V
IH
Master Lock-Bit Override. Set or Clear Block Lock-Bit
Enabled
V
V
HH
Set Master Lock-Bit
X
X
V
Set Master Lock-Bit Disabled
Set Master Lock-Bit Enabled
IH
HH
Table 16. Configuration Coding Definitions
Pulse on
Program
Pulse on
Reserved
Bits 7—2
Erase
Complete(1)
Complete(1)
Bit 1
Bit 0
DQ –DQ = Reserved
DQ –DQ are reserved for future use.
7 2
7
2
DQ –DQ = STS Pin Configuration Codes
00 = default, level mode RY/BY#
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
default (DQ –DQ = 00) RY/BY#, level mode
1 0
1
0
— used to control HOLD to a memory controller to prevent
accessinga flash memory subsystem while any flash device's
WSM is busy.
configuration 01 ER INT, pulse mode
— used to generate a system interrupt pulse when any flash
device in an array has completed a Block Erase or sequence of
Configuration Codes 01b, 10b, and 11b are all pulse mode
such that the STS pin pulses low then high when the operation Queued Block Erases. Helpful for reformattingblocks after file
indicated by the given configuration is completed. system free space reclamation or “cleanup”
Configuration Command Sequences for STS pin configuration configuration 10 PR INT, pulse mode
(maskingbits DQ –DQ to 00h) are as follows:
— used to generate a system interrupt pulse when any flash
device in an array has complete a Program operation. Provides
highest performance for servicing continuous buffer write
operations.
7
2
Default RY/BY# level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
configuration 11 ER/PR INT, pulse mode
— used to generate system interrupts to trigger servicing of
flash arrays when either erase or program operations are
completed when a common interrupt service routine is desired.
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of
250 ns.
30
Datasheet
28F320J5 and 28F640J5
Table 17. Status Register Definition
WSMS
bit 7
ESS
bit 6
ECLBS
bit 5
PSLBS
bit 4
VPENS
bit 3
R
DPS
bit 1
R
bit 2
bit 0
High Z When
Busy?
Status Register Bits
Notes
No
Yes
Yes
Yes
SR.7 = WRITE STATE MACHINE STATUS
Check STS or SR.7 to determine block erase,
program, or lock-bit configuration completion.
SR.6–SR.0 are not driven while SR.7 = “0.”
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
If both SR.5 and SR.4 are “1”s after a block
erase or lock-bit configuration attempt, an
improper command sequence was entered.
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.3 does not provide a continuous
programming voltage level indication. The
WSM interrogates and indicates the
programming voltage level only after Block
Erase, Program, Set Block/Master Lock-Bit, or
Clear Block Lock-Bits command sequences.
SR.4 = PROGRAM AND SET LOCK-BIT STATUS
1 = Error in Programming or Set Master/Block
Lock-Bit
0 = Successful Programming or Set Master/Block
Lock Bit
SR.1 does not provide a continuous indication
of master and block lock-bit values. The WSM
interrogates the master lock-bit, block lock-bit,
and RP# only after Block Erase, Program, or
Lock-Bit configuration command sequences. It
informs the system, dependingon the
Yes
SR.3 = PROGRAMMING VOLTAGE STATUS
1 = Low Programming Voltage Detected,
Operation Aborted
0 = Prog ramming Voltag e OK
attempted operation, if the block lock-bit is set,
Yes
Yes
SR.2 = RESERVED FOR FUTURE ENHANCEMENTS
master lock-bit is set, and/or RP# is not V
Read the block lock and master lock
.
HH
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock
Detected, Operation Abort
configuration codes using the Read Identifier
Codes command to determine master and
block lock-bit status.
0 = Unlock
Yes
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
SR.2 and SR.0 are reserved for future use
and should be masked when pollingthe status
register.
Table 18. eXtended Status Register Definition
WBS
bit 7
Reserved
bits 6—0
High Z When
Status Register Bits
Busy?
Notes
XSR.7 = WRITE BUFFER STATUS
After a Buffer-Write command, XSR.7 = 1
indicates that a Write Buffer is available.
No
1 = Write buffer available
0 = Write buffer not available
SR.6–SR.0 are reserved for future use and
should be masked when polling the status
register.
XSR.6–XSR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
Yes
Datasheet
31
28F320J5 and 28F640J5
Figure 6. Write to Buffer Flowchart
Bus
Operation
Start
Command
Comments
Data = E8H
Set Time-Out
Write
Read
Write to Buffer
Block Address
Issue Write to Buffer
Command E8H, Block
Address
No
XSR. 7 = Valid
Addr = Block Address
Check XSR. 7
1 = Write Buffer Available
0 = Write Buffer Not Available
Read Extended
Status Register
Standby
Data = N = Word/Byte Count
N = 0 Corresponds to Count = 1
Addr = Block Address
Write
(Note 1, 2)
0
Write to
Buffer Time-Out?
XSR.7 =
1
Write
(Note 3, 4)
Data = Write Buffer Data
Addr = Device Start Address
Write Word or Byte
Count, Block Address
Write
(Note 5, 6)
Data = Write Buffer Data
Addr = Device Address
Program Buffer
to Flash
Confirm
Data = D0H
Addr = Block Address
Write Buffer Data,
Start Address
Write
Status Register Data with the
Device Enabled, OE# Low
Updates SR
Read
(Note 7)
X = 0
Yes
Addr = Block Address
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check
X = N?
Standby
No
1. Byte or word count values on DQ 0 - DQ7 are loaded into the
Yes
count register. Count ranges on this device for byte mode are
= 00H to 1FH and for word mode are N = 0000H to 000FH.
2. The device now outputs the status register when read (XSR is
no longer available).
N
Abort Write to
Buffer Command?
Yes
Write to Another
Block Address
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A 4 - A0 of the start
address = 0).
Yes
No
Write to Buffer
Aborted
Write Next Buffer Data,
Device Address
5. The device aborts the Write to Buffer command if the current
address is outside of the original block address.
6. The status register indicates an "improper command
sequence" if the Write to Buffer command is aborted. Follow this
with a Clear Status Register command.
X = X + 1
Program Buffer to Flash
Confirm D0H
7. Toggling OE# (low to high to low) updates the status register.
This can be done in place of issuingthe Read Status Register
command.
Another Write to
Buffer?
Full status check can be done after all erase and write sequences
complete. Write FFH after the last operation to reset the device to
read array mode.
Issue Read
Status Command
No
Read Status Register
1
0
SR.7 =
1
Full Status
Check if Desired
Programming
Complete
0606_07
32
Datasheet
28F320J5 and 28F640J5
Figure 7. Byte/Word Program Flowchart
Start
Bus
Operation
Command
Comments
Setup Byte/
Data = 40H
Write 40H,
Address
Write
Write
Word Program Addr = Location to Be Programmed
Byte/Word
Program
Data = Data to Be Prog rammed
Addr = Location to Be Programmed
Write Data and
Address
Read
(Note 1)
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status
Register
Standby
1. Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuingthe Read Status Register command.
Repeat for subsequent programming operations.
0
SR.7 =
SR full status check can be done after each program operation, or
after a sequence of programming operations.
1
Full Status
Write FFH after the last program operation to place device in read
array mode.
Check if Desired
Byte/Word
Program Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Read Status
Register Data
(See Above)
Check SR.3
Standby
1 = Programming to Voltage Error
Detect
1
Check SR.1
SR.3 =
SR.1 =
SR.4 =
Voltage Range Error
1 = Device Protect Detect
RP# = VIH, Block Lock-Bit Is Set
Only required for systems
implemetinglock-bit configuration.
Standby
Standby
0
0
0
1
1
Check SR.4
Device Protect Error
Programming Error
1 = Programming Error
Toggling OE# (low to high to low) updates the status register. This can
be done in place of issuingthe Read Status Register command.
Repeat for subsequent programming operations.
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed before
full status is checked.
Byte/Word
Program
Successful
If an error is detected, clear the status register before attempting retry
or other error recovery.
0606_08
Datasheet
33
28F320J5 and 28F640J5
Figure 8. Block Erase Flowchart
Bus
Operation
Command
Comments
Data = 20H
Start
Write
Erase Block
Addr = Block Address
Erase
Confirm
Data = D0H
Addr = X
Write (Note 1)
Issue Single Block Erase
Command 20H, Block
Address
Status register data
With the device enabled,
OE# low updates SR
Addr = X
Read
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Write Confirm D0H
Block Address
1. The Erase Confirm byte must follow Erase Setup.
This device does not support erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Read
Status Register
Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
reset the device to read array mode.
No
Suspend
Erase Loop
0
Yes
SR.7 =
Suspend Erase
1
Full Status
Check if Desired
Erase Flash
Block(s) Complete
0606_09
34
Datasheet
28F320J5 and 28F640J5
Figure 9. Block Erase Suspend/Resume Flowchart
Bus
Operation
Start
Command
Comments
Data = B0H
Write
Read
Erase Suspend
Addr = X
Write B0H
Status Register Data
Addr = X
Check SR.7
Standby
1 - WSM Ready
0 = WSM Busy
Read Status Register
Check SR.6
Standby
Write
1 = Block Erase Suspended
0 = Block Erase Completed
0
SR.7 =
Data = D0H
Addr = X
Erase Resume
1
0
SR.6 =
Block Erase Completed
1
Read
Program
Read or Program?
Read Array
Data
Program
Loop
No
Done?
Yes
Write D0H
Write FFH
Block Erase Resumed
Read Array Data
0606_10
Datasheet
35
28F320J5 and 28F640J5
Figure 10. Set Block Lock-Bit Flowchart
Start
Bus
Operation
Command
Comments
Data = 60H
Addr =Block Address (Block),
Device Address (Master)
Set Block/Master
Lock-Bit Setup
Write 60H,
Block/Device Address
Write
Write
Data = 01H (Block)
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Set Block or Master
Lock-Bit Confirm
Write 01H/F1H,
Block/Device Address
Read
Status Register Data
Read Status Register
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
0
SR.7 =
Repeat for subsequent lock-bit operations.
1
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations
Full Status
Check if Desired
Write FFH after the last lock-bit set operation to place device in read
array mode.
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Check SR.3
Read Status Register
Data (See Above)
Standby
1 = Programming Voltage Error
Detect
1
SR.3 =
Voltage Range Error
Check SR.1
1 = Device Protect RP# = V
IH
Standby
(Set Master Lock-Bit Operation)
RP# = VIH, Master Lock-Bit Is Set
(set Block Lock-Bit Operation)
0
SR. 1 =
0
1
1
1
Device Protect Error
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Standby
Command Sequence
Error
Check SR.4
1 = Set Lock-Bit Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command, in cases where multiple lock-bits are set before full
status is checked.
SR.4 =
0
Set Lock-Bit Error
If an error is detected, clear the status register before attempting retry
or other error recovery.
Set Lock-Bit
Successful
0606_11
36
Datasheet
28F320J5 and 28F640J5
Figure 11. Clear Block Lock-Bit Flowchart
Start
Bus
Operation
Command
Comments
Data = 60H
Clear Block
Lock-Bits Setup
Write
Write 60H
Write D0H
Addr = X
Clear Block or
Lock-Bits Confirm Addr = X
Data = D0H
Write
Read
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register
Standby
Write FFH after the clear lock-bits operation to place device in read
array mode.
0
SR.7 =
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Check SR.3
Read Status Register
Data (See Above)
Standby
1 = Programming Voltage Error
Detect
1
SR.3 =
Voltage Range Error
Check SR.1
Standby
1 = Device Protect RP# = V ,
IH
Master Lock-Bit Is Set
Check SR.4, 5
Both 1 = Command Sequence
Error
0
SR. 1 =
0
1
1
1
Standby
Standby
Device Protect Error
Check SR.5
1 = Clear Block Lock-Bits Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Clear Block Lock-Bits
Error
SR.5 =
0
Clear Block Lock-Bits
Successful
0606_12
Datasheet
37
28F320J5 and 28F640J5
5.0
Design Considerations
5.1
Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1,
CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:
• Lowest possible memory power dissipation.
• Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable the device (see Table 2)
while OE# should be connected to all memory devices and the system’s READ# control line. This
assures that only selected memory devices have active outputs while de-selected memory devices
are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent
unintended writes during system power transitions. POWERGOOD should also toggle during
system reset.
5.2
STS and Block Erase, Program, and Lock-Bit Configuration
Polling
STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a
hardware method of detecting block erase, program, and lock-bit configuration completion. In
default mode, it transitions low after block erase, program, or lock-bit configuration commands and
returns to High Z when the WSM has finished executing the internal algorithm. For alternate
configurations of the STS pin, see the Configuration command.
STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the device is in block erase suspend (with programming
inactive) or in reset/power-down mode.
5.3
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers
are interested in three supply current issues; standby current levels, active current levels and
transient peaks produced by falling and rising edges of CE0, CE1, CE2, and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash
memory devices draw their power from three VCC pins (these devices do not include a VPP pin), it
is recommended that systems without separate power and ground planes attach a 0.1 µF ceramic
capacitor between each of the device’s three VCC pins (this includes VCCQ) and ground. These
high-frequency, low-inductance capacitors should be placed as close as possible to package leads
on each Intel StrataFlash memory device. Each device should have a 0.1 µF ceramic capacitor
connected between its VCC and GND. These high-frequency, low inductance capacitors should be
placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed between VCC and GND at the array’s power supply
connection. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductance.
38
Datasheet
28F320J5 and 28F640J5
5.4
Input Signal Transitions – Reducing Overshoots and
Undershoots When Using Buffers/Transceivers
As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory
devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory
specifications (see Section 6.1, Absolute Maximum Ratings). Many buffer/transceiver vendors now
carry bus-interface devices with internal output-damping resistors or reduced-drive outputs.
Internal output-damping resistors diminish the nominal output drive currents, while still leaving
sufficient drive capability for most applications. These internal output-damping resistors help
reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light-
drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When
selecting a buffer/transceiver interface design to flash, devices with internal output-damping
resistors or reduced-drive outputs should be considered to minimize overshoots and undershoots.
For additional information, please refer to AP-647, 5 Volt Intel StrataFlash® Memory Design Guide
(order 292205).
5.5
VCC, VPEN, RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of
the specified operating ranges, or RP# ≠ VIH or VHH. If RP# transitions to VIL during block erase,
program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of
tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device
will enter reset/power-down mode. The aborted operation may leave data partially corrupted after
programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase
and lock-bit configuration commands must be repeated after normal operation is restored. Device
power-off or RP# = VIL clears the status register.
The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or
CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/
power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN
during VCC transitions.
After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK
the CUI must be placed in read array mode via the Read Array command if subsequent access to
the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions.
,
5.6
Power-Up/Down Protection
The device is designed to offer protection against accidental block erasure, programming, or lock-
bit configuration during power transitions. Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious writes for VCC voltages above VLKO when VPEN is
active. Since WE# must be low and the device enabled (see Table 2) for a command write, driving
WE# to VIH or disabling the device will inhibit writes. The CUI’s two-step command sequence
architecture provides added protection against data alteration.
Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock and
unlock capability protects the device against inadvertent programming. The device is disabled
while RP# = VIL regardless of its control inputs.
Datasheet
39
28F320J5 and 28F640J5
5.7
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only
during device operation, but also for data retention during system idle time. Flash memory’s
nonvolatility increases usable battery life because data is retained when system power is removed.
6.0
Electrical Specifications
6.1
Absolute Maximum Ratings
Maximum Rating for
Commercial
Temperature Devices
Maximum Rating for
Extended
Temperature Devices
Parameter
Notes
Temperature under Bias Expanded
Storage Temperature
Voltag e On Any Pin (except RP#)
RP# Voltage with Respect to GND during Lock-Bit
Configuration Operations
Output Short Circuit Current
–20 °C to +70 °C
–65 °C to +125 °C
–2.0 V to +7.0 V
–40 °C to +85 °C
–65 °C to +125 °C
–2.0 V to +7.0 V
5
1
1,2,3
4
–2.0 V to +14.0 V
100 mA
–2.0 V to +14.0 V
100 mA
NOTES:
1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V
on V and V pins. Duringtransitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum
CC
PEN
DC voltage on input/output pins, V , and V
is V +0.5 V which, duringtransitions, may overshoot to
CC
PEN
CC
V
+2.0 V for periods <20 ns.
CC
2. Maximum DC voltage on RP# may overshoot to +14.0 V for periods <20 ns.
3. RP# voltage is normally at V or V . Connection to supply of V is allowed for a maximum cumulative
IL
IH
HH
period of 80 hours.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Extended temperature for 0.4 micron ETOXTM V process technology is from -20° C to +85° C.
NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to
change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only.
Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions”
may affect device reliability.
6.2
Operating Conditions
Table 19. Temperature and VCC Operating Conditions
Symbol
Parameter
Notes
Min
Max
Unit
Test Condition
T
OperatingTemperature
–20
+85
°C
V
Ambient Temperature
A
V
V
V
V
V
V
Supply Voltage (5 V 10%)
4.50
4.50
2.70
5.50
5.50
3.60
CC
CC1
Supply Voltage (5 V 10%)
V
CCQ1
CCQ2
CCQ1
CCQ2
Supply Voltage (2.7 V —3.6 V)
V
40
Datasheet
28F320J5 and 28F640J5
6.3
6.4
Capacitance
TA = +25°C, f = 1 MHz
Symbol
Parameter(1)
Typ
Max
Unit
Condition
C
C
Input Capacitance
Output Capacitance
6
8
8
pF
pF
V
V
= 0.0 V
IN
IN
12
= 0.0 V
OUT
OUT
NOTE: 1. Sampled, not 100% tested.
DC Characteristics
Symbol
Parameter
Notes
Typ
Max
Unit
Test Conditions
= V Max, V = V or GND
I
I
Input and V
Load Current
1
1
±1
µA
µA
V
V
LI
PEN
CC
CC
IN
CC
Output Leakage Current
±10
= V Max, V = V or GND
CC IN CC
LO
CC
CMOS Inputs, V = V Max,
CC
CC
I
V
Standby Current
1,2,3
80
150
900
650
µA
µA
µA
CCS
CC
CE = CE = CE = RP# = V
0.2 V
0
1
2
CCQ1
CMOS Inputs, RP# = V = V Max,
CC
CCQ2
CC
Min
450
325
CE = CE = CE = V
0
1
2
CMOS Inputs, RP# = V = V Max,
CC
CC
CE = GND, CE = CE = V
Min
2
0
1
CCQ2
CMOS Inputs, RP# = V = V Max,
CC
CC
CCQ2
CCQ2
210
400
µA
CE = CE = GND, CE = V
Min or
Min
1
2
0
CE = CE = GND, CE = V
0
2
1
TTL Inputs, V = V Max,
CC
CC
0.71
80
2
mA
CE = CE = CE = RP# = V
0
1
2
IH
RP# = GND 0.2 V
(STS) = 0 mA
I
I
V
V
Power-Down Current
Read Current
125
µA
CCD
CC
CC
I
OUT
CMOS Inputs, V = V
Device is enabled (see Table 2)
f = 5 MHz
=V Max
CC
CC
CCQ
1,3,4
35
45
55
65
mA
mA
CCR
I
= 0 mA
OUT
TTL Inputs ,V = V Max
CC
CC
Device is enabled (see Table 2)
f = 5 MHz
I
= 0 mA
OUT
V
Program or Set Lock-Bit
CC
I
I
I
1,4,5
1,4,5
1,6
35
40
35
40
60
70
70
80
10
mA
mA
mA
mA
mA
CMOS Inputs, V
= V
CCW
PEN
PEN
CC
Current
TTL Inputs, V
= V
PEN
CC
V
Block Erase or Clear Block
CC
CMOS Inputs, V
TTL Inputs, V
= V
CCE
CC
Lock-Bits Current
= V
PEN
CC
V
Block Erase Suspend
CC
Device is disabled (see Table 2)
CCES
Current
Datasheet
41
28F320J5 and 28F640J5
DC Characteristics, Continued
Symbol
Parameter
Input Low Voltage
Notes
Min
Max
Unit
Test Conditions
V
5
–0.5
0.8
V
IL
V
CC
V
V
Input High Voltage
Output Low Voltage
5
2.0
V
IH
OL
+ 0.5
0.45
0.4
2,5
V
V
V
V
V
= V
= V
= V
Min, I = 5.8 mA
OL
CCQ
CCQ
CCQ
CCQ1
CCQ2
CCQ1
Min, I = 2 mA
OL
Min or V
= V
Min
CCQ
CCQ2
V
Output High Voltage
3,7
2.4
V
V
I
= –2.5 mA (V
)
CCQ1
OH
OH
–2 mA (V
)
CCQ2
V
I
= V
Min or V
Min or V
= V
= V
Min
Min
0.85 X
CCQ
CCQ1
CCQ
CCQ
CCQ2
V
= –2.5 mA
CCQ
OH
V
= V
CCQ1
V
–0.4
CCQ
CCQ2
CCQ
V
V
I
= –100 µA
OH
V
Lockout duringNormal
PEN
V
5,7,8
3.6
PENLK
Operations
V
duringBlock Erase,
PEN
V
V
V
7,8
9
4.5
5.5
V
V
V
PENH
LKO
HH
Program, or Lock-Bit Operations
V
Lockout Voltage
3.25
11.4
CC
Set master lock-bit
Override lock-bit
RP# Unlock Voltage
10,11
12.6
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages
and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical
specifications.
2. Includes STS.
3. CMOS inputs are either V
4. Add 5 mA for V
0.2 V or GND 0.2 V. TTL inputs are either V or V .
IL IH
min.
CC
CCQ2
= V
CCQ
5. Sampled, not 100% tested.
6. I
the device’s current draw is I
is specified with the device de-selected. If the device is read or written while in erase suspend mode,
CCES
or I
.
CCR
CCW
7. Tie V
to V (4.5 V–5.5 V).
PEN
CC
8. Block erases, programming, and lock-bit configurations are inhibited when V
guaranteed in the range between V
9. Block erases, programming, and lock-bit configurations are inhibited when V < V
≤ V
PENH
, and not
PENLK
(max).
PEN
(max) and V
(min), and above V
PENLK
PENH
, and not guaranteed
CC
LKO
in the range between V
(min) and V (min), and above V (max).
LKO
CC CC
10.Master lock-bit set operations are inhibited when RP# = V . Block lock-bit configuration operations are
IH
inhibited when the master lock-bit is set and RP# = V . Block erases and programming are inhibited when
the correspondingblock-lock bit is set and RP# = V . Block erase, program, and lock-bit configuration
operations are not guaranteed and should not be attempted with V < RP# < V
IH
IH
.
IH
HH
11.RP# connection to a V supply is allowed for a maximum cumulative period of 80 hours.
HH
42
Datasheet
28F320J5 and 28F640J5
Figure 12. Transient Input/Output Reference Waveform for VCCQ = 5.0 V 10% (Standard
Testing Configuration)
2.4
2.0
0.8
2.0
Output
0.8
Input
Test Points
0.45
NOTE: AC test inputs are driven at V
(2.4 V
) for a Logic “1” and V (0.45 V
TTL OL TTL
) for a Logic "0." Input timing begins at
OH
V
(2.0 V
) and V (0.8 V
). Output timingends at V and V . Input rise and fall times (10% to 90%) <10 ns.
IH
TTL IL TTL
IH IL
Figure 13. Transient Input/Output Reference Waveform
2.7
Input
1.35
Test Points
1.35 Output
0.0
NOTE: AC test inputs are driven at 2.7 V for a Logic “1” and 0.0 V for a Logic “0.” Input timing begins, and output timing ends,
at 1.35 V (50% of V ). Input rise and fall times (10% to 90%) <10 ns.
CCQ
Figure 14. Transient Equivelent Testing Load Circuit
1.3V
1N914
RL = 3.3 k
Ω
Device
Under Test
Out
CL
NOTE:
C Includes JigCapacitance
L
Table 20. Test Configuration Capacitance Loading Value
Test Configuration
C (pF)
L
V
V
= 5.0 V ± 10%
= 2.7 V−3.6 V
100
50
CCQ
CCQ
Datasheet
43
28F320J5 and 28F640J5
6.5
AC Characteristics—Read-Only Operations(1)
Versions
(All units in ns unless otherwise noted)
5 V 10% V
–120/–150(2)
–120/–150(2)
CCQ
2.7 V—10% V
CCQ
#
Sym
Parameter
Notes
Min
Max
120
130 at +85° C
32 Mbit
R1
R2
R3
t
t
t
Read/Write Cycle Time
Address to Output Delay
CEX to Output Delay
AVAV
64 Mbit
32 Mbit
64 Mbit
32 Mbit
64 Mbit
150
120
130 at +85° C
AVQV
ELQV
150
120
130 at +85° C
3
3
3
150
50
R4
R5
t
t
OE# to Output Delay
GLQV
32 Mbit
64 Mbit
180
210
RP# Hig h to Output Delay
PHQV
R6
R7
R8
R9
t
t
t
t
CEX to Output in Low Z
4
4
0
0
ELQX
GLQX
EHQZ
GHQZ
OE# to Output in Low Z
CEX Hig h to Output in Hig h Z
OE# Hig h to Output in Hig h Z
4
4
55
15
Output Hold from Address, CEX, or OE# Change,
Whichever Occurs First
R10
R11
t
4
4
0
OH
t
t
ELFL
CEX Low to BYTE# High or Low
BYTE# to Output Delay
10
ELFH
t
t
FLQV
R12
1000
1000
FHQV
R13
R14
t
t
BYTE# to Output in High Z
CEx Disable Pulse Width
4
4
FLQZ
EHEL
10
NOTE: CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at
X
0
1
2
X
the first edg e of CE, CE , or CE that disables the device (seeTable 2).
0
1
2
1. See Figure 15, “AC Waveform for Read Operations” on page 45 for the maximum allowable input slew rate.
2. See Figure 12, Figure 13, and Fig ure 14 on pag e 4,3for testingcharacteristics
3. OE# may be delayed up to t
-t
.
after the first edge of CE0, CE1, or CE2 that enables the device (see
ELQV GLQV
Table 2) without impact on t
4. Sampled, not 100% tested.
ELQV
44
Datasheet
28F320J5 and 28F640J5
Figure 15. AC Waveform for Read Operations
Device
Address Selection
Standby
VIH
Data Valid
Address Stable
ADDRESSES [A]
VIL
R1
R14
R8
Disabled (V )
CEX [E]
IH
Enabled (V )
IL
R2
R3
VIH
OE# [G]
VIL
R9
VIH
R4
WE# [W]
VIL
R10
R5
High Z
R6
VOH
VOL
DATA [D/Q]
DQ0-DQ15
High Z
Valid Output
R7
VIH
VCC
VIL
VIH
RP# [P]
R11
R12
VIL
VIH
R13
BYTE# [F]
VIL
0606_16
NOTE: CE low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE high is defined at
X
X
the first edg e of CE, CE1, or CE2 that disables the device (see Table 2, “Chip Enable Truth Table” on
0
page 12).
Datasheet
45
28F320J5 and 28F640J5
6.6
AC Characteristics— Write Operations(1,2)
Valid for All
Speeds
Versions
#
Sym
(t
Parameter
RP# High Recovery to WE# (CE ) GoingLow
Notes
Min
Max
Unit
W1
W2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
)
3
4
1
0
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHWL PHEL
X
(t
)
CE (WE#) Low to WE# (CE ) GoingLow
ELWL WLEL
X
X
W3
Write Pulse Width
4
70
50
50
10
0
WP
W4
(t
)
Data Setup to WE# (CE ) GoingHigh
5
DVWH DVEH
X
W5
(t
)
Address Setup to WE# (CE ) GoingHigh
5
AVWH AVEH
X
W6
(t
)
CE (WE#) Hold from WE# (CE ) Hig h
X X
WHEH EHWH
W7
(t
)
Data Hold from WE# (CE ) Hig h
X
WHDX EHDX
W8
(t
)
Address Hold from WE# (CE ) Hig h
0
WHAX EHAX
X
W9
Write Pulse Width Hig h
6
30
0
WPH
W10
W11
W12
W13
W14
W15
(t
)
RP# V Setup to WE# (CE ) GoingHigh
3
3
PHHWH PHHEH
HH
X
(t
)
)
V
Setup to WE# (CE ) GoingHigh
0
VPWH VPEH
PEN
X
(t
Write Recovery before Read
WE# (CE ) Hig h to STS Going Low
7
35
WHGL EHGL
(t
)
8
90
WHRL EHRL
X
RP# V Hold from Valid SRD, STS GoingHigh
3,8,9
3,8,9
0
0
QVPH
QVVL
HH
V
Hold from Valid SRD, STS GoingHigh
PEN
NOTE: CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at
X
0
1
2
X
the first edg e of CE, CE , or CE that disables the device (see Table 2 on pag e 12).
0
1
2
1. Read timingcharacteristics duringblock erase, program, and lock-bit configuration operations are the same
as duringread-only operations. Refer to AC Characteristics–Read-Only Operations.
2. A write operation can be initiated and terminated with either CE or WE#.
X
3. Sampled, not 100% tested.
4. Write pulse width (t ) is defined from CE or WE# going low (whichever goes low last) to CE or WE# going
WP
X
WP
X
high (whichever goes high first). Hence, t
= t
= t
= t
= t
. If CE is driven low 10 ns
WLWH
ELEH
WLEH
ELWH X
before WE# going low, WE# pulse width requirement decreases to t
- 10 ns.
WP
5. Refer to Table 4 on pag e 17for valid A and D for block erase, program, or lock-bit configuration.
IN
IN
6. Write pulse width hig h (t
) is defined from CE or WE# going high (whichever goes high first) to CE or
WPH
X
X
WE# going low (whichever goes low first). Hence, t
= t
= t
= t
= t
.
WPH
WHWL
EHEL
WHEL
EHWL
7. For array access, t
is required in addition to t
for any accesses after a write.
AVQV
WHGL
8. STS timings are based on STS configured in its RY/BY# default mode.
9. V should be held at V (and if necessary RP# should be held at V ) until determination of block
PEN
PENH
HH
erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
46
Datasheet
28F320J5 and 28F640J5
Figure 16. AC Waveform for Write Operations
A
B
C
D
E
F
VIH
VIL
AIN
AIN
ADDRESSES [A]
W5
W8
Disabled (VIH
)
CEX, (WE#) [E(W)]
Enabled (VIL)
W6
W12
W1
VIH
OE# [G]
VIL
W2
W9
W16
Disabled (VIH
)
WE#, (CEX) [W(E)]
Enabled (VIL)
W3
W4
High Z
W7
VIH
Valid
SRD
DIN
DIN
DIN
DATA [D/Q]
VIL
W13
VOH
STS [R]
RP# [P]
VOL
VHH
VIH
W10
W14
W15
VIL
W11
VPENH
V
VPEN [VP]ENLK
VIL
0606_17
NOTE: CE low is defined as the first edge of CE , CE , or CE that enables the device. CE high is defined at
X
0
1
2
X
the first edg e of CE , CE , or CE that disables the device (see Table 2 on pag e 12). STS is shown in its
0
1
2
default mode (RY/BY#).
a. V power-up and standby.
CC
b. Write block erase, write buffer, or program setup.
c. Write block erase or write buffer confirm, or valid address and data.
d. Automated erase delay.
e. Read status register or query data.
f. Write Read Array command.
Datasheet
47
28F320J5 and 28F640J5
Figure 17. AC Waveform for Reset Operation
VIH
STS (R)
VIL
P2
VIH
RP# (P)
VIL
P1
0606_18
NOTE: STS is shown in its default mode (RY/BY#).
Table 21. Reset Specifications(1)
#
Sym
Parameter
Notes Min
Max
RP# Pulse Low Time
P1
t
2
3
35
PLPH
(If RP# is tied to V , this specification is not applicable)
CC
RP# Hig h to Reset during Block Erase, Prog ram, or Lock-Bit
Configuration
P2
t
100
PHRH
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns.
3. A reset time, t
valid.
, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are
PHQV
48
Datasheet
28F320J5 and 28F640J5
6.7
Block Erase, Program, and Lock-Bit Configuration
Performance(1,2)
#
Sym
Parameter
Notes
Typ(3)
Max
Unit
W16
W16
Write Buffer Program Time
4,5,6,7
218
654
µs
t
t
WHQV3
EHQV3
Byte Program Time (Using Word/Byte Program Command)
Block Program Time (Using Write to Buffer Command)
Block Erase Time
4
4
4
210
0.8
1.0
630
2.4
5.0
µs
sec
sec
t
t
WHQV4
EHQV4
W16
W16
W16
W16
t
t
WHQV5
EHQV5
Set Lock-Bit Time
4
4
64
.50
26
75
7.0
35
µs
sec
µs
t
t
WHQV6
EHQV6
Clear Block Lock-Bits Time
Erase Suspend Latency Time to Read
t
t
WHRH
EHRH
NOTES:
1. These performance numbers are valid for all speed versions.
2. Sampled but not 100% tested.
3. Typical values measured at T = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set.
A
Subject to change based on device characterization.
4. Excludes system-level overhead.
5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
6. Effective per-byte program time (t
7. Effective per-word program time (t
, t
) is 6.8 µs/byte (typical).
) is 13.6 µs/byte (typical).
WHQV1 EHQV1
, t
WHQV2 EHQV2
Datasheet
49
28F320J5 and 28F640J5
7.0
Additional Information
Order Number
Document/Tool
Contact Intel/Distribution
Sales Office
5 Volt Intel StrataFlash® Memory 0.25 µ Generation/32-, and 64-Mbit Densities
EAS
3 Volt Intel StrataFlash® Memory; 28F128J3A, 28F640J3A, 28F320J3A
datasheet
290667
290608
290609
290429
290598
290597
292235
297859
292222
292221
292218
292205
292204
292202
297846
3 Volt FlashFile™ Memory; 28F160S3 and 28F320S3 datasheet
5 Volt FlashFile™ Memory; 28F160S5 and 28F320S5 datasheet
5 Volt FlashFile™ Memory; 28F008SA datasheet
3 Volt FlashFile™ Memory; 28F004S3, 28F008S3, 28F016S3 datasheet
5 Volt FlashFile™ Memory; 28F004S5, 28F008S5, 28F016S5 datasheet
AP-687 5 Volt Intel StrataFlash® Memory Interface to the SA-1100
AP-677 Intel StrataFlash® Memory Technology
AP-664 Designing Intel StrataFlash® Memory into Intel® Architecture
AP-663 Using the Intel StrataFlash® Memory Write Buffer
AP-660 Migration Guide to 3 Volt Intel StrataFlash® Memory
AP-647 5 Volt Intel StrataFlash® Memory Design Guide
AP-646 Common Flash Interface (CFI) and Command Sets
AP-644 Migration Guide to 5 Volt Intel StrataFlash® Memory
Comprehensive User’s Guide for µBGA* Packages
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.
For the most current information on Intel StrataFlash memory, visit our website at http://developer.intel.com/
design/flash/isf.
50
Datasheet
28F320J5 and 28F640J5
8.0
Ordering Information
D A 2 8 F 6 4 0 J 5 A - 1 5 0
Package
E = 56-Lead TSOP
DA = 56-Lead SSOP
(Commercial Temp)
Access Speed (ns)
32 Mbit = 120
64 Mbit = 150
DT = 56-Lead SSOP
(Extended Temp)
Intel® .25 micron ETOX VI
TM
Process Technology
Product line designator
for all Intel® Flash
products
Voltage (VCC/VPEN
5 = 5 V/5 V
)
Product Family
Device Density
640 = x8/x16 (64 Mbit)
320 = x8/x16 (32 Mbit)
J = Intel StrataFlash® memory,
2 bits-per-cell
NOTE: Extended temperature for 0.4 micron ETOXTM V process technology is from -20° C to +85° C.
Order Code by Density
Valid Operational Conditions 5 V V
CC
32 Mbit
64 Mbit
2.7 V – 3.6 V V
5 V 10% V
CCQ
CCQ
DA28F320J5-120
E28F320J5-120
DA28F640J5-150
DT28F640J5-150
DA28F640J5A-150
DT28F640J5A-150
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DT28F320J5-120
DA28F320J5A-120
E28F320J5A-120
DT28F320J5A-120
Datasheet
51
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