GD16544-68BA [INTEL]
ATM/SONET/SDH Clock Recovery Circuit, Bipolar, CQFP68,;
| 型号： | GD16544-68BA |
| 厂家： | 
INTEL |
| 描述： | ATM/SONET/SDH Clock Recovery Circuit, Bipolar, CQFP68, ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总16页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10 Gbit/s
Receiver,
CDR and DeMUX
GD16544
Preliminary
General Description
Features
l
GD16544 is a 9.95328 Gbit/s Receiver
chip for use in SDH STM-64 and SONET
OC-192 optical communication systems.
When the VCO frequency is within the
locking range, the Bang-Bang Phase De-
tector takes over. It controls the phase of
the VCO until the sampling point of data
is in the middle of the bit period, where
the eye opening is largest. A ± 40 mV
Decision Threshold Control (DTC) is pro-
vided at the 10 Gbit/s input.
Complete Clock and Data Recovery
IC with auto acquisition.
l
Low noise 10 GHz VCO with ±5 %
tuning range.
GD16544 is a Clock and Data Recovery
IC with:
u
l
an on-chip VCO
a Bang-Bang Phase Detector
Digital controlled lock to data by a
Bang-Bang Phase Detector.
u
u
a 1:16 De-multiplexer
a Lock Detect
a Phase and Frequency Detector.
u
l
The 10 Gbit/s input data is retimed and
de-multiplexed by the 1:16 DeMUX. The
parallel output interface is synchronised
with the 622 MHz output clock.
Automatic capture of the VCO
frequency by a true Phase and
Frequency Detector.
u
Clock and data are regenerated by using
GD16544 in a Phase Lock Loop (PLL)
with an external loop filter.
l
Locking range selectable between
±500 and ±2000 ppm.
GD16544 is manufactured in a Silicon Bi-
polar process.
The VCO frequency is controlled by two
different Phase and Frequency Detectors
to ensure capture and lock to the line
data rate. When the frequency deviates
more than ±500 ppm from the reference
clock, GD16544 automatically switches
the phase and frequency detector into
the PLL loop. In the auto lock mode the
locking range is selectable between
±500 or ±2000 ppm.
l
Input Decision Threshold Control
(DTC): ± 40 mV.
GD16544 uses a single -5.2 V supply
voltage.
l
1:16 DeMUX with differential
622 Mbit/s data outputs.
The power dissipation is 2.9 W typical.
l
GD16544 is delivered in a Multi Layer
Ceramic (MLC) package, with internal
high-speed 50 Ω transmission lines.
Open collector clock and data
outputs.
l
622 MHz Clock output.
The Lock Detector circuit monitors the
VCO frequency and determines when the
VCO is within the locking range. If in lock
it switches the Bang-Bang Phase Detec-
tor into the PLL.
All critical high-speed signals are bonded
with GIGA’s proprietary Flexguide®
Bonding Technique.
l
155 or 622 MHz Reference Clock.
l
Single supply operation: -5.2 V.
l
Power dissipation: 2.9 W (typ).
VCO
CKOUT
CKOUTN
Timing Control
VCTL
l
Silicon Bipolar technology.
l
68 pin Multi Layer Ceramic (MLC)
package.
DO0
DON0
Flexguide
Parallel
Output
Data
1:16
DI
DIN
Bang
Bang
l
Flexguide® Bonding Technique.
Demultiplexer
Phase
Detector
DO15
DON15
Decision
Threshold
Control
DTC
DTCN
U
D
PCTL
POUT
Applications
Phase
Frequency
Detector
l
PHIGH
PLOW
LOCK
Telecommunication systems:
REFCK
REFCKN
–
–
SDH STM-64
SONET OC-192.
1/4
Lock
Detect
l
l
Fibre optic test equipment.
Submarine systems.
SEL3
SEL1
SEL2 TCK RESET VDDO
VDD
VEE
VDDA VEEA
Functional Details
The application of GD16544 is as re-
ceiver in SDH STM-64 and SONET
OC-192 optical communication systems.
Loop Filter
lected by SEL1. In auto lock mode, the
lock range ±500 or ±2000 ppm is se-
lected by SEL2.
The external loop filter is made using a
operational amplifier connected to output
pin (PHIGH and PLOW). The characte-
ristics of the phase lock loop are con-
trolled by the loop filter components
hence the op-amp is designed as an inte-
grator by a feedback capacitor and a re-
sistor. The gain-bandwidth of the op-amp
is larger than the required PLL bandwidth
in order not to limit the PLL. The recom-
mended op-amp is Analog Devices
(AD8042) with a gain-bandwidth of
160 MHz sufficient for PLL bandwidth up
to 50 MHz. The op-amp is used single
supplied by –5.2 V. See Figure 1 for ap-
plication information.
It integrates:
u
a Voltage Controlled Oscillator (VCO)
a Clock and Data Recovery Circuit
The Inputs
u
u
a Lock Detect Circuit
a 1:16 DeMUX
The input amplifier pin (DI/DIN) is de-
signed as a gain buffer stage with high
sensitivity and internal 50 Ω resistors ter-
minated to 0 V. After retiming, the data is
de-multiplexed down to 622 Mbit/s by the
1:16 DeMUX. The input data is
u
u
a Phase and Frequency Detector
(PFD).
de-multiplexed starting with DO0,
DO1...DO15 as the first received bits.
VCO
The VCO is an LC-type differential oscil-
lator at 10 GHz, voltage controlled by pin
VCTL and with a tuning range of approxi-
mately ±5 %.
It is recommended to use the 10 Gbit/s
inputs differentially.
The phase information from the Bang-
Bang phase detector are very high fre-
quency pulses (200 ps pulse width) at
output pins (PHIGH and PLOW). They
are open collector outputs with a 8 mA
current drive and are terminated exter-
nally by 100 Ω to 0 V. A pre-filtering of
the phase pulses are applied by a paral-
lel 10 pF capacitor (see Figure 1).
The 10 Gbit/s inputs (DI and DIN) are
not ESD protected and extra precau-
tions are needed when handling these in-
puts. (Internal 50 Ω resistors provide
some ESD hardness making the input
low impendance.)
With the VCTL voltage at approximately
-3.5 V the VCO frequency is fixed at
9.953 GHz and by changing the voltage
from 0 to -5.2 V the frequency is con-
trolled from 8.9 GHz to 10.2 GHz. The
modulation bandwidth of VCTL is
90 MHz (see VCO Measurement on
page 13 ).
The input voltage decision threshold is
adjustable by pin DTC and DTCN when
connected to a potentiometer. Adjusting
the resistor value of the meter controls
the current into DTC and DTCN. This DC
current is mirrored to the input pin (DI
and DIN) whereby the DC bias voltage at
the input is adjustable by ±40 mV. Opti-
mizing the input decision threshold im-
proves the system input sensitivity by
1-2 dB typical.
The PCB layout of the external loop filter
and the connecting lines to PHIGH,
PLOW and VCTL are critical for the jitter
performance of the component. The art-
work for the op-amp and the passive
components should be placed very close
to the pins of GD16544 in order to have
connecting lines as short as possible.
Ideally the loop filter components are
placed on the opposite side of the PCB
directly underneath GD16544. For more
layout suggestions see the 10 Gbit/s
evaluation board GD90244/255.
PFD
The PFD, ensures predictable locking
conditions for the GD16544. It is used
during acquisition and pulls the VCO into
the locking range where the Bang-Bang
Phase Detector acquires lock to the in-
coming bit-stream. The PFD is made with
digital set/reset cells giving it a true
phase and frequency characteristic. The
reference clock input (REFCK/REFCKN)
to the PFD is differential and selectable
between 155 MHz or 622 MHz by SEL3.
The input impedance into DTC and
DTCN is 1.5 kΩ and when not used they
should be de-coupled to 0 V by 100 nF.
The select inputs (SEL1-3, RESET and
TCK) are low speed inputs that can be
connected directly to the supply rails
(0 / -5.2 V).
Alternatively the phase information is
also available at output pins (PCTL and
POUT) and are used with an external
passive loop filter in applications with a
low PLL bandwidth (< 1 MHz ) instead of
the above recommended active loop fil-
ter. The PCTL and POUT pins should al-
ways be terminated as shown in Figure 1
also even though they are not actively
used in the PLL.
The reference clock input has 50 Ω inter-
nal termination resistors to 0 V. The ref-
erence clock is typically an X-tal
oscillator type as shown on Figure 1. The
reference clock input should be used dif-
ferential for best performance.
The Outputs
The data outputs, the clock output and
LOCK are differential open collector out-
puts with an 8 mA output current. They
are terminated externally with a resistor
(R) to 0 V and the output voltage swing is
V = -50 × 8 mA = -400 mV with R = 50 Ω.
Increasing the resistor increases the out-
put voltage and reduces the bandwidth.
Bang-Bang Phase Detector
POUT is a high impendance input and
will be destroyed if connected directly
(lowohmic, <25 kΩ) to -2.5 V to 0 V.
The Bang-Bang phase detector is de-
signed as a true digital type producing a
binary output. It samples the incoming
data prior to, in the vicinity of and after
any potential bit transition.
Lock Detect Circuit
The open collector outputs can be
configurated as CML or ECL compatible
using external circuit. (See item
When a transition has occurred, these
three samples tell whether the VCO clock
leads or lags the data. The binary output
is filtered through the (low pass) loop fil-
ter, performing an integration of all poten-
tial bit transitions. Hence the PLL is
The lock detect circuit continuously moni-
tors the difference between the reference
clock and the VCO clock. If they are
apart by more than ±500 (or ±2000 ppm),
it switches the PFD into the PLL, to pull it
back into the locking range. The status of
the lock circuit is given by output pin
(LOCK). Manual or automatic lock is se-
“622 Mbit/s Output Interface” on page 6).
When interfacing LDVS see item “Inter-
facing to a Positive Supply Interface
Technology” on next page.
controlled by the bit transition point.
Data Sheet Rev.: 03
GD16544
Page 2 of 16
Timing
inputs e.g. reduced input sensitivity and
reflection.
A version of GD16544 (GD16544/HV-
68XX) is offered with all data outputs and
the clock output DC tested for a minimum
breakdown voltage of 8 V.
The timing between GD16544 and the
system ASIC at 622 Mbit/s is controlled
by the 622 MHz output clock synchro-
nized with the output data. The clock is
used as the input clock to the ASIC,
clocking the input data into 16 parallel
shift registers. The timing relation be-
tween clock and data is given by the AC
Characteristics.
The component is available with straight
leads and with gullwing leads, see the
package outline drawings.
The maximum allowed output voltage on
all outputs is 2.6 V.
In the layout of the printed circuit board
the 10 Gbit/s inputs are connected with
50 Ω Micro Strip Lines (MLS) to the
high-speed connector. The micro strip
lines should be as short as possible
(<15 mm) with a plain and solid ground
plan below. The layout artwork for the
loop filter is placed preferable on the op-
posite side of the component with very
short connections to the pins of
External Circuit
The external circuits needed to make
GD16544 work as a complete clock and
data recovery with automatic acquisition
are:
GD16544. The 100 Ω resistors and
10 pF capacitor connected from PHIGH
and PLOW to 0 V should be placed very
close to the package pin no. 50 and 53.
u
Active loop filter with op-amp
An x-tal oscillator at 155 MHz or
u
622 MHz
Pull up resistors on all outputs and
de-coupling capacitors.
u
The environment around the loop filter
and the 10 Gbit/s inputs is noise sensi-
tive and no noise generating lines are al-
lowed in this area.
Package
The power supply to GD16544 should be
separated from other noise generation
components on the board and be de-
coupled as shown on Figure 2. DC-DC
converters are only allowed on the same
board if proper noise filtering is applied.
GD16544 is packaged in a 68 pin Multi
Layer Ceramic package with internal
50 Ω transmission lines. The cavity of the
package is down for easy cooling with a
mounted head spreader on top.
The 10 Gbit/s inputs are bonded with
GIGA’s proprietary Flexguide® Bonding
Technique. These are flexible 50 Ω
transmission lines bonded from the inter-
nal transmission line to the die pad. With
the use of flex guides the signal quality at
10 Gbit/s is preserved throughout the
package.
Thermal Condition
The component dissipates 2.9 W with a
–5.2 V voltage supply and need forced
cooling with a heat sink thermally con-
nected to the heat spreader. The thermal
connection should ensure the case tem-
perature in the range from 0 to 70 °C with
the given ambient conditions e.g. tempe-
rature and air flow etc.
Mounting and Layout
of PCB.
The component can be mounted on a
standard FR4 epoxy printed circuit board
when special attention is taken in the lay-
out and in the mounting of the compo-
nent.
Power Noise Rejection
In a noisy environment special attention
must be taken as described above to op-
timize the jitter performance and to re-
duce the input sensitivity penalty from
injected noise. The Power Supply Rejec-
tion Ratio (PSRR) is improved by adding
a serial resistor (330 Ω) and capacitor
(33 nF) from the positive input of the
op-amp to the VEEA power pin (no. 52)
as shown in Figure 1.
It is important for the performance of the
component that the leads of pin DI and
DIN (10 Gbit/s inputs) are made very
short (<1 mm) when mounted on the
board. Best way to make the leads short
is to cut a hole in the PCB and to mount
the component inside the hole. The
length of the two critical leads is reduced
to less than 0.5 mm whereas the rest of
the leads are kept at 2-4 mm in order for
mechanical stability. On the backside
the head spreader is thermally mounted
to a metal block with heat sink compound
(see paragraph “Mounting of Component
on PCB” on page 14). In cases where the
above mounting technical is not applica-
ble, the component can be mounted di-
rectly on the board with bend leads
Interfacing to a Positive
Supply Interface Technology
The data outputs (DO0-15) and the clock
output (CKOUT/N) are externally termi-
nated with top resistors. When interfacing
a positive supplied interface technology
(e.g. LVDS) the external resistors can be
terminated directly to the positive supply.
accepting longer leads for the 10 Gbit/s
Data Sheet Rev.: 03
GD16544
Page 3 of 16
Applications
1
0V
0V
VDDO
VDD
0V
TCK / 45
0V
-5.2V
RESET / 41
50Ω
50Ω 50Ω
50Ω
0V
1
0
50Ω MSL
SEL1 / 54
SEL2 / 56
SEL3 / 1
61 / DOO
-5.2V
0V
50Ω MSL
62 / DOON
1
0
-5.2V
50Ω MSL
50Ω MSL
39 / DO15
50Ω MSL
DI / 42
40 / DO15N
10Gb/s
CML Driver
VDD
DIN / 44
50Ω MSL
50Ω MSL
50Ω MSL
15 / CKOUT
16 / CKOUTN
DTC / 17
10k
50Ω
50Ω
VDD
220
0V
DTCN / 18
0V
0V
59 / LOCK
+
-
14
8
330
43
100nF
7
REFCK / 57
RECKN / 58
330Ω
-5.2V
220
XO-PECL
155/622 MHz
KVG
-5.2V
0V
VREF
49 / PCLT
47 / POUT
-5.2V
100Ω 100nF
100nF
220
3.3kΩ
-5.2V
0V
-5.2V
53 / PLOW
VCTL / 48
VEEA / 52
50 / PHIGH
VEE
-5.2V
33nF
-5.2V
0V
-5.2V
330Ω
2k2
+
AD8042
2k2
-
0.1µF
10pF
-5.2V
100Ω
100Ω
0.1µF
100Ω
0V
0V
Figure 1. Application Information.
Pin4
Pin9
Pin14
Pin21
Pin26
Pin31
Pin36
Pin43
Pin48
Pin55
Pin60
Pin65
VDD
VEE
C
C
C
C
C
C
C
C
C
C
C
C
10µF
Pin51
Pin35
VDDO
VEEA
VDDA
10µF
C
C
C is 10nF parallel with 100pF.
VEE pins 34/68; VEEA pin 52
Figure 2. De-coupling Supply.
Data Sheet Rev.: 03
GD16544
Page 4 of 16
Applications Continued
10 Gbit/s Input Interface
GD16544
0V
Postamplifier
50Ω
50Ω
0V
50Ω
50Ω MSL
DI
0/-0.4V
0/-0.4V
DIN
-5.2V
>16mA
Figure 3. 10 Gbit/s Input (DI/DIN), DC Coupled
GD16544
0V
50Ω
50Ω
-5.2V
Post-
amplifier
220Ω
50Ω MSL
DI
DIN
100nF
220Ω
-5.2V
-5.2V
Figure 4. 10 Gbit/s Input (DI/DIN), AC Coupled
Data Sheet Rev.: 03
GD16544
Page 5 of 16
622 Mbit/s Output Interface
GD16544 or
GD16555B
0V
50Ω
50Ω MSL
8mA
-5.2V
Figure 5. Open Collector Output
Open collector outputs should always be terminated at the receiver end, preferably 50 Ω .
0V
GD16544 or
GD16555B
100nF
120Ω
(-1V)
50Ω
0V
ECL 100k/10k
-5.2V
MC100EL16
MC10EL16
8mA
-5.2V
Figure 6. ECL 100k or 10k Output.
ECL 100k or 10k output using ECL driver MC100EL16/ MC10EL16.
GD16544 or
0V
GD16555B
95Ω
50Ω / 75Ω MSL
-1.0V (high)
-1.6V (low)
365Ω
-5.2V
8mA
-5.2V
Figure 7. ECL Compatible Output
ECL compatible output with a voltage swing of 600 mV (single-ended) or 1200 mV (differential).
Data Sheet Rev.: 03
GD16544
Page 6 of 16
0V
GD16544 or
GD16555B
100nF
120Ω
(-1V)
50Ω
+3.3V
LVPECL 100k/10k
-5.2V
MC100LVEL90
MC10LVEL90
8mA
-5.2V
Figure 8. Low Voltage PECL Output
Low voltage PECL output using PECL driver MC100LVEL90/ MC10LVEL90.
GD16544 or
GD16555B
+3.3V
+3.3V
500Ω
LVDS Input
50Ω MSL
100Ω
500Ω
+3.3V
0V
8mA
-5.2V
Figure 9. LVDS Compatible Output. Only applicable with /HV version
Reference Clock Input
GD16544
0V
0V
50Ω
50Ω
-5.2V
220Ω
REFCK
REFCKN
100nF
220Ω
-5.2V
-5.2V
Figure 10. Reference Clock Input (REFCK/REFCKN), Differential AC Coupled.
Data Sheet Rev.: 03
GD16544
Page 7 of 16
Pin List
Mnemonic:
Pin No.:
Pin Type:
Description:
DO0, DON0
DO1, DON1
DO2, DON2
DO3, DON3
DO4, DON4
DO5, DON5
DO6, DON6
DO7, DON7
DO8, DON8
DO9, DON9
DO10, DON10
DO11, DON11
DO12, DON12
DO13, DON13
DO14, DON14
DO15, DON15
61, 62
63, 64
66, 67
Open Collector
Data output, differential 622 Mbit/s. Demultiplexed to output with
DO0, DO1...DO15 as first received bits. All outputs should always
be terminated with a resistor.
2,
5,
7,
3
6
8
10, 11
12, 13
19, 20
22, 23
24, 25
27, 28
29, 30
32, 33
36, 37
39, 40
REFCK, REFCKN
SEL1, SEL2
57, 58
54, 56
CML In
ECL In
Reference clock input, differential 155 MHz or 622 MHz.
Clock and Data recovery setup.
SEL1 SEL2
0
0
1
1
0
1
0
1
Auto Lock, 500 ppm.
Auto Lock, 2000 ppm.
Manual Phase Freq. Detector (PFD).
Manual Bang-Bang Phase Detector.
When left open, the inputs are pulled to VDD.
SEL3
1
ECL In
SEL3
0
1
155 MHz Reference Clock.
622 MHz Reference Clock.
When left open, the input is pulled to VDD.
DI, DIN
42, 44
15, 16
CML In
Data input, differential 10 Gbit/s. No ESD input protection.
CKOUT, CKOUTN
Open Collector
Clock output, differential 622 MHz, should always be terminated
with a resistor.
LOCK
59
Open Collector
Lock detect output. When low, the divided VCO frequency
deviates more than 500/2000 ppm from REFCK/REFCKN, should
always be terminated with a resistor to VDD.
PCTL, POUT
49, 47
50, 53
Analogue Out/In Phase and Frequency Detector output, should always be
terminated with a resistor to VDD.
PHIGH, PLOW
Open Collector
Phase and Frequency Detector output, should always be
terminated with a resistor to VDD.
VCTL
46
17, 18
41
Analogue In
Analogue In
ECL IN
VCO voltage control input.
DTC, DTCN
RESET
TCK
Decision threshold control.
Connect to VEE. Not needed on power up, used for test purpose.
45
ECL IN
Connect to VDD. Used for test purpose. When left open, the input
is pulled to VDD.
VDD
4, 9, 14, 21, 26, 31,
38, 43, 48, 55, 60,
65
PWR
Digital Ground 0 V.
VDDA
VDDO
VEE
35
51
PWR
PWR
PWR
PWR
PLL Ground 0 V.
VCO Ground 0 V. For test purpose, connect to VEE.
-5.2 V Digital supply voltage.
-5.2 V PLL supply voltage.
34, 68
52
VEEA
Data Sheet Rev.: 03
GD16544
Page 8 of 16
Package Pinout
18
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
DTCN
VEE
19
DO8
DON2
DO2
20
DON8
21
VDD
VDD
22
DO9
DON1
DO1
23
DON9
24
DO10
DON0
DO0
25
DON10
26
VDD
VDD
27
DO11
LOCK
REFCKN
REFCK
SEL2
VDD
28
DON11
29
DO12
30
DON12
31
VDD
32
DO13
SEL1
PLOW
VEEA
33
DON13
34
VEE
Figure 11. Package Pinout, Top View
Note:
VDD = Cavity
Data Sheet Rev.: 03
GD16544
Page 9 of 16
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages in table are referred to VDD.
All currents are defined positive out of the pin.
VDD is 0 V or GND.
Symbol:
VEE
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
-6
UNIT:
V
Negative Supply
0
VO CML
IO CML
VI CML
II CML
POUT
CML Output Voltage
CML Output Current
CML Input Voltage
CML Input Current
POUT Voltage
0
0
VEE
V
Note 1
-12
mA
V
VCMLT -1.5
-25
0.5
Note 1
DC
25
mA
V
VEE
-3.6
+125
+150
TJ
Junction Temperature
Storage Temperature
-55
°C
°C
TS
-65
Note 1: Nominal supply voltages.
DC Characteristics
TCASE = 0 °C to 70 °C. VEE = -5.2 V
All voltages in table are referred to VDD.
All currents are defined positive out of pin.
VDD is 0 V or GND.
Symbol:
VEE
Characteristic:
Conditions:
MIN.:
-5.0
TYP.:
-5.2
550
0
MAX.:
-5.4
UNIT:
V
Negative Supply Voltage
IEE
Supply Current
455
660
mA
V
VIH CML
VIL CML
VOH OC
VOL OC
IIH CML
IIL CML
IOH OC
IOL OC
VIH ECL
VIL ECL
IIH ECL
IIL ECL
VADS
RIN CML
CML Input Voltage High
-0.1
+0.1
-1
CML Input Voltage Low
-0.25
-0.05
-0.3
-0.4
0
V
Open Collector Output Voltage High
Open Collector Output Voltage Low
CML Input Current High
Note 1, 3
+0.05
-0.5
V
Note 1, 3
-0.4
0
V
VIH CML, 50 Ω input
VIL CML, 50 Ω input
Note 1, 3
mA
mA
mA
mA
V
CML Input Current Low
8
Open Collector Output Current High
Open Collector Output Current Low
ECL Input Voltage High
-0.1
-7
0
+0.1
-10
-1.1
VEE
30
Note 1, 3
-8
Note 2, 5
0
ECL Input Voltage Low
Note 2, 5
-1.5
V
ECL Input Current High
V = -1.1 V
V = -1.5 V
Note 4, 6
µA
µA
mV
Ω
ECL Input Current Low
30
Offset Adjustment by DTC/DTCN, Differential
CML Input Resistor Termination
±90
DC
45
50
55
Note 1: Output externally terminated by 50 Ω to 0 V.
Note 2: All ECL inputs can be connected directly to VDD/VEE.
Note 3: All open collector outputs should always be terminated with a resistor.
Note 4: With DTC and DTCN connected to a 10k potentiometer with the mid pin grounded (0 V).
Note 5: -5.0 V.
Note 6: With open data inputs.
Data Sheet Rev.: 03
GD16544
Page 10 of 16
AC Characteristics
TCASE = 0 °C to 70 °C. VEE = -5.2 V
CKOUT
DO0-15
T
D
Figure 12. Timing relation between output clock (CKOUT) and output data (DO0-15)
Symbol:
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
UNIT:
JTol
Jitter tolerance
2 Hz < F < 400 kHz
4 MHz < F < 80 MHz
Note 4
1.5
0.15
UI
TD
Delay between DO0-15 and
CKOUT/CKOUTN
40
160
260
100
ps
V DI/DIN
Data input sensitivity, differential
DI/DIN input reflection coefficient
Note 2
Note 3
mVPP
dB
G DI/DIN
-10
DCYCLE CKOUT/N CKOUT/CKOUTN frequency
45
55
%
F REFCK/N
REFCK/REFCKN frequency
Note 1
155/622
MHz
ppm
DC
REFCK frequency deviation from nominal
line frequency
-100
40
100
60
DCYCLE REFCK/N REFCK duty cycle
%
Note 1: Selectable by SEL3.
Note 2: BER = 10-9
Note 3: From DC to 6 GHz. Measured on the GD90244/255 evaluation board.
Depends on lead length, board, soldering etc. of the component.
Note 4: Measured with recommended loop filter (see Figure 1) in the GD90244/255 evaluation board, (1 UI = 100 ps).
Data Sheet Rev.: 03
GD16544
Page 11 of 16
Jitter Tolerance Measurements
Figure 13. Jitter tolerance measured with the recommended loop filter (see Figure 1 on page 4) on the 90244/255 evaluation
board. The case temperature is 85 °C and -5 ° and the supply voltage is -5 and -5.4 V.
Data Sheet Rev.: 03
GD16544
Page 12 of 16
VCO Measurement
Figure 14. VCO Tuning Curve
Data Sheet Rev.: 03
GD16544
Page 13 of 16
Mounting of Component on PCB
50 Ω MSL
Heat sink compound
0.5 mm
2 - 4 mm
PCB
GD16544
SMA
Connector
Metal Block
Figure 15. Example 1.
Mounting of the component inside a hole in the PCB with short leads for the 10 Gbit/s inputs. The headspreader is down side to-
wards the metal side for best cooling of the component.
Heat sink
Heat sink compound
50 Ω MSL
GD16544
PCB
Loop Filter
SMA
Connector
Figure 16. Example 2.
Mounting of the component on the PCB with bend leads (gullwings) The headspreader is thermal mounted to a heat sink.
Data Sheet Rev.: 03
GD16544
Page 14 of 16
Package Outline
0.056" +- 0.006"
0.086" +- 0.01"
17
0.750" +- 0.007" SQ
Pin 1
18
68
52
34
35
51
0.010"
0.950" +- 0.02" SQ
0.040"
Figure 17. Package with Straight Leads (68AB). All Dimensions are in inch.
Figure 18. Package with Gullwings Leads (68BA). All Dimensions are in inch.
Data Sheet Rev.: 03
GD16544
Page 15 of 16
Device Marking
GD16544
<Mask ID><Lot ID>
WWYY
GD16544
Figure 19. Device Marking, Bottom and Top View
Ordering Information
To order, please specify as shown below:
Product Name:
Package Type:
Options:
Case Temperature Range:
GD16544-68AB
68 pin Straight Leads,
Multi Layer Ceramic
0..70 °C
GD16544-68BA
68 pin Gullwings Leads,
Multi Layer Ceramic
0..70 °C
0..70 °C
0..70 °C
GD16544/HV-68AB
GD16544/HV-68BA
68 pin Straight Leads,
Multi Layer Ceramic
Data Outputs DC-tested for
8 V breakdown
68 pin Gullwings Leads,
Multi Layer Ceramic
Data Outputs DC-tested for
8 V breakdown
GD16544, Data Sheet Rev.: 03 - Date: 7 September 1999
Distributor:
The information herein is assumed to be
reliable. GIGA assumes no responsibility
for the use of this information, and all such
information shall be at the users own risk.
Prices and specifications are subject to
change without notice. No patent rights or
licenses to any of the circuits described
herein are implied or granted to any third
party. GIGA does not authorise or warrant
any GIGA Product for use in life support
devices and/or systems.
Mileparken 22, DK-2740 Skovlunde
Denmark
Telephone : +45 4492 6100
Telefax
E-mail
Web site
: +45 4492 5900
: sales@giga.dk
: http://www.giga.dk
Please check our Internet web site
for latest version of this data sheet.
Copyright © 1999 GIGA A/S
All rights reserved
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