GD80960JC-40 [INTEL]

RISC Microprocessor, 32-Bit, 40MHz, CMOS, PBGA196, MINI, PLASTIC, BGA-196;


型号：	GD80960JC-40
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 40MHz, CMOS, PBGA196, MINI, PLASTIC, BGA-196 时钟外围集成电路
文件：	总74页 (文件大小：826K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

80960JS/JC 3.3 V Microprocessor

Advance Information Datasheet

Product Features

■ Pin/Code Compatible with all 80960Jx

■ On-Chip Data RAM

Processors

—1 Kbyte Critical Variable Storage

—Single-Cycle Access

■ High-Performance Embedded Architecture

—One Instruction/Clock Execution

■ 3.3 V Supply Voltage

—Core Clock Rate is:

—5 V Tolerant Inputs

80960JS 1x the Bus Clock

80960JC 2x the Bus Clock

—TTL Compatible Outputs

■ High Bandwidth Burst Bus

—32-Bit Multiplexed Address/Data

—Programmable Memory Configuration

—Selectable 8-, 16-, 32-Bit Bus Widths

—Supports Unaligned Accesses

—Big or Little Endian Byte Ordering

■ High-Speed Interrupt Controller

—31 Programmable Priorities

—Eight Maskable Pins plus NMI#

—Up to 240 Vectors in Expanded Mode

■ Two On-Chip Timers

—Load/Store Programming Model

—Sixteen 32-Bit Global Registers

—Sixteen 32-Bit Local Registers (8 sets)

—Nine Addressing Modes

—User/Supervisor Protection Model

■ Two-Way Set Associative Instruction

Cache

—16 Kbyte

—Programmable Cache-Locking

Mechanism

■ Direct Mapped Data Cache

—4 Kbyte

—Independent 32-Bit Counting

—Clock Prescaling by 1, 2, 4 or 8

—lnternal Interrupt Sources

—Write Through Operation

■ On-Chip Stack Frame Cache

—Seven Register Sets Can Be Saved

—Automatic Allocation on Call/Return

■ Halt Mode for Low Power

■ IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

■ Packages

—0-7 Frames Reserved for High-Priority

Interrupts

—132-Lead Pin Grid Array (PGA)

—132-Lead Plastic Quad Flat Pack

(PQFP)

—196-Ball Mini Plastic Ball Grid Array

(MPBGA)

Notice: This document contains information on products in the sampling and initial production

phases of development. The specifications are subject to change without notice. Verify with your

local Intel sales office that you have the latest datasheet before finalizing a design.

Order Number: 273200-002

December, 1998

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 80960JS and 80960JC microprocessors may contain design defects or errors known as errata which may cause the products to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

Advance Information Datasheet

80960JS/JC 3.3 V Microprocessor

Contents

1.0

2.0

Introduction..................................................................................................................7

80960Jx Overview......................................................................................................8

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

80960 Processor Core ..........................................................................................9

Burst Bus.............................................................................................................10

Timer Unit............................................................................................................10

Priority Interrupt Controller ..................................................................................10

Instruction Set Summary.....................................................................................11

Faults and Debugging .........................................................................................11

Low Power Operation..........................................................................................11

Test Features ......................................................................................................12

Memory-Mapped Control Registers ....................................................................12

Data Types and Memory Addressing Modes ......................................................12

3.0

4.0

Package Information: 80960JS/JC 3.3 V Processors ................................14

3.1

Pin Descriptions ..................................................................................................15

3.1.1 Functional Pin Definitions.......................................................................15

3.1.2 80960Jx 132-Lead PGA Pinout..............................................................21

3.1.3 80960Jx 132-Lead PQFP Pinout............................................................25

3.1.4 80960Jx 196-Ball MPBGA Pinout ..........................................................28

Package Thermal Specifications.........................................................................33

Thermal Management Accessories.....................................................................36

3.3.1 Heatsinks................................................................................................36

3.2

3.3

Electrical Specifications 80960JS/JC 3.3 V Processor.............................37

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Absolute Maximum Ratings.................................................................................37

Operating Conditions...........................................................................................37

Connection Recommendations ...........................................................................38

VCC5 Pin Requirements (VDIFF) .......................................................................38

VCCPLL Pin Requirements.................................................................................39

DC Specifications................................................................................................40

AC Specifications ................................................................................................42

4.7.1 AC Test Conditions and Derating Curves ..............................................44

4.7.2 AC Timing Waveforms ...........................................................................49

5.0

Bus Functional Waveforms..................................................................................55

5.1

5.2

Basic Bus States .................................................................................................65

Boundary-Scan Register .....................................................................................66

6.0

7.0

Device Identification 80960JS/JC 3.3 V Processor.....................................72

Revision History.......................................................................................................74

Advance Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figures

80960Jx Microprocessor Package Options........................................................... 7

80960JS/JC Block Diagram .................................................................................. 9

132-Lead Pin Grid Array Top View - Pins Facing Down .....................................21

132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22

132-Lead PQFP - Top View ................................................................................25

196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down ..................28

196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up..................29

VCC5 Current-Limiting Resistor..........................................................................38

VCCPLL Lowpass Filter......................................................................................39

AC Test Load ......................................................................................................44

Output Delay or Hold vs. Load Capacitance (3.3 V Signals) ..............................45

Output Delay or Hold vs. Load Capacitance (5 V Signals) .................................45

vs. AD Bus Load Capacitance (3.3 V Signals) .............................................46

vs. AD Bus Load Capacitance (5 V Signals) ................................................46

80960JC I Active (Power Supply) vs. Frequency............................................47

80960JC I Active (Thermal) vs. Frequency.....................................................47

80960JS I Active (Power Supply) vs. Frequency............................................48

80960JS I Active (Thermal) vs. Frequency.....................................................48

CLKIN Waveform ................................................................................................49

Output Delay Waveform.............................................................................49

Output Float Waveform................................................................................50

OV1

IS1

IS2

IS3

IS4

and T

Input Setup and Hold Waveform...................................................50

Input Setup and Hold Waveform...................................................51

IH1

IH2

IH3

IH4

, T

and T

Relative Timings Waveform.................................................52

LX LXL

LXA

DT/R# and DEN# Timings Waveform .................................................................52

TCK Waveform....................................................................................................53

and T

Input Setup and Hold Waveforms .........................................53

BSIS1

BSIH1

and T

Output Delay and Output Float Waveform..........................53

Output Delay and Output Float Waveform..........................54

BSOV1

BSOF1

BSOV2

BSOF2

and T

Input Setup and Hold Waveform ...........................................54

BSIS2

BSIH2

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........55

Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................56

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................57

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ...................58

Burst Read and Write Transactions With 1, 0 Wait States and

Extra Tr State on Read, 16-Bit Bus.....................................................................59

Double Word Read Bus Request, Misaligned One Byte From

Quad Word Boundary, 32-Bit Bus, Little Endian .................................................60

HOLD/HOLDA Waveform For Bus Arbitration ....................................................61

Cold Reset Waveform .........................................................................................62

Warm Reset Waveform.......................................................................................63

Entering the ONCE State....................................................................................64

Bus States with Arbitration ..................................................................................66

Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................70

Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................71

80960JS/JC Device Identification Register .........................................................72

Advance Information Datasheet

80960JS/JC 3.3 V Microprocessor

Tables

80960Jx Instruction Set.......................................................................................13

Pin Description Nomenclature.............................................................................15

Pin Description — External Bus Signals .............................................................16

Pin Description — Processor Control Signals, Test Signals and Power.............19

Pin Description — Interrupt Unit Signals.............................................................20

132-Lead PGA Pinout — In Signal Order............................................................23

132-Lead PGA Pinout — In Pin Order ................................................................24

132-Lead PQFP Pinout — In Signal Order .........................................................26

132-Lead PQFP Pinout — In Pin Order ..............................................................27

196-Ball MPBGA Pinout — In Signal Order ........................................................30

196-Ball MPBGA Pinout — In Pin Order.............................................................31

132-Lead PGA Package Thermal Characteristics...............................................34

196-Ball MPBGA Package Thermal Characteristics ...........................................34

132-Lead PQFP Package Thermal Characteristics ............................................35

Maximum T at Various Airflows in °C (80960JC) ..............................................35

Maximum T at Various Airflows in °C (80960JS)...............................................36

Absolute Maximum Ratings.................................................................................37

80960JS/JC Operating Conditions......................................................................37

VDIFF Parameters ..............................................................................................39

80960JS/JC DC Characteristics..........................................................................40

80960JS/JC I Characteristics..........................................................................40

80960JS/JC AC Characteristics..........................................................................42

Note Definitions for Table 22, “80960JC/JS AC Characteristics” ........................44

Boundary-Scan Register Bit Order......................................................................67

Natural Boundaries for Load and Store Accesses ..............................................68

Summary of Byte Load and Store Accesses.......................................................68

Summary of Short Word Load and Store Accesses............................................68

Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)...........................69

80960JS/JC Device Type and Stepping Reference............................................72

Fields of 80960JS/JC Device ID..........................................................................73

80960JS/JC Device ID Model Types...................................................................73

Datasheet Revision History.................................................................................74

Advance Information Datasheet

80960JS/JC 3.3 V Microprocessor

1.0

Introduction

This document contains information for the 80960JS/JC microprocessor, including electrical

characteristics and package pinout information. Detailed functional descriptions — other than

parametric performance — are published in the i960 Jx Microprocessor Developer’s Manual

(order number 272483).

Figure 1. 80960Jx Microprocessor Package Options

A80960JX

GD80960JX

XXXXXXXXSS

XXXXXXXSS

i960

19xx

NG80960JX

XXXXXXXX SS

19xx

196-Ball MPBGA

132-Pin PQFP

132-Pin PGA

This datasheet provides information about these members of the 80960Jx processor family:

• 80960JS — 3.3 V (5 V tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache

• 80960JC — 3.3 V (5 V tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache, and clock

doubling

In addition, this datasheet provides information that is general to the 80960Jx processor family.

The 80960Jx family also includes the 80960JA, JF, JD, and JT processors, which are covered in the

80960JA/JD/JF/JT 3.3 V Microprocessor datasheet (order number 273159).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

2.0

80960Jx Overview

The 80960Jx offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx

is object code compatible with the 80960 core architecture and is capable of sustained execution at

the rate of one instruction per clock. This processor’s features include generous instruction cache,

data cache, and data RAM. It also boasts a fast interrupt mechanism and dual-programmable timer

units.

The 80960JC’s clock multiplication operates the processor core at two times the bus clock rate to

improve execution performance without increasing the complexity of board designs.

Memory subsystems for cost-sensitive embedded applications often impose substantial wait state

penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU

execution from the external bus.

The 80960Jx rapidly allocates and deallocates local register sets during context switches. The

processor needs to flush a register set to the stack only when it saves more than seven sets to its

local register cache.

A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full

complement of control signals simplifies the connection of the 80960Jx to external components.

The user programs physical and logical memory attributes through memory-mapped control

registers (MMRs) — an extension not found on the i960 Kx, Sx or Cx processors. Physical and

logical configuration registers enable the processor to operate with all combinations of bus width

and data object alignment. The processor supports a homogeneous byte ordering model.

This processor integrates two important peripherals: a timer unit, and an interrupt controller. These

and other hardware resources are programmed through memory-mapped control registers, an

extension to the familiar 80960 architecture.

The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and

general-purpose system timing. These operate in either single-shot or auto-reload mode and can

generate interrupts.

The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.

The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The

ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt

latency. Clock doubling reduces interrupt latency by 40% compared to the 80960JS. Local registers

may be dedicated to high-priority interrupts to further reduce latency. Acting independently from

the core, the ICU compares the priorities of posted interrupts with the current process priority, off-

loading this task from the core. The ICU also supports the integrated timer interrupts.

The 80960Jx features a Halt mode designed to support applications where low power consumption

is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up

to 90 percent.

The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary

Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.

The Solutions960 program features a wide variety of development tools which support the i960

processor family. Many of these tools are developed by partner companies; some are developed by

Intel, such as profile-driven optimizing compilers. For more information on these products, contact

your local Intel representative.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 2. 80960JS/JC Block Diagram

Control

Physical Region

32-bit buses

address / data

CLKIN

Configuration

PLL, Clocks,

Power Mgmt

Instruction Cache

80960JS/JC - 16K

Two-Way Set Associative

Bus

Control Unit

Address/

Data Bus

Bus Request

TAP

Queues

Boundary Scan

Controller

Two 32-Bit

Timers

Instruction Sequencer

Interrupt

Port

Constants

Control

Programmable

Interrupt Controller

8-Set

Local Register Cache

Execution

and

Memory

Interface

Unit

Memory-Mapped

Multiply

Divide

Unit

Address

Generation

128

Unit

32-bit Address

32-bit Data

1K Data RAM

Global / Local

effective

address

SRC1 SRC2 DEST

Direct Mapped

Data Cache

80960JS/JC - 4K

3 Independent 32-Bit SRC1, SRC2, and DEST Buses

2.1

80960 Processor Core

The 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this

processor core as a high performance device that is also cost-effective. Factors that contribute to

the core’s performance include:

• Core operates at the bus speed with the 80960JS

• Core operates at two times the bus speed with the 80960JC

• Single-clock execution of most instructions

• Independent Multiply/Divide Unit

• Efficient instruction pipeline minimizes pipeline break latency

• Register and resource scoreboarding allow overlapped instruction execution

• 128-bit register bus speeds local register caching

• Two-way set associative, integrated instruction cache

• Direct-mapped, integrated data cache

• 1 Kbyte integrated data RAM delivers zero wait state program data

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

2.2

Burst Bus

A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory

and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit

words per six clock cycles. The external address/data bus is multiplexed.

Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory

organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and

data caching are programmed through a group of logical memory templates and a defaults register.

The BCU’s features include:

• Multiplexed external bus to minimize pin count

• 32-, 16- and 8-bit bus widths to simplify I/O interfaces

• External ready control for address-to-data, data-to-data and data-to-next-address wait state types

• Support for big or little endian byte ordering to facilitate the porting of existing program code

• Unaligned bus accesses performed transparently

• Three-deep load/store queue to decouple the bus from the core

Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it

performs an external bus confidence test by performing a checksum on the first words of the

initialization boot record (IBR).

The user may examine the contents of the caches by executing special cache control instructions.

2.3

2.4

Timer Unit

The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several

clock rates and generating interrupts. Each is programmed by use of the TU registers. These

memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot

mode and auto-reload capabilities for continuous operation. Each timer has an independent

interrupt request to the 80960Jx’s interrupt controller. The TU can generate a fault when

unauthorized writes from user mode are detected. Clock prescaling is supported.

Priority Interrupt Controller

A programmable interrupt controller manages up to 240 external sources through an 8-bit external

interrupt port. The interrupt inputs may be configured for individual edge- or level-triggered

inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channels and a

single Non-Maskable Interrupt (NMI#) pin. Interrupts are serviced according to their priority levels

relative to the current process priority.

Low interrupt latency is critical to many embedded applications. As part of its highly flexible

interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:

• Interrupt vectors and interrupt handler routines can be reserved on-chip

• Register frames for high-priority interrupt handlers can be cached on-chip

• The interrupt stack can be placed in cacheable memory space

• Interrupt microcode executes at two times the bus frequency for the 80960JC

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

2.5

Instruction Set Summary

The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are:

• Conditional Move

• Conditional Add

• Conditional Subtract

• Byte Swap

• Halt

• Cache Control

• Interrupt Control

Table 1 identifies the instructions that the 80960Jx supports. Refer to the i960 Jx Microprocessor

Developer’s Manual (order number 272483) for a detailed description of each instruction.

2.6

Faults and Debugging

The 80960Jx employs a comprehensive fault model. The processor responds to faults by making

implicit calls to a fault handling routine. Specific information collected for each fault allows the

fault handler to diagnose exceptions and recover appropriately.

The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to

detect as many as seven different trace event types. Alternatively, mark and fmark instructions

can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are

also available to trap on execution and data addresses.

2.7

Low Power Operation

Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s

sub-micron topology provides the circuit density for optimal cache size and high operating speeds

while dissipating modest power. The processor also uses dynamic power management to turn off

clocks to unused circuits.

Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,

the processor core stops completely while the integrated peripherals continue to function, reducing

overall power requirements up to 90 percent. Processor execution resumes from internally or

externally generated interrupts.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

2.8

Test Features

The 80960Jx incorporates numerous features which enhance the user’s ability to test both the

processor and the system to which it is attached. These features include ONCE (On-Circuit

Emulation) mode and Boundary Scan (JTAG).

The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and

Boundary Scan Architecture (IEEE Std. 1149.1).

One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE

mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism.

ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to

electrically “remove” itself from a circuit board. This allows for system-level testing where a

remote tester — such as an in-circuit emulator — can exercise the processor system.

The provided test logic does not interfere with component or circuit board behavior and ensures

that components function correctly, connections between various components are correct, and

various components interact correctly on the printed circuit board.

The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing.

It can examine connections which might otherwise be inaccessible to a test system.

2.9

Memory-Mapped Control Registers

The 80960Jx, though compliant with i960 series processor core, has the added advantage of

memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These

give software the interface to easily read and modify internal control registers.

Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished

through regular memory-format instructions. The processor ensures that these accesses do not

generate external bus cycles.

2.10

Data Types and Memory Addressing Modes

As with all i960 family processors, the 80960Jx instruction set supports several data types and formats:

• Bit

• Bit fields

• Integer (8-, 16-, 32-, 64-bit)

• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)

• Triple word (96 bits)

• Quad word (128 bits)

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

The 80960Jx provides a full set of addressing modes for C and assembly programming:

• Two Absolute modes

• Five Register Indirect modes

• Index with displacement

• IP with displacement

Table 1. 80960Jx Instruction Set

Data Movement

Arithmetic

Logical

Bit, Bit Field and Byte

Add

Subtract

Multiply

And

Set Bit

Divide

Not And

And Not

Clear Bit

Remainder

Modulo

Not Bit

Load

Alter Bit

Store

Shift

Exclusive Or

Not Or

Scan For Bit

Span Over Bit

Extract

Move

^†Conditional Select

Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

^†Conditional Add

^†Conditional Subtract

Rotate

Or Not

Load Address

Nor

Modify

Exclusive Nor

Not

Scan Byte for Equal

^†Byte Swap

Nand

Comparison

Branch

Call/Return

Fault

Compare

Call

Conditional Compare

Compare and Increment

Compare and Decrement

Test Condition Code

Check Bit

Unconditional Branch

Conditional Branch

Compare and Branch

Call Extended

Call System

Return

Conditional Fault

Synchronize Faults

Branch and Link

Debug

Processor Management

Atomic

Flush Local Registers

Modify Arithmetic

Controls

Modify Trace Controls

Mark

Modify Process Controls

^†Halt

Atomic Add

Atomic Modify

Force Mark

System Control

^†Cache Control

^†Interrupt Control

†

Denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB

implementations.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

3.0

Package Information: 80960JS/JC 3.3 V Processors

The 80960JS/JC is offered with six speeds and three package types. The 132-pin Pin Grid Array

(PGA) device is specified for operation at V = 3.3 V ± 0.15 V over a case temperature range of

0° to 100°C:

• A80960JC-66 (66 MHz core, 33 MHz bus)

• A80960JC-50 (50 MHz core, 25 MHz bus)

• A80960JC-40 (40 MHz core, 20 MHz bus)

• A80960JC-33 (33 MHz core, 16 MHz bus)

• A80960JS-33 (33 MHz)

• A80960JS-25 (25 MHz)

• A80960JS-16 (16 MHz)

The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at

= 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:

• NG80960JC-66 (66 MHz core, 33 MHz bus)

• NG80960JC-50 (50 MHz core, 25 MHz bus)

• NG80960JC-40 (40 MHz core, 20 MHz bus)

• NG80960JC-33 (33 MHz core, 16 MHz bus)

• NG80960JS-33 (33 MHz)

• NG80960JS-25 (25 MHz)

• NG80960JS-16 (16 MHz)

The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation at

= 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:

• GD80960JC-66 (66 MHz core, 33 MHz bus)

• GD80960JC-50 (50 MHz core, 25 MHz bus)

• GD80960JC-40 (40 MHz core, 20 MHz bus)

• GD80960JC-33 (33 MHz core, 16 MHz bus)

• GD80960JS-33 (33 MHz)

• GD80960JS-25 (25 MHz)

• GD80960JS-16 (16 MHz)

For package specifications and information, refer to Intel’s Packaging Handbook (order number

240800).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

3.1

Pin Descriptions

This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA)

package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid

Array (MPBGA).

Section 3.1.1, “Functional Pin Definitions,” describes pin function. Section 3.1.2, “80960Jx 132-

Lead PGA Pinout,” Section 3.1.3, “80960Jx 132-Lead PQFP Pinout,” and Section 3.1.4, “80960Jx

196-Ball MPBGA Pinout,” define the signal and pin locations for the supported package types.

3.1.1

Functional Pin Definitions

Table 2 presents the legend for interpreting the pin descriptions which follow. Pins associated with

the bus interface are described in Table 3. Pins associated with basic control and test functions are

described in Table 4. Pins associated with the Interrupt Unit are described in Table 5.

Table 2. Pin Description Nomenclature

Symbol

Description

Input pin only.

Output pin only.

I/O

–

Pin can be either an input or output.

Pin must be connected as described.

Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.

S(E) Edge sensitive input

S(L) Level sensitive input

Asynchronous. Inputs may be asynchronous relative to CLKIN.

A(E) Edge sensitive input

A (...)

A(L) Level sensitive input

While the processor’s RESET# pin is asserted, the pin:

R(1) is driven to V_CC

R(0) is driven to V_SS

R(Q) is a valid output

R (...)

R(X) is driven to unknown state

R(H) is pulled up to V_CC

While the processor is in the hold state, the pin:

H(1) is driven to V_CC

H (...)

P (...)

H(0) is driven to V_SS

H(Q) Maintains previous state or continues to be a valid output

H(Z) Floats

While the processor is halted, the pin:

P(1) is driven to V_CC

P(0) is driven to V_SS

P(Q) Maintains previous state or continues to be a valid output

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)

NAME

TYPE

DESCRIPTION

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data

to and from memory. During an address (T ) cycle, bits 31:2 contain a physical word

address (bits 0-1 indicate SIZE; see below). During a data (T_d) cycle, read or write

data is present on one or more contiguous bytes, comprising AD[31:24], AD[23:16],

AD[15:8] and AD[7:0]. During write operations, unused pins are driven to

determinate values.

SIZE, which comprises bits 0-1 of the AD lines during a T cycle, specifies the

number of data transfers during the bus transaction.

I/O

S(L)

R(X)

H(Z)

P(Q)

AD1 AD0 Bus Transfers

AD[31:0]

1 Transfer

2 Transfers

3 Transfers

4 Transfers

When the processor enters Halt mode, if the previous bus operation was a:

•

write — AD[31:2] are driven with the last data value on the AD bus.

read — AD[31:4] are driven with the last address value on the AD bus; AD[3:2]

are driven with the value of A[3:2] from the last data cycle.

Typically, AD[1:0] reflect the SIZE information of the last bus transaction (either

instruction fetch or load/store) that was executed before entering Halt mode.

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is

R(0)

H(Z)

P(0)

ALE

ALE#

ADS#

asserted during a T cycle and deasserted before the beginning of the T_dstate. It is

active HIGH and floats to a high impedance state during a hold cycle (T_h).

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE# is

the inverted version of ALE. This signal gives the 80960Jx a high degree of

compatibility with existing 80960Kx systems.

R(1)

H(Z)

P(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access.

R(1)

H(Z)

P(1)

The processor asserts ADS# for the entire T cycle. External bus control logic

typically samples ADS# at the end of the cycle.

ADDRESS[3:2] comprise a partial demultiplexed address bus.

32-bit memory accesses: the processor asserts address bits A[3:2] during T . The

partial word address increments with each assertion of RDYRCV# during a ^aburst.

R(X)

H(Z)

P(Q)

16-bit memory accesses: the processor asserts address bits A[3:1] during T with A1

driven on the BE1# pin. The partial short word address increments with each

assertion of RDYRCV# during a burst.

A[3:2]

8-bit memory accesses: the processor asserts address bits A[3:0] during T , with

A[1:0] driven on BE[1:0]#. The partial byte address increments with each assertion

of RDYRCV# during a burst.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 3. Pin Description — External Bus Signals (Sheet 2 of 4)

NAME

TYPE

DESCRIPTION

BYTE ENABLES select which of up to four data bytes on the bus participate in the

current bus access. Byte enable encoding is dependent on the bus width of the

memory region accessed:

32-bit bus:

BE3# enables data on AD[31:24]

BE2# enables data on AD[23:16]

BE1# enables data on AD[15:8]

BE0# enables data on AD[7:0]

16-bit bus:

BE3# becomes Byte High Enable (enables data on AD[15:8])

BE2# is not used (state is high)

R(1)

H(Z)

P(1)

BE1# becomes Address Bit 1 (A1)

BE0# becomes Byte Low Enable (enables data on AD[7:0])

BE[3:0]#

8-bit bus:

BE3# is not used (state is high)

BE2# is not used (state is high)

BE1# becomes Address Bit 1 (A1)

BE0# becomes Address Bit 0 (A0)

The processor asserts byte enables, byte high enable and byte low enable during T .

Since unaligned bus requests are split into separate bus transactions, these signals

do not toggle during a burst. They remain active through the last T_dcycle.

For accesses to 8- and 16-bit memory, the processor asserts the address bits in

conjunction with A[3:2] described above.

WIDTH/HALTED signals denote the physical memory attributes for a bus

transaction:

WIDTH/HLTD1

WIDTH/HLTD0

WIDTH/

HLTD[1:0]

R(0)

H(Z)

P(1)

8 Bits Wide

16 Bits Wide

32 Bits Wide

Processor Halted

The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in

response to a HOLD request, regardless of prior operating state.

DATA/CODE indicates that a bus access is a data access (1) or an instruction

access (0). D/C# has the same timing as W/R#.

R(X)

H(Z)

P(Q)

D/C#

W/R#

0 = instruction access

1 = data access

WRITE/READ specifies, during a T cycle, whether the operation is a write (1) or

read (0). It is latched on-chip and remains valid during T_dcycles.

R(0)

H(Z)

P(Q)

0 = read

1 = write

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the

address/data bus. It is low during T_aand T_w/T_dcycles for a read; it is high during T

and T_w/T_dcycles for a write. DT/R# never changes state when DEN# is asserted. ^a

R(0)

H(Z)

P(Q)

DT/R#

0 = receive

1 = transmit

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 3. Pin Description — External Bus Signals (Sheet 3 of 4)

NAME

TYPE

DESCRIPTION

DATA ENABLE indicates data transfer cycles during a bus access. DEN# is

asserted at the start of the first data cycle in a bus access and deasserted at the end

of the last data cycle. DEN# is used with DT/R# to provide control for data

transceivers connected to the data bus.

R(1)

H(Z)

P(1)

DEN#

0 = data cycle

1 = not data cycle

BURST LAST indicates the last transfer in a bus access. BLAST# is asserted in the

last data transfer of burst and non-burst accesses. BLAST# remains active as long

as wait states are inserted via the RDYRCV# pin. BLAST# becomes inactive after

the final data transfer in a bus cycle.

R(1)

H(Z)

P(1)

BLAST#

0 = last data transfer

1 = not last data transfer

READY/RECOVER indicates that data on AD lines can be sampled or removed. If

RDYRCV# is not asserted during a T_dcycle, the T_dcycle is extended to the next

cycle by inserting a wait state (T_w).

0 = sample data

1 = don’t sample data

RDYRCV#

S(L)

The RDYRCV# pin has another function during the recovery (T_r) state. The

processor continues to insert additional recovery states until it samples the pin

HIGH. This function gives slow external devices more time to float their buffers

before the processor begins to drive address again.

0 = insert wait states

1 = recovery complete

BUS LOCK indicates that an atomic read-modify-write operation is in progress. The

LOCK# output is asserted in the first clock of an atomic operation and deasserted in

the last data transfer of the sequence. The processor does not grant HOLDA while it

is asserting LOCK#. This prevents external agents from accessing memory involved

in semaphore operations.

I/O

0 = Atomic read-modify-write in progress

1 = Atomic read-modify-write not in progress

S(L)

R(H)

H(Z)

P(1)

LOCK#/

ONCE#

ONCE MODE: The processor samples the ONCE# input during reset. If it is

asserted LOW at the end of reset, the processor enters ONCE mode. In ONCE

mode, the processor stops all clocks and floats all output pins. The pin has a weak

internal pullup which is active during reset to ensure normal operation when the pin

is left unconnected.

0 = ONCE mode enabled

1 = ONCE mode not enabled

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 3. Pin Description — External Bus Signals (Sheet 4 of 4)

NAME

TYPE

DESCRIPTION

HOLD: A request from an external bus master to acquire the bus. When the

processor receives HOLD and grants bus control to another master, it asserts

HOLDA, floats the address/data and control lines and enters the T_hstate. When

HOLD is deasserted, the processor deasserts HOLDA and enters either the T_ior T

HOLD

S(L)

state, resuming control of the address/data and control lines.

0 = no hold request

1 = hold request

HOLD ACKNOWLEDGE indicates to an external bus master that the processor has

relinquished control of the bus. The processor can grant HOLD requests and enter

the T_hstate during reset and while halted as well as during regular operation.

R(Q)

H(1)

P(Q)

HOLDA

BSTAT

0 = hold not acknowledged

1 = hold acknowledged

BUS STATUS indicates that the processor may soon stall unless it has sufficient

access to the bus; see i960^®Jx Microprocessor Developer’s Manual (order number

272483). Arbitration logic can examine this signal to determine when an external bus

master should acquire/relinquish the bus.

R(0)

H(Q)

P(0)

0 = no potential stall

1 = potential stall

Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 1 of 2)

NAME

TYPE

DESCRIPTION

CLOCK INPUT provides the processor’s fundamental time base; both the processor

core and the external bus run at the CLKIN rate. All input and output timings are

specified relative to a rising CLKIN edge.

CLKIN

RESET initializes the processor and clears its internal logic. During reset, the

processor places the address/data bus and control output pins in their idle (inactive)

states.

During reset, the input pins are ignored with the exception of LOCK#/ONCE#,

STEST and HOLD.

RESET#

A(L)

The RESET# pin has an internal synchronizer. To ensure predictable processor

initialization during power up, RESET# must be asserted a minimum of 10,000

CLKIN cycles with V_CCand CLKIN stable. On a warm reset, RESET# should be

asserted for a minimum of 15 cycles.

SELF TEST enables or disables the processor’s internal self-test feature at

initialization. STEST is examined at the end of reset. When STEST is asserted, the

processor performs its internal self-test and the external bus confidence test. When

STEST is deasserted, the processor performs only the external bus confidence test.

STEST

S(L)

0 = self test disabled

1 = self test enabled

FAIL indicates a failure of the processor’s built-in self-test performed during

initialization. FAIL# is asserted immediately upon reset and toggles during self-test to

indicate the status of individual tests:

•

When self-test passes, the processor deasserts FAIL# and begins operation

from user code.

R(0)

H(Q)

P(1)

FAIL#

•

When self-test fails, the processor asserts FAIL# and then stops executing.

0 = self test failed

1 = self test passed

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1

Boundary Scan Testing (JTAG). State information and data are clocked into the

processor on the rising edge; data is clocked out of the processor on the falling edge.

TCK

TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising

edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.

TDI

S(L)

TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling

edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At

other times, TDO floats. TDO does not float during ONCE mode.

R(Q)

HQ)

P(Q)

TDO

TEST RESET asynchronously resets the Test Access Port (TAP) controller function

of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan

feature, connect a pulldown resistor between this pin and V_SS. If TAP is not used,

this pin must be connected to V_SS; however, no resistor is required. See Section 4.3,

“Connection Recommendations” on page 38.

TRST#

A(L)

TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of

the test logic for IEEE 1149.1 Boundary Scan testing.

TMS

V_CC

S(L)

–

POWER pins intended for external connection to a V_CCboard plane.

PLL POWER is a separate V_CCsupply pin for the phase lock loop clock generator. It

is intended for external connection to the V_CCboard plane. In noisy environments,

add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects

on timing relationships.

VCCPLL

VCC5

5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O

buffers. This signal should be connected to +5 V for use with inputs which exceed

3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V.

–

V_SS

–

GROUND pins intended for external connection to a V_SSboard plane.

NO CONNECT pins. Do not make any system connections to these pins.

Table 5. Pin Description — Interrupt Unit Signals

NAME

TYPE

DESCRIPTION

EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT[7:0]#

pins can be configured in three modes:

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs

can be programmed to be level (low) or edge (falling) sensitive.

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins

are level sensitive in this mode.

XINT[7:0]#

A(E/L)

Mixed Mode: The XINT[7:5]# pins act as dedicated sources and the XINT[4:0]# pins

act as the five most significant bits of a vectored source. The least significant bits of

the vectored source are set internally to 010₂(binary).

Unused external interrupt pins should be connected to V_CC

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

NMI# is the highest priority interrupt source and is falling edge-triggered. If NMI# is

NMI#

A(E)

unused, it should be connected to V_CC

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

3.1.2

80960Jx 132-Lead PGA Pinout

Figure 3. 132-Lead Pin Grid Array Top View - Pins Facing Down

V_CC

V_SS

AD9

V_CC

AD6 AD11 AD13

AD18 AD19 AD22 AD25

AD20 AD24 AD26 AD27

V_SS

AD3

AD7 AD10

AD12

AD21 AD23

AD0

V_CC

AD4 AD8

AD1 AD5

AD14 AD15 AD16

AD17

NC AD29 AD30

BE3# BE2#

AD28

V_CC

V_SSAD2

AD31 V_SS

BE1# V_SS

V_CC

V_SS

V_CC

A80960Jx

CLKIN V_SSVCCPLL

BE0#

V_CC

V_SS

ALE V_SS

V_CC

V_SS

BSTAT

DEN#

V_SS

V_CC

V_SSRDYRCV#

XXXXXXXX SS

V_CC

V_SS

RESET#

TDI

V_SS

DT/R# V_SS

V_CC

LOCK#/

ONCE#

NC STEST TRST# XINT0# XINT1# HOLD NC

VCC5

V_SS

FAIL#

V_SS

A3 BLAST# HOLDA

WIDTH/

TCK

XINT4#

XINT3# XINT6# V_SS

V_SS

NC TDO

D/C# W/R#

HLTD0

ALE#

TMS XINT2# XINT5# XINT7# NMI# V_CCV_CC

V_CC

WIDTH/ ADS#

HLTD1

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 4. 132-Lead Pin Grid Array Bottom View - Pins Facing Up

AD25 AD22 AD19 AD18 V_CC

AD27 AD26 AD24 AD20 V_SS

V_CC

V_CCAD13 AD11

V_SSAD10 AD7

AD6

AD3

V_SS

AD23 AD21

AD12

AD9

AD17

AD16 AD15 AD14

AD8 AD4

AD0

V_CC

AD30 AD29 NC

AD1

V_SS

AD5

AD2

BE2# BE3# AD28

V_CC

V_SS

V_CC

AD31

V_SS

V_CC

V_SSBE1#

VCCPLL V_SSCLKIN

V_CC

V_SS

BE0#

V_CC

V_SSALE

V_SS

V_CC

BSTAT

DEN#

V_CC

V_SS

RDYRCV#V_SS

RESET# V_SS

V_CC

V_SS

V_CC

V_SSDT/R#

TDI

V_SS

LOCK#/

ONCE#

HOLDA BLAST# A3

WIDTH/

FAIL#

V_SS

VCC5

V_SS

HOLD XINT1# XINT0# TRST# STEST NC

XINT4# TCK

XINT3#

W/R# D/C#

TDO NC

V_SS

V_SSXINT6#

HLTD0

ALE#

ADS# WIDTH/

HLTD1

V_CC

V_CCV_CCNMI# XINT7# XINT5# XINT2# TMS

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 6. 132-Lead PGA Pinout — In Signal Order

Signal

AD31

ADS#

ALE

TDO

TMS

TRST#

V_CC

VCCPLL

VCC5

V_SS

A14

C12

V_SS

AD0

M14

L13

K12

N14

M13

L12

P14

N13

M12

M11

N12

P13

M10

P12

V_SS

D13

AD1

ALE#

BE0#

BE1#

BE2#

BE3#

BLAST#

BSTAT

CLKIN

D/C#

V_SS

AD2

V_SS

E13

AD3

V_SS

AD4

V_SS

F13

AD5

V_SS

AD6

D14

V_SS

G13

AD7

V_SS

AD8

H14

E14

V_SS

H13

AD9

V_SS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

DEN#

DT/R#

FAIL#

HOLD

HOLDA

LOCK#/ONCE#

F14

G14

V_SS

J13

V_SS

K13

V_SS

J14

V_SS

K14

L14

V_SS

N10

N11

B14

V_SS

W/R#

WIDTH/HLTD0

WIDTH/HLTD1

XINT0#

XINT1#

XINT2#

XINT3#

XINT4#

XINT5#

XINT6#

XINT7#

C14

G12

J12

A10

F12

E12

C13

B13

D12

C11

C10

A13

B12

B11

A12

B10

A11

P10

P11

H12

NMI#

RDYRCV#

RESET#

STEST

TCK

V_SS

TDI

V_SS

NOTE: Do not connect external logic to pins marked NC (no connect pins).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 7. 132-Lead PGA Pinout — In Pin Order

Signal

ADS#

WIDTH/HLTD1

ALE#

FAIL#

VCC5

V_CC

V_SS

M10

M11

M12

M13

M14

AD12

AD9

AD8

AD4

AD0

AD27

AD26

AD24

AD20

V_SS

BE0#

VCCPLL

V_SS

HOLD

XINT1#

XINT0#

TRST#

STEST

H12

H13

H14

C10

C11

C12

C13

C14

V_CC

CLKIN

V_CC

V_SS

V_CC

BE1#

A10

A11

A12

A13

A14

NMI#

V_CC

J12

J13

J14

XINT7#

XINT5#

XINT2#

TMS

V_SS

DT/R#

TDI

V_CC

V_SS

D12

D13

D14

V_CC

V_SS

W/R#

V_CC

AD31

AD2

N10

N11

N12

N13

N14

V_SS

D/C#

V_CC

K12

K13

K14

V_SS

WIDTH/HLTD0

TDO

V_SS

AD10

AD7

AD3

AD25

AD22

AD19

AD18

V_CC

DEN#

RESET#

V_SS

V_CC

E12

E13

E14

BE2#

BE3#

AD28

AD5

V_SS

V_CC

V_SS

V_CC

L12

L13

L14

V_SS

AD1

B10

B11

B12

B13

B14

XINT6#

XINT4#

XINT3#

TCK

BSTAT

RDYRCV#

V_SS

V_CC

F12

F13

F14

AD30

AD29

V_CC

AD23

AD21

AD17

AD16

AD15

AD14

V_CC

LOCK#/ONCE#

HOLDA

BLAST#

V_SS

P10

P11

P12

P13

P14

V_CC

ALE

V_CC

G12

G13

G14

AD13

AD11

AD6

V_SS

V_CC

NOTE: Do not connect external logic to pins marked NC (no connect pins).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

3.1.3

80960Jx 132-Lead PQFP Pinout

Figure 5. 132-Lead PQFP - Top View

AD9

TRST#

TCK

TMS

HOLD

XINT0#

XINT1#

XINT2#

V_CC(I/O)

V_SS(I/O)

AD10

AD11

V_CC(I/O)

V_SS(I/O)

V_CC(Core)

XINT3#

_CC(I/O)

V_SS(I/O)

XINT4#

XINT5#

XINT6#

V_SS(Core)

AD12

AD13

AD14

AD15

V_CC(I/O)

XINT7#

NMI#

V_SS(I/O)

AD16

AD17

AD18

AD19

V_CC(Core)

V_SS(Core)

i960

_CC(I/O)

VCC5

FAIL#

ALE#

TDO

V_SS(I/O)

AD20

NG80960Jx

AD21

AD22

XXXXXXXX SS

AD23

V_CC(Core)

V_CC(I/O)

V_SS(I/O)

_SS(Core)

V_CC(I/O)

V_SS(I/O)

AD24

WIDTH/HLTD1

V_CC(Core)

V_SS(Core)

WIDTH/HLTD0

AD25

AD26

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 8. 132-Lead PQFP Pinout — In Signal Order

Signal

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

ALE#

ADS#

132

V_CC(Core)

V_SS(Core)

V_SS(I/O)

124

106

112

131

121

122

126

127

V_CC(Core)

BE3#

113

115

123

BE2#

BE1#

BE0#

_CC(I/O)

WIDTH/HLTD1

WIDTH/HLTD0

D/C#

W/R#

DT/R#

DEN#

BLAST#

RDYRCV#

LOCK#/ONCE#

HOLD

HOLDA

BSTAT

CLKIN

RESET#

STEST

FAIL#

117

125

128

105

111

129

119

VCCPLL

VCC5

AD8

100

101

102

103

104

107

108

109

110

_SS(CLK)

_SS(Core)

118

AD7

TCK

XINT7#

XINT6#

XINT5#

XINT4#

XINT3#

XINT2#

XINT1#

XINT0#

NMI#

AD6

TDI

130

AD5

TDO

AD4

TRST#

TMS

AD3

AD2

_CC(CLK)

120

V_SS(Core)

AD1

_CC(Core)

AD0

114

116

ALE

NOTE: Do not connect external logic to pins marked NC (no connect pins).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 9. 132-Lead PQFP Pinout — In Pin Order

Signal

TRST#

TCK

BLAST#

D/C#

AD26

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

AD8

AD7

TMS

ADS#

W/R#

AD25

AD6

HOLD

XINT0#

XINT1#

XINT2#

XINT3#

AD24

AD5

V_SS(Core)

V_SS(I/O)

V_CC(I/O)

V_SS(Core)

V_CC(Core)

AD23

AD4

V_CC(Core)

V_CC(I/O)

V_SS(I/O)

AD3

_SS(I/O)

V_CC(I/O)

DT/R#

DEN#

AD2

_SS(I/O)

AD22

AD1

XINT4#

XINT5#

XINT6#

XINT7#

NMI#

HOLDA

ALE

AD21

AD0

AD20

V_CC(I/O)

V_SS(Core)

V_SS(I/O)

V_CC(I/O)

AD19

V_SS(I/O)

V_CC(Core)

V_SS(Core)

V_CC(Core)

V_SS(Core)

CLKIN

V_CC(Core)

_SS(I/O)

_CC(Core)

V_CC(I/O)

LOCK#/ONCE#

BSTAT

AD18

_SS(Core)

AD17

AD16

BE0#

_SS(I/O)

_CC(I/O)

AD15

V_SS(CLK)

VCCPLL

V_{CC (CLK)}

VCC5

BE1#

BE2#

BE3#

AD14

FAIL#

ALE#

TDO

_SS(I/O)

_CC(I/O)

AD13

AD12

V_CC(Core)

V_SS(Core)

RESET#

V_SS(Core)

V_CC(Core)

V_SS(I/O)

V_CC(I/O)

V_CC(Core)

AD31

_SS(I/O)

WIDTH/HLTD1

_CC(Core)

_SS(Core)

AD30

_CC(I/O)

AD11

AD29

STEST

AD28

AD10

V_CC(I/O)

TDI

WIDTH/HLTD0

_SS(I/O)

_CC(I/O)

AD27

V_SS(I/O)

V_CC(I/O)

AD9

V_SS(I/O)

RDYRCV#

NOTE: Do not connect external logic to pins marked NC (no connect pins).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

3.1.4

80960Jx 196-Ball MPBGA Pinout

Figure 6. 196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down

AD28

V_CC

V_CCAD22

V_CC

AD18 V_CC

AD15 AD13 V_CC

AD8

AD30 AD27 AD29 V_CCAD23 AD20 AD17 AD14 AD12 AD10 AD9 AD7

AD4

V_CC

AD26 AD25

V_CC

AD3

AD24 AD21 AD19 AD16

AD11 AD6

AD5 AD0

AD2

AD1

AD31

V_SS

V_CC

V_SS

V_CC

V_CCVCCPLL

V_SS

NC CLKIN

V_SS

V_CC

BE1# BE2# BE3#

BSTAT

V_SS

V_CC

ALE

BE0#

V_SS

TDI

NC RESET#

LOCK#/

ONCE#

V_SS

STEST

V_CC

V_SS

HOLDA DEN#

V_CC

V_SS

NC RDYRCV#

DT/R#

V_CC

ALE# VCC5 V_CCXINT2# XINT0# TMS TRST# TCK

V_CC

TDO

NC XINT4#

XINT6#

XINT3# HOLD

XINT1#

W/R# D/C#

BLAST# V_CCWIDTH0

ADS#

WIDTH1FAIL#

NMI# XINT7#XINT5# V_CC

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 7. 196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up

V_CCAD13 AD15

V_CCAD18

V_CC

AD22 V_CC

V_CC

AD28

AD8

AD4

AD7 AD9 AD10 AD12 AD14 AD17 AD20 AD23 V_CCAD29 AD27 AD30

V_CC

AD3

V_SS

V_CC

V_SS

AD25 AD26

AD2

AD1

AD6 AD11

AD0 AD5

AD16 AD19 AD21 AD24

AD31

V_SS

V_CC

V_SS

V_CC

VCCPLL V_CC

V_CC

V_SS

V_CC

CLKIN NC

V_SS

V_CC

V_SS

V_SSBE3# BE2# BE1#

V_CC

V_SS

BSTAT

V_SS

BE0#

V_CC

ALE

RESET# NC

STEST V_CC

RDYRCV# NC

TDI

V_SS

LOCK#/

ONCE#

V_SS

V_CC

V_SS

DEN# HOLDA

V_SS

V_CC

DT/R#

TCK TRST# TMS XINT0# XINT2# V_CCVCC5 ALE#

V_CC

HOLD XINT3# XINT1# XINT6# NC XINT4# NC

TDO

V_CC

D/C# W/R#

WIDTH0 V

BLAST#

V_CCXINT5# XINT7# NMI# NC

FAIL# WIDTH1

ADS#

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 10. 196-Ball MPBGA Pinout — In Signal Order (Sheet 1 of 2)

Signal

D13

D14

C14

D11

B14

D12

C13

B13

A13

B12

B11

C12

B10

A11

BE0#

BE1#

BE2#

BE3#

BLAST#

BSTAT

CLKIN

DEN#

D/C#

DT/R#

FAIL#

HOLD

HOLDA

LOCK#/ONCE#

V_CC

VCCPLL

V_SS

AD0

K13

AD1

AD2

N10

AD3

AD4

G13

AD5

AD6

P14

P10

L14

J14

K14

M14

J12

AD7

NMI#

RDYRCV#

RESET#

STEST

TCK

TDI

P13

F14

D10

AD8

AD9

N14

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

ADS#

ALE

TDO

TMS

TRST#

VCC5

V_CC

A14

M12

M13

A10

V_CC

A12

V_CC

E10

E11

V_CC

G12

G14

H12

H14

J13

K12

L12

L13

V_CC

C10

C11

V_CC

E12

E13

E14

V_CC

F10

F11

V_CC

F12

F13

V_CC

ALE#

V_CC

H13

NOTE: Do not connect external logic to pins marked NC (no connect pins).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 10. 196-Ball MPBGA Pinout — In Signal Order (Sheet 2 of 2)

Signal

V_SS

G10

G11

V_SS

H11

V_SS

K10

K11

V_SS

L11

WIDTH0

WIDTH1

W/R#

XINT0#

XINT1#

XINT2#

XINT3#

XINT4#

XINT5#

XINT6#

XINT7#

M11

N12

M10

N13

J10

J11

P12

N11

P11

L10

H10

NOTE: Do not connect external logic to pins marked NC (no connect pins).

Table 11. 196-Ball MPBGA Pinout — In Pin Order (Sheet 1 of 2)

Signal

AD28

V_CC

C11

C12

C13

C14

V_CC

AD11

AD6

AD2

V_SS

V_CC

VCCPLL

BSTAT

V_SS

F10

F11

F12

F13

F14

V_SS

V_CC

V_SS

AD22

V_CC

V_SS

AD18

V_CC

V_SS

AD3

AD5

AD0

AD1

J10

J11

J12

J13

J14

V_SS

A10

A11

A12

A13

A14

AD15

AD13

V_CC

TDI

V_CC

V_SS

RESET#

ALE

AD8

D10

D11

D12

D13

D14

LOCK#/ONCE#

V_CC

V_SS

AD30

AD27

AD29

V_CC

G10

G11

G12

AD23

NOTE: Do not connect external logic to pins marked NC (no connect pins).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 11. 196-Ball MPBGA Pinout — In Pin Order (Sheet 2 of 2)

Signal

AD20

AD17

AD14

AD12

AD10

AD9

V_CC

V_SS

G13

G14

CLKIN

K10

K11

K12

K13

K14

V_SS

BE1#

BE2#

BE3#

V_SS

B10

B11

B12

B13

B14

V_SS

V_CC

V_SS

STEST

HOLDA

DEN#

V_CC

AD7

V_SS

AD4

E10

E11

E12

E13

E14

V_SS

AD31

V_CC

V_SS

AD26

AD25

AD24

AD21

AD19

AD16

V_CC

H10

H11

H12

H13

H14

V_SS

V_CC

V_SS

V_CC

V_SS

L10

L11

L12

V_SS

V_CC

V_SS

C10

L13

L14

V_SS

BE0#

TDO

M10

M11

M12

M13

M14

XINT2#

XINT0#

TMS

TRST#

TCK

W/R#

D/C#

V_CC

RDYRCV#

DT/R#

V_CC

WIDTH0

WIDTH1

FAIL#

XINT4#

NC#

N10

N11

N12

N13

N14

XINT6#

XINT1#

XINT3#

HOLD

P10

P11

P12

P13

P14

NMI#

XINT7#

XINT5#

V_CC

ALE#

VCC5

V_CC

ADS#

BLAST#

V_CC

NOTE: Do not connect external logic to pins marked NC (no connect pins).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

3.2

Package Thermal Specifications

The 80960Jx is specified for operation when T (case temperature) is within the range of 0°C to

100°C for PGA, MPBGA and PQFP packages. Case temperature may be measured in any

environment to determine whether the 80960Jx is within its specified operating range. The case

temperature should be measured at the center of the top surface, opposite the pins.

is the thermal resistance from case to ambient. Use the following equation to calculate T , the

maximum ambient temperature to conform to a particular case temperature:

T_A= T_C- P (θ_CA

)

Junction temperature (T ) is commonly used in reliability calculations. T can be calculated from

(thermal resistance from junction to case) using the following equation:

T_J= T_C+ P (θ_JC

)

Similarly, if T is known, the corresponding case temperature (T ) can be calculated as follows:

T_C= T_A+ P (θ_CA

)

Compute P by multiplying I from Table 21 and V . Values for θ and θ are given in

Table 12 for the PGA package, Table 13 for the MPBGA package, and Table 14 for the PQFP

package. For high speed operation, the processor’s θ may be significantly reduced by adding a

heatsink and/or by increasing airflow.

Tables 15 and 16 show the maximum ambient temperature (T ) permitted without exceeding T

for the PGA, MPBGA, and PQFP packages. The values are based on typical I and V of

+3.3 V, with a T

of +100°C.

CASE

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 12. 132-Lead PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft/min (m/sec)

Parameter

200

400

600

800

1000

(0)

(1.01)

(2.03)

(3.04)

(4.06)

(5.08)

θ_JC(Junction-to-Case)

θ_CA(Case-to-Ambient) (No Heatsink)

0.7

_CA(Case-to-Ambient) (Omnidirectional Heatsink)

_CA(Case-to-Ambient) (Unidirectional Heatsink)

θ_JA

θ_CA

θ_JC

θ_J-PIN

θ_J-CAP

NOTES:

1. This table applies to a PGA device plugged into a socket or soldered directly into a board.

2. θ = θ + θ

3. θ

4. θ

5. θ

6. θ

7. θ

8. θ

= 5.6°C/W (approximate) (no heatsink)

J-CAP

J-PIN

J-CAP

J-PIN

= 6.4°C/W (inner pins) (approximate) (no heatsink)

= 6.2°C/W (outer pins) (approximate) (no heatsink)

= 3°C/W (approximate) (with heatsink)

= 3.3°C/W (inner pins) (approximate) (with heatsink)

= 3.3°C/W (outer pins) (approximate) (with heatsink)

Table 13. 196-Ball MPBGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft/min (m/sec)

Parameter

200

400

600

800

1000

(0)

(1.01)

(2.03)

(3.04)

(4.06)

(5.08)

θ_JC(Junction-to-Case)

θ_CA(Case-to-Ambient) (No Heatsink)

TBD

_CA(Case-to-Ambient) (Omnidirectional Heatsink)

_CA(Case-to-Ambient) (Unidirectional Heatsink)

TBD

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 14. 132-Lead PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft/min (m/sec)

Parameter

100

200

400

600

800

(0)

(0.25)

(0.50)

(1.01)

(2.03)

(3.04)

(4.06)

θ_JC(Junction-to-Case)

4.1

4.3

4.7

4.9

θ_CA(Case-to-Ambient -No Heatsink)

θ_CA

θ_JA

θ_JC

θ_JB

θ_JL

NOTES:

1. This table applies to a PQFP device soldered directly into board.

2. θ = θ + θ

JA JC

3. θ = 13°C/W (approx.)

4. θ = 13.5°C/W (approx.)

Table 15. Maximum T at Various Airflows in °C (80960JC)

Airflow — ft/min (m/sec)

200 400 600 800

f_CLKIN

(MHz)

(0)

1000

(1.01) (2.03) (3.04) (4.06) (5.07)

PQFP

Package

T_Awithout Heatsink

16.67

T_Awithout Heatsink

16.67

PGA

T_Awith Omnidirectional

Package Heatsink¹

16.67

T_Awith Unidirectional

Heatsink²

16.67

TBD

MPBGA

Package

T_Awithout Heatsink

NOTES:

1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).

2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 16. Maximum T at Various Airflows in °C (80960JS)

Airflow — ft/min (m/sec)

f_CLKIN(MHz)

(0)

200

400

600

800

1000

(1.01) (2.03) (3.04) (4.06) (5.07)

PQFP

Package

T_Awithout Heatsink

PGA

T_Awith Omnidirectional

Package Heatsink¹

_Awith Unidirectional

Heatsink²

TBD

MPBGA

Package

T_Awithout Heatsink

NOTES:

1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).

2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).

3.3

Thermal Management Accessories

The following is a list of suggested sources for 80960Jx thermal solutions. This is neither an

endorsement or a warranty of the performance of any of the listed products and/or companies.

3.3.1

Heatsinks

1. Thermalloy, Inc.

2021 West Valley View Lane

Dallas, TX 75234-8993

(972) 243-4321

2. Wakefield Engineering

60 Audubon Road

Wakefield, MA 01880

(617) 245-5900

3. Aavid Thermal Technologies, Inc.

One Kool Path

Laconia, NH 03247-0400

(603) 528-3400

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

4.0

Electrical Specifications 80960JS/JC 3.3 V

Processor

Note: This document contains information on products in the sampling and initial production phases of

development. It is valid for the devices indicated in the revision history. The specifications within

this data sheet are subject to change without notice. Verify with your local Intel sales office that

you have the latest data sheet before finalizing a design.

4.1

Absolute Maximum Ratings

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only.

Table 17. Absolute Maximum Ratings

Parameter

Maximum Rating

Storage Temperature

–65^oC to +150^oC

–65^oC to +110^oC

–0.5 V to + 4.6 V

–0.5 V to + 6.5 V

Case Temperature Under Bias

Supply Voltage wrt. V_SS

Voltage on VCC5 wrt. V_SS

Voltage on Other Pins wrt. V_SS

–0.5 V to V_CC+ 0.5 V

4.2

Operating Conditions

Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond

the “Operating Conditions” may affect device reliability.

Table 18 indicates the operating conditions for the 80960JS/JC.

Table 18. 80960JS/JC Operating Conditions

Symbol

Parameter

Min

Max

Units

Notes

Supply Voltage

3.15

3.45

5.5

VCC5

Input Protection Bias

Input Clock Frequency

(1)

80960JC-66

80960JC-50

80960JC-40

80960JC-33

80960JS-33

80960JS-25

80960JS-16

33.3

16.67

33.3

MHz

°C

CLKIN

Operating Case Temperature

PGA, MPBGA, and PQFP

T_C

100

1. See Section 4.4, “VCC5 Pin Requirements (VDIFF)” on page 38.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

4.3

Connection Recommendations

For clean on-chip power distribution, V and V pins separately feed the device’s functional units.

Power and ground connections must be made to all 80960Jx power and ground pins. On the circuit board,

every V pin should connect to a power plane and every V pin should connect to a ground plane. Place

liberal decoupling capacitance near the 80960Jx, since the processor can cause transient power surges.

Pay special attention to the Test Reset (TRST#) pin. It is essential that the JTAG Boundary Scan Test Access

Port (TAP) controller initializes to a known state whether it will be used or not. If the JTAG Boundary Scan

function will be used, connect a pulldown resistor between the TRST# pin and V . If the JTAG Boundary

Scan function will not be used (even for board-level testing), connect the TRST# pin to V .

Do not connect the TDI, TDO, and TCK pins if the TAP Controller will not be used.

Note: Pins identified as NC must not be connected in the system.

4.4

VCC5 Pin Requirements (VDIFF)

In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5

pin directly to the 3.3 V V plane.

In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V

components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation,

and prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and

its 3.3 V V pins must not exceed 2.25 V. If this requirement is not met, current flow through the

pin may exceed the value at which the processor is damaged. Instances when the voltage can

exceed 2.25 V is during power up or power down, where one source reaches its level faster than the

other, briefly causing an excess voltage differential. Another instance is during steady-state

operation, where the differential voltage of the regulator (provided a regulator is used) cannot be

maintained within 2.25 V. Two methods are possible to prevent this from happening:

• Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V, or,

• As shown in Figure 8, place a 100 Ω resistor in series with the VCC5 pin to limit the current

through VCC5.

Figure 8. VCC5 Current-Limiting Resistor

VCC5 Pin

+5 V (±0.25 V)

100 Ω

(±5%, 0.5 W)

If the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and

reliable method for limiting current. The resistor can also prevent damage in the case of a power

failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 19. VDIFF Parameters

Symbol

Parameter

Min

Max

Units

Notes

VCC5 input should not exceed V_CCby more than 2.25 V

during power-up and power-down, or during steady-

state operation.

VCC5-V_CC

Difference

VDIFF

2.25

4.5

VCCPLL Pin Requirements

To reduce clock skew on the i960 80960Jx processor, the VCCPLL pin for the Phase Lock Loop

(PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 9, reduces noise

induced clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor

must be low ESR solid tantalum; the 0.01 µF capacitor must be of the type X7R and the node

connecting VCCPLL must be as short as possible.

Figure 9. VCCPLL Lowpass Filter

Ω

VCCPLL

(On 80960Jx)

V_CC

(Board Plane)

4.7 µF

0.01 µF

F_CA078A

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

4.6

DC Specifications

Table 20. 80960JS/JC DC Characteristics

Symbol

V_IL

Parameter

Min

Typ

Max

Units

Notes

Input Low Voltage

Input High Voltage

-0.3

2.0

0.8

V_IH

VCC5 + 0.3

0.4

0.2

I_OL= 3 mA

V_OL

Output Low Voltage

= 100 µA

2.4

V_CC- 0.2

I_OH= -1 mA

_OH= -200 µA

V_OH

Output High Voltage

V_OLP

Output Ground Bounce

<0.8

(1,2)

Input Capacitance

PGA

PQFP

C_IN

= f_MIN(2)

CLKIN

MPBGA

I/O or Output Capacitance

PGA

PQFP

MPBGA

C_OUT

= f_MIN(2)

CLKIN Capacitance

PGA

PQFP

C_CLK

= f_MIN(2)

MPBGA

NOTES:

1. Typical is measured with V_CC= 3.3 V and temperature = 25°C.

2. Not tested.

Table 21. 80960JS/JC I Characteristics (Sheet 1 of 2)

Symbol

Parameter

Typ

Max

Units

Notes

Input Leakage Current for each pin

except TCK, TDI, TRST# and TMS

I_LI1

I_LI2

I_LO

R_pu

± 1

µA

kΩ

0 ≤ V_IN≤ V_CC

Input Leakage Current for TCK,

TDI, TRST# and TMS

-140

-250

± 1

V_IN= 0.45 V (1)

0.4 ≤ V_OUT

≤

Output Leakage Current

V_CC

Internal Pull-UP Resistance for

ONCE#, TMS, TDI and TRST#

NOTES:

1. These pins have internal pullup devices. Typical leakage current is not tested.

2. Measured with device operating and outputs loaded to the test condition in Figure 10 “AC Test Load” on

page 44.

3. I_CCActive (Power Supply) value is provided for selecting your system’s power supply. It is measured using

one of the worst case instruction mixes with V_CC= 3.45 V. This parameter is characterized but not tested.

4. I_CCActive (Thermal) value is provided for your system’s thermal management. Typical I_CCis measured with

V_CC=3.3 V and temperature = 25°C. This parameter is characterized but not tested.

5. I_CCTest (Power modes) refers to the I_CCvalues that are tested when the 80960JS/JC is in Reset mode,

Halt mode or ONCE mode with V_CC= 3.45 V.

6. I_CC5is tested at V_CC= 3.3 V, VCC5 = 5.25 V.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 21. 80960JS/JC I Characteristics (Sheet 2 of 2)

Symbol

Parameter

Typ

Max

Units

Notes

80960JC-66

439

330

267

225

250

190

120

(2,3)

80960JC-50

80960JC-40

80960JC-33

80960JS-33

80960JS-25

80960JS-16

I_CCActive

(Power Supply)

(2,4)

80960JC-66

80960JC-50

80960JC-40

80960JC-33

80960JS-33

80960JS-25

80960JS-16

370

280

220

185

180

138

I_CCActive

(Thermal)

Reset mode

80960JC-66

80960JC-50

80960JC-40

80960JC-33

80960JS-33

80960JS-25

80960JS-16

246

190

144

120

138

100

(5)

_CCTest

Halt mode

(Power modes)

80960JC-66

80960JC-50

80960JC-40

80960JC-33

80960JS-33

80960JS-25

80960JS-16

(5)

TBD

Once Mode

(5)

80960JC-66

80960JC-50

80960JC-40

80960JC-33

80960JS-33

80960JS-25

80960JS-16

(6)

_CC5Current on the

200

µA

VCC5 Pin

NOTES:

1. These pins have internal pullup devices. Typical leakage current is not tested.

2. Measured with device operating and outputs loaded to the test condition in Figure 10 “AC Test Load” on

page 44.

3. I_CCActive (Power Supply) value is provided for selecting your system’s power supply. It is measured using

one of the worst case instruction mixes with V_CC= 3.45 V. This parameter is characterized but not tested.

4. I_CCActive (Thermal) value is provided for your system’s thermal management. Typical I_CCis measured with

V_CC=3.3 V and temperature = 25°C. This parameter is characterized but not tested.

5. I_CCTest (Power modes) refers to the I_CCvalues that are tested when the 80960JS/JC is in Reset mode,

Halt mode or ONCE mode with V_CC= 3.45 V.

6. I_CC5is tested at V_CC= 3.3 V, VCC5 = 5.25 V.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

4.7

AC Specifications

The 80960JS/JC AC timings are based upon device characterization.

Table 22. 80960JS/JC AC Characteristics (Sheet 1 of 2)

Symbol

Parameter

Min

Max

Unit

Notes

INPUT CLOCK TIMINGS

CLKIN Frequency

80960JC-66

80960JC-50

80960JC-40

80960JC-33

80960JS-33

80960JS-25

80960JS-16

33.3

16.67

33.3

T_F

MHz

CLKIN Period

80960JC-66

80960JC-50

80960JC-40

80960JC-33

80960JS-33

80960JS-25

80960JS-16

66.7

T_C

62.5

T_CS

T_CH

CLKIN Period Stability

CLKIN High Time

± 250

(1, 2)

Measured at 1.5 V

(1)

Measured at 1.5 V

(1)

T_CL

CLKIN Low Time

T_CR

T_CF

CLKIN Rise Time

CLKIN Fall Time

0.8 V to 2.0 V (1)

2.0 V to 0.8 V (1)

SYNCHRONOUS OUTPUT TIMINGS

Output Valid Delay, Except ALE/ALE#

Inactive and DT/R# for 3.3 V input signals

2.5

13.5

16.5

T_OV1

(3)

(4)

Output Valid Delay, Except ALE/ALE#

Inactive and DT/R# for 5.0 V input signals

T_OV2

T_OF

Output Valid Delay, DT/R#

Output Float Delay

0.5T_C+ 7 0.5T_C+ 9

2.5 13.5

NOTE: See Table 23 on page 44 for note definitions for this table.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 22. 80960JS/JC AC Characteristics (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Unit

Notes

SYNCHRONOUS INPUT TIMINGS

Input Setup to CLKIN — AD[31:0], NMI#,

XINT[7:0]#

T_IS1

T_IH1

T_IS2

T_IH2

(5)

(6)

Input Hold from CLKIN — AD[31:0], NMI#,

XINT[7:0]#

1.5

6.5

Input Setup to CLKIN — RDYRCV# and

HOLD

Input Hold from CLKIN — RDYRCV# and

HOLD

T_IS3

T_IH3

T_IS4

Input Setup to CLKIN — RESET#

(7)

(8)

Input Hold from CLKIN — RESET#

Input Setup to RESET# — ONCE#, STEST

Input Hold from RESET# — ONCE#,

STEST

T_IH4

(8)

RELATIVE OUTPUT TIMINGS

Address Valid to ALE/ALE# Inactive

0.5T_C- 5

For 3.3 V Data Input Signals

T_LX

(9)

Address Valid to ALE/ALE# Inactive

For 5.0 V Data Input Signals

0.5T_C- 8

T_LXL

T_LXA

T_DXD

ALE/ALE# Width

Address Hold from ALE/ALE# Inactive

DT/R# Valid to DEN# Active

0.5T_C- 7

Equal Loading (9)

BOUNDARY SCAN TEST SIGNAL TIMINGS

T_BSF

TCK Frequency

TCK High Time

0.5T_F

MHz

Measured at 1.5 V

(1)

T_BSCH

Measured at 1.5 V

(1)

T_BSCL

TCK Low Time

T_BSCR

T_BSCF

T_BSIS1

T_BSIH1

TCK Rise Time

TCK Fall Time

0.8 V to 2.0 V (1)

2.0 V to 0.8 V (1)

Input Setup to TCK — TDI, TMS

Input Hold from TCK — TDI, TMS

T_BSOV1TDO Valid Delay

(1,10)

T_BSOF1TDO Float Delay

T_BSOV2All Outputs (Non-Test) Valid Delay

T_BSOF2All Outputs (Non-Test) Float Delay

T_BSIS2

T_BSIH2

Input Setup to TCK — All Inputs (Non-Test)

Input Hold from TCK — All Inputs (Non-

Test)

NOTE: See Table 23 on page 44 for note definitions for this table.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 23. Note Definitions for Table 22, “80960JC/JS AC Characteristics”

NOTES:

1. Not tested.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN

frequency.

3. Inactive ALE/ALE# refers to the falling edge of ALE and the rising edge of ALE#. For inactive ALE/ALE#

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is

designed to be no longer than the valid delay.

5. AD[31:0] are synchronous inputs. Setup and hold times must be met for proper processor operation.

NMI# and XINT[7:0]# may be synchronous or asynchronous. Meeting setup and hold time guarantees

recognition at a particular clock edge. For asynchronous operation, NMI# and XINT[7:0]# must be

asserted for a minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV# and HOLD are synchronous inputs. Setup and hold times must be met for proper processor

operation.

7. RESET# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at

a particular clock edge.

8. ONCE# and STEST# must be stable at the rising edge of RESET# for proper operation.

9. Guaranteed by design. May not be 100% tested.

10.Relative to falling edge of TCK.

11.Worst-case T_OVcondition occurs on I/O pins when pins transition from a floating high input to driving a

low output state. The Address/Data Bus pins encounter this condition between the last access of a read,

and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at

50 pF loads.

4.7.1

AC Test Conditions and Derating Curves

The AC Specifications in Section 4.7, “AC Specifications” are tested with the 50 pF load indicated

in Figure 10. Figure 11 shows how timings and output rise and fall times vary with load

capacitance.

Figure 10. AC Test Load

Output Pin

_L= 50 pF for all signals

C_L

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 11. Output Delay or Hold vs. Load Capacitance (3.3 V Signals)

AC Timings vs. Load Capacitance

(3.3 V Signals)

nom + 10

nom + 8

nom + 6

nom + 4

nom + 2

nom + 0

100

150

AD Bus Capacitive Load (pF)

Figure 12. Output Delay or Hold vs. Load Capacitance (5 V Signals)

AC Timings vs. Load Capacitance

(5 V Signals)

nom + 16

nom + 14

nom + 12

nom + 10

nom + 8

nom + 6

nom + 4

nom + 2

nom + 0

100

150

AD Bus Capacitive Load (pF)

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 13. T vs. AD Bus Load Capacitance (3.3 V Signals)

AC Timings vs. Load Capacitance

(3.3 V Signals)

nom - 10

nom - 8

nom - 6

nom - 4

nom - 2

nom - 0

100

150

AD Bus Capacitive Load (pF)

Note: The T Derating curve applies only when an imbalance in the capacitive load occurs between the

AD bus and ALE. The T derating is based on a 50 pF load on ALE. The derating applies to ALE

and ALE#.

Figure 14. T vs. AD Bus Load Capacitance (5 V Signals)

AC Timings vs. Load Capacitance

(5 V Signals)

nom - 20

nom - 15

nom - 10

nom - 5

nom - 0

100

AD Bus Capacitive Load (pF)

150

Note: The T Derating curve applies only when an imbalance in the capacitive load occurs between the

AD bus and ALE. The T derating is based on a 50 pF load on ALE. The derating applies to ALE

and ALE#.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 15. 80960JC I Active (Power Supply) vs. Frequency

Icc Active (Power Supply) vs Frequency

80960 JC

500

450

400

350

300

250

200

150

100

CLKIN Frequency MHz

Figure 16. 80960JC I Active (Thermal) vs. Frequency

Icc Active (Thermal) vs Frequency

80960 JC

400

350

300

250

200

150

100

CLKIN Frequency M Hz

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 17. 80960JS I Active (Power Supply) vs. Frequency

Icc Active (Power Supply) vs Frequency

80960 JS

300

250

200

150

100

CLKIN Frequency MHz

Figure 18. 80960JS I Active (Thermal) vs. Frequency

Icc Active (Thermal) vs. Frequency

80960 JS

200

180

160

140

120

100

CLKIN Frequency MHz

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

4.7.2

AC Timing Waveforms

Figure 19. CLKIN Waveform

2.0V

1.5V

0.8V

Figure 20. T

Output Delay Waveform

OV1

1.5V

CLKIN

OV1

AD[31:0],

ALE (active),

ALE# (active),

ADS#, A[3:2],

1.5V

BE[3:0]#,

WIDTH/HLTD[1:0],

D/C#, W/R#, DEN#,

BLAST#, LOCK#,

HOLDA, BSTAT, FAIL#

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 21. T Output Float Waveform

1.5V

CLKIN

AD[31:0],

ALE, ALE#

ADS#, A[3:2],

BE[3:0]#,

WIDTH/HLTD[1:0],

D/C#, W/R#, DT/R#,

DEN#, BLAST#, LOCK#

Figure 22. T_IS1and T_IH1Input Setup and Hold Waveform

1.5V

CLKIN

IH1

IS1

AD[31:0]

NMI#

Valid

1.5V

XINT[7:0]#

Figure 23. T_IS2and T_IH2Input Setup and Hold Waveform

1.5V

CLKIN

IH2

IS2

HOLD,

1.5V

Valid

1.5V

RDYRCV#

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 24. T_IS3and T_IH3Input Setup and Hold Waveform

1.5V

CLKIN

IS3

IH3

RESET#

Figure 25. T_IS4and T_IH4Input Setup and Hold Waveform

RESET#

IH4

IS4

ONCE#,

Valid

STEST

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 26. T_LX, T_LXLand T_LXARelative Timings Waveform

T_a

T_w/T_d

1.5V

CLKIN

T_LXL

ALE

1.5V

Valid

1.5V

ALE#

T_LX

T_LXA

1.5V

AD[31:0]

Valid

Figure 27. DT/R# and DEN# Timings Waveform

T_a

T_w/T_d

CLKIN

1.5V

T_OV2

Valid

DT/R#

T_DXD

DEN#

T_OV1

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 28. TCK Waveform

BSCR

BSCF

2.0V

1.5V

0.8V

BSCH

BSCL

Figure 29. T_BSIS1and T_BSIH1Input Setup and Hold Waveforms

1.5V

TCK

BSIH1

BSIS1

TMS

TDI

1.5V

Valid

1.5V

Figure 30. T_BSOV1and T_BSOF1Output Delay and Output Float Waveform

TCK

1.5V

BSOV1

BSOF1

Valid

1.5V

TDO

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 31. T_BSOV2and T_BSOF2Output Delay and Output Float Waveform

TCK

1.5V

BSOF2

BSOV2

Non-Test

Outputs

Valid

1.5V

Figure 32. T_BSIS2and T_BSIH2Input Setup and Hold Waveform

TCK

1.5V

T_BSIH2

T_BSIS2

Non-Test

Inputs

1.5V

Valid

1.5V

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

5.0

Bus Functional Waveforms

Figure 33 through Figure 38 illustrate typical 80960Jx bus transactions. Figure 39 depicts the bus

arbitration sequence. Figure 40 illustrates the processor reset sequence from the time power is

applied to the device. Figure 41 illustrates the processor reset sequence when the processor is in

operation. Figure 42 illustrates the processor ONCE# sequence from the time power is applied to

the device. Figure 44 and Figure 45 also show accesses on 32-bit buses. Table 26 through Table 27

summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to

data alignment.

Figure 33. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus

T_a

T_d

T_r

T_i

T_a

T_d

T_r

T_i

CLKIN

ADDR

Invalid

DATA Out

AD[31:0]

ALE

ADS#

A[3:2]

BE[3:0]#

WIDTH[1:0]

D/C#

W/R#

BLAST#

DT/R#

DEN#

RDYRCV#

F_JF030A

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 34. Burst Read and Write Transactions Without Wait States, 32-Bit Bus

T_A

T_D

T_R

T_A

T_D

T_DT_D

T_R

CLKIN

DATA

Out

DATA

Out

DATA DATA

Out

ADDR

AD[31:0]

Out

ALE

ADS#

00 or 10

01 or 11

A[3:2]

BE[3:0]#

1 0

WIDTH[1:0]

D/C#

W/R#

BLAST#

DT/R#

DEN#

RDYRCV#

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 35. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus

T_A

T_W

T_D

T_W

T_D

T_W

T_D

T_W

T_D

T_R

CLKIN

AD[31:0]

ALE

DATA

Out

DATA

Out

DATA

Out

DATA

Out

ADDR

ADS#

A[3:2]

0 0

0 1

1 0

1 1

BE[3:0]#

WIDTH[1:0]

D/C#

1 0

W/R#

BLAST#

DT/R#

DEN#

RDYRCV#

F_JF032A

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 36. Burst Read and Write Transactions Without Wait States, 8-Bit Bus

T_A

T_D

T_R

T_A

T_D

T_R

CLKIN

DATA

Out

DATA DATA

DATA

ADDR

AD[31:0]

Out

Out Out

ALE

ADS#

A[3:2]

00,01,10 or 11

01 or

BE1#/A1

BE0#/A0

00 or 10

WIDTH[1:0]

D/C#

W/R#

BLAST#

DT/R#

DEN#

RDYRCV#

F_JF033A

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 37. Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on Read,

16-Bit Bus

T_WT_D

T_D

T_R

T_A

T_W

T_DT_D

T_R

T_A

CLKIN

AD[31:0]

ALE

DATA

Out

ADDR

Out

ADS#

00,01,10, or 11

A[3:2]

BE1#/A1

BE3#/BHE

BE0#/BLE

WIDTH[1:0]

D/C#

W/R#

BLAST#

DT/R#

DEN#

F_JF034A

RDYRCV#

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 38. Double Word Read Bus Request, Misaligned One Byte From

Quad Word Boundary, 32-Bit Bus, Little Endian

T_A

T_D

T_R

T_A

T_D

T_R

T_A

T_D

T_R

T_A

T_D

T_R

CLKIN

AD[31:0]

ALE

ADS#

A[3:2]

BE[3:0]#

WIDTH[1:0]

D/C#

0 0 0 0

1 1 1 0

0 0 1 1

1 1 0 1

1 0

Valid

W/R#

BLAST#

DT/R#

DEN#

RDYRCV#

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 39. HOLD/HOLDA Waveform For Bus Arbitration

T_Ior T_R

T_H

T_Ior T_A

CLKIN

Outputs:

AD[31:0],

ALE, ALE#,

ADS#, A[3:2],

BE[3:0]#,

Valid

WIDTH/HLTD[1:0],

D/C#, W/R#,

DT/R#, DEN#,

BLAST#, LOCK#

HOLD

HOLDA

(Note)

NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the

same edge in which it recognizes HOLD if the last state was T_ior the last T_rof a bus transaction. Similarly,

the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 40. Cold Reset Waveform

~ ~

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 41. Warm Reset Waveform

~ ~

~ ~ ~ ~ ~ ~ ~ ~ ~

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 42. Entering the ONCE State

~ ~

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

5.1

Basic Bus States

The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold

(Th). During system operation, the processor continuously enters and exits different bus states.

The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET#

is asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address.

Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data

lines. Assertion of the RDYRCV# input signal indicates completion of each transfer. When data is

not ready, the processor can wait as long as necessary for the memory or I/O device to respond.

After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a

burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word.

The processor asserts the BLAST# signal during the last Tw/Td states of an access. Once all data

words transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to

recover.

The processor remains in the Tr state until RDYRCV# is deasserted. When the recovery state

completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the

bus enters the Ta state to transmit the new address.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 43. Bus States with Arbitration

(READY AND BURST)

OR NOT READY

Tw/Td

RECOVERED AND

REQUEST

PENDING AND (NO

HOLD OR LOCKED)

READY AND NO BURST

REQUEST PENDING

AND (NO HOLD OR

LOCKED)

NOT

RECOVERED

RECOVERED AND

NO REQUEST AND

(NO HOLD OR

LOCKED)

REQUEST

PENDING AND

NO HOLD

NO REQUEST

AND (NO HOLD

OR LOCKED)

ONCE & RESET

DEASSERTION

RECOVERED AND

HOLD AND NOT

LOCKED

NO REQUEST

AND NO HOLD

RESET

HOLD AND

NOT LOCKED

HOLD

READY — RDYRCV# ASSERTED

Ti — IDLE STATE

Ta — ADDRESS STATE

NOT READY — RDYRCV# NOT ASSERTED

BURST — BLAST# NOT ASSERTED

NO BURST — BLAST# ASSERTED

Tw / Td — WAIT/DATA STATE

Tr — RECOVERY STATE

Th — HOLD STATE

RECOVERED — RDYRCV# NOT ASSERTED

NOT RECOVERED — RDYRCV# ASSERTED

REQUEST PENDING — NEW TRANSACTION

NOREQUEST — NO NEW TRANSACTION

HOLD — HOLD REQUEST ASSERTED

To — ONCE STATE

NO HOLD — HOLD REQUEST NOT ASSERTED

LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS

NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS

RESET — RESET# ASSERTED

ONCE — ONCE# ASSERTED

5.2

Boundary-Scan Register

The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins.

Table 24 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that

contain “CTL” select the direction of bidirectional pins or HIGHZ output pins. If a “1” is loaded

into the control cell, the associated pin(s) are HIGHZ or selected as input.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 24. Boundary-Scan Register Bit Order

Input/

Output

Input/

Output

Input/

Output

Bit

Signal

Bit

Signal

Bit

Signal

RDYRCV#

(TDI)

DEN#

AD17

I/O

HOLD

HOLDA

ALE

AD16

AD15

I/O

XINT0#

LOCK#/ONCE#

cell

XINT1#

Enable cell^†

AD14

I/O

XINT2#

XINT3#

LOCK#/ONCE#

BSTAT

I/O

AD13

AD12

I/O

Enable

cell^†

XINT4#

BE0#

AD cells

XINT5#

XINT6#

XINT7#

NMI#

BE1#

BE2#

BE3#

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD11

AD10

AD9

I/O

AD8

FAIL#

AD7

ALE#

AD6

WIDTH/HLTD1

WIDTH/HLTD0

AD5

AD4

AD3

AD2

CONTROL1

CONTROL2

BLAST#

D/C#

Enable cell^†

AD1

Enable cell^†

AD0

CLKIN

RESET#

STEST

(TDO)

ADS#

AD20

I/O

W/R#

AD19

AD18

I/O

DT/R#

†

Enable cells are active low.

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 25. Natural Boundaries for Load and Store Accesses

Data Width

Natural Boundary (Bytes)

Byte

Short Word

Word

Double Word

Triple Word

Quad Word

Table 26. Summary of Byte Load and Store Accesses

Address Offset from

Natural Boundary

(in Bytes)

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit

Bus (WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

+0 (aligned)

•

byte access

•

byte access

•

byte access

Table 27. Summary of Short Word Load and Store Accesses

Address Offset from

Natural Boundary

(in Bytes)

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit

Bus (WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

+0 (aligned)

•

burst of 2 bytes

2 byte accesses

•

short-word access

2 byte accesses

•

short-word access

2 byte accesses

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 28. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)

Address Offset

from Natural

Boundary in Bytes

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit Bus

(WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

•

case n=1:

burst of 2 short words

case n=2:

burst of 4 short words

+0 (aligned)

(n =1, 2, 3, 4)

•

n burst(s) of 4 bytes

•

burst of n word(s)

case n=3:

burst of 4 short words

burst of 2 short words

•

case n=4:

2 bursts of 4 short words

•

byte access

•

byte access

+1 (n =1, 2, 3, 4)

+5 (n = 2, 3, 4)

+9 (n = 3, 4)

•

byte access

short-word access

burst of 2 bytes

n-1 burst(s) of 4 bytes

byte access

n-1 burst(s) of 2 short

words

n-1 word

access(es)

+13 (n = 3, 4)

•

byte access

•

byte access

+2 (n =1, 2, 3, 4)

+6 (n = 2, 3, 4)

+10 (n = 3, 4)

+14 (n = 3, 4)

•

short-word access

•

short-word access

•

burst of 2 bytes

n-1 burst(s) of 2 short

words

n-1 word

access(es)

n-1 burst(s) of 4 bytes

burst of 2 bytes

•

short-word access

•

short-word access

•

byte access

•

byte access

+3 (n =1, 2, 3, 4)

+7 (n = 2, 3, 4)

+11 (n = 3, 4)

+15 (n = 3, 4)

•

byte access

n-1 burst(s) of 2 short

words

n-1 word

access(es)

n-1 burst(s) of 4 bytes

burst of 2 bytes

byte access

•

short-word access

byte access

•

short-word access

byte access

+4 (n = 2, 3, 4)

+8 (n = 3, 4)

•

n burst(s) of 4 bytes

•

n burst(s) of 2 short words

•

n word access(es)

+12 (n = 3, 4)

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 44. Summary of Aligned and Unaligned Accesses (32-Bit Bus)

Byte Offset

Word Offset

Short Access (Aligned)

Byte, Byte Accesses

Short-Word

Load/Store

Short Access (Aligned)

Byte, Byte Accesses

Word Access (Aligned)

Byte, Short, Byte, Accesses

Short, Short Accesses

Word

Load/Store

Byte, Short, Byte Accesses

One Double-Word Burst (Aligned)

Byte, Short, Word, Byte Accesses

Short, Word, Short Accesses

Double-Word

Load/Store

Byte, Word, Short, Byte Accesses

Word, Word Accesses

One Double-Word

Burst (Aligned)

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Figure 45. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)

Byte Offset

Word Offset

One Three-Word

Burst (Aligned)

Byte, Short, Word,

Word, Byte Accesses

Short, Word, Word,

Short Accesses

Triple-Word

Load/Store

Byte, Word, Word,

Short, Byte Accesses

Word, Word,

Word Accesses

Word, Word,

Word Accesses

Word,

Word

Accesses

One Four-Word

Burst (Aligned)

Byte, Short, Word, Word,

Word, Byte Accesses

Short, Word, Word, Word,

Short Accesses

Quad-Word

Load/Store

Byte, Word, Word, Word,

Short, Byte Accesses

Word, Word, Word,

Word Accesses

Word,

Accesses

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

6.0

Device Identification 80960JS/JC 3.3 V Processor

80960JS/JC processors may be identified electrically, according to device type and stepping (see

Figure 46, and Table 29 through Table 31). Table 29 identifies the device type and stepping for the

80960JS/JC processors. Figure 46, and Table 30 and Table 31 identify all 3.3 V-5 V-tolerant

80960JS/JC processors. The device ID was enhanced to differentiate between non-clock-doubled

and clock-doubled cores. The 32-bit identifier is accessible in three ways:

• Upon reset, the identifier is placed into the g0 register.

• The identifier may be accessed from supervisor mode at any time by reading the DEVICEID

• The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the

IDCODE instruction.

• The device and stepping letter is also printed on the top side of the product package.

Table 29. 80960JS/JC Device Type and Stepping Reference

Device and

Stepping

Version

Number

Complete ID

(Hex)

Part Number

Manufacturer

80960JC A1

80960JS A1

0011

0000 1000 0011 0011

0000 1000 0010 0011

0000 0001 001

30833013

30823013

Figure 46. 80960JS/JC Device Identification Register

Part Number

Product

V_CC

Type

Version

Gen

Model

Manufacturer ID

0 1

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

Table 30. Fields of 80960JS/JC Device ID

Field

Version

Value

See Table 31

Definition

Indicates major stepping changes.

V_CC

0 = 3.3 V device

Indicates that a device is 3.3 V.

000 100

(Indicates i960 CPU)

Product Type

Designates type of product.

Generation Type 0001 = J-series

Indicates the product’s generation (or series).

D DPCC

D = Clock Multiplier

(00) Not Clock-Doubled

(10) Clock-Doubled

Indicates member within a series and specific model

information.

Model

(P) Product Derivative

(0) Jx

C = Cache Size

(11) 16K I-cache, 4K

D-cache

000 0000 1001

(Indicates Intel)

Manufacturer ID

Manufacturer ID assigned by IEEE.

Table 31. 80960JS/JC Device ID Model Types

Device

80960JS A1

Version V_CC

Product

Gen.

Model

Manufacturer ID

‘1’

0000

000100

0001

00011

10011

00000001001

80960JC A1

Advanced Information Datasheet

80960JS/JC 3.3 V Microprocessor

7.0

Revision History

Table 32. Datasheet Revision History

Version

Date

Description

002

001

12/98

09/98

Corrected orientation of MPBGA package diagrams (Figures 6 and 7).

Initial version.

Advanced Information Datasheet

GD80960JC-40 [INTEL]

相关型号：

GD80960JC-50

GD80960JD-33

GD80960JD-40

GD80960JD-50

GD80960JD-66

GD80960JF-16

GD80960JF-25

GD80960JF-33

GD80960JF16

GD80960JF25

GD80960JF33

GD80960JS-25