N80930AD4 [INTEL]
UNIVERSAL SERIAL BUS MICROCONTROLLER; 通用串行总线的微控制器
| 型号： | N80930AD4 |
| 厂家： | 
INTEL |
| 描述： | UNIVERSAL SERIAL BUS MICROCONTROLLER |
| 文件： | 总38页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
8x930Ax
UNIVERSAL SERIAL BUS
MICROCONTROLLER
■ Complete Universal Serial Bus
■ Low Clock Mode
Specification 1.0 Compatibility
■ User-selectable Configurations
— External Wait State
— Address Range
— Supports Isochronous and
Non-isochronous Data
— Bidirectional Half-duplex Link
— Page Mode
■ On-chip USB Transceiver
■ Real-time Wait Function
■ Serial Bus Interface Engine (SIE)
— Packet Decoding/Generation
— CRC Generation and Checking
■ 256-Kbyte External Code/Data Memory
Space
■ On-chip ROM Options
— NRZI Encoding/Decoding and
Bit-stuffing
— 0, 8, or 16 Kbytes
■ 1 Kbyte On-chip Data RAM
■ Four Input/Output Ports
— 1 Open-drain port
■ USB Reset Interrupt
■ Four Transmit FIFOs
— Three 16-byte FIFOs
— 3 Quasi-bidirectional Ports
— One Configurable FIFO (up to
1 Kbyte)
■ Programmable Counter Array (PCA)
— 5 Capture/Compare Modules
■ Four Receive FIFOs
■ Serial I/O Port (UART)
— Three 16-byte FIFOs
■ Hardware Watchdog Timer
■ Three Flexible 16-bit Timer/Counters
— One Configurable FIFO (up to
1 Kbyte)
■ Automatic Transmit/Receive FIFO
■ Power-saving Idle and Powerdown
Management
Modes
■ Register-based MCS® 251 Architecture
■ Suspend/Resume Operation
■ Three New USB Interrupt Vectors
— USB Function Interrupt
— Start of Frame
— 40-byte Register File
— Registers Accessible as Bytes,
Words, or Doublewords
■ Code Compatible with MCS 51 and MCS
— Suspend/Resume
251 Microcontrollers
■ Phase-locked Loop
■ 6 or 12 MHz Crystal Operation
— 12 Mbps or 1.5 Mbps Data Rate
The 8x930Ax USB microcontroller is based on an 8xC251Sx microcontroller core. It consists of standard
8xC251Sx peripherals plus an added USB function. The 8x930Ax uses the standard instruction set of the
MCS 251 architecture, which is binary code compatible with the MCS 51 architecture. The USB function
integrates the USB transceiver, serial bus interface engine (SIE), function interface unit (FIU) and
transmit/receive FIFOs. The USB function also supports full-speed/low-speed data rates, suspend/resume
modes, isochronous/non-isochronous transfers, and is fully compliant with the USB rev 1.0 specification.
COPYRIGHT © INTEL CORPORATION, 1997
February 1997
Order Number: 272917-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth-
erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The product may contain design defects or errors known as errata. Current characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
COPYRIGHT © INTEL CORPORATION, 1997
CONTENTS
1.0 Nomenclature Overview...................................................................................................... 3
2.0 Pinout.................................................................................................................................. 4
3.0 Signals ................................................................................................................................ 7
4.0 Address Map..................................................................................................................... 10
5.0 Electrical Characteristics................................................................................................... 11
5.1 Operating Frequencies................................................................................................. 12
5.2 DC Characteristics........................................................................................................ 13
5.3 Definition of AC Symbols.............................................................................................. 15
5.4 AC Characteristics........................................................................................................ 16
5.4.1 System Bus AC Characteristics ............................................................................16
5.4.2 System Bus Timing Diagrams, Nonpage Mode ....................................................18
5.4.3 System Bus Timing Diagrams, Page Mode ...........................................................20
5.4.4 Definition of Real-time Wait Symbols ....................................................................22
5.4.5 Real-time Wait Function AC Characteristics .........................................................22
5.4.6 Real-Time Wait Function Timing Diagrams ...........................................................23
5.5 AC Characteristics — Serial Port, Synchronous Mode 0 ............................................. 27
5.6 External Clock Drive..................................................................................................... 28
5.7 Testing Waveforms ...................................................................................................... 29
6.0 Thermal Characteristics .................................................................................................... 30
7.0 Product Reference ............................................................................................................ 30
7.1 External Bus Timing and Peripheral Timing Affected by PLLSEL2:0 Selection........... 30
7.2 Low Clock Mode Frequency......................................................................................... 30
7.3 Setting FFRC Bit Clears Only the Oldest Packet in the FIFO ...................................... 30
7.4 Series Resistor Requirement for Impedance Matching................................................ 30
7.5 Pullup Requirement for Full Speed Device and Low Speed Device............................. 30
7.6 Powerdown Mode Cannot Be Invoked Before USB Suspend...................................... 30
8.0 Specification Supplement for 8x930Ax3 and 8x930Ax4.................................................... 31
8.1 Six Endpoint Pairs Functionality................................................................................... 31
8.2 DC Characteristics........................................................................................................ 31
8.3 Extended Data Float (EDF) AC Timing Feature........................................................... 31
9.0 Device Errata .................................................................................................................... 34
10.0 Datasheet Revision History............................................................................................... 34
iii
8x930Ax UNIVERSAL SERIAL BUS MICROCONTROLLER
Figures
1.
2.
3.
4.
5.
6.
7.
8.
9.
8x930Ax Internal Block Diagram..........................................................................................1
USB Module Block Diagram.................................................................................................2
Product Nomenclature .........................................................................................................3
8x930Ax 68-pin PLCC Package...........................................................................................4
Clock Circuit.......................................................................................................................12
8x930Ax Code Fetch, Nonpage Mode...............................................................................18
8x930Ax Data Read, Nonpage Mode ................................................................................19
8x930Ax Data Write, Nonpage Mode.................................................................................19
8x930Ax Code Fetch, Page Mode .....................................................................................20
10. 8x930Ax Data Read, Page Mode.......................................................................................21
11. 8x930Ax Data write, Page Mode........................................................................................21
12. External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State) .........................23
13. External Data Write (Nonpage Mode, Real-time Wait State) .............................................24
14. External Data Read (Page Mode, Real-time Wait State) ...................................................25
15. External Data Write (Page Mode, Real-time Wait State) ...................................................26
16. Serial Port Waveform — Synchronous Mode 0..................................................................27
17. External Clock Drive Waveforms........................................................................................28
18. AC Testing Input, Output Waveforms.................................................................................29
19. Float Waveforms ................................................................................................................29
Tables
1.
2.
3.
4.
5.
6.
7.
8.
9.
Description of Product Nomenclature...................................................................................3
Proliferation Options.............................................................................................................3
68-pin PLCC Pin Assignment...............................................................................................5
68-pin PLCC Signal Assignments Arranged by Functional Category ..................................6
Signal Descriptions ..............................................................................................................7
Memory Signal Selections (RD1:0) ....................................................................................10
8x930Ax Address Map.......................................................................................................10
Frequency Selection and Operating Frequency.................................................................12
DC Characteristics at Operating Conditions.......................................................................13
10. AC Timing Symbol Definitions............................................................................................15
11. AC Characteristics at Operating Conditions.......................................................................16
12. Real-time Wait Timing Symbol Definitions .........................................................................22
13. Real-time Wait AC Timing Specifications...........................................................................22
14. Serial Port Timing — Synchronous Mode 0 .......................................................................27
15. External Clock Drive...........................................................................................................28
16. Thermal Characteristics .....................................................................................................30
17. SIx Endpoint Pair Feature..................................................................................................31
18. Effect of “EDF#” on Wait States .........................................................................................31
19. AC Characteristics for 8x930Ax3 and 8x930Ax4 in Compatibility Mode............................32
20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings.................................32
21. 8x930Ax3 and 8x930Ax4 Real-time Wait State AC Timing Specifications ........................33
iv
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
I/O Ports and
Peripheral Signals
System Bus and I/O Ports
P0.7:0
P1.7:0
P2.7:0
P3.7:0
Port 0
Drivers
Port 2
Drivers
Port 1
Drivers
Port 3
Drivers
RAM
ROM
Memory Data (16)
Watchdog
Timer
Memory Address (16)
Bus Interface
Peripheral
Interface
Timer/
Counters
Code Bus (16)
Code Address (24)
Interrupt
Handler
Instruction Sequencer
PCA
SRC1 (8)
SRC2 (8)
Serial I/O
Clock
&
Reset
Data
Register
File
Memory
Interface
ALU
†
USB
DST (16)
Microcontroller Core
USB Ports
†
For details, see the USB module block diagram.
A4340-01
Figure 1. 8x930Ax Internal Block Diagram
ADVANCE INFORMATION
1
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
USB
Upstream
Port
Transceiver
Serial Bus
Interface Engine
(SIE)
Control
Function
Interface Unit
(FIU)
To
CPU
Control
FIFOs
Control
A4231-03
Figure 2. USB Module Block Diagram
2
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
1.0 NOMENCLATURE OVERVIEW
X
XX
8
X
X
XXXXX XX
A2815-01
Figure 3. Product Nomenclature
Table 1. Description of Product Nomenclature
Parameter
Options
Description
o
o
Temperature and Burn-in
no mark
Commercial operating temperature range (0 C to 70 C) with
Intel standard burn-in.
Packaging Options
N
Plastic Leaded Chip Carrier (PLCC)
Without ROM
Program Memory Options
0
3
With ROM
Process and Voltage Information
Product Family
no mark
930
CHMOS
Advanced 8-bit microcontroller architecture with on-chip Uni-
versal Serial Bus (USB) function peripherals
Device Speed
no mark
6 or 12 MHz crystal
Table 2. Proliferation Options
ROM Size
Product Name
80930AD
RAM Size
0
1 Kbyte
1 Kbyte
1 Kbyte
83930AD
8 Kbytes
83930AE
16 Kbytes
ADVANCE INFORMATION
3
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
2.0 PINOUT
Figure 4 illustrates the 8x930Ax PLCC package.
Table 3 lists the pin assignments by pin number,
and Table 4 lists the pin assignments by functional
categories. Table 5 describes the signals.
AD7 / P0.7
AD6 / P0.6
AD5 / P0.5
AD4 / P0.4
AD3 / P0.3
AD2 / P0.2
AD1 / P0.1
AD0 / P0.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Reserved
Reserved
Reserved
Reserved
Reserved
D
P0
D
M0
ECAP
V
V
SSP
SSP
V
V
CCP
View of component as
mounted on PC board
CCP
P3.0 / RXD
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
SOF#
Reserved
Reserved
Reserved
Reserved
Reserved
PLLSEL0
P3.5 / T1
P3.6 / WR#
Note: Reserved pins must be left unconnected.
A4392-02
Figure 4. 8x930Ax 68-pin PLCC Package
4
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 3. 68-pin PLCC Pin Assignment
Pin
1
Name
VSS
Pin
Name
Pin
Name
24 P3.4/T0
25 P3.5/T1
47 Reserved
48 Reserved
49 Reserved
50 SOF#
2
A15/P2.7
A14/P2.6
A13/P2.5
A12/P2.4
A11/P2.3
A10/P2.2
A9/P2.1
3
26 P3.6/WR#
27 P3.7/RD#/A16
28 P1.0/T2
4
5
51 VCCP
6
29 P1.1/T2EX
30 P1.2/ECI
31 P1.3/CEX0
32 P1.4/CEX1
33 P1.5/CEX2
34 P1.6/CEX3/WAIT#
35 P1.7/CEX4/A17/WCLK
36 VCC
52 VSSP
7
53 ECAP
8
54 DM0
9
A8/P2.0
55 DP0
10 AD7/P0.7
11 AD6/P0.6
12 AD5/P0.5
13 AD4/P0.4
14 AD3/P0.3
15 AD2/P0.2
16 AD1/P0.1
17 AD0/P0.0
18 VSSP
56 Reserved
57 Reserved
58 Reserved
59 Reserved
60 Reserved
61 Reserved
62 Reserved
63 Reserved
64 Reserved
65 PSEN#
66 ALE
37 VSS
38 XTAL1
39 XTAL2
40 AVCC
41 RST
19 VCCP
42 PLLSEL1
43 PLLSEL2
44 PLLSEL0
45 Reserved
46 Reserved
20 P3.0/RXD
21 P3.1/TXD
22 P3.2/INT0#
23 P3.3/INT1#
67 EA#
68 VCC
ADVANCE INFORMATION
5
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 4. 68-pin PLCC Signal Assignments Arranged by Functional Category
Address & Data
Name
Input/Output
Name
USB
Name
PLLSEL0
Pin
17
16
15
14
13
12
11
10
9
Pin
28
29
30
31
32
33
34
35
20
21
24
25
Pin
44
42
43
50
53
54
55
AD0/P0.0
P1.0/T2
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P2.0
P1.1/T2EX
P1.2/ECI
PLLSEL1
PLLSEL2
SOF#
ECAP
DM0
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
P3.0/RXD
DP0
Processor Control
A9/P2.1
8
P3.1/TXD
Name
P3.2/INT0#
P3.3/INT1#
EA#
Pin
A10/P2.2
7
P3.4/T0
22
23
67
41
38
39
A11/P2.3
6
P3.5/T1
A12/P2.4
5
A13/P2.5
4
Bus Control & Status
Name Pin
P3.6/WR#
RST
A14/P2.6
3
XTAL1
A15/P2.7
2
26
27
66
65
XTAL2
P3.7/RD#/A16
P1.7/CEX4/A17/WCLK
27
35
P3.7/RD#/A16
ALE
PSEN#
Power & Ground
Name
Pin
36, 68
19, 51
40
VCC
VCCP
AVCC
EA#
VSS
67
1, 37
18, 52
VSSP
6
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 5. Signal Descriptions
3.0 SIGNALS
Signal
Name
Type
Description
Alternate Function
A17
O
18th Address Bit (A17). Output to memory as 18th exter-
nal address bit (A17) in extended bus applications, depend-
ing on the values of bits RD0 and RD1 in configuration byte
UCONFIG0. See also RD#, PSEN#.
P1.7/CEX4/WCLK
A16
O
O
Address Line 16. See RD#.
RD#
†
A15:8
Address Lines. Upper address lines for the external bus.
P2.7:0
P0.7:0
†
AD7:0
ALE
I/O
Address/Data Lines. Multiplexed lower address lines and
data lines for external memory.
O
Address Latch Enable (ALE). ALE signals the start of an
external bus cycle and indicates that valid address informa-
tion is available on lines A15:8 and AD7:0. An external latch
can use ALE to demultiplex the address from the
address/data bus.
PROG#
AVCC
PWR Analog VCC. A separate VCC input for the phase-locked loop
circuitry.
CEX2:0
CEX3
CEX4
I/O
Programmable Counter Array (PCA) Input/Output Pins. P1.5:3
These are input signals for the PCA capture mode and out- P1.6/WAIT#
put signals for the PCA compare mode and PCA PWM
mode.
P1.7/A17/WCLK
DM0
DP0
EA#
I/O
I/O
I
Data Minus. USB minus data line interface.
Data Plus. USB plus data line interface.
—
—
External Access. Directs program memory accesses to
on-chip or off-chip code memory. For EA# strapped to
ground, all program memory accesses are off-chip. For EA#
strapped to VCC, program accesses on-chip ROM if the
address is within the range of the on-chip ROM; otherwise,
the access is off-chip. The value of EA# is latched at reset.
For devices without on-chip ROM, EA# must be strapped to
ground.
ECAP
I
External Capacitor. Must be connected to a 1 µF capacitor
(or larger) to ensure proper operation of the differential line
driver. The other lead of the capacitor must be connected to
VSS
.
ECI
I
I
PCA External Clock Input. External clock input to the 16-
P1.2
bit PCA timer.
INT1:0#
External Interrupts 0 and 1. These inputs set bits IE1:0 in P3.3:2
the TCON register. If bits IT1:0 in the TCON register are
set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If
bits INT1:0 are clear, bits IE1:0 are set by a low level on
INT1:0#.
P0.7:0
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the
chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-
ries the upper address bits (A15:8) and the data (D7:0).
ADVANCE INFORMATION
7
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 5. Signal Descriptions (Continued)
Signal
Type
Description
Alternate Function
Name
P1.0
I/O
Port 1. This is an 8-bit, bidirectional I/O port with internal
pullups.
T2
P1.1
P1.2
P1.5:3
P1.6
P1.7
T2EX
ECI
CEX2:0
CEX3/WAIT#
CEX4/A17/WCLK
P2.7:0
I/O
I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal
A15:8
pullups.
P3.0
P3.1
Port 3. This is an 8-bit, bidirectional I/O port with internal
pullups.
RXD
TXD
P3.3:2
P3.5:4
P3.6
INT1:0#
T1:0
WR#
P3.7
RD#/A16
PLLSEL2:0
I
Phase-locked Loop Select. Three-bit code selects USB
data rate (see Table 8 on page 12).
—
PSEN#
O
Program Store Enable. Read signal output. This output is
asserted for a memory address range that depends on bits
RD0 and RD1 in configuration byte UCONFIG0 (see RD#).
—
RD#
RST
O
I
Read or 17th Address Bit (A16). Read signal output to
external data memory or 17th external address bit (A16),
depending on the values of bits RD0 and RD1 in configura-
tion byte UCONFIG0 (See PSEN#).
P3.7/A16
—
Reset. Reset input to the chip. Holding this pin high for 64
oscillator periods while the oscillator is running resets the
device. The port pins are driven to their reset conditions
when a voltage greater than V is applied, whether or not
IH1
the oscillator is running. This pin has an internal pulldown
resistor which allows the device to be reset by connecting a
capacitor between this pin and VCC
.
Asserting RST when the chip is in idle mode or powerdown
mode returns the chip to normal operation.
RXD
I/O
O
Receive Serial Data. RXD sends and receives data in
serial I/O mode 0 and receives data in serial I/O modes 1, 2,
and 3.
P3.0
—
SOF#
Start of Frame. Start of Frame pulse. Active low, asserted
for 8 states (see Table 8 on page 12 for state versus XTAL
clock) when Frame Timer is locked to USB frame timing
and SOF token or artificial SOF is detected.
T1:0
I
Timer 1:0 External Clock Inputs. When timer 1:0 operates P3.5:4
as a counter, a falling edge on the T1:0 pin increments the
count.
T2
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode, P1.0
this signal is the external clock input. For the clock-out
mode, it is the timer 2 clock output.
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the
chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-
ries the upper address bits (A15:8) and the data (D7:0).
8
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 5. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate Function
T2EX
I
Timer 2 External Input. In timer 2 capture mode, a falling
edge initiates a capture of the timer 2 registers. In auto-
reload mode, a falling edge causes the timer 2 registers to
be reloaded. In the up-down counter mode, this signal
determines the count direction: 1 = up, 0 = down.
P1.1
TXD
O
Transmit Serial Data. TXD outputs the shift clock in serial
I/O mode 0 and transmits serial data in serial I/O modes 1,
2, and 3.
P3.1
VCC
PWR Supply Voltage. Connect this pin to the +5V supply volt-
—
—
age.
VCCP
PWR Supply Voltage for I/O buffers. Connect this pin to the
+5V supply voltage.
VSS
GND Circuit Ground. Connect this pin to ground.
—
VSSP
GND Circuit Ground for I/O buffers. Connect this pin to ground.
—
WAIT#
I
Real-time Wait State Input. The real-time WAIT# input is
enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit
at S:A7H. During bus cycles, the external memory system
can signal ‘system ready’ to the microcontroller in real time
by controlling the WAIT# input signal on the port 1.6 input.
P1.6/CEX3
WCLK
O
Wait Clock Output. The real-time WCLK output is driven at P1.7/CEX4/A17
port 1.7 (WCLK) by writing a logical ‘1’ to the WCON.1
(RTWCE) bit at S:A7H. When enabled, the WCLK output
produces a square wave signal with a period of TCLK
.
WR#
O
I
Write. Write signal output to external memory.
P3.6
—
XTAL1
Input to the On-chip, Inverting, Oscillator Amplifier. To
use the internal oscillator, a crystal/resonator circuit is con-
nected to this pin. If an external oscillator is used, its output
is connected to this pin. XTAL1 is the clock source for inter-
nal timing.
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier. To
use the internal oscillator, a crystal/resonator circuit is con-
nected to this pin. If an external oscillator is used, leave
XTAL2 unconnected.
—
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the
chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-
ries the upper address bits (A15:8) and the data (D7:0).
ADVANCE INFORMATION
9
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 6. Memory Signal Selections (RD1:0)
RD1:0
A17/P1.7
/CEX4/WCLK
A16/P3.7/RD#
PSEN#
WR#
Features
†
0
0
1
0
1
0
A17
A16
Asserted for
Asserted for writes to 256-Kbyte external
memory
all addresses all memory locations
P1.7/CEX4/WCLK A16
Asserted for
all addresses all memory locations memory
Asserted for writes to 128-Kbyte external
P1.7/CEX4/WCLK P3.7 only
Asserted for
all addresses all memory locations
Asserted for writes to 64-Kbyte external
memory
One additional port
pin
1
1
P1.7/CEX4/WCLK RD# Asserted Asserted for
Asserted for all com-
Compatible with
for addresses
addresses
patible MCS 51 mem- MCS 51 microcon-
≤ 7F:FFFFH
≥ 80:0000H
ory locations
trollers
†
RD1:0 are bits 3:2 of configuration byte UCONFIG0. Refer to figure 4-3 on page 4-5 in the 8x930Ax Uni-
versal Serial Bus Microcontroller User’s Manual.
4.0 ADDRESS MAP
Table 7. 8x930Ax Address Map
Description
Internal
Address
Notes
FF:FFFFH
FF:0000H
External Memory: The last eight bytes of the external address range FF:XFF8H–
FF:XFFFH contain configuration byte information.
1, 2, 3
FE:FFFFH
FE:0000H
External Memory
2
FD:FFFFH
02:0000H
Reserved Addresses
External Memory
4
01:FFFFH
01:0000H
2
00:FFFFH
00:0420H
External Memory
5
00:041FH
00:0080H
On-chip RAM
5
00:007FH
00:0020H
On-chip RAM
6
00:001FH
00:0000H
Storage for R0–R7 of Register File
7, 8
NOTES:
1. Eighteen address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. Data in this area is accessible by indirect addressing only.
3. Eight addresses at the top of all external memory maps are reserved for current and future device
configuration byte information.
4. This reserved area returns unspecified values and writes no data.
5. Data is accessible by direct and indirect addressing.
6. Data is accessible by direct, indirect, and bit addressing.
7. The special function registers (SFRs) and the register file have separate internal address spaces.
8. Data is accessible by direct, indirect, and register addressing.
10
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
NOTICE: This document contains information on
products in the sampling and initial production
phases of development. The specifications are
subject to change without notice. Verify with your
local Intel sales office that you have the latest
datasheet before finalizing a design.
OL per I/O Pin................................................................. 15 mA
Ambient Temperature Under Bias.................... -40°C to +85°C
Storage Temperature ................................... -65°C to +150°C
Voltage on Any Pins to VSS ............................. -0.5 V to +6.5 V
I
Power Dissipation .......................................................... 1.5 W
†
WARNING: Stressing the device beyond the
†
OPERATING CONDITIONS
“Absolute Maximum Ratings” may cause perma-
nent damage. These are stress ratings only. Oper-
ation beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device
reliability.
TA (Ambient Temperature Under Bias):
Commercial........................................................ -0°C to +70°C
V
V
CC/VCCP (Digital Supply Voltage) .................. 4.00 V to 5.25 V
SS / VSSP............................................................................ 0 V
AVCC (Analog Supply Voltage) ...................... 4.00 V to 5.25 V
OSC .............................................................. 6 MHz or 12 MHz
F
NOTE: Maximum power dissipation is based on
package heat-transfer limitations, not device
power consumption.
ADVANCE INFORMATION
11
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.1 Operating Frequencies
Table 8. Frequency Selection and Operating Frequency
8x930Ax
Number of
XTAL1
Clocks
Internal
Frequency
for CPU
and
Peripherals
USB Rate
(Low
Speed
or Full
Speed)
XTAL1
External
Frequency
PLLSEL2 PLLSEL1 PLLSEL0
(TOSC
)
Comments
Pin 43
Pin 42
Pin 44
in One
StateTime
(4)
(FOSC)
(FCLK
(5)
)
0
0
0
1
1
0
0
1.5 Mbps
(LS)
3 MHz
6 MHz
12 MHz
12 MHz
2 TOSC/state PLL Off
2TOSC/state PLL Off
1TOSC/state PLL On
1
1
1.5 Mbps
(LS)
6 MHz (3)
12 MHz (3)
12 Mbps
(FS)
NOTES:
1. Other PLLSELx combinations are not valid.
2. The sampling rate is 4X the USB rate.
3. The 8x930Ax CPU and peripherals frequency is 3 MHz (low clock mode) until firmware disables the
low clock mode.
4. The number of XTAL clocks in one state depends on the PLLSELx selections. When the CPU is oper-
ating at low clock mode (3 MHz), there are four TOSC per state for the PLLSEL2:1:0 = 100 and 110.
5. The AC timing specification (Table 11) defines the following symbol: CPU frequency = FCLK = 1/TCLK
.
FOSC
Internal Clock
(6 or 12 MHz)
÷ 2
0
FCLK
XTAL1
XTAL2
Clock
Generator
0
1
On-chip
Peripherals
1
3 MHz
CPU
PD
LC
PCON.5
(Low-clock Mode)
IDL
PCON.1
(Powerdown)
PCON.0
(Idle Mode)
2
1
0
PLLSEL
A5135-01
Figure 5. Clock Circuit
12
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.2 DC Characteristics
Table 9. DC Characteristics at Operating Conditions
Symbol
Parameter
Min
Typical (1)
Max
Units
Test Conditions
VIL
Input Low Voltage
(Except EA#)
-0.5
0.2 VCC – 0.1
V
VIL1
VIH
Input Low Voltage
(EA#)
0
0.2 VCC – 0.3
VCC + 0.5
V
V
V
Input High Voltage
(Except XTAL1, RST)
0.2 VCC + 0.9
0.7 VCC
VIH1
VOL
Input High Voltage
(XTAL1, RST)
VCC + 0.5
Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
IOL = 100 µA (2, 3)
IOL = 1.6 mA
V
V
V
V
IOL = 3.5 mA
VOL1
Output Low Voltage
(Port 0, ALE, PSEN#,
SOF#)
0.3
0.45
1.0
IOL = 200 µA (2, 3)
IOL = 3.2 mA
IOL = 7.0 mA
VOH
Output High Voltage
(Port 1, 2, 3,ALE,
PSEN#, SOF#)
V
CC – 0.3
IOH = -10 µA (4)
VCC – 0.7
VCC – 1.5
IOH = -30 µA
IOH = -60 µA
VOH1
Output High Voltage
(Port 0 in External
Address)
V
CC – 0.3
IOH = -200 µA (4)
VCC – 0.7
VCC – 1.5
IOH = -3.2 mA
IOH = -7.0 mA
IIL
Logical 0 Input
–150
VIN = 0.45 V
µA
µA
Current (Port 1,2,3)
ILI
Input Leakage Current
(Port 0)
±10
0.45 < VIN < VCC
NOTE:
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOH per port pin:10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total IOL for all output pins: 71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC specifica-
tion when the address lines are stabilizing.
5. The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
ADVANCE INFORMATION
13
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 9. DC Characteristics at Operating Conditions (Continued)
Symbol
Parameter
Min
Typical (1)
Max
Units
Test Conditions
ITL
Logical 1-to-0
Transition Current
(Port 1, 2,3)
-650
VIN = 2.0 V
µA
RRST
CIO
RST Pulldown
Resistor
40
225
KΩ
10
FOSC = 12 MHz
TA = 25°C
pF
IPD
Powerdown Current
— Normal powerdown
— USB suspend
25
50
µA
145
175
IDL (5)
Idle Mode ICC
40
PLLSEL = 110
3MHz – FS
(in low clock mode)
100
PLLSEL = 110
12MHz – FS
mA
(not in low clock
mode)
30
55
PLLSEL = 001
3MHz – LS
PLLSEL = 100
6 MHz – LS
NOTE:
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOH per port pin:10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total IOL for all output pins: 71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC specifica-
tion when the address lines are stabilizing.
5. The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
14
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 9. DC Characteristics at Operating Conditions (Continued)
Symbol
Parameter
Active ICC
Min
Typical (1)
Max
Units
Test Conditions
ICC (5)
60
PLLSEL = 110
3 MHz – FS
(in low clock mode)
150
PLLSEL = 110
12 MHz – FS
(not in low clock
mode)
mA
45
75
PLLSEL = 001
3 MHz – LS
PLLSEL = 100
6 MHz – LS
NOTE:
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOH per port pin:10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total IOL for all output pins: 71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC specifica-
tion when the address lines are stabilizing.
5. The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
5.3 Definition of AC Symbols
Table 10. AC Timing Symbol Definitions
Signals
Conditions
A
D
L
Address
Data In
ALE
H
L
High
Low
V
X
Z
Valid
Hold
Q
R
W
Data Out
RD#/PSEN#
WR#
Floating
ADVANCE INFORMATION
15
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4 AC Characteristics
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall times = 10 ns, FOSC = 6 MHz or 12 MHz
5.4.1 SYSTEM BUS AC CHARACTERISTICS
Table 11. AC Characteristics at Operating Conditions
CPUFrequency CPU Frequency (FCLK) Variable
Symbol
Parameter
@ 12 MHz
(M, N = 0)
Units
Min
Max
TCLK
1/(CPU Frequency)
83.33
(Typical)
ns
(1, 2)
TLHLL
ALE Pulse Width
34.66
(0.5+M)TCLK – 7
ns (3)
ns (3)
TAVLL
Address Valid to ALE Low
26.66
(0.5+M)TCLK
17
–
TLLAX
Address Hold after ALE Low
RD# or PSEN# Pulse Width
WR# Pulse Width
4
4
ns (4)
ns (6)
ns (6)
ns
TRLRH (5)
TWLWH
73.33
71.33
8
(1+N)TCLK – 10
(1+N)TCLK – 12
8
TLLRL (5)
TLHAX
ALE Low to RD# or PSEN# Low
ALE High to Address Hold
40.33
50.33
(1+M)TCLK – 43
ns (3)
TRLDV (5)
RD# or PSEN# Low to Valid
Data/Instruction In
(1+N)TCLK – 33 ns (6)
T
RHDX (5)
RLAZ (5)
Data/Instruct. Hold After RD# or
PSEN# High
0
0
0
ns
T
RD# or PSEN# Low to Address
Float
0
ns
TRHDZ1 (5) Instruct. Float After PSEN# High
10
10
ns
ns
TRHDZ2 (5) Data Float After RD# or PSEN#
High
83.33
TCLK
TRHLH1 (5) PSEN# High to ALE High
(Instruction)
10
10
ns
ns
ns
TRHLH2 (5) RD# or PSEN# High to ALE
High (Data)
83.33
TCLK
TWHLH
WR# High to ALE High
88.33
TCLK + 5
TAVDV1
Address (P0) Valid to Valid
Data/Instruction In
106.66
(2+M+N)TCLK
63
–
ns
(3, 6)
NOTES:
1. Refer to Table 8 on page 12 for CPU frequencies vs. XTAL1 frequencies.
2. XTAL1 frequency is ± 0.25% for full speed and ± 1.5% for low speed.
3. M= 0,1 is the extended ALE state.
4. At 50° C, TLLAX = 8 ns
5. Specifications for PSEN# are identical to those for RD#.
6. N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
16
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 11. AC Characteristics at Operating Conditions (Continued)
CPUFrequency CPU Frequency (FCLK) Variable
Symbol
Parameter
@ 12 MHz
(M, N = 0)
Units
Min
Max
TAVDV2
Address (P2) Valid to Valid
Data/Instruction In
118.66
(2+M+N)TCLK
ns
(3, 6)
– 48
TAVDV3
Address (P2) Valid to Valid
Instruction In
23.33
40.33
(1+N)TCLK – 60 ns (6)
ns (3)
TAVRL (5)
Address Valid to RD# or PSEN#
Low
(1+M)TCLK – 46
TAVWL1
TAVWL2
TWHQX
Address (P0) Valid to WR# Low
Address (P2) Valid to WR# Low
Data Hold after WR# High
Data Valid to WR# High
40.33
66.33
28.66
68.33
70.33
(1+M)TCLK – 46
(1+M)TCLK – 17
0.5 TCLK – 13
(1+N)TCLK –15
TCLK – 13
ns (3)
ns (3)
ns
TQVWH
ns (6)
ns
TWHAX
WR# High to Address Hold
NOTES:
1. Refer to Table 8 on page 12 for CPU frequencies vs. XTAL1 frequencies.
2. XTAL1 frequency is ± 0.25% for full speed and ± 1.5% for low speed.
3. M= 0,1 is the extended ALE state.
4. At 50° C, TLLAX = 8 ns
5. Specifications for PSEN# are identical to those for RD#.
6. N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
ADVANCE INFORMATION
17
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4.2 SYSTEM BUS TIMING DIAGRAMS, NONPAGE MODE
State 1
State 2
State 1
(next cycle)
ALE
TLHLL
TLLRL
TRHLH1
TRLRH
RD#/PSEN#
TAVLL
TRLDV
TRLAZ
TAVRL
TRHDX
TLLAX
TLHAX
TRHDZ1
P0
A7:0
Instruction In
TAVDV1
A17/A16/P2
A17/A16/A15:8
TAVDV2
A5011-01
Figure 6. 8x930Ax Code Fetch, Nonpage Mode
18
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
State 1
State 2
State 3
ALE
TLHLL
TLLRL
TRHLH2
TRLRH
RD#/PSEN#
TAVLL
TAVRL
TRLAZ
TRLDV
TRHDX
TRHDZ2
TLLAX
TLHAX
P0
A7:0
D7:0
TAVDV1
A17/A16/P2
A17/A16/A15:8
TAVDV2
A5025-02
Figure 7. 8x930Ax Data Read, Nonpage Mode
State 1
State 2
State 3
ALE
TLHLL
TWHLH
TWLWH
WR#
TAVLL
TAVWL1
TAVWL2
TLLAX
TWHQX
TLHAX
A7:0
TQVWH
P0
D7:0
TWHAX
A17/A16/P2
A17/A16/A15:8
A5026-02
Figure 8. 8x930Ax Data Write, Nonpage Mode
ADVANCE INFORMATION
19
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4.3 SYSTEM BUS TIMING DIAGRAMS, PAGE MODE
Cycle 1, Page Miss
State 2
Cycle 2, Page Hit
State 1
State 1
ALE
TLHLL
TRHLH1
TLLRL
TRLRH
†
RD#/PSEN#
TAVLL
TRLDV
TRLAZ
TAVRL
TRHDX
TLLAX
TLHAX
TRHDZ1
P2
A15:8
Instruction 1 In
TAVDV3
Instruction 2 In
TAVDV1
A17/A16/P0
A17/A16/A7:0
TAVDV2
†
During a sequence of page hits, PSEN# remains low until the end of the last page hit cycle.
A5028-02
Figure 9. 8x930Ax Code Fetch, Page Mode
20
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
State 1
State 2
State 3
ALE
TLHLL
TLLRL
TRHLH2
TRLRH
RD#/PSEN#
TAVLL
TAVRL
TRLAZ
TRLDV
TRHDX
TRHDZ2
TLLAX
TLHAX
P2
A15:8
D7:0
TAVDV1
A17/A16/P0
A17/A16/A7:0
TAVDV2
A5029-02
Figure 10. 8x930Ax Data Read, Page Mode
State 1
State 2
State 3
ALE
TLHLL
TWHLH
TWLWH
WR#
TAVLL
TAVWL1
TAVWL2
TLLAX
TWHQX
TLHAX
A15:8
TQVWH
P2
D7:0
TWHAX
A17/A16/P0
A17/A16/A7:0
A5030-02
Figure 11. 8x930Ax Data write, Page Mode
ADVANCE INFORMATION
21
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4.4 DEFINITION OF REAL-TIME WAIT SYMBOLS
Table 12. Real-time Wait Timing Symbol Definitions
Signals
Conditions
A
Address
Data
L
Low
D
C
Y
X
V
Hold
Setup
WCLK
WAIT#
WR#
W
R
RD#/PSEN#
5.4.5 REAL-TIME WAIT FUNCTION AC CHARACTERISTICS
Table 13. Real-time Wait AC Timing Specifications
(1) (2)
FCLK Variable
Typ
Symbol
Parameter
Units
Min
Max
TCLYV
Wait Clock Low to Wait Setup
Wait Hold after Wait Clock Low
PSEN# or RD# Low to Wait Setup
Wait Hold after PSEN# or RD# Low
WR# Low to Wait Setup
0
0.5 TCLK – 13
ns
ns
ns
ns
ns
ns
TCLYX
(W)TCLK + 5
0
(0.5+W)TCLK – 13
0.5 TCLK – 13
TRLYV
TRLYX
(W)TCLK + 5
0
(0.5+W)TCLK – 13
0.5 TCLK – 13
TWLYV
TWLYX
NOTES:
Wait Hold after WR# Low
(W)TCLK + 5
(0.5+W)TCLK – 13
1. W = 0, 1, 2, ... is the number of real-time wait states.
2. Real-time Wait function has a critical timing for instruction read. It is not advisable to use this feature
for instruction read during page mode.
22
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4.6 REAL-TIME WAIT FUNCTION TIMING DIAGRAMS
State 1
State 2
State 3
State 1 (next cycle)
WCLK
TCLYX min
TCLYX max
ALE
TCLYV
RD#/PSEN#
RD#/PSEN#
stretched
TRLYX max
TRLYX min
TRLYV
WAIT#
P0
A7:0
D7:0
stretched
stretched
A7:0
P2
A15:8
A15:8
A5000-02
Figure 12. External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State)
ADVANCE INFORMATION
23
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
State 1
State 2
State 3
State 4
WCLK
TCLYX min
ALE
TCLYX max
TCLYV
WR#
WR# stretched
TWLYX max
T
WLYX min
TWLYV
WAIT#
P0
D7:0
A7:0
stretched
stretched
P2
A15:8
A5002-02
Figure 13. External Data Write (Nonpage Mode, Real-time Wait State)
24
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
State 1
State 2
State 3
State 1 (next cycle)
WCLK
TCLYX min
TCLYX max
ALE
TCLYV
RD#/PSEN#
RD#/PSEN# stretched
TRLYX max
TRLYX min
TRLYV
WAIT#
P2
A15:8
D7:0
stretched
stretched
A15:8
P0
A7:0
A7:0
A5001-02
Figure 14. External Data Read (Page Mode, Real-time Wait State)
ADVANCE INFORMATION
25
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
State 1
State 2
State 3
State 4
WCLK
TCLYX min
ALE
TCLYX max
TCLYV
WR#
WR# stretched
TWLYX max
T
WLYX min
TWLYV
WAIT#
P2
A15:8
D7:0
stretched
stretched
P0
A7:0
A5003-02
Figure 15. External Data Write (Page Mode, Real-time Wait State)
26
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.5 AC Characteristics — Serial Port, Synchronous Mode 0
Table 14. Serial Port Timing — Synchronous Mode 0
Symbol
TXLXL
Parameter
Min
6 TOSC
Max
Units
ns
Serial Port Clock Cycle Time
TQVSH
TSHQX
TXHDX
Output Data Setup to Clock Rising Edge
Output Data hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
5 TOSC – 133
TOSC – 50
0
ns
ns
ns
TXHDV
5 TOSC – 133
ns
T
XLXL
TXD
T
XHQX
†
†
Set TI
T
QVXH
RXD
(Out)
0
1
2
7
4
6
3
5
T
T
XHDV
XHDX
Set RI
RXD
(In)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
†
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 16. Serial Port Waveform — Synchronous Mode 0
ADVANCE INFORMATION
27
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.6 External Clock Drive
Table 15. External Clock Drive
Symbol
1/TOSC
TCHCX
TCLCX
Parameter
Oscillator Frequency (FOSC
High Time
Min
6
Max
12
Units
MHz
ns
)
0.35 TOSC
0.35 TOSC
0.65 TOSC
0.65 TOSC
10
Low Time
ns
TCLCH
Rise Time
ns
TCHCL
Fall Time
10
ns
TCLCH
TCHCX
VCC – 0.5
0.45 V
0.7 VCC
0.2 VCC – 0.1
TCLCX
TCHCL
TCLCL
A4119-01
Figure 17. External Clock Drive Waveforms
28
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.7 Testing Waveforms
Outputs
Inputs
VCC – 0.5
0.45 V
0.2 VCC + 0.9
0.2 VCC – 0.1
VIH MIN
VOL MAX
AC inputs during testing are driven at VCC – 0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 18. AC Testing Input, Output Waveforms
VLOAD + 0.1 V
VLOAD
VOH – 0.1 V
Timing Reference
Points
V
OL + 0.1 V
VLOAD – 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH = ± 20 mA.
A4117-01
Figure 19. Float Waveforms
ADVANCE INFORMATION
29
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
6.0 THERMAL CHARACTERISTICS
7.3 Setting FFRC Bit Clears Only the
Oldest Packet in the FIFO
This microcontroller operates over the commercial
o
o
temperature range from 0 C to 70 C. All thermal
impedance data (Table 16) is approximate for static
air conditions at 1 watt of power dissipation. Values
change depending on operating conditions and
application requirements. The Intel Packaging
Handbook (order number 240800) describes Intel’s
thermal impedance test methodology. The
Components Quality and Reliability Handbook
(order number 210997) provides quality and
reliability information.
If the receive FIFO is set as a dual packet mode, it
can receive two packets. Setting FFRC to indicate
FIFO Read Complete will not flush the entire FIFO,
only the oldest packet will be flushed. The read
marker will be advanced to the location of the read
pointer.
7.4 Series Resistor Requirement for
Impedance Matching
Table 16. Thermal Characteristics
Per the USB 1.0 specification (page 111, section
7.1.1.1), the impedance of the differential driver
must be between 29 and 44 Ohms. To match the
cable impedance, a series resistor of 27 to 33 Ohms
should be connected to each USB line; i.e., on DP0
(pin 55) and on DM0 (pin 54). If the USB line is
improperly terminated or not matched, signal fidelity
will suffer. This can be seen on the scope as
excessive overshoot and undershoot. This will
potentially introduce bit errors.
Package Type
θ
θ
JC
JA
68-pin PLCC
N/A
N/A
7.0 PRODUCT REFERENCE
This section lists design considerations for the
8x930Ax Universal Serial Bus microcontroller.
7.1 External Bus Timing and
Peripheral Timing Affected by
PLLSEL2:0 Selection
7.5 Pullup Requirement for Full
Speed Device and Low Speed
Device
PLLSEL2 (pin43), PLLSEL1 (pin 42), and PLLSEL0
(pin 44) determine the 8x930Ax internal CPU
operating frequency. The selected CPU operating
frequency also influences all the peripherals. If the
PLLSEL2:0 pins of the 8x930Ax are set to 110, then
the internal clock frequency is 12MHz, and one
state time equals one clock time (please refer to
Table 8 on page 12). Therefore, all internal and
external instruction times for the timer, serial port,
PCA, are two times faster than with other
PLLSEL2:0 selections. Refer to the 8x930Ax,
8x930Hx Universal Serial Bus Microcontroller
User’s Manual for the new peripheral timing
formulas.
The pullup is a USB requirement to allow the host to
identify which devices are low speed and which are
full speed in order to communicate at the appro-
priate data rate. For Full Speed devices (12 Mbps)
use a 1.5K pullup resistor (to 3.0 V – 3.6 V) on the
DP0 line. For Low Speed devices (1.5Mbps), use a
1.5K pullup resistor (to 3.0 V – 3.6 V) on the DM0
line.
7.6 Powerdown Mode Cannot Be
Invoked Before USB Suspend
If the 8x930Ax is put into powerdown mode prior to
receiving a USB Suspend signal from the host, a
USB Resume will not properly wake up the
8x930Ax from powerdown mode.
7.2 Low Clock Mode Frequency
In low clock mode, the CPU and peripherals run at 3
MHz. All external bus accesses are affected,
including instruction fetch, data read/write, and
peripheral timing. Please refer to Table 8 on page
12 for the relationship of 3 MHz CPU and peripheral
timing (TCLK) to state times. One peripheral cycle is
6 state times.
30
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
8.0 SPECIFICATION SUPPLEMENT
8.2 DC Characteristics
FOR 8X930AX3 AND 8X930AX4
The VOH specification given in the DC Character-
istics section of this datasheet is changed to VOH
{min} VCC – 1.7 V when IOH = -60 µA for the A3
stepping onward.
=
All descriptions above apply to the 8x930Ax and
8x930Ax2 microcontrollers. The following specifica-
tions apply to recent steppings of the 8x930Ax
(8x930Ax3 and 8x930Ax4). This information is in
addition to (or in place of) the specifications
described above.
8.3 Extended Data Float (EDF) AC
Timing Feature
To provide a direct interface capability to slower
memory without the use of tristate drivers, an
extended data float (EDF) option has been added to
the 8x930Ax3 and 8x930Ax4. This option is
controlled by the EDF# bit (bit 3 in the UCONFIG1
configuration byte).
8.1 Six Endpoint Pairs Functionality
In the default state, the SIXEPPEN bit of
8x930Ax3’s and 8x930Ax4’s EPCONFIG SFR is
cleared and the 6 endpoint pair feature is disabled.
In this state, the endpoint pairs of the 8x930Ax3 and
8x930Ax4 are similar to those of the 8x930Ax and
8x930Ax2 devices.
If the EDF# bit is configured to 1, the 8x930Ax3 and
8x930Ax4 behave per the current specification
(some AC timings are different). This is known as
"Compatibility Mode". Table 19 on page 32 lists the
AC characteristics in this "Compatibility Mode" that
are different compared to the 8x930Ax and
8x930Ax2. Parameters not listed in the table remain
the same as for 8x930Ax and 8x930Ax2.
To enable the
6 endpoint pair feature, set
EPCONFIG’s SIXEPPEN bit. The 8x930Ax3 and
8x930Ax4 will then have the endpoint pairs shown
in Table 17.
Table 17. SIx Endpoint Pair Feature
Transmit Receive
If the 8x930Ax3 and 8x930Ax4 are configured with
EDF# = 0, the device will have extended data float
timings. This mode is known as the “Increased
TRHDZ1 Mode.” Table 20 on page 32 and Table 21
on page 33 show the parameters that are affected
when EDF#= 0.
EPINDEX
FFSZ1:0
FIFO
FIFO
(bytes)
(bytes)
0xxx x000
0xxx x001
0xxx x010
0xxx x011
0xxx x100
0xxx x101
xx
00
xx
xx
xx
xx
16
256
32
16
256
32
Configuring the device with EDF# = 0 does not
affect wait state A (all regions except 01:). Wait
state A can have 0, 1, 2, or 3 wait states. EDF#=0
affects external wait state B (region 01:). The
summary of the effect EDF# has on wait states is
listed in Table 18.
32
32
32
32
16
16
When the 6 endpoint pair feature is enabled, two
additional SFRs — the Function Interrupt Enable
Register 1 (FIE1) and the Function Interrupt Flag
Register 1 (FIFLG1) — are enabled to manage
interrupts for the additional endpoint pairs.
Table 18. Effect of “EDF#” on Wait States
Wait-state
EDF#
WSB#[1:0]
(for page 01)
1
1
1
1
1 1
1 0
0 1
00
0
1
2
3
See the 8x930Ax, 8x930Hx Universal Serial Bus
Microcontroller User’s Manual for additional infor-
mation.
0
0
0
0
11
10
01
00
1
1
3
3
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31
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 19. AC Characteristics for 8x930Ax3 and 8x930Ax4 in Compatibility Mode
8x930Ax3/8x930Ax4
Symbol
Parameter
Compatibility Mode (ns)
(EDF# =1) (1)
TAVLL
Address Valid to ALE Low
(0.5+M)TCLK - 13 [min]
10 [min]
TLLAX
Address Hold after ALE Low
TWLWH
TLLRL
WR# Pulse Width
(1+N)TCLK - 10 [min]
10 [min]
ALE Low to RD# or PSEN# low
ALE High to Address Hold
TLHAX
(1+M)TCLK - 27 [min]
(1+N)TCLK - 30 [max]
3 max (2)
TRLDV
RD# or PSEN# Low to Valid Data/Inst. In
RD# or PSEN# Low to Address Float
Data Float After PSEN# or RD# High
RD# or PSEN# High to ALE High (data)
WR# High to ALE High
TRLAZ
TRHDZ2
TRHLH2
TWHLH
TAVDV2
TAVRL
TCLK + 10 [max]
TCLK + 10 [min]
TCLK+10 [min]
Address (demux’ed) Valid to Valid Data/Instr. In
Address Valid to RD# or PSEN# Low
Address (mux’ed) Valid to WR# Low
(2+M+N)TCLK - 38 [max]
(1+M)TCLK - 40 [min]
(1+M)TCLK - 40 [min]
TAVWL1
NOTES:
1. Device configured with default data float timing for fast memory interface.
2. Typical value is 0 ns.
Table 20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings
Default Data Float
Timing (ns)
Compatibility Mode
(EDF# =1) (1,2,4,5)
Extended Data Float
Sym-
bol
Timing (ns)
Parameter
Increased TRHDZ1 mode
(EDF#=0) (1,3,4,5)
TLLAX
Address Hold after ALE Low
RD# or PSEN# Pulse Width
WR# Pulse Width
10 [min]
20 [min]
TRLRH
TWLWH
TLLRL
(1+N)TCLK - 10 [min]
(1+N)TCLK - 10 [min]
10 [min]
(1+N)TCLK - 32 [min]
(1+N)TCLK - 32 [min]
20 [min]
ALE Low to RD# or PSEN# low
ALE High to Address Hold
TLHAX
(1+M)TCLK - 27 [min]
(1+N)TCLK - 30 [max]
10 [max]
(0.5+M)TCLK + 15 [min]
(1+N)TCLK - 50 [max]
(0.5)TCLK - 5 [max]
TRLDV
RD# or PSEN# Low to Valid Data/Inst. In
Instruct. Float After PSEN# or RD# High
TRHDZ1
NOTES:
1. Worst-case numbers based on silicon data collected to date.
2. Device configured with default data float timing for fast memory interface.
3. Device configured with extended data float timing for slow memory interface.
4. The values listed are for 12 MHz. For 6 MHz, the value of TCLK will double and will equal 166.6 ns.
5. M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
32
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings (Continued)
Default Data Float
Timing (ns)
Compatibility Mode
(EDF# =1) (1,2,4,5)
Extended Data Float
Timing (ns)
Increased TRHDZ1 mode
(EDF#=0) (1,3,4,5)
Sym-
bol
Parameter
TRHDZ2
TRHLH2
TRHLH1
TWHLH
Data Float After PSEN# or RD# High
RD# or PSEN# High to ALE High (data)
PSEN# High to ALE High (inst.)
WR# High to ALE High
TCLK + 10 [max]
TCLK + 10 [min]
10 [min]
1.5 TCLK - 5 [max]
(1.5)TCLK - 7 [min]
(0.5)TCLK - 7 [min]
(1.5)TCLK - 7 [min]
TCLK + 10 [min]
TAVDV1
TAVRL
Address (mux’ed) Valid to Valid Data/Inst. In (2+M+N)TCLK - 60 [max] (1.5+M+N)TCLK - 28 [max]
Address Valid to RD# or PSEN# Low
Address (mux’ed) Valid to WR# Low
Address (demux’ed) Valid to WR# Low
(1+M)TCLK- 40 [min]
(1+M)TCLK- 40 [min]
(1+M)TCLK- 17 [min]
(0.5+M)TCLK + 10 [min]
(0.5+M)TCLK + 10 [min]
(1+M)TCLK + 10 [min]
TAVWL1
TAVWL2
NOTES:
1. Worst-case numbers based on silicon data collected to date.
2. Device configured with default data float timing for fast memory interface.
3. Device configured with extended data float timing for slow memory interface.
4. The values listed are for 12 MHz. For 6 MHz, the value of TCLK will double and will equal 166.6 ns.
5. M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
Table 21. 8x930Ax3 and 8x930Ax4 Real-time Wait State AC Timing Specifications
FCLK Variable
Default Data Float Timing (ns)
(EDF#=1)
FCLK Variable
Extended Data Float Timing (ns)
(EDF#=0)
Symbol (Parameter)
M i n
T y p
M a x
M i n
T y p
M a x
T RLYV (PSEN# or RD# Low to
Wait Setup)
0
0.5 TCLK - 13
0
0.5 TCLK - 35
TWLYV (WR# Low to Wait Setup)
0
0.5 TCLK - 13
0.5 TCLK - 35
ADVANCE INFORMATION
33
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
9.0 DEVICE ERRATA
The 8x930Ax may contain design defects or errors
known as errata. Characterized errata that may
cause the 8x930Ax’s behavior to deviate from
published specifications are documented in a speci-
fication update. Refer to the 8x930Ax (8x930AD,
8x930AE) Specification Update (Order Number
272940, Revision 007 or later). Specification
updates can be obtained from your local Intel sales
office or from the World Wide Web (www.intel.com).
10.0 DATASHEET REVISION HISTORY
This datasheet is valid for A-2 through A-4 step
devices. Datasheets are changed as new device
information becomes available. Verify with your
local Intel sales office that you have the latest
version before finalizing
devices.
a design or ordering
This (-003) revision of the 8x930Ax datasheet
replaces earlier product information. The following
changes were made in this version:
1. Added “Specification Supplement for
8x930Ax3 and 8x930Ax4” on page 31.
2. The following AC Characteristics were
changed: TAVLL, TAVDV1, TAVRL, TAVWL1.
3. ICC characteristics updated.
34
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