NG80960KB [INTEL]
RISC Microprocessor, 32-Bit, 25MHz, CMOS, PQFP132, PLASTIC, QFP-132;
| 型号： | NG80960KB |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 32-Bit, 25MHz, CMOS, PQFP132, PLASTIC, QFP-132 时钟 外围集成电路 |
| 文件： | 总102页 (文件大小：1363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® i960® RM/RN I/O Processor
Design Guide
April 2002
Order Number: 273139-004
Intel® i960® RM/RN I/O Processor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel® i960® RM/RN I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2002
*Other brands and names are the property of their respective owners.
Design Guide
Intel® i960® RM/RN I/O Processor
Contents
1.0
2.0
Introduction...................................................................................................................................9
Intel® 80960RM/RN Processor Ball Map......................................................................................9
2.1
Routing Guidelines .....................................................................................................................11
3.1 Trace Length Limits .......................................................................................................11
Intel® 80960RM/RN Processor Memory Subsystem ..................................................................12
4.1 ROM, SRAM, or Flash Guidelines.................................................................................12
Intel® 80960RM/RN Processor PBGA Signal Ball Map.................................................10
3.0
4.0
4.1.1 Layout Guidelines..........................................................................................................13
4.1.2 Wait State Profiles .........................................................................................................13
4.2
SDRAM Guidelines........................................................................................................14
4.2.1 Layout Guidelines..........................................................................................................15
4.2.2 SDRAM Clocking and Clock Buffer Specifications ........................................................20
4.2.3 SDRAM Power Failure Guidelines.................................................................................23
4.2.4 System Assumptions .....................................................................................................23
4.2.5 External Logic Required for Power Failure....................................................................23
5.0
6.0
Interrupt Routing.........................................................................................................................25
5.1
5.2
Intel® 80960RM/RN Processor Implementation on a MotherBoard...............................25
Intel® 80960RM/RN Processor Implementation on an Add-in Card ..............................26
Clocking Guidelines....................................................................................................................27
6.1
6.2
6.3
Layout Guidelines for Add-in Cards...............................................................................27
Layout Guidelines for Motherboards..............................................................................28
Clock Vendors ...............................................................................................................29
7.0
8.0
9.0
Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors...............................30
Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors...............................32
Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations.......................................34
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Providing 3.3 V in a 5 V System ....................................................................................34
Choosing a Power Source.............................................................................................36
PCI Adapter Card Power Source...................................................................................37
VCC5REF Pin Requirement (VDIFF).................................................................................37
VCCPLL Pins Requirement..............................................................................................38
Pullups and Pulldown Resistors ....................................................................................38
FAIL# .............................................................................................................................39
10.0
Processor Power Supply Decoupling .........................................................................................40
10.1
10.2
High Frequency Decoupling ..........................................................................................40
Bulk Decoupling Capacitance........................................................................................41
11.0
12.0
Intel® 80960RM/RN Processor Based Reference Design..........................................................42
Debug Connector Recommendations.........................................................................................43
12.1
12.2
PBGA Sockets and Headers .........................................................................................43
Logic Analyzer Connectivity...........................................................................................45
Design Guide
3
Intel® i960® RM/RN I/O Processor
12.3
JTAG Connector and Test Interface..............................................................................48
12.3.1 Intel® i960® RM/RN I/O Processor JTAG Emulator.....................................................48
12.3.2 Intel® i960® RM/RN I/O Processor Target Debug Interface Connector.......................48
12.3.3 Connecting The Emulator To The Target ......................................................................50
12.3.4 Other Tools....................................................................................................................51
13.0
14.0
Design for Manufacturability.......................................................................................................52
Thermal Solutions.......................................................................................................................53
14.1
14.2
14.3
14.4
14.5
Thermal Recommendations ..........................................................................................53
3-Dimensional View: Processor with Heat Sink Attached..............................................54
PCB Heatsink Hole Dimensions ....................................................................................55
Clearances of PCI Board and Components ..................................................................57
Heat Sink Information ....................................................................................................58
14.5.1 Socket Information.........................................................................................................58
14.5.2 Socket-Header Vendor ..................................................................................................58
14.5.3 Burn-in Socket Vendor ..................................................................................................58
14.5.4 Shipping Tray Vendor....................................................................................................59
14.5.5 Logic Analyzer Interposer Vendor .................................................................................59
14.5.6 JTAG Emulator Vendor .................................................................................................59
15.0
References .................................................................................................................................60
15.1
15.2
Related Documents.......................................................................................................60
Electronic Information....................................................................................................60
A
B
C
D
E
F
Intel® i960® RM I/O Processor Schematics..............................................................................61
Intel® IQ80960RM Board Bill of Material ....................................................................................72
Intel® i960® RN I/O Processor Schematics ..............................................................................76
Intel® IQ80960RN Board Bill of Material.....................................................................................88
Intel® IQ80960RM/RN SDRAM Battery Backup PLD Equations................................................92
Intel® 80960RM/RN Processor PBGA Signal Ball Map..............................................................93
4
Design Guide
Intel® i960® RM/RN I/O Processor
Figures
2-1
3-2
4-3
4-4
4-5
4-6
4-7
4-8
540L H-PBGA Diagram (Bottom View).......................................................................................10
Examples of Stubless and Short Stub Traces ............................................................................11
4 Mbyte Flash Memory System ..................................................................................................13
Dual-Bank SDRAM Memory Subsystem ....................................................................................15
SDRAM DIMM Layout Topology #1............................................................................................17
SDRAM DIMM Layout Topology #2............................................................................................17
Address and Control Topology for Two Discrete SDRAM Devices ............................................18
Address and Control Topology for Four or More Discrete SDRAM Devices ..............................18
Data and DQM Topology for Discrete SDRAM Devices.............................................................19
Clocking for a Dual-Bank SDRAM DIMM ...................................................................................20
Clock Routing for a Two Device SDRAM Subsystem.................................................................22
External Power Failure State Machine .......................................................................................23
External Power Failure Logic in the System...............................................................................24
Example Secondary PCI Connector Interrupt Routing ...............................................................26
PCI Add-in Card Example Configuration ....................................................................................27
Motherboard Example Configuration..........................................................................................28
Creating a Power “Island”...........................................................................................................35
Power Supply Circuit ..................................................................................................................36
Recommended Power Supply Connection Layout .....................................................................36
VCC5REF Current-Limiting Resistor.............................................................................................37
VCCPLL Low-Pass Filter ..............................................................................................................38
Recommended FAIL# Circuit......................................................................................................39
4-9
4-10
4-11
4-12
4-13
5-14
6-15
6-16
9-17
9-18
9-19
9-20
9-21
9-22
10-23 High-Frequency Capacitor Values and Layout...........................................................................41
12-24 540L PBGA Header....................................................................................................................43
12-25 540L PBGA Socket.....................................................................................................................44
12-26 Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View.............................................46
12-27 Packard-Hughes Direct Mount (Flex Tape) Interposer - Side View............................................46
12-28 Flex Tape Interposer Application (Add-In Card) .........................................................................47
12-29 Flex Tape Interposer (Top View) ................................................................................................47
12-30 Flex Tape Interposer (Side View) ...............................................................................................47
12-31 JTAG Emulator Connector (Top View) .......................................................................................48
14-32 Conceptual 3-D View of Processor with a Heat Sink..................................................................54
14-33 Hole Dimensions for Passive Heatsink.......................................................................................55
14-34 Board Level Keep Out Areas......................................................................................................56
14-35 Clearances of PCI Board and Components................................................................................57
15-36 Decoupling and 3.3 V Power Schematic ....................................................................................62
15-37 Primary PCI Interface Schematic................................................................................................63
15-38 Memory Controller Schematic ....................................................................................................64
15-39 Flash ROM, UART and LEDs Schematic ...................................................................................65
15-40 Logic Analyzer I/F Schematic .....................................................................................................66
15-41 SDRAM 168-Pin DIMM Schematic.............................................................................................67
15-42 Secondary PCI/80960 Core Schematic......................................................................................68
15-43 Secondary PCI Bus 1/2 Schematic.............................................................................................69
15-44 Secondary PCI Bus 3/4 Schematic.............................................................................................70
15-45 Battery Monitor Schematic..........................................................................................................71
15-46 Decoupling and 3.3 V Power Schematic ....................................................................................77
15-47 Primary PCI Interface Schematic................................................................................................78
15-48 Memory Controller Schematic ....................................................................................................79
15-49 Flash ROM, UART and LEDs Schematic ...................................................................................80
Design Guide
5
Intel® i960® RM/RN I/O Processor
15-50 Logic Analyzer I/F Schematic.....................................................................................................81
15-51 SDRAM 168-Pin DIMM Schematic.............................................................................................82
15-52 Secondary PCI/80960 Core Schematic......................................................................................83
15-53 Secondary PCI Bus 1/2 Schematic ............................................................................................84
15-54 Secondary PCI Bus 3/4 Schematic ............................................................................................85
15-55 SPCI Pull-Ups Schematic...........................................................................................................86
15-56 Battery/Monitor Schematic .........................................................................................................87
6
Design Guide
Intel® i960® RM/RN I/O Processor
Tables
4-1
4-2
4-3
4-4
4-5
4-6
5-7
6-8
Flash Interface Signals ...............................................................................................................12
ROM, SRAM, or Flash Wait State Profile Programming.............................................................13
SDRAM Interface Signals...........................................................................................................14
Drive Strength Programmability Options ....................................................................................16
DCLKIN Routing and Loading Requirements.............................................................................21
SDRAM Clock Buffer Information ...............................................................................................22
Intel® 80960RM/RN Processor Interrupt Routing Signals ..........................................................25
Low Skew Clock Buffer Information............................................................................................29
Memory Controller, Core and JTAG Signals ..............................................................................30
I2C Bus Signals...........................................................................................................................30
PCI Signals.................................................................................................................................30
Memory Controller, Core and JTAG Signals ..............................................................................32
I2C Bus Signals...........................................................................................................................32
PCI Signals.................................................................................................................................32
VDIFF Specification for Dual-Power Supply Requirements (3.3 V, 5 V)......................................37
7-9
7-10
7-11
8-12
8-13
8-14
9-15
12-16 Logic Analyzer Header Definitions (Mictor) ................................................................................45
12-17 i960® RM/RN I/O Processor Debug Connector Wiring...............................................................49
12-18 i960® RM/RN I/O Processor with PC-1149.1/100F (cable P/N AS01090025-Ax)......................50
12-19 i960® RM/RN I/O Processor with PCMCIA-1149.1 (cable P/N AS01090025-Bx) ......................51
14-20 H-PBGA Package Characteristics ..............................................................................................53
14-21 Heat Sink Vendors and Contacts................................................................................................58
14-22 Socket-Header Vendor ...............................................................................................................58
14-23 Burn-in Socket Vendor................................................................................................................58
14-24 Shipping Tray Vendor.................................................................................................................59
14-25 Logic Analyzer Interposer Vendor ..............................................................................................59
14-26 JTAG Emulator Vendor...............................................................................................................59
15-27 Related Documentation ..............................................................................................................60
15-28 Electronic Information.................................................................................................................60
B-1
D-1
F-1
F-2
Intel® IQ80960RM Bill of Materials.............................................................................................72
Intel® IQ80960RN Bill of Materials .............................................................................................88
540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor..................................93
540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor ..................................98
Design Guide
7
Intel® i960® RM/RN I/O Processor
Revision History
Rev
Date
Description of Changes
004
003
04/2002
08/2000
•
•
Changed “Thermal Recommendations” section.
Added schematics.
•
•
•
•
Updated Trademarks and Branding.
Updated vendor tables.
Minor text rewrites.
002
06/2000
Updated Pinout tables.
•
•
•
•
Added reference schematics.
Added debug connector recommendations section.
Added more detailed heat-sink drawings.
Updated heat-sink vendor table.
1.0
0.9
06/1998
12/10/97
Original Document
8
Design Guide
Intel® i960® RM/RN I/O Processor
Introduction
1.0
2.0
Introduction
This design guide addresses design considerations for designing with either the Intel® i960® RN
I/O processor or the Intel® i960® RM I/O processor. Where necessary and applicable, differences
in design constraints between the two processors is clarified.
The i960 RN I/O Processor is an Intel I/O processor supporting both 64-bit and 32-bit PCI
operation. The i960 RM I/O Processor is an Intel I/O processor only supporting 32-bit PCI
operation.
Intel® 80960RM/RN Processor Ball Map
Intel® i960® RM/RN I/O processor signals, by design, are located on the PBGA package to
simplify signal routing and system implementation. Figure 2-1 shows the RM/RN I/O processor
major signal sections. To simplify routing and minimize the number of cross traces, keep this
layout in mind when placing components in your system. Individual signals within the respective
groups have also been laid out to minimize signal crossings.
For detailed signal descriptions refer to the Tuzigoot Processor Target Specification document.
Contact your Intel sales representative to obtain a copy of the document.
Design Guide
9
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Ball Map
Figure 2-1. 540L H-PBGA Diagram (Bottom View)
Secondary PCI Bus Signals
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
W
V
U
U
T
T
R
R
P
P
N
N
M
M
L
L
K
K
J
J
H
H
G
G
F
F
E
E
D
D
C
C
B
B
A
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Memory Controller and Miscellaneous Signals
2.1
Intel® 80960RM/RN Processor PBGA Signal Ball
Map
Table F-1 and Table F-2 detail the ballout for the 80960RM and 80960RN processor, respectively.
See Appendix F.
10
Design Guide
Intel® i960® RM/RN I/O Processor
Routing Guidelines
3.0
Routing Guidelines
The order in which signals are routed first and last varies from designer to designer. Some prefer to
route all clock signals first, while others prefer to route all high speed bus signals first. Either order
can be used, provided the guidelines listed here are followed.
Route the RM/RN I/O processor address/data and control signals using a “daisy chain” topology.
This topology assumes that no stubs are used to connect any devices on the net. Figure 3-2 shows
two possible techniques to achieve a stubless trace. When it is not possible to apply one of these
two techniques due to congestion, a very short stub is allowed — preferably not to exceed
250 mils.
Figure 3-2. Examples of Stubless and Short Stub Traces
Stubless
Short Stub
<250 mils
3.1
Trace Length Limits
For add-in cards, trace lengths from the top of the card edge connector to the RM/RN I/O processor
are as follows:
• The maximum trace length for all 32-bit interface signals should not exceed 1.5 inches for
32-bit and 64-bit cards. This includes all signals except those listed as ‘Signal Pins’, ‘Interrupt
Pins’, and ‘JTAG Pins’ as per PCI Local Bus Specification, Revision 2.1.
• The trace length of the additional signals used in the 64-bit extension are limited to 2 inches on
all 64-bit cards.
• The trace length for the PCI CLK signal is 2.5 inches ± 0.1 inch for 32-bit and 64-bit cards and
should be routed to only a single load.
Design Guide
11
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
4.0
Intel® 80960RM/RN Processor Memory
Subsystem
The RM/RN I/O processor integrates a memory controller to provide a direct interface between the
RM/RN I/O processor and its local memory subsystem. The memory controller supports:
• Up to 16 Mbytes of 8-bit Flash, ROM, or SRAM
• Between 8 and 128 Mbytes of 64-bit synchronous DRAM (SDRAM)
• Between 4 and 64 Mbytes of 32-bit synchronous DRAM for low cost solutions
• Single-bit error correction, double-bit and nibble detection support (ECC)
The Flash interface provides an 8-bit data bus, 23-bit address bus, and control to support up to two
64 Mbit Bulk-Erase or Boot-Block Flash devices. The Flash devices provide storage for the
RM/RN I/O processor initialization code.
The memory controller provides a separate SDRAM interface from the Flash interface. The SDRAM
interface consists of a 66 MHz, 64-bit wide data path to support 528 Mbytes/sec throughput. An 8-bit
Error Correction Code (ECC) across each 64-bit word improves system reliability.
• The memory controller supports two banks of SDRAM in the form of a single two-bank dual
inline memory module (DIMM) or two single-bank DIMMs.
• The memory controller supports a 32-bit SDRAM data interface. This mode enables
lower-cost solutions at the cost of system bandwidth.
• The memory controller responds to internal bus memory accesses within its programmed
address range and issues the memory request to either the Flash or SDRAM interface.
The memory controller provides four chip enables to the memory subsystem. Two chip enables
service the SDRAM subsystem (one per bank) and two service the Flash devices.
Note: If the design does not follow the listed guidelines, then it is very important that the design be
simulated. Even if the guidelines are followed it is still recommended that the design be simulated
for proper signal integrity, flight time, and cross talk.
4.1
ROM, SRAM, or Flash Guidelines
The RM/RN I/O processor memory controller provides an interface to two banks of static memory
ranging from 64 Kbytes to 16 Mbytes. This memory may be SRAM, ROM, or Flash. Optionally,
one of the banks may be dedicated to a UART device. Table 4-1 defines all Flash interface signals.
Table 4-1.
Flash Interface Signals
Pin Name
Description
RCE[1:0]#
RWE#
Chip Enable - Asserted for all transactions to the Flash device.
Write Enable - Controls the Flash input data buffers.
Output Enable - Asserted for reads, deasserted for writes. Controls the Flash output data
buffers for write transactions.
ROE#
RAD[16:0]
RALE
Address/Data bus - Capable of supporting 16 Mbit of Flash (2Mx8). The data bus is
multiplexed on RAD[16:9].
Address Latch Enable - Indicates the transfer of a physical address. RALE is asserted
during a Flash address cycle and deasserted before the beginning of the data cycle.
12
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
4.1.1
Layout Guidelines
Figure 4-3 illustrates how two Flash devices would interface to the RM/RN I/O processor with the
memory controller. The Flash subsystem requires an external latch for address and data
demultiplexing on RAD[16:3]. The data is multiplexed on RAD[16:9].
Figure 4-3. 4 Mbyte Flash Memory System
A[2:0]
A[8:3]
RAD[2:0]
RAD[8:3]
A[22:17]
Latch
Latch
A[20:0]
OE#
A[16:9]
DQ[7:0]
RAD[16:9]
Intel 28F016-70
16 Mbit Flash
WE#
80960RM/RN
DQ[7:0]
CE#
RALE
RAD[16:0]
ROE#
RWE#
RCE0#
RCE1#
A[20:0]
OE#
Intel 28F016-70
16 Mbit Flash
WE#
DQ[7:0]
CE#
Flash signal loading should not exceed 50 pF. If the system conforms to I2O specification, then a
minimum 16 Mbit Flash such as Intel’s 28F016SA is suggested.
All traces between the RM/RN I/O processor and Flash/SRAM should not exceed 8 inches.
4.1.2
Wait State Profiles
Table 4-2 summarizes various wait state profiles of SRAM and writable non-volatile memory devices.
ROM, SRAM, or Flash Wait State Profile Programming
Table 4-2.
Device Speed
Address-to-Data Wait States
Recovery Wait States
≤ 55 ns
≤ 115 ns
≤ 175 ns
4
8
0
4
4
12
Design Guide
13
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
4.2
SDRAM Guidelines
The RM/RN I/O processor memory controller supports up to two banks of 66 MHz, 72-bit
SDRAM. The memory controller supports 16 Mbit or 64 Mbit technology offering up to 128
Mbytes of ECC protected memory. For low-cost solutions, the memory controller provides a 32-bit
SDRAM interface offering up to 64 Mbytes of memory.
Table 4-3 shows the SDRAM interface signals.
Table 4-3.
SDRAM Interface Signals
Pin Name
DCLKOUT
Description
SDRAM Clock Out - This is the clock to the off-chip SDRAM clock buffer driven by the
RM/RN I/O processor. Section 4.2.2 describes the SDRAM clocking strategy.
SDRAM Clock In - This is the clock returning from the off-chip SDRAM clock buffer.
Section 4.2.2 describes the SDRAM clocking strategy.
DCLKIN
Clock enables - One clock after SCKE[1:0] is deasserted, the data is latched on DQ[63:0]
and SCB[7:0]. The burst counters within the SDRAM device are not incremented.
Deasserting this signal places the SDRAM in self-refresh mode. For normal operation,
SCKE[1:0] must be asserted.
SCKE[1:0]
Data Mask - On a write, these signals disable the data on a byte-by-byte basis, thus
preventing certain bytes from being written. On a read, two clocks after asserting
SDQM[7:0] the output data bytes from the SDRAM device are disabled.
SDQM[7:0]
SCE[1:0]#
SWE#
Chip Select - Must be asserted for all transactions to the SDRAM device. One per bank.
Write Enable - Controls the SDRAM data input buffers. Asserting SWE# causes the data on
DQ[63:0] and SCB[7:0] to be written into the SDRAM devices.
SDRAM Bank Selects - Controls which of the internal SDRAM banks to read or write. For
16 Mbit devices (2 banks), only SBA[0] is used while 64 Mbit devices use SBA[1:0].
SBA[1:0]
SA[10]
Address bit 10 - If high during a read or write command, then auto-precharge occurs after
the command. During a row-activate command, this bit is part of the address.
Address bits 11 through 0 - Indicates the row or column to access depending on the state of
SRAS# and SCAS#.
SA[11:0]
SRAS#
SCAS#
Row Address Strobe - Indicates that the current address on SA[11:0] is the row.
Column Address Strobe - Indicates that the current address on SA[11:0] is the column.
Data Bus - 64-bit wide data bus.
DQ[63:0]
SCB[7:0]
ECC Bus - 8-bit error correction code which accompanies the data on DQ[63:0].
14
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
4.2.1
Layout Guidelines
The SDRAM subsystem may be implemented with:
• up to two banks directly connected on the printed circuit board (32, 64, or 72 bits wide)
• up to two 168-pin DIMM sockets (64-bit data bus with or without ECC)
• up to two 144-pin SO-DIMM sockets (64-bit data bus without ECC)
The memory controller supports either one dual-bank DIMM or two single-bank DIMMs. The
4-Clock 66 MHz 72-bit ECC Unbuffered SDRAM DIMM Specification requires four clock inputs.
Figure 4-4 illustrates how two banks of 16 Mbits SDRAM would interface with the RM/RN I/O
processor memory controller. SBA[1] is only connected for 64 Mbit SDRAM devices. For the
clock routing, refer to Figure 4-10.
Figure 4-4. Dual-Bank SDRAM Memory Subsystem
80960RM/RN
DQ[63:0]
CB[7:0]
RAS#
DQ[63:0]
SCB[7:0]
SRAS#
SCAS#
SWE#
CAS#
SDRAM DIMM
using 16 Mbit
devices
WE#
A[10:0]
BA0
SA[10:0]
SBA[0]
DQM[7:0]
CKE[1:0]
CS[3:0]#
SBA[1]
SDQM[7:0]
SCKE
SCE0#
SCE1#
DQ[63:0]
CB[7:0]
RAS#
SDRAM DIMM
using 16 Mbit
devices
CAS#
WE#
A[10:0]
BA0
DQM[7:0]
CKE[1:0]
CS[3:0]#
Design Guide
15
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
The drive strengths for the SDRAM signals are independently programmable using the SDCR
register. Table 4-4 lists some example SDRAM configurations and how the SDCR should be
programmed. The RM/RN I/O processor determines the SDRAM configuration with the Serial
Presence Detect EEROM (SPD) located on the DIMM. The I2C bus interfaces the RM/RN I/O
processor with the SPD.
Table 4-4.
Drive Strength Programmability Options
Memory
Size
(Mbytes)
Bus
Width
Form
Factor
SDCR[3] SDCR[4] SDCR[5] SDCR[6] SDCR[7]
1
Bank 0
Bank 1
(DQ)
(CKE0)
(CKE1)
(DQM) (SA[11:0])
2
4
8
2x1M16
4x2M8
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
32
2
0
On-board
2
8
4x1M16
8X2M8
4x1M16
0
2
None
16
8
0
2
1
0
Single-si
ded
DIMM
2
16
16
32
8x2M8
0
1
1
1
0
1
0
0
1
1
1
1
1
1
4x1M16 4x1M16
8x2M8 8x2M8
4x1M16 4x1M16
0
1
64
Double-si
ded
DIMM
16
32
24
32
16
1
1
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
2
4x1M16
8x2M8
8x2M8
8x2M8
4x1M16
8x2M8
Single-si
ded
DIMMs
2
On-board 9x2M8
1
Single-si
9x2M8
ded
0
None
2
16
32
32
0
1
1
1
1
1
0
0
1
1
1
1
1
DIMM
1
72
Double-si
9x2M8
ded
DIMM
9x2M8
9x2M8
1
1
2
Single-si
9x2M8
ded
DIMMs
NOTES:
1. The Memory Size column is based on 16 Mbit SDRAM technology. If 64 Mbit SDRAM is populated, then the
size will increase appropriately. Each bank’s technology may be programmed independently.
2. If one SDRAM bank is unpopulated, then the corresponding SCKE and SCE is unconnected.
Specific SDRAM signal topologies have been validated for 66 MHz operation. Figure 4-5 through
Figure 4-9 illustrate the proven topologies and are recommended. Proper signal integrity analysis
should verify any other signal topologies.
To minimize crosstalk, SDRAM signal routing should use a minimum of 4 mils spacing and 4 mils
trace width. SDRAM clocks (out of the buffer) should use a minimum of 12 mils spacing and
6 mils trace width.
16
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
Figure 4-5. SDRAM DIMM Layout Topology #1
DIMM
DIMM
1 to 8 inches
0 to 0.6 inches
Intel®
Address, Data and Control
80960RM/RN
I/O Processor
1 to 8 inches
SCE[0], SCKE[0]
1 to 8 inches
SCE[1], SCKE[1]
Trace Lengths apply for all SDRAM
signals except the clock
Figure 4-6. SDRAM DIMM Layout Topology #2
T ra c e s fro m th e p ro ce s so r
to D IM M 0 m u s t b e to
in c h e s
1
8
D IM M 0
In te l®
8 0 9 6 0 R M /R N
I/O P ro ce s so r
D IM M 1
T ra c e s fro m th e
p ro ce ss o r to D IM M 1
m u s t b e
1 to 8 in c h e s
T ra ce L e n g th s a p p ly fo r a ll S D R A M
sig n a ls e xc e p t th e clo ck
Design Guide
17
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
Figure 4-7. Address and Control Topology for Two Discrete SDRAM Devices
SDRAM0
Signals must be 3 to 9.5
inches from the processor and
each SDRAM device
Intel®
Address and Control
80960RM/RN
I/O Processor
SDRAM1
Applicable to all signals except
DQ[63:0], SCB[7:0], and SDQM[7:0].
Figure 4-8. Address and Control Topology for Four or More Discrete SDRAM Devices
S D R A M 0
0
to 0 .5 in c h
to 0 .5 in c h
to 0 .5 in c h
S D R A M 1
0
In te l®
8 0 9 6 0 R M /R N
I/O P ro c e s s o r
1
to
8
in c h e s
S D R A M 2
0
A p p lic a b le to a ll s ig n a ls e x c e p t
D Q [6 3 :0 ], S C B [7 :0 ], a n d S D Q M [7 :0 ].
18
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
Figure 4-9. Data and DQM Topology for Discrete SDRAM Devices
D a ta s ig n a ls m u s t b e
3 to 8
in c h e s fro m th e p ro c e s s o r a n d
e a c h S D R A M d e v ic e
S D R A M 0
1 0 o h m s + /- 5 %
S D Q [6 3 :0 ], S C B [7 :0 ]
S D Q M [7 :0 ]
In te l®
8 0 9 6 0 R M /R N
I/O P ro c e s s o r
S D Q M s ig n a ls m u s t b e
3 to
9 .5 in c h e s fro m th e p ro c e s s o r
a n d e a c h S D R A M d e v ic e
S D R A M 1
1 0 o h m s + /- 5 %
R e s is to rs m u s t b e w ith in 0 .5
in c h e s fro m th e S D R A M d e vic e
The address and control signals for the SDRAM subsystem include SA[11:0], SCAS#, SCE[1:0]#,
SCKE[1:0], SRAS#, and SWE#. The SDRAM data signals include DQ[63:0], and SCB[7:0].
Design Guide
19
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
4.2.2
SDRAM Clocking and Clock Buffer Specifications
The MCU provides one clock (DCLKOUT) to the SDRAM memory subsystem with a 66 MHz
frequency. The 72-bit, 2-bank SDRAM DIMM specification requires four clocks to distribute the
loading across eighteen x8 SDRAM components. The board designer must buffer DCLKOUT
external to the RM/RN I/O processor with a Texas Instruments CDC318 or equivalent buffer. Refer
to Figure 4-10 for the clock routing diagram. External resistors and capacitors are required for
proper signal integrity and clock skew management.
Figure 4-10. Clocking for a Dual-Bank SDRAM DIMM
Traces from the
processor to the
resistor must be within
0.5 inches.
Traces from the clock buffer
to the resistors must be
within 0.5 inches.
30 ohms +/- 5%
Clock0
Clock1
25 ohms
+/- 5%
35 ohms
+/- 5%
Intel®
80960RM/RN
I/O Processor
30 ohms +/- 5%
30 ohms +/- 5%
DCLKOUT
Clock
Buffer
Clock2
Clock3
30 ohms +/- 5%
30 ohms +/- 5%
DCLKIN
X pF
Traces from the processor
to the capacitor must be
within 0.5 inches.
Note: Any single SDRAM bank will use two clock buffer outputs. Four clock buffer outputs are used
only when two SDRAM banks are populated.
20
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
DCLKOUT and the clock buffer outputs may be between 1 and 8 inches. Each of the four clock
buffer outputs must be equal in length. Refer to Table 4-5 for the DCLKIN trace length and
capacitance requirements. DCLKIN requires an external capacitor to match the loading seen on
the other clock buffer outputs. Traces from the processor to the capacitor must be within 0.5
inches. The DCLKIN trace length must be equal to the clock buffer output trace length plus the
additional length specified in Table 4-5.
Table 4-5.
DCLKIN Routing and Loading Requirements
Memory Configuration
Additional DCLKIN Trace Length
DCLKIN Capacitance
168-pin SDRAM DIMM
144-pin SO-DIMM
4.5 +/- 0.1 inches
3.4 +/- 0.1 inches
1.3 +/- 0.1 inches
4.5 +/- 0.1 inches
4.5 +/- 0.1 inches
4.5 +/- 0.1 inches
18 pF
8.2 pF
3.3 pF
12 pF
12 pF
18 pF
Two discrete SDRAM devices
Four discrete SDRAM devices
Eight discrete SDRAM devices
Nine discrete SDRAM devices
Note: The 66 MHz Unbuffered 168-Pin SDRAM DIMM requires four clock inputs. The lumped
capacitance value required on DCLKIN is 18 pf in this reference design.
Design Guide
21
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
Any memory configuration using four or more discrete SDRAM components directly on the board
must adhere to the same routing requirements specified in the 4-Clock 66 MHz 72-bit ECC
Unbuffered SDRAM DIMM Specification. Figure 4-11 illustrates the routing requirements for the
SDRAM input clock when the configuration uses two SDRAM components.
Figure 4-11. Clock Routing for a Two Device SDRAM Subsystem
Traces from the
processor to the resistor
must be within 0.5 inches
SDRAM
1Mx16
Clock
Buffer
30 ohms +/- 5%
Clock
1 to 8 inches
0.4 inches
SDRAM
1Mx16
Suggested clock driver components are listed in Table 4-6. This is neither an endorsement nor a
warranty of the performance of the listed product and company.
Table 4-6.
SDRAM Clock Buffer Information
Manufacturer
Part Number
Cypress
Motorola
Pericom
Pericom
CY2310NZPVC-1
MPC9140SD
P16C182
P16C180V
22
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
4.2.3
SDRAM Power Failure Guidelines
SDRAM technology provides a simple way of enabling data preservation through the self-refresh
command. When the memory controller issues this command, the SDRAM refreshes itself
autonomously with internal logic and timers.
The SDRAM device remains in self-refresh mode as long as:
• The device continues to be powered.
• SCKE is held low until the memory controller is ready to control the SDRAM once again.
The board design should ensure power to the SDRAM subsystem with an adequate battery backup
and a reliable method for switching between system power and battery power. The memory
controller is responsible for deasserting SCKE[1:0] when issuing the self-refresh command
however, while power gradually drops, SCKE[1:0] MUST remain deasserted regardless of the state
of Vcc powering the RM/RN I/O processor.
4.2.4
4.2.5
System Assumptions
The board design should ensure that P_RST# is asserted to the RM/RN I/O processor when at least
1 ms of reliable power is remaining. This is required so that the memory controller can execute its
power-failure state machine in response to the assertion of P_RST#.
External Logic Required for Power Failure
Refer to Figure for a state machine of the external logic required for power failure mode. Actual
implementations may vary. This state machine can be implemented in a programmable logic device
illustrated in Figure 4-13.
Figure 4-12. External Power Failure State Machine
SCKEout
PULLCKE = 1
PULLCKE = 0
P_RST#
Design Guide
23
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Memory Subsystem
Figure 4-13. External Power Failure Logic in the System
Address, Data, and Control
Memory
Controller
SCKEout
SDRAM
Subsystem
SCKE[0]
External PLD
PULLCKE
P_RST#
The implementation illustrated in Figure 4-13 requires that all external logic be powered by Vbatt
.
The edge detect state machine activates the pull-down when the MCU deasserts SCKE[1:0]. As
long as Vbatt is active, SCKE[1:0] is held low. Once the memory controller is reset, the rising edge
of P_RST# deactivates the pull-down. The memory controller will reliably control SCKE[1:0] at
this point, driving it low. The pull-down is activated within the PLD device. Refer to the
IQ80960RM/RN schematics in Appendix E for details.
Note: Figure 4-13 shows logic for one of the SCKE signals. The loading of this signal is large enough so
that two signals are required (one per SDRAM bank) and the above logic should be replicated for
each SCKE[1:0].
24
Design Guide
Intel® i960® RM/RN I/O Processor
Interrupt Routing
5.0
Interrupt Routing
As stated in the PCI Local Bus Specification, Revision 2.1 and the PCI-to-PCI Bridge Architecture
Specification, Revision 1.0, interrupt routing is system-specific. In general, the BIOS maps the
device’s interrupt line to the RM/RN I/O processor’s secondary bus INTx line. The IDSEL address
originates from the RM/RN I/O processor’s secondary address bus and connects to the device’s
IDSEL pin or PCI connector slots.
Table 5-7 provides interrupt routing for devices with a single interrupt pin. Multifunction devices,
which have more than one interrupt pin, would follow the interrupt routing guidelines shown in
Figure 5-14. In this case, replace the connector with the multifunction device.
Table 5-7.
Intel® 80960RM/RN Processor Interrupt Routing Signals
Device’s IDSEL Signal Pin
Device Interrupt Signal
S_AD16, 20, 24, 28
S_AD17, 21, 25, 29
S_AD18, 22, 26, 30
S_AD19, 23, 27, 31
INTA#
INTB#
INTC#
INTD#
Secondary Address lines S_AD[25:16] can be configured for public devices or private devices
depending on the Secondary ID Select Register (SISR). S_AD[31:26] are for public devices only.
When PCI connectors are present on the RM/RN I/O processor’s secondary bus, the interrupts
rotate on the subsequent PCI connectors as shown in Figure 5-14.
5.1
Intel® 80960RM/RN Processor Implementation on a
MotherBoard
When implementing the RM/RN I/O processor onto a motherboard, you must adhere to the Device
ID address and interrupt routing scheme used on the primary side of the PCI bus which is
dependent on the individual motherboard implementation.
Design Guide
25
Intel® i960® RM/RN I/O Processor
Interrupt Routing
5.2
Intel® 80960RM/RN Processor Implementation on an
Add-in Card
When designing the RM/RN I/O processor into an add-in card, refer to Figure 5-14 for Device ID
address and interrupt routing.
Figure 5-14. Example Secondary PCI Connector Interrupt Routing
Intel® 80960RM/RN Processor
S_INTD:A#
S_AD31:0
Secondary
Secondary
Secondary
Secondary
PCI Connector 1
PCI Connector 2
PCI Connector 3
PCI Connector 4
S_INTA#
INTA#
S_INTB#
INTA#
S_INTC#
INTA#
S_INTD#
INTA#
S_INTB#
INTB#
S_INTC#
INTB#
S_INTD#
INTB#
S_INTA#
INTB#
S_INTC#
INTC#
S_INTD#
INTC#
S_INTA#
INTC#
S_INTB#
INTC#
S_INTD#
INTD#
S_INTA#
INTD#
S_INTB#
INTD#
S_INTC#
INTD#
S_AD16
IDSEL
S_AD17
IDSEL
S_AD18
IDSEL
S_AD19
IDSEL
NOTE:
Secondary PCI Bus interrupt signals “rotate” on subsequent PCI connectors.
26
Design Guide
Intel® i960® RM/RN I/O Processor
Clocking Guidelines
6.0
Clocking Guidelines
RM/RN I/O processor uses P_CLK (synchronous clock) input for clocking. All AC timings on the
primary PCI bus and the secondary PCI bus are referenced to the P_CLK input. The system must
provide clocks for any devices on the secondary PCI bus and ensure that system level goals for
clock skew and jitter are met.
6.1
Layout Guidelines for Add-in Cards
A PCI edge connector provides a singular PCI clock which must only be connected to one load on
the add-in card. Add-in cards which contain the RM/RN I/O processor should use a low skew, low
jitter clock driver/buffer to make multiple copies of the PCI clock for the RM/RN I/O processor
and any devices on the secondary PCI bus. See Figure 6-15. Such clock driver/buffer devices are
widely available (typically from Cypress, Motorola, National Semiconductor, etc.)
The PCI bus specification allows a maximum PCI clock skew of 2 ns between any two devices
connected on the PCI bus. To minimize skew on the primary PCI bus, place the clock driver device
as close as possible to the PCI edge connector. Trace lengths from the PCI edge connector to the
clock driver (“A” in Figure 6-15), and from the clock driver to the RM/RN I/O processor P_CLK
input (“B” in Figure 6-15) must be as short as physically possible (max length 2.5 inches).
For the secondary PCI bus, allowable skew is 2 ns between the RM/RN I/O processor P_CLK
input and any device on the secondary PCI bus. This allows the trace lengths from the clock driver
to the secondary PCI clock inputs (“C” and “D” in Figure 6-15) to be longer than the trace to the
RM/RN I/O processor P_CLK input to accommodate layout. In general, keep these secondary
clock routes shorter than eight inches to provide a skew of less than 2 ns.
Figure 6-15. PCI Add-in Card Example Configuration
80960RM/RN
P_CLK
PLL Clock
Generator
See notes 1,2
B
A
PCLK0
P_CLK
from Edge
Connector
PCLK1
PCLK2
C
D
Secondary
PCI Device
Secondary
PCI Device
NOTES:
1. Trace length between source component and resistor must be <1 inch.
2. All resistor values are 22 Ohms.
Design Guide
27
Intel® i960® RM/RN I/O Processor
Clocking Guidelines
6.2
Layout Guidelines for Motherboards
For motherboard implementations, the designer has much more flexibility with PCI clocking,
primarily related to controlling the central clock resources. Skew requirements for the motherboard
are more stringent due to the uncertainty of having PCI edge connectors on the secondary bus.
For motherboard implementation designs, it is best to choose a central clocking resource with enough
PCI clock outputs to drive all PCI devices in the system, including the RM/RN I/O processor and any
PCI devices on the secondary bus. All trace lengths should be equalized to both the primary and
secondary PCI devices. If it is not possible to find a central clock resource with enough clock outputs
for your design, then use a clock buffer/driver for the secondary PCI bus as shown in Figure 6-16.
To minimize skew for these designs, use the following equation for trace length (see Figure 6-16):
Equation 6-1. A = B + C + F = B + D + F - 2.5 Inches
The total trace length must be under 18 inches. Also, since implementations can be varied, each
design must be simulated to meet specifications as per PCI Local Bus Specification, Revision 2.1.
To minimize skew, clocks to connectors should be 2.5 inches shorter than traces routed to
motherboard devices.
Figure 6-16. Motherboard Example Configuration
Primary PCI Connector
See notes 1,2,3,4
A
PCI DEVICE
Central
Clock
Resource
2.5”
80960RM/RN
D
P_CLK
B
Secondary PCI Connector
PLL
Clock
Generator
PCLKO
C
D
PCLK1
PCLK3
PCLK2
PCI DEVICE
FB
2.5”
Secondary
PCI Device
NOTES:
1. Trace length between source component and resistor must be <1 inch.
2. All resistor values are 22 Ohms.
3. To minimize skew, trace length A = B + C = B + D - 2.5 inches.
4. F is the length of the feedback path in the clock generator.
28
Design Guide
Intel® i960® RM/RN I/O Processor
Clocking Guidelines
6.3
Clock Vendors
The low-skew clock buffer components in Table 6-8 are suggested. This is neither an endorsement
nor a warranty of the performance of the listed product and/or company.
Table 6-8.
Low Skew Clock Buffer Information
Manufacturer
Part Number
Cypress
Cypress
W217 (new)
CY7B9910
Design Guide
29
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors
7.0
Intel® 80960RM/RN Processor Signals
Requiring Pull-Up/Down Resistors
Table 7-9 through Table 7-11 identify the signals that require pull-up and/or pull-down resistors
and the recommended resistor values.
Table 7-9.
Memory Controller, Core and JTAG Signals
Resistor Value
(in Ohms)
Signal
Pull-up or Pull-down
Comments
Dependent on which reset
mode is desired. This signal has
an internal pull-up.
1
RAD[6]/RST_MODE#
1.5K
Pull-down
Pull-up to enable
RAD[4]/STEST, pull-down to
disable.
RAD[4]/STEST
RAD[3]/RETRY
2.7K
1.5K
1.5K
1.5K
Pull-up or Pull-down
Dependent on which reset
mode is desired. This signal has
an internal pull-up.
1
Pull-down
Pull-down for 32-bit SDRAM
protocol. This signal has an
internal pull-up.
2
RAD[2]/32BITMEM_EN#
RAD[1]/32BITPCI_EN#
Pull-down
Pull-down for 32-bit SPCI bus
protocol. This signal has an
internal pull-up.
3
Pull-down
NMI#
TRST#
2.7K
1.5K
Pull-up
Alternatively this signal may be
tied to P_RST#.
Pull-down
NOTES:
1. Pull-down only if other than default Reset Mode is required.
2. Pull-down only if the memory controller is required to support the 32-bit SDRAM protocol for access to
SDRAM memory.
3. Pull-down only if the secondary PCI bus is required to function as a 32-bit bus.
Table 7-10. I2C Bus Signals
Resistor value
(in Ohms)
Signal
Pull-up or Pull-down
Comments
2
SCL
SDA
2.7K
2.7K
pull-up
pull-up
When I C unit is not used
2
When I C unit is not used
Table 7-11. PCI Signals (Sheet 1 of 2)
Resistor value
(in Ohms)
Pull-up or
Pull-down
Signal
Comments
S_SERR#
S_TRDY#
S_LOCK#
S_PERR#
S_DEVSEL#
2.7K
2.7K
2.7K
2.7K
2.7K
pull-up
pull-up
pull-up
pull-up
pull-up
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
30
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors
Table 7-11. PCI Signals (Sheet 2 of 2)
Resistor value
(in Ohms)
Pull-up or
Pull-down
Signal
Comments
On Secondary Bus
S_ FRAME#
S_ STOP#
S_ IRDY#
S_ INTA#
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
S_ INTB#
S_ INTC#
S_ INTD#
XINT4#
XINT5#
S_ REQ0#
S_ REQ1#
S_ REQ2#
S_ REQ3#
S_ REQ4#
S_ REQ5#
S_AD[63:32]
S_C/BE[7:4]#
S_PAR64
S_REQ64#
S_ACK64#
Design Guide
31
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors
8.0
Intel® 80960RM/RN Processor Signals
Requiring Pull-Up/Down Resistors
Table 8-12 through Table 8-14 identify the signals that require pull-up and/or pull-down resistors
and the recommended resistor values.
Table 8-12. Memory Controller, Core and JTAG Signals
Resistor Value
(in Ohms)
Signal
Pull-up or Pull-down
Comments
Dependent on which reset
mode is desired. This signal has
an internal pull-up.
1
RAD[6]/RST_MODE#
1.5K
Pull-down
Pull-up to enable
RAD[4]/STEST, pull-down to
disable.
RAD[4]/STEST
RAD[3]/RETRY
2.7K
1.5K
1.5K
1.5K
Pull-up or Pull-down
Dependent on which reset
mode is desired. This signal has
an internal pull-up.
1
Pull-down
Pull-down for 32-bit SDRAM
protocol. This signal has an
internal pull-up.
2
RAD[2]/32BITMEM_EN#
RAD[1]/32BITPCI_EN#
Pull-down
Pull-down for 32-bit SPCI bus
protocol. This signal has an
internal pull-up.
3
Pull-down
NMI#
TRST#
2.7K
1.5K
Pull-up
Alternatively this signal may be
tied to P_RST#.
Pull-down
NOTES:
1. Pull-down only if other than default Reset Mode is required.
2. Pull-down only if the memory controller is required to support the 32-bit SDRAM protocol for access to
SDRAM memory.
3. Pull-down only if the secondary PCI bus is required to function as a 32-bit bus.
Table 8-13. I2C Bus Signals
Resistor value
(in Ohms)
Signal
Pull-up or Pull-down
Comments
2
SCL
SDA
2.7K
2.7K
pull-up
pull-up
When I C unit is not used
2
When I C unit is not used
Table 8-14. PCI Signals (Sheet 1 of 2) (Sheet 1 of 2)
Resistor value
(in Ohms)
Pull-up or
Pull-down
Signal
Comments
S_SERR#
S_TRDY#
S_LOCK#
S_PERR#
S_DEVSEL#
2.7K
2.7K
2.7K
2.7K
2.7K
pull-up
pull-up
pull-up
pull-up
pull-up
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
32
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors
Table 8-14. PCI Signals (Sheet 2 of 2) (Sheet 2 of 2)
Resistor value
(in Ohms)
Pull-up or
Pull-down
Signal
Comments
On Secondary Bus
S_ FRAME#
S_ STOP#
S_ IRDY#
S_ INTA#
S_ INTB#
S_ INTC#
S_ INTD#
XINT4#
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
2.7K
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
On Secondary Bus
XINT5#
S_ REQ0#
S_ REQ1#
S_ REQ2#
S_ REQ3#
S_ REQ4#
S_ REQ5#
Design Guide
33
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations
9.0
Intel® 80960RM/RN Processor 5 V and 3.3 V
Design Considerations
9.1
Providing 3.3 V in a 5 V System
In most system board designs, the 5 V system power supply is routed to board components through
a dedicated board layer. With the requirement of a 3.3 V supply for the RM/RN I/O processor, it is
not necessary to add a completely new power supply layer to the circuit board. It is possible to
create a 3.3 V “island” around the processor in the existing power supply plane.
Figure 9-17 shows a recommended “island” layout. The RM/RN I/O processor 5 V-tolerant input
buffers and TTL-compatible outputs allow the processor to interface with existing TTL-compatible
external logic, without requiring extra components. Thus, the processor runs at 3.3 V and the
system logic can run at 3.3 V or 5 V.
Other important considerations are:
• The “island” must be large enough to include the processor, the required power supply
decoupling capacitance, and the necessary connection to the 3.3 V source.
• To minimize signal degradation, the gap between the 3.3 V island and the 5 V plane should be
kept to a minimum: typical gap size is about 0.02 inches.
• Minimize the number of traces routed across the power plane gap, since each crossing
introduces signal degradation due to the impedance discontinuity that occurs at the gap. For
traces that must cross the gap, route them on the side of the board next to the ground plane to
reduce or eliminate the signal degradation caused by crossing the gap. If this is not possible,
then route the trace to cross the gap at a right angle (90 degrees).
• Use liberal decoupling capacitance between the 5 V plane and the 3.3 V island. Decoupling
the island reduces impedance discontinuity.
34
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations
Figure 9-17. Creating a Power “Island”
3.3V island
Gap in Plane
Connection Point for 3.3V Source
5V Plane
Design Guide
35
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations
9.2
Choosing a Power Source
The primary concern that must be addressed when selecting a power source is the maximum load
current requirement. The processor power supply must maintain correct voltage regulation at a
current of 5.0 A for the RM/RN I/O processor.
Two options for supplying 3.3 V to the processor are:
• Add a 3.3 V tap to the primary system power supply
• Use on-board secondary regulation to derive 3.3 V from the 5 V system power supply
For on-board secondary regulation, a linear voltage regulator performs adequately for most designs
as shown in Figure 9-18.
Figure 9-18. Power Supply Circuit
Intel®
80960RM/RN
I/O Processor
100 MHz / 3.3 V
+5V
V
V
IN
3.3V
Linear
Regulator
OUT
V
CC
10 µF
10 µF
If low heat or power dissipation is a design goal, then the higher complexity and cost of a switching
regulator may be warranted. Switching regulators offer better efficiency, thereby lowering
regulator power consumption and heat.
Figure 9-19 shows recommended layouts for power supply or linear regulator connection to the
3.3 V “island.”
Figure 9-19. Recommended Power Supply Connection Layout
3.3V Regulator (upright) and Heatsink
Use a wide trace to power supply connector
3.3V Supply Using System Power Supply
3.3V Supply Using Linear Regulator
36
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations
9.3
9.4
PCI Adapter Card Power Source
Currently, PCI Adapter card vendors cannot rely on the PCI connector to provide 3.3V. Hence, any
adapter card designed with the RM/RN I/O processor must design an on-board 3.3V regulator for
the processor power supply.
VCC5REF Pin Requirement (VDIFF
)
In mixed voltage systems that drive RM/RN I/O processor inputs in excess of 3.3V, the VCC5REF
pin must be connected to the system’s 5V supply. To limit current flow into the VCC5REF pin, there
is a limit to the voltage differential between the VCC5REF pin and the other VCC pins. The voltage
differential between the VCC5REF pin and its 3.3V VCC pins should never exceed 2.25V. Meeting
this requirement ensures proper operation and guarantees component reliability. This limit applies
to power-up, power-down, and steady-state operation. Table 9-15 outlines this requirement.
Table 9-15.
V
DIFF Specification for Dual-Power Supply Requirements (3.3 V, 5 V)
Sym
Parameter
Min
Max
Unit
Notes
V
input should not exceed V by more than
CC5REF
CC
V
-V
CC5 CC
V
2.25
V
2.25V during power-up and power-down, or during
steady-state operation.
DIFF
Difference
If the voltage difference requirements cannot be met due to system design limitations, an alternate
solution may be employed. As shown in Figure 9-20, a 100 ohm 0.5W series resistor may be used
to limit the current into the VCC5REF pin. This resistor ensures that current drawn by the VCC5REF
pin does not exceed the maximum rating for this pin.
Figure 9-20. VCC5REF Current-Limiting Resistor
+5V (±0.25V)
VCC5REF Pin
100 Ω
(±5%, 0.5 W)
This resistor is not necessary in systems that can guarantee the VDIFF specification. Also, in
3.3V-only systems and systems that drive pins from 3.3V logic, connect the VCC5REF pin directly
to the 3.3V VCC plane.
Design Guide
37
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations
9.5
VCCPLL Pins Requirement
To reduce clock skew on the processor, the VCCPLL pin for the Phase Lock Loop (PLL) circuit is
isolated on the pinout. The low-pass filter, shown in Figure 9-21, reduces noise induced clock jitter
and its effects on timing relationships in system designs. The trace lengths between the 4.7 µF
capacitor, the 0.01 µF capacitor, and VCCPLL must be as short as possible.
There are three VCCPLL pins on the RM/RN I/O processor: VCCPLL1, VCCPLL2 and VCCPLL3. Each
pin requires a low-pass filter. Providing just one low-pass filter and tying it to all three VCCPLL
inputs is not recommended.
Figure 9-21. VCCPLL Low-Pass Filter
10Ω, 5%, 1/8W
V
+
CCPLL
V
CC
(Processor input pin)
4.7µF
0.01µF
(Board Plane)
9.6
Pullups and Pulldown Resistors
RM/RN I/O processor inputs which require a pull-up should have the pullup resistor tied to the
appropriate supply voltage. In a 3.3V only design, the resistor should be tied to the 3.3V supply. In
a design where the RM/RN I/O processor interface to components operating at 5V, the resistors can
be tied to either the 3.3V power island or the 5V supply.
38
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations
9.7
FAIL#
Many applications use a light emitting diode (LED) to indicate when the FAIL# pin is low (active).
However, when an RM/RN I/O processor is in the design, and the FAIL# pin is high (inactive) at
3.3 V, the LED can still be forward biased enough to glow. To ensure the LED extinguishes when
FAIL# goes high, Intel recommends the circuit shown in Figure 9-22.
The two diodes dissipate about 1.4 V, so the LED voltage drops too low to glow when the FAIL#
pin goes high. Use a low current LED that can operate at 3-5 mA. This design works whether VCC
is 5 V or 3.3 V nominal.
An alternative is to eliminate the diodes and power the LED from the 3.3 V VCC supply of the
RM/RN I/O processor.
Figure 9-22. Recommended FAIL# Circuit
V
CC
1N4002, or Equivalent
~3.1 - 4.1V
390 Ω,
10%,
0.125 W
80960RM/RN
FAIL#
LED
Design Guide
39
Intel® i960® RM/RN I/O Processor
Processor Power Supply Decoupling
10.0 Processor Power Supply Decoupling
Processor power supply decoupling is critical for reliable operation. With the 3.3 V ready system,
two areas of concern are described in Section 10.1 and Section 10.2:
• High frequency decoupling, necessitated by the processor’s high speed operation
• Low frequency decoupling, necessitated by the processor’s power saving features
10.1
High Frequency Decoupling
Decoupling capacitors reduce voltage spikes by supplying extra current needed during switching.
Decoupling is especially critical on the RM/RN I/O processor because of its 100 MHz internal
operation.
A reliable design will include a minimum of thirty-two 0.1 µF surface mount ceramic chip
capacitors between power and ground, evenly distributed, around the processor. The capacitors
must be placed as close to the processor as possible, attached directly to the power and ground
planes, otherwise circuit board inductance will significantly reduce their effectiveness.
Figure 10-23 is an example of how to place high frequency capacitors on the back (solder) side of
the motherboard or add-in card. The BGA package in Figure 10-23 is shown for reference only;
normally it is not be visible from the back side. The outline around the BGA package is the 3.3 V
power island which is only needed on mixed voltage designs. When the design does not permit
components on the back side of the PCB, place the decoupling capacitors around the perimeter on
the component side of the PCB.
Inadequate high frequency decoupling results in unreliable or inconsistent program behavior.
These failures are often intermittent, and are difficult to diagnose and debug.
40
Design Guide
Intel® i960® RM/RN I/O Processor
Processor Power Supply Decoupling
Figure 10-23. High-Frequency Capacitor Values and Layout
Legend:
= 0.1 µF Capacitor
10.2
Bulk Decoupling Capacitance
Bulk, or low-frequency decoupling is needed on the RM/RN I/O processor. If the processor is on a
separate power plane “island”, it is necessary to place capacitance on the processor “island.” For
bulk decoupling, place two 47 mF surface mount capacitors in parallel, directly between the power
and ground planes. Place the capacitors close to the processor, within the power “island”. If other
3.3V components are on the PCB, then the two 47 mF capacitors may be omitted since the other
components would have bulk decoupling capacitors. However, the value and number of capacitors
required is dependent on the individual board design and layout characteristics.
Design Guide
41
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor Based Reference Design
11.0
Intel® 80960RM/RN Processor Based
Reference Design
See Appendix A through Appendix D for schematics and bill of material. OrCAD libraries for the
RM/RN I/O processor are available and can be supplied upon request.
42
Design Guide
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
12.0 Debug Connector Recommendations
This section describes debug hardware and connectors developed for the RM/RN I/O processor.
This includes sockets, headers, logic analyzer interposer, Mictor* signal cross reference lists and
JTAG emulator debug connector/pin assignments.
12.1
PBGA Sockets and Headers
Figure 12-24 and Figure 12-25 illustrate surface mount sockets and headers available for the
RM/RN I/O processor. See Table 14-22 for socket and header vendor information.
Figure 12-24. 540L PBGA Header
.062 inch
.05 Chamfer
.158 inch
.060 inch
1.67 inch
Side View
Top View
A5858-02
Design Guide
43
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
Figure 12-25. 540L PBGA Socket
.340 inch
.125 inch
.05 inch Chamfer
.812
inch
.667
inch
.312
inch
.062 inch
.193 inch
.050 inch
.062 inch
1.674 inch
Side View
Top View
A5857-02
44
Design Guide
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
12.2
Logic Analyzer Connectivity
The Mictor connector is the common connector used by the RM/RN I/O processor for logic
analysis connectivity. The Cyclone evaluation board developed for the 80960RM/RN integrates
five Mictor connectors to route the appropriate signals for logic analysis and probing. See
Table 12-16.
A removable interposer is also available for designs that may not have the available board space for
Mictor connectors. See Figure 12-26, Figure 12-27 and Figure 12-28. Refer to Table 14-25 for
logic analyzer interposer vendor information.
Table 12-16 is the signal cross-reference list for the RM/RN I/O processor and associated Mictor
connectors for the Cyclone board and the flex tape interposer. Pins1,2,37 and 38 are not used.
Table 12-16. Logic Analyzer Header Definitions (Mictor)
Cyclone J9
Cyclone J11
Cyclone J12
Cyclone J10
Cyclone J8
PIN
Interposer J2
N/C
Interposer J3
SDRAMCLK
SDQM7
SDQM6
SDQM5
SDQM4
SDQM3
SDQM2
SDQM1
SDQM0
SCB7
SCB6
SCB5
SCB4
SCB3
SCB2
SCB1
SCB0
SA0
Interposer J4
N/C
Interposer J5
N/C
Interposer J1
N/C
3
4
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
N/C
N/C
RAD15
RAD14
RAD13
RAD12
RAD11
RAD10
RAD9
RAD8
RAD7
RAD6
RAD5
RAD4
RAD3
RAD2
RAD1
RAD0
RAD16
N/C
5
N/C
6
N/C
7
N/C
8
N/C
9
N/C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
N/C
DQ8
N/C
DQ7
N/C
DQ6
N/C
DQ5
N/C
DQ4
N/C
DQ3
SCE0#
SCE1#
SBA1
DQ2
DQ1
DQ0
SBA0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
N/C
SREQ0#
SREQ1#
SREQ2#
SREQ3#
SREQ4#
SREQ5#
SGNT0#
SGNT1#
SGNT2#
SGNT3#
SGNT4#
SGNT5#
N/C
SA1
SA2
N/C
SA3
RALE
RCE0#
RCE1#
ROE#
RWE#
N/C
SA4
SA5
SA6
SA7
SA8
SA9
N/C
SA10
N/C
SA11
N/C
N/C
N/C
SWE#
SCAS#
SRAS#
N/C
N/C
N/C
N/C
N/C
N/C
N/C
P_PCICLK
RALE
Design Guide
45
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
Figure 12-26. Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View
Packard-Hughes Interconnect Direct Mount Interposer
4.59 inch
Mictor* Connectors
1
38
1.91
inch
J1
J2
J5
J4
J3
Flex Tape
* Other brands and names are the property of their respective owners.
Socket
Pin #1
A5880-01
Figure 12-27. Packard-Hughes Direct Mount (Flex Tape) Interposer - Side View
Packard-Hughes Interconnect Direct Mount Interposer
Mictor Connector
Socket
J1
J2
J5
J4
J3
~.25 inch
~.35 inch
Flex Tape
Header
A5881-01
46
Design Guide
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
Figure 12-28. Flex Tape Interposer Application (Add-In Card)
Flex Tape Interposer
Mictor
connector
312 mm
Top view of Flex Tape Interposer
Add-in Card
Pin #1
Side View
PCI Connector
Motherboard
A5882-01
Figure 12-29. Flex Tape Interposer (Top View)
Figure 12-30. Flex Tape Interposer (Side View)
Design Guide
47
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
12.3
JTAG Connector and Test Interface
®
®
12.3.1
Intel i960 RM/RN I/O Processor JTAG Emulator
The JTAG emulator for the i960® RM/RN I/O processor is designed to provide a convenient and
non-intrusive means of debugging. The JTAG emulator is connected to the processor by means of a
simple 16-pin connector. The hardware provided with the JTAG emulator can also be used (with
additional software) to test opens and shorts on the processor without the necessity for any
additional circuitry, other than a single 16-pin connector once it has been installed onto the PCB. A
JTAG emulator provides a designer the ability to download code, read data from registers,
single-step the processor, insert breakpoints (both hardware and software) and perform full source
level debugging without the need of an intrusive monitor program or a bulky hardware pod.
®
®
12.3.2
Intel i960 RM/RN I/O Processor Target Debug Interface
Connector
The i960 microprocessor target should have a 16-pin, two row header connector. Use 3M part
number 2516-6002UG or equivalent. The header is made from a keyed plastic shroud with two
rows of 8 pins and the spacing between adjacent pins and between the two rows is 0.100”. The
header pin assignment is illustrated in Figure 12-31.
Figure 12-31. JTAG Emulator Connector (Top View)
0.1”
1
2
0.1”
15
16
48
Design Guide
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
Figure 12-17 describes the interconnections required between the target debug interface connector
and the pins/balls of the i960 RM/RN I/O processor family.
Table 12-17. i960® RM/RN I/O Processor Debug Connector Wiring
®
i960 RM/RN I/O
Header Pin
Processor
Signal Name
Recommended Target Resistor
Ball/Direction
1
2
C11
A12
E11
B11
C12
A21
A11
TRST#
GND
1KΩ pull-down
3
TDI
1KΩ pull-up
4
GND
5
TDO
6
GND
7
TMS
1KΩ pull-up
1KΩ pull-up
1KΩ pull-up
8
GND
9
TCK
10
11
12
13
14
GND
LCDINIT#
GND
I_RST#
GND
Connected to V through 1KΩ series
CC
15
16
PWRVLD
GND
resistor
Design Guide
49
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
12.3.3
Connecting The Emulator To The Target
The emulation software uses the first Test Access Port (TAP) on the PC-1149.1/100F
boundary-scan controller card to control the i960 RM/RN I/O processor. A cable should be
connected from the boundary-scan controller to the i960 RM/RN I/O processor target debug
interface connector as shown in the following tables. A cable built to one of the following
specifications is supplied with the corresponding emulator.
Table 12-18. i960® RM/RN I/O Processor with PC-1149.1/100F (cable P/N AS01090025-Ax)
PC-1149.1/100F Signal
Name
Target Debug Header
PC-1149.1/100F Pin
Target Signal Name
Pin
TRST#
GND
1
2
TRST#
GND
TDI
1
2
TDO12
GND
3
3
4
GND
TDO
GND
TMS
GND
TCK
4
TDI12
5
5
GND
6
6
TMS1
7
7
GND
8
8
TCK12 (see note)
GND
9
9
10
GND
10
LCDINIT#/
RSTIN#
TMS3
GND
25
12
13
11
12
13
GND
I_RST/
SENSE#
RSTOUT#
GND
T_OFF# (see note)
GND
14
11
16
GND
PWRVLD
GND
14
15
16
NOTE: Connected to target through 33Ω series resistor.
50
Design Guide
Intel® i960® RM/RN I/O Processor
Debug Connector Recommendations
Table 12-19. i960® RM/RN I/O Processor with PCMCIA-1149.1 (cable P/N AS01090025-Bx)
Target Debug Header
PCMCIA-1149.1 Signal Name
PCMCIA-1149.1 Pin
Target Signal Name
Pin
TRST#
GND
8
9
TRST#
GND
TDI
1
2
TDO1
7
3
GND
5
GND
TDO
GND
TMS
GND
TCK
4
TDI1
6
5
GND
3
6
TMS1
4
7
GND
1
8
TCK1 (see note)
GND
2
9
11
GND
10
LCDINIT#/
RSTIN#
PIO_0
GND
17
13
18
11
12
13
GND
I_RST/
PIO_1
RSTOUT#
GND
25
19
GND
PWRVLD
GND
14
15
16
PIO_2 (see note)
-
No Connection
NOTE: Connected to target through 33Ω series resistor.
12.3.4
Other Tools
Other tools are available that are designed to complement the i960 family of JTAG emulators.
These include a full complement of boundary-scan hardware and software for testing the
80960RM/RN for opens, shorts, and other manufacturing defects once it has been installed onto the
target board. In addition, Corelis has available a preprocessor (PI-PCI32/64) for use with the HP
family of logic analyzers that allows a designer to examine the full complement of signals on the
PCI bus including all the boundary-scan signals. Since 80960RM/RN designs typically incorporate
PCI connectivity, this tool has been proven particularly effective in troubleshooting designs
utilizing the 80960RM/RN.
Design Guide
51
Intel® i960® RM/RN I/O Processor
Design for Manufacturability
13.0 Design for Manufacturability
The RM/RN I/O processor is offered in a high-thermal BGA (H-PBGA) package. PBGA
packaging is explained extensively in the Intel® Packaging Databook (Order Number 240800).
52
Design Guide
Intel® i960® RM/RN I/O Processor
Thermal Solutions
14.0 Thermal Solutions
In general, three factors affect the thermal performance of the BGA: package and board materials,
package geometry and use environment. The H-PBGA package utilizes a heat spreader or slug
across the top of the package to dissipate heat efficiently.
Environmental conditions play a critical role in the thermal performance of PBGAs. Ambient
conditions, junction and case temperatures, the device’s placement and orientation on a board, in
conjunction with the volume and temperature of air flowing past the unit present a broad range of
possible thermal solutions. The profiles of the H-PBGA package are characterized in Table 14-20.
Table 14-20. H-PBGA Package Characteristics
Description
Criteria
Die Junction temperature
110° C
a
Case Temperature (maximum)
Ambient temperature
90° C
up to 55° C
Airflow (on motherboard) from system fan
Airflow (on add-in card)
up to 50 LFM (worst case)
0 LFM (worst case)
Clip = 45 mm x 45 mm < 11 mm (thickness)
Passive heatsink dimensions
Acceptable flange adds 5 mm per side on hole direction of
fan
Flange type =55 mm x 45 mm <11 mm
(thickness) with pins.
Maximum heatsink thickness
Clip Hole Pattern
<11 mm
4 holes (3.175 mm diameter), 48.4632 x 34.798
mm rectangular (see Figure 14-33 and
Figure 14-34)
From center of heatsink to 1/2 inch in x and y
directions, 2 mils maximum
Heatsink Flatness
a.
Case temperature is dependent on the ambient temperature and airflow surrounding the processor. Refer to the application
note “Thermal Data for the 540-Lead PBGA Package” for more information.
14.1
Thermal Recommendations
Refer to the thermal sections of the Intel® 80960 RM I/O Processor Datasheet (273156), the Intel®
80960 RN I/O Processor Datasheet (273157), and the Intel® 80960 RS I/O Processor Datasheet
(273328) and to the thermal section of the Thermal Data for the 540-Lead PBGA Package
Application Note (273390).
Design Guide
53
Intel® i960® RM/RN I/O Processor
Thermal Solutions
14.2
3-Dimensional View: Processor with Heat Sink
Attached
To assist the board designer in component placement, hole placement and dimensions,
Figure 14-33 and Figure 14-34 detail specifics. Figure 14-33 details dimensions for board designs
requiring a Passive Heat Sink.
Figure 14-32. Conceptual 3-D View of Processor with a Heat Sink
Push Pins
Heatsink
Heatsink Flange
Heat Slug
BGA Package
Customer’s Board
54
Design Guide
Intel® i960® RM/RN I/O Processor
Thermal Solutions
14.3
PCB Heatsink Hole Dimensions
Figure 14-33. Hole Dimensions for Passive Heatsink
2.98 mm REF
4 Holes of diameter 3.175 ± 0.0508 mm
48.4632 mm
25.4 mm
Outline of
Passive
Heat Sink
Heat Slug of
80960RM/RN
(over component)
45 mm
25.4
mm
34.798 mm
Package:
42.5 mm x 42.5 mm
5.10 mm
55 mm
Top View
Clips
Flange uses pins
Heat Slug
Board
Side View
Pin
Spring
Heat Sink
Thermal Interface Material
Board
Heat Slug
Balls
NOTES:
The sides of the H-PBGA package are electrically
conductive; traces run out to the edge of the package.
Therefore, no materials are allowed to contact the sides
of this package at any time, including during shock and vibration testing.
Heatsink actual dimensions vary depending on vendor (see Table 21).
A5860-03
Design Guide
55
Intel® i960® RM/RN I/O Processor
Thermal Solutions
Figure 14-34. Board Level Keep Out Areas
Trace Keep-Out Areas
Heat Sink
Area
Pin Keep-Out Area = 3.81 mm
(Top and Bottom View)
Clip Keep-Out Area = 9.2 mm
(Bottom View)
Mounting hole diameter 3.175 ± 0.0508 mm
Periphery Components Keep-Out Area
[Top View]
55 mm
45 mm
Trace and
Component
Keep Out Area
= 3.81 mm
Component Keep Out Area - except when component height is less
than the height of the top of the package
Package
A5878-02
56
Design Guide
Intel® i960® RM/RN I/O Processor
Thermal Solutions
14.4
Clearances of PCI Board and Components
Figure 14-35. Clearances of PCI Board and Components
Add-in card #1
Heat sink mounted on the package
Maximum
allowable
Add-in card #2
component
dimension on
the backside
(as per PCI
Local Bus
Specification
Rev 2.1)
312 mm
Heat sink mounted
on the processor
Add-in Card
106.68 mm
height
15.49 mm
6.35 mm
1.57 mm
2.67 mm
PCI Connector
Motherboard
14.48 mm
18.72 mm = total
overall dimension
Side View
Note:
The two PCI add-in cards are
assumed to be in two adjacent slots.
A5853-03
Design Guide
57
Intel® i960® RM/RN I/O Processor
Thermal Solutions
14.5
Heat Sink Information
Table 14-21 provides a list of suggested sources for heat sinks. This is neither an endorsement nor a
warranty of the performance of any of the listed products and/or companies.
Table 14-21. Heat Sink Vendors and Contacts
Heatsink
Part #
Company
Factory Rep
Phone #
Fax #
Passive
21933B w/o
thermal grease
(uses pins)
AAVID THERMALLOY, LLC
2021 W. Valley View Lane
Dallas Texas 75234-8993
(972)
243-4321
(972)
241-4656
Email:sales@thermalloyusa.com
Attn: Sales
21935B with
Easy Ply
(thermal
Outside of USA, refer to web page for contact
information:
http://www.thermalloy.com
grease (uses
pins)
14.5.1
14.5.2
Socket Information
Table 14-22 and Table 14-23 provide vendor details for socket-headers and burn-in sockets for the
RM/RN I/O processor. This is neither an endorsement nor a warranty of the performance of any of
the listed products and/or companies.
Socket-Header Vendor
Table 14-22. Socket-Header Vendor
Part #
Factory
Represen-
tative
Company
Phone/Fax #
BGA 540 Pin
Header
BGA 540 Pin
Socket Carrier
Adapter Technologies, Inc.
214-218 South 4th St.
Perkasie, PA 18944
215-258-5750/ BGAH-540-0-01-320 BGA-540-0-02-3201
John Miller
215-258-5760
1-0277-1
-0275P-130
14.5.3
Burn-in Socket Vendor
Table 14-23. Burn-in Socket Vendor
Factory
Representative
Burn-in Socket
Part #
Company
Phone #
Texas Instruments
111 Forbes Blvd.
W. Ray Johnson
508-236-5375
ULGA540-005
Mansfield, MA 02048
58
Design Guide
Intel® i960® RM/RN I/O Processor
Thermal Solutions
14.5.4
Shipping Tray Vendor
Table 14-24. Shipping Tray Vendor
Company
Factory Rep
Phone #
602-465-5381
Shipping Tray Part #
3M
Ron Goth
7-0000-21001-184-167
14.5.5
Logic Analyzer Interposer Vendor
Table 14-25. Logic Analyzer Interposer Vendor
Company
Factory Rep
Phone/Fax #
Part #
Packard-Hughes Interconnect
17150 Von Karman Ave
Irvine, CA 92614-0968
714-660-5766
714-660-5825
Sue Wood
1126898
14.5.6
JTAG Emulator Vendor
Table 14-26. JTAG Emulator Vendor
Company
Factory Rep
Phone/Fax #
Part #
562-926-6727
562-484-6196
Corelis
Mike Winters
TBD
Design Guide
59
Intel® i960® RM/RN I/O Processor
References
15.0 References
15.1
Related Documents
Intel documentation is available from your local Intel Sales Representative or Intel Literature
Sales.
To obtain Intel literature:
call 1-800-548-4725 or
visit Intel’s website at http://www.intel.com
Table 15-27. Related Documentation
Document Title
Intel Order #
Intel Packaging Databook
240800
PCI Special Interest Group
1-800-433-5177
PCI Local Bus Specification Revision 2.2
http://developer.intel.com/
technology/memory/unb_001.pdf
PC SDRAM Unbuffered DIMM Specification v1.0
PCI Special Interest Group
1-800-433-5177
PCI-to-PCI Bridge Architecture Specification Revision 1.1
15.2
Electronic Information
Table 15-28. Electronic Information
Intel’s World-Wide Web (WWW) Location:
Customer Support (US and Canada):
http://www.intel.com
800-628-8686
60
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Intel® i960® RM I/O Processor
Schematics
A
Schematics in this document supersede schematics in Document #AZ1-00886.
Design Guide
61
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-36. Decoupling and 3.3 V Power Schematic
2 2 0 u F
C A P T 7 3 4 3
2
2
1
C 7 8
2 2 0 u F
C A P T 7 3 4 3
1
C 7 5
1
C O I L - S M T 2
3 . 3 u H
L 2
C 8 6
1
C A P 0 8 0 5
0 . 1 u F
2
1
2
R 5 4
1
2
% 5
1 / 8 W
1 0
62
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-37. Primary PCI Interface Schematic
R 3 9
1
2
% 5
1 / 1 0 W
1 0 K
R 5 8
1
2
% 5
1 / 1 0 W
1 0 K
C 8 9
1
2
2
C A P T 7 3 4 3
4 7 u F
C 9 4
1
C A P 0 8 0 5
0 . 1 u F
C 9 5
1
2
C A P 0 8 0 5
0 . 1 u F
C 1 0 4
P _ A D 0
U 1
P A D 0
P _ A D 1
2
1
U 2
P A D 1
C A P 0 8 0 5
0 . 1 u F
C 1 0 2
P _ A D 2
U 3
P A D 2
P _ A D 3
T 1
P A D 3
P _ A D 4
T 3
P A D 4
2
2
2
2
2
1
P _ A D 5
C A P 0 8 0 5
0 . 1 u F
C 1 0 1
T 4
P _ A D 6
T 5
P A D 5
P A D 6
P _ A D 7
R 1
P A D 7
1
P _ A D 8
R 3
P A D 8
C A P 0 8 0 5
0 . 1 u F
C 1 0 0
P _ A D 9
R 5
P A D 9
P _ A D 1 0
P 1
P A D 1 0
P A D 1 1
P A D 1 2
P A D 1 3
P A D 1 4
P A D 1 5
P A D 1 6
P A D 1 7
P A D 1 8
P A D 1 9
P A D 2 0
P A D 2 1
P A D 2 2
P A D 2 3
P A D 2 4
P A D 2 5
P A D 2 6
P A D 2 7
P A D 2 8
P A D 2 9
P A D 3 0
P A D 3 1
P _ A D 1 1
1
P 3
C A P 0 8 0 5
P _ A D 1 2
P 4
0 . 1 u F
C 9 8
P _ A D 1 3
P 5
P _ A D 1 4
N 1
1
P _ A D 1 5
C A P 0 8 0 5
N 2
0 . 1 u F
C 9 7
P _ A D 1 6
K 3
P _ A D 1 7
K 4
1
P _ A D 1 8
K 5
C A P 0 8 0 5
P _ A D 1 9
0 . 1 u F
J 1
P _ A D 2 0
J 2
P _ A D 2 1
J 3
P _ A D 2 2
J 5
P _ A D 2 3
H 1
P _ A D 2 4
H 5
P _ A D 2 5
G 1
P _ A D 2 6
G 2
P _ A D 2 7
G 3
P _ A D 2 8
E 5
P _ A D 2 9
A 6
P _ A D 3 0
C 6
P _ A D 3 1
D 6
Design Guide
63
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-38. Memory Controller Schematic
R 5 7
1
2
% 5
1 / 1 0 W
2 . 7 K
R 4 1
1
2
% 5
1 / 1 0 W
1 . 5 K
R 4 2
1
2
% 5
1 / 1 0 W
1 . 5 K
1
D Q 3 2
D Q 3 3
D Q 3 4
D Q 3 5
D Q 3 6
D Q 3 7
D Q 3 8
D Q 3 9
D Q 4 0
D Q 4 1
D Q 4 2
D Q 4 3
D Q 4 4
D Q 4 5
D Q 4 6
D Q 4 7
D Q 4 8
D Q 4 9
D Q 5 0
D Q 5 1
D Q 5 2
D Q 5 3
D Q 5 4
D Q 5 5
D Q 5 6
D Q 5 7
D Q 5 8
D Q 5 9
D Q 6 0
D Q 6 1
D Q 6 2
D Q 6 3
D Q 0
D Q 1
D Q 3 2
D Q 3 3
D Q 3 4
D Q 3 5
D Q 3 6
D Q 3 7
D Q 3 8
D Q 3 9
D Q 4 0
D Q 4 1
D Q 4 2
D Q 4 3
D Q 4 4
D Q 4 5
D Q 4 6
D Q 4 7
D Q 4 8
D Q 4 9
D Q 5 0
D Q 5 1
D Q 5 2
D Q 5 3
D Q 5 4
D Q 5 5
D Q 5 6
D Q 5 7
D Q 5 8
D Q 5 9
D Q 6 0
D Q 6 1
D Q 6 2
D Q 6 3
E 2 2
D 2 2
A 2 3
D Q 0
D Q 1
B 2 3
D Q 2
E 2 3
C 2 3
D Q 2
D Q 3
C 2 4
A 2 4
D Q 3
D Q 4
E 2 4
D 2 4
D Q 4
D Q 5
B 2 5
A 2 5
D Q 5
D Q 6
E 2 5
C 2 5
D Q 6
D Q 7
C 2 6
A 2 6
D Q 7
D Q 8
E 2 6
A 2 7
D Q 8
D Q 9
C 2 7
B 2 7
D Q 9
D Q 1 0
A 2 8
E 2 7
D Q 1 0
D Q 1 1
D Q 1 2
D Q 1 3
D Q 1 4
D Q 1 5
D Q 1 6
D Q 1 7
D Q 1 8
A A 3 2 D Q 1 9
D Q 1 1
C 2 8
G 3 2
H 3 1
D Q 1 2
H 3 2
D Q 1 3
H 2 8
H 3 0
D Q 1 4
J 3 0
J 3 2
D Q 1 5
J 2 8
J 2 9
D Q 1 6
W 2 8
Y 3 1
W 2 9
D Q 1 7
Y 3 2
D Q 1 8
Y 3 0
Y 2 8
D Q 1 9
D Q 2 0
D Q 2 1
D Q 2 2
D Q 2 3
D Q 2 4
D Q 2 5
D Q 2 6
D Q 2 7
D Q 2 8
D Q 2 9
D Q 3 0
D Q 3 1
A A 3 0
A A 2 8
A B 3 1
A B 2 8
A C 3 0
A C 2 8
A D 3 1
A D 2 8
A E 3 0
A E 2 8
A F 3 1
A F 2 8
A H 3 2
A A 2 9
A B 3 2
A B 3 0
A C 3 2
D Q 2 0
D Q 2 1
D Q 2 2
D Q 2 3
A C 2 9 D Q 2 4
A D 3 2
A D 3 0
A E 3 2
A E 2 9
A F 3 2
A F 3 0
A G 3 2
D Q 2 5
D Q 2 6
D Q 2 7
D Q 2 8
D Q 2 9
D Q 3 0
D Q 3 1
C 1 1 0
2
1
C A P 0 8 0 5
1 8 p F
64
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-39. Flash ROM, UART and LEDs Schematic
C R 1
9
1 2
4 7 0
R 1 5
2
4
6
8
1
L E D 0
L E D 1
L E D 2
L E D 3
L E D 4 S M
C R 1
5
6
7
8
4
3
3
2
1
L E D 4 S M
C R 1
5
L E D 4 S M
C R 1
R N C 4 R 8 P
7
L E D 4 S M
4 7 0
R 1 6
C R 2
2
4
6
8
1
L E D 4
L E D 5
L E D 6
L E D 7
L E D 4 S M
C R 2 4
5
6
7
8
3
3
2
1
L E D 4 S M
C R 2
2
5
5
L E D 4 S M
C R 2
R N C 4 R 8 P
7
L E D 4 S M
R 5 9
1
2
% 5
1 / 1 0 W
1 0 K
Design Guide
65
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-40. Logic Analyzer I/F Schematic
66
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-41. SDRAM 168-Pin DIMM Schematic
C 1 2 0
C 1 2 1
2
1
2
1
C A P 0 8 0 5
0 . 1 u F
C A P 0 8 0 5
0 . 1 u F
C 1 1 8
C 1 1 9
1
2
1
2
C A P 0 8 0 5
0 . 0 4 7 u F
C A P 0 8 0 5
0 . 0 4 7 u F
Design Guide
67
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-42. Secondary PCI/80960 Core Schematic
R 1 4
1
2
% 5
1 / 1 0 W
1 . 5 K
C 7 6
1
C 9 2
1
C 5 7
1
2
2
2
2
2
2
C A P T 7 3 4 3
C A P T 7 3 4 3
C A P T 7 3 4 3
4 . 7 u F
4 . 7 u F
4 . 7 u F
C 7 7
1
C 9 6
1
C 6 1
1
C A P 0 8 0 5
0 . 0 1 u F
C A P 0 8 0 5
0 . 0 1 u F
C A P 0 8 0 5
0 . 0 1 u F
S _ A D 0
A H 1 4
S A D 0
S _ A D 1
A K 1 4
S A D 1
S _ A D 2
A L 1 4
S A D 2
S _ A D 3
A M 1 4
S _ A D 4
S A D 3
A H 1 5
S A D 4
S _ A D 5
A J 1 5
S A D 5
S _ A D 6
A K 1 5
S _ A D 7
S A D 6
A M 1 5
S A D 7
S _ A D 8
A J 1 7
S A D 8
S _ A D 9
A K 1 7
S A D 9
S _ A D 1 0
A M 1 7
S A D 1 0
S A D 1 1
S A D 1 2
S A D 1 3
S A D 1 4
S A D 1 5
S A D 1 6
S A D 1 7
S A D 1 8
S A D 1 9
S A D 2 0
S A D 2 1
S A D 2 2
S A D 2 3
S A D 2 4
S A D 2 5
S A D 2 6
S A D 2 7
S A D 2 8
S A D 2 9
S A D 3 0
S A D 3 1
S _ A D 1 1
A H 1 8
S _ A D 1 2
A K 1 8
S _ A D 1 3
A L 1 8
S _ A D 1 4
A M 1 8
S _ A D 1 5
A H 1 9
S _ A D 1 6
A H 2 2
S _ A D 1 7
A K 2 2
S _ A D 1 8
A L 2 2
S _ A D 1 9
A M 2 2
S _ A D 2 0
A H 2 3
S _ A D 2 1
A J 2 3
S _ A D 2 2
A K 2 3
S _ A D 2 3
A M 2 3
S _ A D 2 4
A K 2 4
S _ A D 2 5
A L 2 4
S _ A D 2 6
A M 2 4
S _ A D 2 7
A H 2 5
S _ A D 2 8
A J 2 5
S _ A D 2 9
A K 2 5
S _ A D 3 0
A M 2 5
S _ A D 3 1
A H 2 6
68
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-43. Secondary PCI Bus 1/2 Schematic
Design Guide
69
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-44. Secondary PCI Bus 3/4 Schematic
70
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RM I/O Processor Schematics
Figure 15-45. Battery Monitor Schematic
C 6 3
1
C A P T 7 3 4 3
3 3 u F
2
2
3 3 0 u F
C A P T 7 3 4 3 H
1
C 6 4
1 0 0 u F
C A P T 7 3 4 3 H
2
2
1
C 5 6
4 7 u H
L 1
C 5 3
1
C A P 0 8 0 5
0 . 1 u F
R 2 1
3
2
1
7
6
5
1
2
1
2
1 % 1 W
0 . 0 5
R 4 7
1
2
1 / 1 0 W
% 5
C 5 1
2 . 4 K
2
1
C A P 0 8 0 5
0 . 1 u F
C 5 2
1
2
C A P T 7 3 4 3
1 0 u F
C 6 5
1
1
2
1
2
1
2
1
2
2
C A P 1 2 0 6
0 . 4 7 u F
C R 8
C 4 7
1
C A P T 7 3 4 3
2 2 u F
R 3 5
R 3 2
1
1
2
1
2
1
2
1
2
1
2
C M R 1 - 0 2
1
2
2
2
% 5
1 / 1 0 W
1 0 K
5 % 1 / 1 0 W
1 0 0 K
2
Q 4
1
2 N 6 1 0 9
R 2 0
3
C 8 2
R 4 8
1
2
1 / 1 0 W
% 5
1 5 0
1
2
2
1
% 5
% 5
% 5
1 / 1 0 W
4 . 7 K
C A P 0 8 0 5
0 . 0 4 7 u F
C 5 5
R 2 4
R 4 9
2
1
C A P 0 8 0 5
0 . 0 1 u F
1
2
1
2
1 / 1 0 W
% 5
1 / 1 0 W
4 . 7 K
1 0 0 K
R 5 3
1
C 5 8
1
C A P 0 8 0 5
0 . 0 1 u F
R 2 5
C 6 8
1
C A P 0 8 0 5
0 . 0 1 u F
2
2
1
2
1 / 1 0 W
% 5
1 / 1 0 W
2
4 7 K
1 K
R 2 6
1
R 3 4
1
1 u F
1
2
2
% 5
1 / 1 0 W % 5
1 / 1 0 W
C A P T 3 2 1 6
R 2 8
1
R 2 7
1
6 8 K
2 2 K
2
2
2
% 5
1 / 1 0 W % 5
1 / 1 0 W
C 7 4
1
1
R 6 0
1
C 5 4
2
2
1
% 5
1 / 1 0 W
C A P T 7 3 4 3
1 0 u F
1 0
Design Guide
71
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RM Board Bill of Material
Intel® IQ80960RM Board Bill of MaterialB
This appendix identifies all components on the IQ80960RM Evaluation Platform (Table B-1).
Table B-1.
Intel® IQ80960RM Bill of Materials (Sheet 1 of 4)
Item Qty
Location
U13
Part Description
Manufacturer
Manufacturer Part #
National
Semiconductor
1
2
3
4
5
6
7
1
1
1
2
1
1
1
IC/SM 74ALS32 SOIC-14
DM74ALS32M
National
Semiconductor
U6
IC/SM 74ALS04 SOIC
IC/SM 74ABT273 SOIC
IC/SM 74ABT573 SOIC
IC/SM 74ALS08 SOIC
IC / SM 1488A SOIC
IC / SM 1489A SOIC
DM74ALS04BM
SN74ABT273DW
SN74ABT573DW
DM74ALS08M
DS1488M
Texas
Instruments
U3
Texas
Instruments
U1, U2
U16
U5
National
Semiconductor
National
Semiconductor
National
Semiconductor
U7
DS1489AM
8
9
1
1
Q1
U9
IC/SM Si9430DY SOIC-8
Siliconix
Motorola
Si9430DY
MPC9140
IC/SM LVCMOS Fanout Buffr SSOP
National
Semiconductor
10
1
U10
IC/SM LM339 SOIC-14
LM339M
11
12
13
14
1
1
1
1
U8
IC/SM MAX1651CSA SOIC-8
IC/SM MAX712CSE SOIC-16
IC/SM MAX767CAP SOIC
Maxim
Maxim
Maxim
Intel
MAX1651CSA
MAX712CSE
MAX767CAP
U14
U17
U15
PROCESSOR (frm Intel) i960RM
Texas
Instruments
15
16
1
1
U12
C65
VLSI I/O UART 16C550 PLCC
TL16C550AFN
CAP SM, 0.47 µF (1206) Philips
Philips
12062F474Z9BB0
C2, C3,
C10, C11,
C18, C19,
C26, C27,
C55, C58,
C61, C68,
C77, C83,
C96
17
15
CAP SM, 0.01 µF (0805)
Kemet
C0805C103K5RAC
72
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RM Board Bill of Material
Table B-1.
Intel® IQ80960RM Bill of Materials (Sheet 2 of 4)
Item Qty
Location
Part Description
Manufacturer
Manufacturer Part #
C1, C4, C5,
C6, C7, C8,
C9, C12,
C13, C14,
C15, C16,
C17, C20,
C21, C22,
C23, C24,
C25, C28,
C29, C30,
C31, C32,
C33, C34,
C35, C36,
C37, C38,
C39, C40,
C41, C42,
C43, C44,
C45, C46,
C48, C49,
C50, C51,
C53, C59,
C62, C66,
C67, C69,
C70, C71,
C73, C79,
C80, C81,
C85, C86,
C87, C94,
C95, C97,
C98, C99,
C100,C101,
C102,C103,
C104,C105,
C106,C107,
C108,C109,
C111, C112,
C113, C114,
C115, C116,
C117
18
79
CAP SM, 0.1 µF (0805)
Philips
08052R104K8BB2
19
20
21
22
1
2
1
1
C110
CAP SM, 18 pF(0805)
Kemet
Dale
C0805C180J5GAC
CRCW0805100JT
CRCW08051000JT
CRCW08051001FRT
R27, R28
R60
R/SM 1/10 W 5% 1 ohm (0805)
R/SM 1/10 W 5% 10 ohm (0805)
R/SM 1/10 W 5% 1 Kohm (0805)
Dale
R25
Dale
R5, R6, R7
R8, R9,
R10, R11,
R12, R35,
R39, R58,
R59
23
12
R/SM 1/10 W 5% 10 Kohm (0805)
Dale
CRCW08051002FRT
24
25
2
1
R24, R32
R20
R/SM 1/10 W 5% 100 Kohm (0805)
R/SM 1/10 W 1% 150 ohm (0805)
Dale
Dale
CRCW08051003FRT
CRCW08051500FRT
R14, R41,
R42
26
3
R/SM 1/10 W 5% 1.5 Kohm (0805)
Dale
CRCW0805152JT
27
28
29
1
2
1
R18
R/SM 1/10 W 5% 1.6 Kohm (0805)
R/SM 1/10 W 5% 22 ohm (0805)
R/SM 1/10 W 5% 22 Kohm (0805)
Dale
Dale
Dale
CRCW0805162JT
CRCW0805220JT
CRCW0805223JT
R50, R51
R34
Design Guide
73
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RM Board Bill of Material
Table B-1.
Intel® IQ80960RM Bill of Materials (Sheet 3 of 4)
Item Qty
Location
R37
Part Description
Manufacturer
Manufacturer Part #
30
31
32
33
34
35
36
37
38
1
1
1
1
1
1
2
1
1
R/SM 1/10 W 5% 24 ohm (0805)
R/SM 1/10 W 5% 2.4 Kohm (0805)
R/SM 1/10 W 5% 2.7 Kohm (0805)
R/SM 1/10 W 5% 330 ohm (0805)
R/SM 1/10 W 5% 36 ohm (0805)
R/SM 1/10 W 5% 470 ohm (0805)
R/SM 1/10 W 1% 4.7 Kohm (0805)
R/SM 1/10 W 5% 47 Kohm (0805)
R/SM 1/10 W 5% 68 Kohm (0805)
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
Dale
CRCW0805240JT
CRCW0805242JT
CRCW0805272JT
CRCW0805331JT
CRCW0805360JT
CRCW 0805 471JT
CRCW08054701FRT
CRCW0805473JT
CRCW0805683JT
R47
R57
R19
R29
R17
R48, R49
R53
R26
R30, R43,
R54, R56
39
40
41
4
5
4
R/SM 1/8 W 5% 10 ohm chip 1206
CONN SM/TH Mictor 43P Recptcl
CONN PCI Slot 5V/PCB ThruHole
Dale
AMP
AMP
CRCW1206100FT
767054-1
J8, J9, J10,
J11, J12
J1, J2, J3,
145154-4
a
J4
42
43
44
45
1
1
1
1
J5
CONN DIMM 168P/RAng/Socket/TH
CONN TJ6 PCB 6/6 LP through hole
CONN/FAN ASSY/Socket/ThruHole
CONN Hdr 16 pin/w shell, pcb
Molex
KYCON
AMP
73790-0059
GM-N-66
J7
J13
J6
173981-03
103308-3
AMP
Z1, Z2, Z3,
Z4
46
4
Jumper JUMP2X1
Molex
22-54-1402
47
48
49
50
51
1
1
1
1
1
L1
Inductor/SM 47 µH 20%
Coilcraft
Coilcraft
Mors
D03340P-473
D03316P-332
DHS-4S
L2
Inductor/SM 3.3 µH 20%
S1
U4
U18
Switch/SM DIP4 Mors# DHS-4S
OSC 1.8432 MHz 1/2 - Through hole
Clock Chip CY7B9910-7SC
Kyocera
Cypress
KH0HC1CSE 1.843
CY7B9910-7SC
Hewlett
Packard
52
53
54
1
1
1
CR5
CR3
CR4
LED Green
LED-Red
HLMP-3507$010
HLMP3301$010
HLMP4740#010
Hewlett
Packard
Hewlett
Packard
LED Green LP
55
56
57
58
60
2
2
1
1
1
CR1, CR2
Q2, Q3
Q4
LED-Red-Small Group
Dialight
Harris
555-4001
Transistor/SM N-Channel
RFD16N05LSM
2N6109
Transistor 2N6109 (Through Hole)
SOCKET PLCC20 LP Surface Mount
SOCKET / SM / TSOP / 40 pin
Motorola
AMP
U19
822269-1
U11
Meritec
980020-40-02
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
61
8
Battery Clips/PC/Snap-In/AA
Keystone
#92
62
63
1
1
U19
U11
PALLV16V8Z-20JI
AMD
Intel
PALLV16V8Z-20JI
E28F016S5-090
MEM Flash E28F016S5-090 TSOP
74
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RM Board Bill of Material
Table B-1.
Intel® IQ80960RM Bill of Materials (Sheet 4 of 4)
Item Qty
Location
Part Description
Manufacturer
Manufacturer Part #
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
64
8
Battery AA NiCd @ 600 mA/Hour
SAFT
NIC-AA-600-SAFT
65
66
1
3
U15
C84
HeatSink/Fan Assy 80960RN/RM
Panasonic
Philips
UDQFNBEOIF
CAP SM, 0.22 µF (1206)
12062E224M9BB2
C60, C75,
C78
67
3
CAP TANT SM 220 µF, 10 V (7343)
AVX
TPSE227K010R010
C89, C90,
C91, C93
68
69
70
4
1
4
CAP TANT SM 47 µF, 16 V (7343)
CAP TANT SM 33 µF, 10 V (7343)
CAP TANT SM 4.7 µF, 35 V (7343)
AVX
TPSD476K016R015
293D336X9016D2T
293D475X9035D2T
C63
Sprague
Sprague
C57, C76,
C88, C92
71
72
73
74
75
76
77
78
79
1
1
2
1
1
1
1
1
1
C47
CAP TANT SM 22 µF, 20 V (7343)
CAP TANT SM 1 µF, 16 V (3216)
CAP TANT SM 10 µF, 25/35 V
CAP TANT SM 100 µF 10 V (7343)
CAP TANT SM 330 µF 6.3 V (7343)
CAP SM, 0.047 µF (0805)
Sprague
Sprague
Sprague
AVX
293D226X9020D2T
293D105X0016A2T
293D1060025D2T
TPSD107K010R0100
TPSE337K063R0100
C0805C473K5RAC
WSL-2512-R012
C74
C52, C54
C56
C64
AVX
C82
Kemet
Dale
R46
Res/SM 1 W 1% 0.012 ohm (2512)
Res/SM 1 W 1% 0.05 ohm (2512)
Resistor/SM 1/2 W 5% 100 ohm
R21
Dale
WSL-2512-R050
R52
Beckmen
BCR 1/2 101 JT
R1, R31,
R33, R36,
R38, R44,
R45
80
7
Resistor Pk SM RNC4R8P 2.7 Kohm
CTS
742083272JTR
81
82
83
84
2
2
1
2
R40, R55
R15, R16
R13
Resistor Pk SM RNC4R8P 22 ohm
Resistor Pk SM RNC4R8P 470 ohm
Resistor Pk SM RNC4R8P 1.5 Kohm
Resistor Pk SM RNC4R8P 30 ohm
CTS
CTS
CTS
CTS
742083220JTR
742083471JTR
742083152JTR
742083300JTR
R22, R23
Central
Semiconductor
85
86
87
88
1
2
1
1
CR9
Diode CMPSH3 Surface Mount
Diode SM / MBRS340T3
CMPSH3
CR6, CR7
CR8
Motorola
MBRS340T3
CMR1-02
Central
Semiconductor
Diode/SM 1N4001 (CMR1-02)
SDRAM, DIMM, ECC, 2Mx72, 16 MB
J5
Unigen
UG52S7408GSG
a.
Connectors for IQ80960RM, CONN PCI 32-BIT 5 V/PCB ThruHole, AMP #145154-4.
Design Guide
75
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Intel® i960® RN I/O Processor
Schematics
C
Schematics in this document supersede schematics in Document #AZ1-00886.
76
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-46. Decoupling and 3.3 V Power Schematic
2 2 0 u F
C A P T 7 3 4 3
2
2
1
C 7 8
2 2 0 u F
C A P T 7 3 4 3
1
C 7 5
1
C O I L - S M T 2
3 . 3 u H
L 2
C 8 6
1
C A P 0 8 0 5
0 . 1 u F
2
1
2
R 5 4
1
2
5 % 1 / 8 W
1 0
Design Guide
77
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-47. Primary PCI Interface Schematic
R 3 9
1
2
% 5
1 / 1 0 W
1 0 K
C 8 9
2
2
1
C A P T 7 3 4 3
4 7 u F
C 9 4
1
C A P 0 8 0 5
0 . 1 u F
R 5 8
1
2
% 5
1 / 1 0 W
1 0 K
C 9 5
1
2
C A P 0 8 0 5
0 . 1 u F
C 1 0 4
P _ A D 3 2
P _ A D 3 3
P _ A D 3 4
P _ A D 3 5
P _ A D 3 6
P _ A D 3 7
P _ A D 3 8
P _ A D 3 9
P _ A D 4 0
P _ A D 4 1
P _ A D 4 2
P _ A D 4 3
P _ A D 4 4
P _ A D 4 5
P _ A D 4 6
P _ A D 4 7
P _ A D 4 8
P _ A D 4 9
P _ A D 5 0
P _ A D 5 1
P _ A D 5 2
P _ A D 5 3
P _ A D 5 4
P _ A D 5 5
P _ A D 5 6
P _ A D 5 7
P _ A D 5 8
P _ A D 5 9
P _ A D 6 0
P _ A D 6 1
P _ A D 6 2
P _ A D 6 3
P _ A D 0
U 1
P A D 3 2 A G 2
P A D 3 3 A G 3
P A D 3 4 A F 1
P A D 3 5 A F 3
P A D 3 6 A F 4
P A D 3 7 A F 5
P A D 3 8 A E 1
P A D 3 9 A E 2
P A D 4 0 A E 3
P A D 4 1 A E 5
P A D 4 2 A D 1
P A D 4 3 A D 3
P A D 4 4 A D 4
P A D 4 5 A D 5
P A D 4 6 A C 1
P A D 4 7 A C 2
P A D 4 8 A C 3
P A D 4 9 A C 5
P A D 5 0 A B 1
P A D 5 1 A B 3
P A D 5 2 A B 4
P A D 5 3 A B 5
P A D 5 4 A A 1
P A D 5 5 A A 2
P A D 5 6 A A 3
P A D 5 7 A A 5
P A D 5 8 Y 1
P A D 0
P _ A D 1
2
1
U 2
P A D 1
C A P 0 8 0 5
0 . 1 u F
C 1 0 2
P _ A D 2
U 3
P A D 2
P _ A D 3
T 1
P A D 3
P _ A D 4
T 3
P A D 4
2
2
2
2
2
1
P _ A D 5
C A P 0 8 0 5
0 . 1 u F
C 1 0 1
T 4
P A D 5
P _ A D 6
T 5
P A D 6
P _ A D 7
R 1
P A D 7
1
P _ A D 8
R 3
P A D 8
C A P 0 8 0 5
0 . 1 u F
C 1 0 0
P _ A D 9
R 5
P A D 9
P _ A D 1 0
P 1
P A D 1 0
P A D 1 1
P A D 1 2
P A D 1 3
P A D 1 4
P A D 1 5
P A D 1 6
P A D 1 7
P A D 1 8
P A D 1 9
P A D 2 0
P A D 2 1
P A D 2 2
P A D 2 3
P A D 2 4
P A D 2 5
P A D 2 6
P A D 2 7
P A D 2 8
P A D 2 9
P A D 3 0
P A D 3 1
P _ A D 1 1
1
P 3
C A P 0 8 0 5
0 . 1 u F
C 9 8
P _ A D 1 2
P 4
P _ A D 1 3
P 5
P _ A D 1 4
N 1
1
P _ A D 1 5
C A P 0 8 0 5
0 . 1 u F
C 9 7
N 2
P _ A D 1 6
K 3
P _ A D 1 7
K 4
1
P _ A D 1 8
K 5
C A P 0 8 0 5
0 . 1 u F
P _ A D 1 9
J 1
P _ A D 2 0
J 2
P _ A D 2 1
J 3
P _ A D 2 2
J 5
P _ A D 2 3
H 1
P _ A D 2 4
H 5
P _ A D 2 5
G 1
P _ A D 2 6
G 2
P _ A D 2 7
P A D 5 9 Y 3
G 3
P _ A D 2 8
E 5
P A D 6 0 Y 4
P _ A D 2 9
P A D 6 1 Y 5
A 6
P _ A D 3 0
C 6
P A D 6 2 W 1
P A D 6 3 W 2
P _ A D 3 1
D 6
78
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-48. Memory Controller Schematic
R 5 7
1
2
5 % 1 / 1 0 W
2 . 7 K
R 4 1
1
2
5 % 1 / 1 0 W
1 . 5 K
R 4 2
1
2
5 % 1 / 1 0 W
1 . 5 K
1
D Q 3 2
D Q 3 3
D Q 3 4
D Q 3 5
D Q 3 6
D Q 3 7
D Q 3 8
D Q 3 9
D Q 4 0
D Q 4 1
D Q 4 2
D Q 4 3
D Q 4 4
D Q 4 5
D Q 4 6
D Q 4 7
D Q 4 8
D Q 4 9
D Q 5 0
D Q 5 1
D Q 5 2
D Q 5 3
D Q 5 4
D Q 5 5
D Q 5 6
D Q 5 7
D Q 5 8
D Q 5 9
D Q 6 0
D Q 6 1
D Q 6 2
D Q 6 3
D Q 0
D Q 1
D Q 3 2
D Q 3 3
D Q 3 4
D Q 3 5
D Q 3 6
D Q 3 7
D Q 3 8
D Q 3 9
D Q 4 0
D Q 4 1
D Q 4 2
D Q 4 3
D Q 4 4
D Q 4 5
D Q 4 6
D Q 4 7
D Q 4 8
D Q 4 9
D Q 5 0
D Q 5 1
D Q 5 2
D Q 5 3
D Q 5 4
D Q 5 5
D Q 5 6
D Q 5 7
D Q 5 8
D Q 5 9
D Q 6 0
D Q 6 1
D Q 6 2
D Q 6 3
E 2 2
D 2 2
A 2 3
D Q 0
D Q 1
B 2 3
D Q 2
E 2 3
C 2 3
D Q 2
D Q 3
C 2 4
A 2 4
D Q 3
D Q 4
E 2 4
D 2 4
D Q 4
D Q 5
B 2 5
A 2 5
D Q 5
D Q 6
E 2 5
C 2 5
D Q 6
D Q 7
C 2 6
A 2 6
D Q 7
D Q 8
E 2 6
A 2 7
D Q 8
D Q 9
C 2 7
B 2 7
D Q 9
D Q 1 0
A 2 8
E 2 7
D Q 1 0
D Q 1 1
D Q 1 2
D Q 1 3
D Q 1 4
D Q 1 5
D Q 1 6
D Q 1 7
D Q 1 8
A A 3 2 D Q 1 9
D Q 1 1
C 2 8
G 3 2
H 3 1
D Q 1 2
H 3 2
D Q 1 3
H 2 8
H 3 0
D Q 1 4
J 3 0
J 3 2
D Q 1 5
J 2 8
J 2 9
D Q 1 6
W 2 8
Y 3 1
W 2 9
D Q 1 7
Y 3 2
D Q 1 8
Y 3 0
Y 2 8
D Q 1 9
D Q 2 0
D Q 2 1
D Q 2 2
D Q 2 3
D Q 2 4
D Q 2 5
D Q 2 6
D Q 2 7
D Q 2 8
D Q 2 9
D Q 3 0
D Q 3 1
A A 3 0
A A 2 8
A B 3 1
A B 2 8
A C 3 0
A C 2 8
A D 3 1
A D 2 8
A E 3 0
A E 2 8
A F 3 1
A F 2 8
A H 3 2
A A 2 9
A B 3 2
A B 3 0
A C 3 2
D Q 2 0
D Q 2 1
D Q 2 2
D Q 2 3
A C 2 9 D Q 2 4
A D 3 2
A D 3 0
A E 3 2
A E 2 9
A F 3 2
A F 3 0
A G 3 2
D Q 2 5
D Q 2 6
D Q 2 7
D Q 2 8
D Q 2 9
D Q 3 0
D Q 3 1
C 1 1 0
2
1
C A P 0 8 0 5
1 8 p F
Design Guide
79
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-49. Flash ROM, UART and LEDs Schematic
C R 1
9
1 2
4 7 0
R 1 5
2
4
6
8
1
L E D 0
L E D 1
L E D 2
L E D 3
L E D 4 S M
C R 1
5
6
7
8
4
3
3
2
1
L E D 4 S M
C R 1
5
L E D 4 S M
C R 1
R N C 4 R 8 P
7
L E D 4 S M
4 7 0
R 1 6
C R 2
2
4
6
8
1
L E D 4
L E D 5
L E D 6
L E D 7
L E D 4 S M
C R 2 4
5
6
7
8
3
3
2
1
L E D 4 S M
C R 2
2
5
5
L E D 4 S M
C R 2
R N C 4 R 8 P
7
L E D 4 S M
R 5 9
1
2
5 % 1 / 1 0 W
1 0 K
80
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-50. Logic Analyzer I/F Schematic
Design Guide
81
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-51. SDRAM 168-Pin DIMM Schematic
C 1 2 0
C 1 2 1
2
1
2
1
C A P 0 8 0 5
C A P 0 8 0 5
0 . 1 u F
0 . 1 u F
C 1 1 8
1
C A P 0 8 0 5
0 . 0 4 7 u F
C 1 1 9
2
2
1
C A P 0 8 0 5
0 . 0 4 7 u F
82
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-52. Secondary PCI/80960 Core Schematic
R 1 4
1
2
5 % 1 / 1 0 W
1 . 5 K
C 7 6
1
C 9 2
1
C 5 7
1
2
2
2
2
2
2
C A P T 7 3 4 3
C A P T 7 3 4 3
C A P T 7 3 4 3
4 . 7 u F
4 . 7 u F
4 . 7 u F
C 7 7
1
C 9 6
1
C 6 1
1
C A P 0 8 0 5
0 . 0 1 u F
C A P 0 8 0 5
0 . 0 1 u F
C A P 0 8 0 5
0 . 0 1 u F
S _ A D 3 2
S _ A D 0
A H 1 4
S A D 3 2
S A D 3 3
S A D 3 4
S A D 3 5
S A D 3 6
S A D 3 7
S A D 3 8
S A D 3 9
S A D 4 0
S A D 4 1
S A D 4 2
S A D 4 3
S A D 4 4
S A D 4 5
S A D 4 6
S A D 4 7
S A D 4 8
S A D 4 9
S A D 5 0
S A D 5 1
S A D 5 2
S A D 5 3
S A D 5 4
S A D 5 5
S A D 5 6
S A D 5 7
S A D 5 8
S A D 5 9
S A D 6 0
S A D 6 1
S A D 6 2
S A D 6 3
A H 1
A H 3
A H 4
A J 2
S A D 0
S _ A D 3 3
S _ A D 3 4
S _ A D 3 5
S _ A D 3 6
S _ A D 3 7
S _ A D 3 8
S _ A D 3 9
S _ A D 4 0
S _ A D 4 1
S _ A D 4 2
S _ A D 4 3
S _ A D 4 4
S _ A D 4 5
S _ A D 4 6
S _ A D 4 7
S _ A D 4 8
S _ A D 4 9
S _ A D 5 0
S _ A D 5 1
S _ A D 5 2
S _ A D 5 3
S _ A D 5 4
S _ A D 5 5
S _ A D 5 6
S _ A D 5 7
S _ A D 5 8
S _ A D 5 9
S _ A D 6 0
S _ A D 6 1
S _ A D 6 2
S _ A D 6 3
S _ A D 1
A K 1 4
S A D 1
S _ A D 2
A L 1 4
S A D 2
S _ A D 3
A M 1 4
S _ A D 4
S A D 3
A J 5
A H 1 5
S A D 4
S _ A D 5
A K 5
A J 1 5
S A D 5
S _ A D 6
A M 5
A H 6
A K 6
A K 1 5
S _ A D 7
S A D 6
A M 1 5
S A D 7
S _ A D 8
A J 1 7
S A D 8
S _ A D 9
A L 6
A K 1 7
S A D 9
S _ A D 1 0
A M 6
A H 7
A J 7
A M 1 7
S A D 1 0
S A D 1 1
S A D 1 2
S A D 1 3
S A D 1 4
S A D 1 5
S A D 1 6
S A D 1 7
S A D 1 8
S A D 1 9
S A D 2 0
S A D 2 1
S A D 2 2
S A D 2 3
S A D 2 4
S A D 2 5
S A D 2 6
S A D 2 7
S A D 2 8
S A D 2 9
S A D 3 0
S A D 3 1
S _ A D 1 1
A H 1 8
S _ A D 1 2
A K 1 8
S _ A D 1 3
A K 7
A L 1 8
S _ A D 1 4
A M 7
A H 8
A K 8
A M 1 8
S _ A D 1 5
A H 1 9
S _ A D 1 6
A H 2 2
S _ A D 1 7
A L 8
A K 2 2
S _ A D 1 8
A M 8
A H 9
A J 9
A L 2 2
S _ A D 1 9
A M 2 2
S _ A D 2 0
A H 2 3
S _ A D 2 1
A K 9
A J 2 3
S _ A D 2 2
A M 9
A H 1 0
A K 1 0
A L 1 0
A M 1 0
A H 1 1
A J 1 1
A K 1 1
A M 1 1
A H 1 2
A K 2 3
S _ A D 2 3
A M 2 3
S _ A D 2 4
A K 2 4
S _ A D 2 5
A L 2 4
S _ A D 2 6
A M 2 4
S _ A D 2 7
A H 2 5
S _ A D 2 8
A J 2 5
S _ A D 2 9
A K 2 5
S _ A D 3 0
A M 2 5
S _ A D 3 1
A H 2 6
Design Guide
83
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-53. Secondary PCI Bus 1/2 Schematic
84
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-54. Secondary PCI Bus 3/4 Schematic
Design Guide
85
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-55. SPCI Pull-Ups Schematic
86
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® i960® RN I/O Processor Schematics
Figure 15-56. Battery/Monitor Schematic
C 6 3
1
C A P T 7 3 4 3
3 3 u F
2
2
3 3 0 u F
C A P T 7 3 4 3 H
1
C 6 4
1 0 0 u F
C A P T 7 3 4 3 H
2
2
1
C 5 6
4 7 u H
L 1
C 5 3
1
C A P 0 8 0 5
0 . 1 u F
R 2 1
3
2
1
7
6
5
1
2
1
2
1 % 1 W
0 . 0 5
R 4 7
1
2
1 / 1 0 W
5 %
C 5 1
2 . 4 K
2
1
C A P 0 8 0 5
0 . 1 u F
C 5 2
1
2
C A P T 7 3 4 3
1 0 u F
C 6 5
1
1
2
1
2
1
2
1
2
2
C A P 1 2 0 6
0 . 4 7 u F
C R 8
C 4 7
1
C A P T 7 3 4 3
2 2 u F
R 3 5
R 3 2
1
1
2
1
2
1
2
1
2
1
2
C M R 1 - 0 2
1
2
2
2
5 %
1 / 1 0 W
1 0 K
5 %
1 / 1 0 W
1 0 0 K
2
Q 4
1
2 N 6 1 0 9
R 2 0
3
C 8 2
R 4 8
1
2
5 %
1 / 1 0 W
1 5 0
1
2
2
1
5 %
5 %
5 %
1 / 1 0 W
4 . 7 K
C A P 0 8 0 5
0 . 0 4 7 u F
C 5 5
R 2 4
R 4 9
2
1
C A P 0 8 0 5
0 . 0 1 u F
1
2
1
2
1 / 1 0 W
5 %
1 / 1 0 W
4 . 7 K
1 0 0 K
R 5 3
1
C 5 8
1
C A P 0 8 0 5
0 . 0 1 u F
R 2 5
1
C 6 8
1
C A P 0 8 0 5
0 . 0 1 u F
2
2
2
1 / 1 0 W
5 %
1 / 1 0 W
2
4 7 K
1 K
R 2 6
R 3 4
1
1 u F
1
2
2
5 %
1 / 1 0 W 5 %
1 / 1 0 W
C A P T 3 2 1 6
R 2 8
1
R 2 7
1
6 8 K
2 2 K
2
1
C 7 4
2
2
5 %
1 / 1 0 W 5 %
1 / 1 0 W
1
1
R 6 0
C 5 4
1
2
1 / 1 0 W
2
1
5 %
C A P T 7 3 4 3
1 0 u F
1 0
Design Guide
87
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RN Board Bill of Material
Intel® IQ80960RN Board Bill of MaterialD
This appendix identifies all components on the IQ80960RN Evaluation Platform (Table D-1).
Table D-1.
Intel® IQ80960RN Bill of Materials (Sheet 1 of 4)
Item Qty
Location
U13
Part Description
Manufacturer
Manufacturer Part #
National
Semiconductor
1
2
3
4
5
6
7
1
1
1
2
1
1
1
IC/SM 74ALS32 SOIC-14
DM74ALS32M
National
Semiconductor
U6
IC/SM 74ALS04 SOIC
IC/SM 74ABT273 SOIC
IC/SM 74ABT573 SOIC
IC/SM 74ALS08 SOIC
IC / SM 1488A SOIC
IC / SM 1489A SOIC
DM74ALS04BM
SN74ABT273DW
SN74ABT573DW
DM74ALS08M
DS1488M
Texas
Instruments
U3
Texas
Instruments
U1,U2
U16
U5
National
Semiconductor
National
Semiconductor
National
Semiconductor
U7
DS1489AM
8
9
1
1
Q1
U9
IC/SM Si9430DY SOIC-8
Siliconix
Motorola
Si9430DY
MPC9140
IC/SM LVCMOS Fanout Buffr SSOP
National
Semiconductor
10
1
U10
IC/SM LM339 SOIC-14
LM339M
11
12
13
14
1
1
1
1
U8
IC/SM MAX1651CSA SOIC-8
IC/SM MAX712CSE SOIC-16
IC/SM MAX767CAP SOIC
80960RN PROCESSOR
Maxim
Maxim
Maxim
Intel
MAX1651CSA
MAX712CSE
MAX767CAP
U14
U17
U15
Texas
Instruments
15
16
1
1
U12
C65
VLSI I/O UART 16C550 PLCC
TL16C550AFN
CAP SM, 0.47 µF (1206) Philips
Philips
12062F474Z9BB0
C2, C3,
C10, C11,
C18, C19,
C26, C27,
C55, C58,
C61, C68,
C77, C83,
C96
17
15
CAP SM, 0.01 µF (0805)
Kemet
C0805C103K5RAC
88
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RN Board Bill of Material
Table D-1.
Intel® IQ80960RN Bill of Materials (Sheet 2 of 4)
Item Qty
Location
Part Description
Manufacturer
Manufacturer Part #
C1, C4, C5,
C6, C7, C8,
C9, C12,
C13, C14,
C15, C16,
C17, C20,
C21, C22,
C23, C24,
C25, C28,
C29, C30,
C31, C32,
C33, C34,
C35, C36,
C37, C38,
C39, C40,
C41, C42,
C43, C44,
C45, C46,
C48, C49,
C50, C51,
C53, C59,
C62, C66,
C67, C69,
C70, C71,
C73, C79,
C80, C81,
C85, C86,
C87, C94,
C95, C97,
C98, C99,
C100,C101,
C102,C103,
C104,C105,
C106,C107,
C108,C109,
C111, C112,
C113, C115,
C116, C114,
C117
18
79
CAP SM, 0.1 µF (0805)
Philips
08052R104K8BB2
19
20
21
22
1
2
1
1
C110
CAP SM, 18 pF (0805)
Kemet
Dale
C0805C180J5GAC
CRCW0805100JT
CRCW08051000JT
CRCW08051001FRT
R27, R28
R60
R/SM 1/10 W 5% 1 ohm (0805)
R/SM 1/10 W 5% 10 ohm (0805)
R/SM 1/10 W 5% 1 Kohm (0805)
Dale
R25
Dale
R35, R39,
R58, R59
23
4
R/SM 1/10 W 5% 10 Kohm (0805)
Dale
CRCW08051002FRT
24
25
2
1
R24, R32
R20
R/SM 1/10 W 5% 100 Kohm (0805)
R/SM 1/10 W 1% 150 ohm (0805)
Dale
Dale
CRCW08051003FRT
CRCW08051500FRT
R14, R41,
R42
26
3
R/SM 1/10 W 5% 1.5 Kohm (0805)
Dale
CRCW0805152JT
27
28
29
30
31
32
1
2
1
1
1
2
R18
R/SM 1/10 W 5% 1.6 Kohm (0805)
R/SM 1/10 W 5% 22 ohm (0805)
R/SM 1/10 W 5% 22 Kohm (0805)
R/SM 1/10 W 5% 24 ohm (0805)
R/SM 1/10 W 5% 2.4 Kohm (0805)
R/SM 1/10 W 5% 2.7 Kohm (0805)
Dale
Dale
Dale
Dale
Dale
Dale
CRCW0805162JT
CRCW0805220JT
CRCW0805223JT
CRCW0805240JT
CRCW0805242JT
CRCW0805272JT
R50, R51
R34
R37
R47
R2, R57
Design Guide
89
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RN Board Bill of Material
Table D-1.
Intel® IQ80960RN Bill of Materials (Sheet 3 of 4)
Item Qty
Location
R19
Part Description
Manufacturer
Manufacturer Part #
33
34
35
36
37
38
1
1
1
2
1
1
R/SM 1/10 W 5% 330 ohm (0805)
R/SM 1/10 W 5% 36 ohm (0805)
R/SM 1/10 W 5% 470 ohm (0805)
R/SM 1/10 W 1% 4.7 Kohm (0805)
R/SM 1/10 W 5% 47 Kohm (0805)
R/SM 1/10 W 5% 68 Kohm (0805)
Dale
Dale
Dale
Dale
Dale
Dale
CRCW0805331JT
CRCW0805360JT
CRCW 0805 471JT
CRCW08054701FRT
CRCW0805473JT
CRCW0805683JT
R29
R17
R48, R49
R53
R26
R30, R43,
R54, R56
39
40
41
4
5
4
R/SM 1/8 W 5% 10 ohm chip 1206
CONN SM/TH Mictor 43P Recptcl
CONN PCI 64BIT 5 V/PCB ThruHole
Dale
AMP
AMP
CRCW1206100FT
767054-1
J8, J9, J10,
J11, J12
J1, J2, J3,
145166-4
a
J4
42
43
44
45
1
1
1
1
J5
CONN DIMM 168P/RAng/Socket/TH
CONN TJ6 PCB 6/6 LP through hole
CONN/FAN ASSY/Socket/ThruHole
CONN Hdr 16 pin/w shell, pcb
Molex
KYCON
AMP
73790-0059
GM-N-66
J7
J13
J6
173981-03
103308-3
AMP
Z1, Z2, Z3,
Z4
46
4
Jumper JUMP2X1
Molex
22-54-1402
47
48
49
50
51
1
1
1
1
1
L1
Inductor/SM 47µH 20%
Coilcraft
Coilcraft
Mors
D03340P-473
D03316P-332
DHS-4S
L2
Inductor/SM 3.3 µH 20%
S1
U4
U18
Switch/SM DIP4 Mors# DHS-4S
OSC 1.8432 MHz 1/2 - Through hole
Clock Chip CY7B9910-7SC
Kyocera
Cypress
KH0HC1CSE 1.843
CY7B9910-7SC
Hewlett
Packard
52
53
54
1
1
1
CR5
CR3
CR4
LED Green
LED-Red
HLMP-3507$010
HLMP3301$010
HLMP4740#010
Hewlett
Packard
Hewlett
Packard
LED Green LP
55
56
57
58
2
2
1
1
CR1, CR2
Q2, Q3
Q4
LED-Red-Small Group
Dialight
Harris
555-4001
Transistor/SM N-Channel
RFD16N05LSM
2N6109
Transistor 2N6109 (Through Hole)
SOCKET PLCC20 LP Surface Mount
Motorola
AMP
U19
822269-1
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
60
8
Battery Clips/PC/Snap-In/AA
Keystone
#92
61
62
1
1
U19
U11
PALLV16V8Z-20JI
AMD
Intel
PALLV16V8Z-20JI
E28F016S5-090
MEM Flash E28F016S5-090 TSOP
BT1, BT2,
BT3, BT4,
BT5, BT6,
BT7, BT8
63
64
8
1
Battery AA NiCd @ 600 mA/Hour
HeatSink/Fan Assy 80960RM/RN
SAFT
NIC-AA-600-SAFT
UDQFNBEOIF
U15
Panasonic
90
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RN Board Bill of Material
Table D-1.
Intel® IQ80960RN Bill of Materials (Sheet 4 of 4)
Item Qty
Location
C84
Part Description
Manufacturer
Manufacturer Part #
65
66
1
3
CAP SM, 0.22 µF (1206)
Philips
12062E224M9BB2
C60, C75,
C78
CAP TANT SM 220 µF, 10 V (7343)
AVX
TPSE227K010R010
C89, C90,
C91, C93
67
68
69
4
1
4
CAP TANT SM 47 µF, 16 V (7343)
CAP TANT SM 33 µF, 10 V (7343)
CAP TANT SM 4.7 µF, 35 V (7343)
AVX
TPSD476K016R015
293D336X9016D2T
293D475X9035D2T
C63
Sprague
Sprague
C57, C76,
C88, C92
70
71
72
73
74
75
76
77
78
1
1
2
1
1
1
1
1
1
C47
CAP TANT SM 22 µF, 20 V (7343)
CAP TANT SM 1 µF, 16 V (3216)
CAP TANT SM 10 µF, 25/35 V
CAP TANT SM 100 µF 10 V (7343)
CAP TANT SM 330 µF 6.3 V (7343
CAP SM, 0.047 µF (0805)
Sprague
Sprague
Sprague
AVX
293D226X9020D2T
293D105X0016A2T
293D1060025D2T
TPSD107K010R0100
TPSE337K063R0100
C0805C473K5RAC
WSL-2512-R012
C74
C52, C54
C56
C64
AVX
C82
Kemet
Dale
R46
Res/SM 1 W 1% 0.012 ohm (2512)
Res/SM 1 W 1% 0.05 ohm (2512)
Resistor/SM 1/2 W 5% 100 ohm
R21
Dale
WSL-2512-R050
R52
Beckmen
BCR 1/2 101 JT
R1, R3, R4,
R5, R6, R7,
R8, R9,
79
16
R10, R11,
R12, R33,
R36, R38,
R44, R45,
Resistor Pk SM RNC4R8P 2.7 Kohm
CTS
742083272JTR
80
81
82
83
2
2
1
2
R40, R55
R15, R16
R13
Resistor Pk SM RNC4R8P 22 ohm
Resistor Pk SM RNC4R8P 470 ohm
Resistor Pk SM RNC4R8P 1.5 Kohm
Resistor Pk SM RNC4R8P 30 ohm
CTS
CTS
CTS
CTS
742083220JTR
742083471JTR
742083152JTR
742083300JTR
R22, R23
Central
Semiconductor
84
85
86
87
1
2
1
1
CR9
Diode CMPSH3 Surface Mount
Diode SM / MBRS340T3
CMPSH3
CR6, CR7
CR8
Motorola
MBRS340T3
CMR1-02
Central
Semiconductor
Diode/SM 1N4001 (CMR1-02)
SDRAM, DIMM, ECC, 2Mx72, 16 MB
J5
Unigen
UG52S7408GSG
a.
Connectors for IQ80960RN, CONN PCI 32-BIT 5 V/PCB ThruHole, AMP #145154-4.
Design Guide
91
Intel® i960® RM/RN I/O Processor
Intel® IQ80960RM/RN SDRAM Battery Backup PLD Equations
Intel® IQ80960RM/RN SDRAM Battery
Backup PLD Equations
E
MODULE BATT
//TITLE
SDRAM Battery Backup Enable
//PATTERN101-1809-01
//REVISION
//AUTHORJ. Neumann
//COMPANYCyclone Microsystems Inc.
//DATE
//CHIP
10/30/97
PALLV16V8Z-20JI
// 1/20/98 Modify target device to PALLV16V8Z-20JI
//Initial release.
PRSTn
SCKE0
SCKE1
OUT0
PIN 9;//Primary PCI reset
PIN 13; //SDRAM bank 0 clock enable
PIN 16; //SDRAM bank 1 clock enable
PIN 14; //SCKE0 output enable
PIN 17; //SCKE1 output enable
OUT1
EQUATIONS
// If SDRAM clock enable goes low, SDRAM clock enable
// must be held low to ensure that the SDRAM is held in auto refresh mode.
// Reset going high will release the hold on SCKE.
OUT0 = SCKE0.PIN & PRSTn//SCKE is the set term, PRSTn is the reset term
# SCKE0.PIN & OUT0.PIN
# !SCKE0.PIN & PRSTn;
SCKE0 = 0;
SCKE0.OE = !OUT0;//When OUT = 0, SCKE is grounded
//When OUT = 1, SCKE is high impedance
OUT1 = SCKE1.PIN & PRSTn
# SCKE1.PIN & OUT1.PIN
# !SCKE1.PIN & PRSTn;
SCKE1 = 0;
SCKE1.OE = !OUT1;
92
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Intel® 80960RM/RN Processor PBGA
Signal Ball Map
F
Table F-1 details the ballout for the 80960RM processor.
Table F-1.
540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 1 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
A1
A2
V
V
V
V
V
A32
B1
V
V
V
V
V
V
V
B31
B32
C1
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
CC
CC
CC
CC
CC
CC
SS
SS
CC
CC
SS
CC
A3
B2
A4
B3
C2
A5
B4
C3
A6
P_AD29
P_GNT#
SCL
B5
C4
A7
B6
C5
A8
B7
P_RST#
C6
P_AD30
P_INTD#
SDA
A9
NMI#
B8
V
C7
CC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
XINT3#
I_RST#
TDI
B9
XINT0#
C8
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
V
C9
XINT1#
XINT4#
TRST#
TCK
CC
TMS
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
RAD00
RAD04
RAD08
N/C
V
CC
RAD01
V
RAD02
RAD05
RAD09
CC
VCCPLL2
V
V
V
V
CC
CC
CC
CC
RAD12
RAD16
RWE#
V
V
CC
SS
RALE
RAD13
RCE0#
P_CLK
ONCE#
VCCPLL1
DQ02
LCDINIT#
DCLKOUT
DQ01
V
V
V
CC
SS
CC
DQ03
DQ33
DQ05
V
CC
DQ07
DQ37
DQ35
DQ40
V
DQ06
CC
DQ42
DQ09
DQ39
V
V
V
V
V
V
DQ41
CC
SS
SS
CC
CC
CC
DQ11
V
CC
Design Guide
93
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-1.
540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 2 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
C30
C31
C32
D1
V
V
E5
E6
P_AD28
P_REQ#
P_INTC#
P_INTA#
XINT2#
G2
G3
P_AD26
P_AD27
CC
CC
V
V
E7
G4
V
SS
SS
SS
CC
E8
G5
N/C
D2
V
E9
G28
G29
G30
G31
G32
H1
V
V
SS
SS
CC
CC
D3
V
V
V
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
F1
V
CC
SS
SS
SS
D4
TDO
V
V
D5
FAIL#
D6
P_AD31
RAD03
RAD07
RAD10
DQ43
D7
V
P_AD23
SS
D8
P_INTB#
H2
V
CC
D9
V
V
H3
P_IDSEL
P_C/BE3#
P_AD24
DQ45
SS
SS
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
E1
XINT5#
RAD11
RAD15
RCE1#
H4
V
H5
SS
CC
V
H28
H29
H30
H31
H32
J1
V
V
V
SS
SS
CC5REF
RAD06
DCLKIN
DQ13
DQ44
V
V
V
DQ32
DQ34
DQ36
DQ38
DQ08
DQ10
SS
SS
SS
DQ12
P_AD19
P_AD20
P_AD21
RAD14
J2
V
J3
SS
ROE#
J4
V
SS
V
V
V
V
J5
P_AD22
DQ47
SS
SS
SS
SS
CC
DQ00
J28
J29
J30
J31
J32
K1
V
DQ15
SS
DQ04
V
DQ46
V
V
V
V
CC
SS
SS
SS
CC
CC
CC
VCCPLL3
DQ14
V
V
V
F2
V
V
V
P_C/BE2#
SS
SS
SS
CC
CC
CC
F3
K2
V
CC
F4
K3
P_AD16
P_AD17
P_AD18
SCB5
V
V
V
F5
V
V
V
V
V
V
K4
SS
SS
SS
SS
SS
SS
F28
F29
F30
F31
F32
G1
K5
K28
K29
K30
K31
K32
V
V
SS
SS
CC
CC
E2
V
V
SCB1
SCB4
SCB0
E3
E4
V
P_AD25
SS
94
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-1.
540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 3 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
L1
L2
P_DEVSEL#
P_TRDY#
P_IRDY#
P32
R1
SA03
V31
V32
W1
SCB2
P_AD07
P_C/BE0#
P_AD08
SDQM7
L3
R2
P_AD62/ N/C
P_AD63/ N/C
P_PAR64/ N/C
L4
V
R3
W2
SS
L5
P_FRAME#
SDQM4
R4
V
W3
SS
L28
L29
L30
L31
L32
M1
R5
P_AD09
SA10
W4
V
SS
SDQM0
R28
R29
R30
R31
R32
T1
W5
P_C/BE4#|| N/C
DQ48
SCAS#
SA09
W28
W29
W30
W31
W32
Y1
V
SA08
DQ16
CC
SWE#
V
SCB7
CC
P_SERR#
SA07
V
CC
M2
V
P_AD03
SCB3
CC
M3
P_PERR#
P_LOCK#
P_STOP#
SCE1#
T2
V
P_AD58/ N/C
CC
M4
T3
P_AD04
P_AD05
P_AD06
SCKE0
Y2
V
CC
M5
T4
Y3
P_AD59/ N/C
P_AD60/ N/C
P_AD61/ N/C
DQ50
M28
M29
M30
M31
M32
N1
T5
Y4
V
T28
T29
T30
T31
T32
U1
Y5
SS
SCE0#
SDQM5
SDQM1
P_AD14
P_AD15
P_PAR
V
Y28
Y29
Y30
Y31
Y32
AA1
AA2
AA3
AA4
AA5
AA28
AA29
AA30
AA31
AA32
AB1
AB2
AB3
AB4
AB5
AB28
AB29
SS
SBA1
SBA0
V
SS
DQ18
DQ49
SA11
N2
P_AD00
P_AD01
P_AD02
DQ17
N3
U2
P_AD54/ N/C
P_AD55/ N/C
P_AD56/ N/C
N4
V
U3
SS
N5
P_C/BE1#
SA02
U4
V
SS
N28
N29
N30
N31
N32
P1
U5
P_REQ64#/ N/C
SDQM3
V
SS
SA01
U28
U29
U30
U31
U32
V1
P_AD57/ N/C
DQ52
SA00
SDQM6
V
SDQM2
DQ20
CC
SRAS#
V
DQ51
CC
P_AD10
SCKE1
V
CC
P2
V
N/C
DQ19
CC
P3
P_AD11
P_AD12
P_AD13
SA06
V2
V
P_AD50/ N/C
CC
P4
V3
N/C
N/C
N/C
N/C
V
CC
P5
V4
N/C
N/C
P28
P29
P30
P31
V5
V
V28
V29
V30
N/C
SS
SA05
SA04
V
DQ54
SS
SCB6
V
SS
Design Guide
95
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-1.
540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 4 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
AB30
AB31
AB32
AC1
DQ22
DQ53
AF29
AF30
AF31
AF32
AG1
V
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AJ1
S_AD31
S_REQ1#
S_REQ3#
SS
DQ30
DQ61
DQ21
P_AD46/ N/C
P_AD47/ N/C
P_AD48/ N/C
DQ29
V
SS
CC
CC
AC2
NC1/ N/C
P_AD32/ N/C
P_AD33/ N/C
V
V
AC3
AG2
AC4
V
AG3
DQ63
SS
AC5
P_AD49/ N/C
DQ56
AG4
V
V
V
V
V
CC
SS
SS
SS
SS
CC
CC
AC28
AC29
AC30
AC31
AC32
AD1
AG5
AJ2
S_AD35/ N/C
DQ24
AG28
AG29
AG30
AG31
AG32
AH1
AJ3
V
V
SS
SS
DQ55
AJ4
V
V
V
AJ5
S_AD36/ N/C
CC
DQ23
AJ6
V
SS
P_AD42/ N/C
DQ31
AJ7
S_AD44/ N/C
AD2
V
S_AD32/ N/C
AJ8
V
SS
CC
AD3
P_AD43/ N/C
P_AD44/ N/C
P_AD45/ N/C
DQ58
AH2
V
AJ9
S_AD52/ N/C
CC
AD4
AH3
S_AD33/ N/C
S_AD34/ N/C
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
V
SS
AD5
AH4
S_AD60/ N/C
AD28
AD29
AD30
AD31
AD32
AE1
AH5
V
V
SS
SS
V
AH6
S_AD39/ N/C
S_AD43/ N/C
S_AD47/ N/C
S_AD51/ N/C
S_C/BE7#|| N/C
SS
DQ26
DQ57
AH7
V
SS
AH8
S_AD05
DQ25
AH9
V
SS
P_AD38/ N/C
P_AD39/ N/C
P_AD40/ N/C
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
S_AD55 N/C
S_AD08
/
AE2
S_AD59/ N/C
S_AD63/ N/C
S_C/BE6#|| N/C
S_AD00
V
SS
AE3
S_C/BE1#
AE4
V
V
SS
SS
AE5
P_AD41/ N/C
DQ60
S_IRDY#
AE28
AE29
AE30
AE31
AE32
AF1
S_AD04
V
SS
DQ28
V
S_AD21
SS
DQ59
S_C/BE0#
S_AD11
V
SS
V
S_AD28
CC
DQ27
S_AD15
S_PERR#
S_TRDY#
S_AD16
S_AD20
S_C/BE3#
S_AD27
V
SS
N/C
S_GNT1#
AF2
V
V
SS
CC
AF3
N/C
N/C
S_REQ5#
AF4
V
V
CC
CC
AF5
N/C
AF28
DQ62
V
SS
96
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-1.
540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 5 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
AK1
AK2
V
V
V
V
AL1
AL2
V
V
V
V
V
AM1
AM2
V
V
V
V
SS
CC
CC
SS
SS
CC
CC
CC
CC
SS
SS
SS
CC
AK3
AL3
AM3
AK4
AL4
AM4
AK5
S_AD37/ N/C
S_AD40/ N/C
S_AD45/ N/C
S_AD48/ N/C
S_AD53/ N/C
S_AD56/ N/C
S_AD61/ N/C
S_PAR64/ N/C
AL5
AM5
N/C
N/C
AK6
AL6
N/C
AM6
AK7
AL7
V
AM7
N/C
CC
AK8
AL8
N/C
AM8
N/C
AK9
AL9
V
AM9
N/C
CC
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
N/C
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
N/C
V
N/C
CC
N/C
N/C
S_REQ64# N/C
V
N/C
/
CC
S_AD01
S_AD06
S_AD02
S_AD03
S_AD07
V
CC
V
N/C
V
CC
SS
S_AD09
S_AD12
S_PAR
V
S_AD10
S_AD14
CC
S_AD13
V
S_SERR#
S_DEVSEL#
S_C/BE2#
S_AD19
CC
S_LOCK#
S_FRAME#
S_AD17
S_AD22
S_AD24
S_AD29
S_RST#
S_REQ2#
S_GNT3#
S_GNT5#
S_STOP#
V
CC
S_AD18
V
S_AD23
CC
S_AD25
S_AD26
V
S_AD30
CC
S_REQ0#
S_GNT0#
S_GNT2#
S_GNT4#
V
CC
S_REQ4#
V
V
V
V
V
V
V
V
CC
CC
CC
SS
SS
SS
SS
SS
V
V
V
CC
CC
SS
Design Guide
97
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-2 details the ballout for the 80960RN processor.
Table F-2.
540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor (Sheet 1 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
A1
A2
V
V
V
V
V
B6
B7
V
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
D1
TRST#
TCK
SS
SS
SS
SS
SS
CC
P_RST#
A3
B8
V
RAD02
RAD05
RAD09
CC
A4
B9
XINT0#
A5
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
C1
V
CC
A6
P_AD29
P_GNT#
SCL
TMS
V
V
CC
SS
A7
V
CC
A8
RAD01
RAD13
RCE0#
P_CLK
ONCE#
VCCPLL1
DQ02
A9
NMI#
V
CC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
B1
XINT3#
I_RST#
TDI
VCCPLL2
V
V
V
CC
CC
CC
RAD00
RAD04
RAD08
N/C
RALE
DQ35
V
V
V
DQ06
CC
SS
CC
DQ39
V
DQ41
CC
RAD12
RAD16
RWE#
DQ33
DQ11
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
SS
SS
CC
SS
SS
SS
DQ37
LCDINIT#
DCLKOUT
DQ01
V
CC
DQ09
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
SS
SS
CC
CC
SS
CC
DQ03
D2
DQ05
D3
DQ07
D4
DQ40
D5
DQ42
D6
P_AD31
V
V
V
V
V
V
V
V
V
C2
D7
V
SS
CC
SS
SS
SS
SS
CC
CC
CC
CC
C3
D8
P_INTB#
C4
D9
V
SS
C5
D10
D11
D12
D13
D14
D15
XINT5#
C6
P_AD30
P_INTD#
SDA
V
V
V
SS
CC
SS
B2
C7
B3
C8
B4
C9
XINT1#
XINT4#
RAD06
B5
C10
V
SS
98
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-2.
540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor (Sheet 2 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
E1
V
V
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
F01
F02
F03
F04
F05
F28
F29
F30
F31
F32
G1
DQ34
DQ36
DQ38
DQ08
DQ10
H32
J1
DQ12
SS
P_AD19
P_AD20
P_AD21
SS
RAD14
J2
V
J3
SS
ROE#
J4
V
SS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
J5
P_AD22
DQ47
SS
SS
SS
SS
CC
SS
SS
CC
CC
CC
SS
SS
SS
SS
SS
SS
DQ00
J28
J29
J30
J31
J32
K1
V
DQ15
SS
DQ04
DQ46
V
V
CC
SS
VCCPLL3
DQ14
V
V
V
V
V
V
V
V
V
V
P_C/BE2#
SS
SS
SS
CC
CC
CC
SS
CC
CC
SS
K2
V
CC
K3
P_AD16
P_AD17
P_AD18
SCB5
K4
K5
K28
K29
K30
K31
K32
L1
V
SS
E2
SCB1
SCB4
E3
E4
P_AD25
P_AD26
P_AD27
SCB0
E5
P_AD28
P_REQ#
P_INTC#
P_INTA#
XINT2#
G2
P_DEVSEL#
P_TRDY#
P_IRDY#
E6
G3
L2
E7
G4
V
L3
SS
E8
G5
N/C
L4
V
SS
E9
G28
G29
G30
G31
G32
H1
V
V
V
V
L5
P_FRAME#
SDQM4
SS
SS
CC
CC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
V
L28
L29
L30
L31
L32
M1
M2
M3
M4
M5
M28
M29
M30
CC
TDO
SDQM0
FAIL#
SCAS#
RAD03
RAD07
RAD10
DQ43
V
CC
P_AD23
SWE#
H2
V
P_SERR#
CC
V
H3
P_IDSEL
P_C/BE3#
P_AD24
DQ45
V
CC
SS
RAD11
RAD15
RCE1#
H4
P_PERR#
P_LOCK#
P_STOP#
SCE1#
H5
H28
H29
H30
H31
V
V
SS
CC5REF
DCLKIN
DQ13
DQ44
V
SS
DQ32
SCE0#
Design Guide
99
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-2.
540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor (Sheet 3 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
M31
M32
N1
SDQM5
SDQM1
P_AD14
P_AD15
P_PAR
T30
T31
T32
U1
SBA1
SBA0
Y29
Y30
V
SS
DQ18
DQ49
SA11
Y31
N2
P_AD00
P_AD01
P_AD02
Y32
DQ17
N3
U2
AA1
AA2
AA3
AA4
AA5
AA28
AA29
AA30
AA31
AA32
AB1
AB2
AB3
AB4
AB5
AB28
AB29
AB30
AB31
AB32
AC1
AC2
AC3
AC4
AC5
AC28
AC29
AC30
AC31
AC32
AD1
AD2
AD3
AD4
AD5
P_AD54
P_AD55
P_AD56
N4
V
U3
SS
N5
P_C/BE1#
SA02
U4
V
SS
N28
N29
N30
N31
N32
P1
U5
P_REQ64#
SDQM3
V
SS
SA01
U28
U29
U30
U31
U32
V1
P_AD57
DQ52
SA00
SDQM6
V
SDQM2
DQ20
CC
SRAS#
V
DQ51
CC
P_AD10
SCKE1
V
CC
P2
V
P_C/BE5#
DQ19
CC
P3
P_AD11
P_AD12
P_AD13
SA06
V2
V
P_AD50
CC
P4
V3
P_C/BE6#
P_C/BE7#
P_ACK64#
N/C
V
CC
P5
V4
P_AD51
P_AD52
P_AD53
DQ54
P28
P29
P30
P31
P32
R1
V5
V
V28
V29
V30
V31
V32
W1
W2
W3
W4
W5
W28
W29
W30
W31
W32
Y1
SS
SA05
SA04
V
SS
SCB6
SCB2
V
SS
SA03
DQ22
DQ53
P_AD07
P_C/BE0#
P_AD08
SDQM7
P_AD62
P_AD63
P_PAR64
R2
DQ21
R3
P_AD46
P_AD47
P_AD48
R4
V
SS
R5
P_AD09
SA10
V
SS
R28
R29
R30
R31
R32
T1
P_C/BE4#
DQ48
V
SS
SA09
P_AD49
DQ56
SA08
DQ16
V
SCB7
DQ24
CC
SA07
V
DQ55
CC
P_AD03
SCB3
V
CC
T2
V
P_AD58
DQ23
CC
T3
P_AD04
P_AD05
P_AD06
SCKE0
Y2
V
P_AD42
CC
T4
Y3
P_AD59
P_AD60
P_AD61
DQ50
V
CC
T5
Y4
P_AD43
P_AD44
P_AD45
T28
T29
Y5
V
Y28
SS
100
Design Guide
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-2.
540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor (Sheet 4 of 5)
Ball #
Signal
DQ58
Ball #
Signal
Ball #
Signal
AD28
AD29
AD30
AD31
AD32
AE1
AH5
AH6
V
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AK1
V
SS
SS
V
S_AD39
S_AD43
S_AD47
S_AD51
S_AD55
S_AD59
S_AD63
S_C/BE6#
S_AD00
S_AD04
S_C/BE7#
SS
DQ26
DQ57
AH7
V
SS
AH8
S_AD05
DQ25
AH9
V
SS
P_AD38
P_AD39
P_AD40
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AJ1
S_AD08
AE2
V
SS
AE3
S_C/BE1#
AE4
V
V
SS
SS
AE5
P_AD41
DQ60
S_IRDY#
AE28
AE29
AE30
AE31
AE32
AF1
V
SS
DQ28
V
S_AD21
SS
DQ59
S_C/BE0#
S_AD11
V
SS
V
S_AD28
CC
DQ27
S_AD15
V
SS
P_AD34
S_PERR#
S_TRDY#
S_AD16
S_GNT1#
AF2
V
V
SS
CC
AF3
P_AD35
P_AD36
P_AD37
DQ62
S_REQ5#
AF4
S_AD20
V
V
V
V
V
V
V
CC
CC
SS
SS
CC
CC
SS
AF5
S_C/BE3#
S_AD27
AF28
AF29
AF30
AF31
AF32
AG1
AG2
AG3
AG4
AG5
AG28
AG29
AG30
AG31
AG32
AH1
V
S_AD31
SS
DQ30
DQ61
S_REQ1#
S_REQ3#
AK2
AK3
DQ29
V
V
V
AK4
SS
CC
CC
N/C
AK5
S_AD37
S_AD40
S_AD45
S_AD48
S_AD53
S_AD56
S_AD61
S_PAR64
S_REQ64#
S_AD01
S_AD06
P_AD32
P_AD33
AK6
DQ63
AK7
V
V
V
V
V
V
V
AK8
SS
SS
SS
SS
CC
CC
CC
AJ2
S_AD35
AK9
AJ3
V
V
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
SS
SS
AJ4
AJ5
S_AD36
AJ6
V
SS
DQ31
AJ7
S_AD44
S_AD32
AJ8
V
SS
AH2
V
AJ9
S_AD52
V
SS
CC
AH3
S_AD33
S_AD34
AJ10
AJ11
V
S_AD09
S_AD12
SS
AH4
S_AD60
Design Guide
101
Intel® i960® RM/RN I/O Processor
Intel® 80960RM/RN Processor PBGA Signal Ball Map
Table F-2.
540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor (Sheet 5 of 5)
Ball #
Signal
Ball #
Signal
Ball #
Signal
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AL1
S_PAR
S_LOCK#
S_FRAME#
S_AD17
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AM1
V
AM7
AM8
S_AD46
S_AD50
S_AD54
S_AD58
S_AD62
S_C/BE5#
S_ACK64#
S_AD03
S_AD07
CC
S_AD02
V
AM9
CC
N/C
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
S_AD22
V
CC
S_AD24
S_AD13
S_AD29
V
CC
S_RST#
S_STOP#
S_REQ2#
S_GNT3#
S_GNT5#
V
CC
S_AD18
V
CC
V
S_AD10
S_AD14
CC
V
V
V
V
V
V
V
V
S_AD25
CC
CC
SS
SS
CC
CC
CC
CC
V
S_SERR#
S_DEVSEL#
S_C/BE2#
S_AD19
CC
S_REQ0#
V
CC
AL2
S_REQ4#
AL3
V
V
V
V
V
V
V
V
S_AD23
CC
CC
CC
SS
SS
SS
SS
CC
AL4
S_AD26
AL5
S_AD30
AL6
S_AD41
S_GNT0#
S_GNT2#
S_GNT4#
AL7
V
CC
AL8
S_AD49
AM2
AL9
V
AM3
V
V
V
V
CC
SS
SS
SS
SS
AL10
AL11
AL12
S_AD57
AM4
V
AM5
S_AD38
S_AD42
CC
S_C/BE4#
AM6
102
Design Guide
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