NLXT907APCE2 [INTEL]
Ethernet Transceiver, PQCC44, PLASTIC, LCC-44;
| 型号： | NLXT907APCE2 |
| 厂家： | 
INTEL |
| 描述： | Ethernet Transceiver, PQCC44, PLASTIC, LCC-44 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总48页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® LXT901A/907A Universal 3.3 V
Ethernet Transceiver
Datasheet
The Intel® LXT901A and LXT907A Transceivers (called hereafter the LXT901A/907A
Transceivers) are new generation Universal Ethernet Transceivers with improved noise
immunity and output filtering. The feature set of the LXT901A/907A has been streamlined,
removing Remote Signaling capabilities. The LXT901A and LXT907A provide all the active
circuitry to interface most standard IEEE 802.3 controllers to either the 10BASE-T media or
Attachment Unit Interface (AUI).
The LXT901A and LXT907A Transceivers are identical except for the function of one pin. The
LXT901A Transceiver, with selectable termination impedance, allows the use of either shielded
or unshielded twisted-pair cable. The LXT907A Transceiver offers a Signal Quality Error
Disable (DSQE) function.
The LXT901A/907A Transceivers functions include Manchester encoding/decoding, receiver
squelch and transmit pulse shaping, jabber, link testing, and reversed polarity detection/
correction.
Applications
■ Access devices (DSL, Cable Modems, and ■ Telecom Backplane
Set-top Boxes)
■ Routers/Bridges/Switches/Hubs
■ USB to Ethernet Converters
Product Features
Functional Features
Convenience Features
■ Automatic/Manual AUI/RJ-45 Selection
■ Automatic Polarity Correction
■ Integrated Filters - Simplify FCC
Compliance
■ Integrated Manchester Encoder/Decoder
■ 10BASE-T Transceiver
■ SQE Disable function (LXT907A
Transceiver)
■ AUI Transceiver
■ Full-Duplex Capable (20 Mbps)
■ Programmable Impedance Driver
(LXT901A Transceiver)
■ Single 3.3V operation
Diagnostic Features
■ Four LED Drivers
■ Power-Down Mode and four loopback
modes
■ Available in 64-pin LQFP and 44-pin
■ AUI/RJ-45 Loopback
PLCC packages
■ Commercial (0 to +70oC)
Order Number: 249098-003
27-Nov-2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or
in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by
estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
The Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation. All Rights Reserved.
2
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Contents
Contents
1.0
Pin Assignments and Signal Descriptions ....................................................................8
2.0
Functional Description ..................................................................................................12
2.1
2.2
Controller Compatibility Modes ...........................................................................12
Transmit Function................................................................................................13
2.2.1 Jabber Control Function .........................................................................13
2.2.2 SQE Function.........................................................................................14
2.2.2.1 SQE Disable Function (LXT907A Transceiver only) .................14
2.3
2.4
Receive Function.................................................................................................15
2.3.1 Polarity Reverse Function ......................................................................15
2.3.2 Collision Detection Function...................................................................16
Loopback Functions ............................................................................................17
2.4.1 Standard TP Loopback...........................................................................17
2.4.2 Forced TP Loopback..............................................................................17
2.4.3 AUI Loopback.........................................................................................17
2.4.4 External Loopback..................................................................................17
Link Integrity Test Function .................................................................................17
Link Pulse Transmission .....................................................................................19
2.5
2.6
3.0
Application Information.................................................................................................19
3.1
3.2
3.3
3.4
Twisted-Pair Impedance Matching......................................................................19
Crystal Information ..............................................................................................19
Magnetics Information.........................................................................................19
Typical Applications.............................................................................................20
3.4.1 Auto Port Select with External Loopback Control...................................20
3.4.2 Full-Duplex Support................................................................................22
3.4.3 Dual Network Support - 10Base-T and Token Ring ...............................23
3.4.4 Manual Port Select with Link Test Function ...........................................24
3.4.5 Three Media Application.........................................................................26
3.4.6 AUI Encoder/Decoder Only....................................................................27
3.4.7 150W Shielded Twisted-Pair Only (LXT901A Transceiver only)............28
4.0
Test Specifications.........................................................................................................29
4.1
4.2
4.3
4.4
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low) Figures 17 - 22............33
Timing Diagrams for Mode 2 (MD1 = Low, MD0 = High) Figures 23 - 28...........35
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low) Figures 29 - 36...........37
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High) Figures 37 - 42 ..........40
5.0
6.0
Mechanical Specifications.............................................................................................42
5.1 Top-Label Marking ..............................................................................................44
Ordering Information .....................................................................................................47
Datasheet
3
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Contents
Figures
1
2
3
4
5
6
7
8
Intel® LXT901A/907A Transceiver Block Diagram................................................ 7
Intel® LXT901A and LXT907A Transceiver Pin Assignments .............................. 8
TPO Output Waveform .......................................................................................13
Jabber Control Function .....................................................................................14
SQE Function .....................................................................................................15
Collision Detection Function ...............................................................................16
Link Integrity Test Function ................................................................................18
Transmitted Link Integrity Pulse Timing .............................................................19
LAN Adapter Board - Auto Port Select with External LPBK Control ..................21
Full-Duplex Operation ........................................................................................22
380C26 Interface for Dual Network Support of 10BASE-T and Token Ring ......23
LAN Adapter Board - Manual Port Select with Link Test Function......................24
Manual Port Select with Seeq 8005 Controller ..................................................25
Three Media Application ....................................................................................26
AUI Encoder/Decoder Only Application .............................................................27
150 W Shielded Twisted-Pair Only Application (LXT901A Transceiver ) ...........28
Mode 1 RCLK/Start-of-Frame Timing ................................................................33
Mode 1 RCLK/End-of-Frame Timing ..................................................................33
Mode 1 Transmit Timing ....................................................................................34
Mode 1 Collision Detect Timing .........................................................................34
Mode 1 COL/CI Output Timing ...........................................................................34
Mode 1 Loopback Timing ...................................................................................34
Mode 2 RCLK/Start-of-Frame Timing ................................................................35
Mode 2 RCLK/End-of-Frame Timing ..................................................................35
Mode 2 Transmit Timing ....................................................................................36
Mode 2 Collision Detect Timing .........................................................................36
Mode 2 COL/CI Output Timing ...........................................................................36
Mode 2 Loopback Timing ...................................................................................36
Mode 3 RCLK/Start-of-Frame Timing (LXT901A Transceiver) ..........................37
Mode 3 RCLK/End-of-Frame Timing (LXT901A Transceiver) ...........................37
Mode 3 RCLK/Start-of-Frame Timing (LXT907A Transceiver) ..........................38
Mode 3 RCLK/End-of-Frame Timing (LXT907A Transceiver) ...........................38
Mode 3 Transmit Timing ....................................................................................39
Mode 3 Collision Detect Timing ..........................................................................39
Mode 3 COL/CI Output Timing ...........................................................................39
Mode 3 Loopback Timing ...................................................................................39
Mode 4 RCLK/Start-of-Frame Timing .................................................................40
Mode 4 RCLK/End-of-Frame Timing ..................................................................40
Mode 4 Transmit Timing ....................................................................................41
Mode 4 Collision Detect Timing .........................................................................41
Mode 4 COL/CI Output Timing ...........................................................................41
Mode 4 Loopback Timing ...................................................................................41
44-Pin PLCC .......................................................................................................42
64-Pin LQFP ......................................................................................................43
Sample LQFP Package – Intel® DJLXT901ALC Transceiver .............................44
Sample Pb-Free (RoHS-Compliant) LQFP Package –
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Intel® WJLXT901ALC Transceiver......................................................................44
Sample TQFP Package – Intel® DJLXT907ALC Transceiver.............................45
47
4
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Contents
48
Sample Pb-Free (RoHS-Compliant) TQFP Package –
Intel® WJLXT907ALC Transceiver......................................................................45
Sample PLCC Package – Intel® NLXT90xAPC Transceiver...............................46
Sample Pb-Free (RoHS-Compliant) PLCC Package –
49
50
Intel® EELXT90xAPC Transceiver ......................................................................46
Ordering Information Matrix – Sample ................................................................48
51
Tables
1
2
3
4
5
6
7
8
Signal Descriptions................................................................................................9
Controller Compatibility Modes ...........................................................................12
Suitable Crystals .................................................................................................19
Absolute Maximum Values..................................................................................29
Recommended Operating Conditions .................................................................29
I/O Electrical Characteristics ...............................................................................29
AUI Electrical Characteristics..............................................................................30
TP Electrical Characteristics ...............................................................................30
Switching Characteristics ....................................................................................31
RCLK/Start-of-Frame Timing...............................................................................31
RCLK/End-of-Frame Timing................................................................................32
Transmit Timing...................................................................................................32
Collision, COL/CI Output and Loopback Timing..................................................32
Product Information.............................................................................................47
9
10
11
12
13
14
Datasheet
5
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Contents
Revision History
Date
Revision
Page
Description
Updated Figure 2 “Intel® LXT901A and LXT907A Transceiver Pin
Assignments” on page 8.
8
44
47
Added Section 5.1, “Top-Label Marking” on page 44.
Modfied Table 14 “Product Information” on page 47.
27-Nov-2005
003
Modified Figure 51 “Ordering Information Matrix – Sample” on
page 48.
48
1
New items under “Applications”
23
24
25
26
27
Figure 9: Added 0.1 μF label to capacitor at bottom of graphic.
Figure 10: Added 0.1 μF label to capacitor at bottom of graphic.
Figure 11Added 0.1 μF label to capacitor at bottom of graphic.
Figure 12: Added 0.1 μF label to capacitor at bottom of graphic.
Figure 13: Added 0.1 μF label to capacitor at bottom of graphic.
June 2001
002
Added 2nd para under Test Specification regarding Quality and
Reliability information.
31
Removed “Ambient operating temperature” from Absolute Maximum
Values table.
31
45
Added Appendix: Product Ordering Information
6
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 1. Intel® LXT901A/907A Transceiver Block Diagram
MD0
MD1
AUTOSEL
PAUI
MODE SELECT LOGIC
Controller Compatibility
Port Select
TWISTED PAIR
INTERFACE
STP
(LXT901A only)
Select:
PLS Only
or
LBK
RC
RC
Loopback
Link test
LI
TPOPB
TPOPA
TPONA
TPONB
PLS / MAU
CMOS
TX
AMP
PULSE SHAPER
AND FILTER
TCLK
CLKI
DO
WATCHDOG
TIMER
COLLISION/
POLARITY
DETECT
XTAL
OSC
TPIP
TPIN
RX
SLICER
CLKO
TEN
CORRECT
MANCHESTER
ENCODER
TXD
DROP CABLE
INTERFACE
+
ECL
TX
AMP
DOP
DON
-
SQUELCH / LINK
DETECT
CD
LEDL
LPBK
RXD
DI
CI
DIP
DIN
MANCHESTER
DECODER
RCLK
RX SLICER
CIP
CIN
COLLISION
RECEIVER
COLLISION LOGIC
COL
LEDT/
PDN
DSQE
LEDR
LEDC/FDE
NTH JAB
PLR
Datasheet
7
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
1.0
Pin Assignments and Signal Descriptions
Figure 2. Intel® LXT901A and LXT907A Transceiver Pin Assignments
39 TPIN
38 TPIP
n/c
LI
7
8
9
37
DSQE (907A) or STP (901A)
JAB
Rev #
36 TPONB
35 TPONA
34 VCC2
33 GND2
32 TPOPA
31 TPOPB
30 PLR
TEST 10
TCLK 11
TXD 12
Part #
FPO #
LXT901A/907APC XX
XXXXXXXX
TEN 13
CLKO 14
CLKI 15
BSMC
COL 16
29 n/c
AUTOSEL 17
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
n/c
RCLK
CD
RXD
n/c
n/c
n/c
PAUI
DIP
1
2
3
4
5
6
7
8
DIN
n/c
DOP
DON
n/c
Rev #
RBIAS
n/c
GNDA
GND1
LBK
LEDC/FDE
LEDL
LEDT/PDN
LEDR
Part #
FPO #
LXT901A/907ALC XX
XXXXXXXX
VCCA
VCC1
CIP
9
10
11
12
BSMC
CIN
NTH
MD0
MD1
n/c
13
14
15
16
n/c
8
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Table 1. Signal Descriptions
Pin #
Symbol
I/O1
Description
PLCC
LQFP
1
34
10
56
VCC1
VCC2
–
–
Power Supply 1 and 2. Power supply inputs of +3.3 volts.
Analog Supply. (+3.3V)
–
9
VCCA
–
2
3
11
12
CIP
CIN
I
I
AUI Collision Pair. Differential input to the AUI transceiver CI circuit. The input is
collision signaling or SQE.
Normal Threshold. Selects normal or reduced threshold.
4
13
NTH
I
When NTH is High, the normal TP squelch threshold is in effect.
When NTH is Low, the normal TP squelch threshold is reduced by 4.5 dB.
I
I
5
6
14
15
MD0
MD1
Mode Select 0 (MD0) and Mode Select 1 (MD1). Mode select pins determine the
controller compatibility mode in accordance with Table 2.
Link Test Enable. Controls Link Integrity Test; enabled when LI = High, disabled
when LI = Low
8
9
19
21
22
LI
I
O
I
JAB
Jabber Indicator. Output goes High to indicate Jabber state.
Test. For Intel internal use only.
It is recommended to tie this pin High externally.
10
TEST
Transmit Clock. A 10 MHz clock output. This clock signal should be directly
connected to the transmit clock input of the controller.
11
12
13
23
24
25
TCLK
TXD
TEN
O
I
Transmit Data. Input signal containing NRZ data to be transmitted on the
network. Connect TXD directly to the transmit data output of the controller.
Transmit Enable. Enables data transmission and starts the watchdog timer.
Synchronous to TCLK (see Test Specifications for details).
I
14
15
26
27
CLKO
CLKI
O
I
Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a
20 MHz clock applied at CLKI with CLKO left open.
16
28
COL
O
Collision Detect. Output which drives the collision detect input of the controller.
Automatic Port Select.
When High, automatic port selection is enabled (the 901A/907A defaults to the
AUI port only if TP link integrity = Fail).
17
29
AUTOSEL
I
When Low, manual port selection is enabled (the PAUI pin determines the active
port).
Receive LED. Open drain driver for the receive indicator LED. Output is pulled
Low during receive.
18
19
34
35
LEDR
OD
OD
Transmit LED (LEDT)/Power-Down (PDN). Open drain driver for the transmit
indicator. Output is pulled Low during transmit. Do not allow this pin to float. If
unused, tie High.
LEDT/
PDN
If externally pulled Low, the LXT901A/907A goes to power-down state.
Link LED. Open drain driver for link integrity indicator. Output is pulled Low
during link test pass.
20
36
LEDL
OD
If externally tied Low, internal circuitry is forced to “Link Pass” state and the
LXT901A/907A Transceiver transmits link test pulses continuously.
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
Datasheet
9
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Table 1. Signal Descriptions (Continued)
Pin #
Symbol
I/O1
Description
PLCC
LQFP
Collision LED (LEDC)/Full-Duplex Enable (FDE). Open drain driver for the
collision indicator pulls Low during collision.
LED “On” (i.e., Low output) time is extended by approximately 100 ms.
LEDC/
FDE
21
37
OD
If externally tied Low, enables full-duplex operation by disabling the internal TP
loopback and collision detection circuits in anticipation of external twisted-pair
loopback or full-duplex operation.
If this pin is not used, tie High or directly to Vcc.
Loopback. Enables internal loopback mode. Refer to Functional Description for
details.
22
38
LBK
I
23
33
39
55
GND1
GND2
–
–
Ground Returns 1 and 2. Grounds
–
40
42
GNDA
RBIAS
–
I
Analog Ground.
Bias Control. A 12.4 kΩ 1% resistor to ground at this pin controls operating
circuit bias.
24
Receive Data. Output signal. Connect directly to the receive data input of the
controller.
26
27
28
45
46
47
RXD
CD
O
O
O
Carrier Detect. An output to notify the controller of activity on the network.
Receive Clock. A recovered 10 MHz clock that is synchronous to the received
data. Connect to the controller receive clock input.
RCLK
Polarity Reverse. Output goes High to indicate reversed polarity at the twisted-
pair input.
30
52
PLR
O
Twisted-Pair Transmit Pairs A & B. Two differential driver pair outputs (A and B)
to the twisted-pair cable. The outputs are pre-equalized.
31
36
53
58
TPOPB
TPONB
O
O
Each pair must be shorted together and tied to the transformer through a
24.9Ω 1% series resistor to match impedance of 100Ω.
Refer to Figure 16 on page 28 in the Applications Section for information on 150Ω
configurations.
32
35
54
57
TPOPA
TPONA
O
O
STP Select (LXT901A Transceiver only).
When STP is Low, 150Ω termination for shielded twisted-pair is selected.
When STP is High, 100Ω termination for unshielded twisted-pair is selected.
LXT907A Transceiver is designed for 100Ω unshielded twisted-pair termination
(not selectable).
37
59
STP
I
I
Disable SQE (LXT907A Transceiver only).
When DSQE is High, the SQE function is disabled.
DSQE
When DSQE is Low, the SQE function is enabled.
SQE must be disabled for normal operation in Hub/Switch applications.
The LXT901A Transceiver operates with SQE enabled (not selectable).
38
39
61
62
TPIP
TPIN
I
I
Twisted-Pair Receive Pair. A differential input pair from the twisted-pair cable.
Receive filter is integrated on-chip. No external filters are required.
Port/AUI Select. In Manual Port Select mode (AUTOSEL Low), PAUI selects the
active port.
When PAUI is High, the AUI port is selected.
When PAUI is Low, the TP port is selected.
40
3
PAUI
I
In Auto Port Select mode, PAUI must be tied to ground.
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
10
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Table 1. Signal Descriptions (Continued)
Pin #
LQFP
Symbol
I/O1
Description
PLCC
41
42
4
5
DIP
DIN
I
I
AUI Receive Pair. Differential input pair from the AUI transceiver DI circuit. The
input is Manchester encoded.
43
44
7
8
DOP
DON
O
O
AUI Transmit Pair. A differential output driver pair for the AUI transceiver cable.
The output is Manchester encoded.
1, 2, 6, 16,
17, 18, 20,
30, 31, 32,
33, 41, 43,
44, 48, 49,
50, 51, 60,
63, 64
7, 25,
29
N/C
–
No Connect (Internally tied to ground).
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
Datasheet
11
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
2.0
Functional Description
The LXT901A/907A Transceiver performs the physical layer signaling (PLS) and Media
Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. They function as a
PLS-Only device (for use with 10BASE-2 or 10BASE-5 coaxial cable networks) or as an
Integrated PLS/MAU (for use with 10BASE-T twisted-pair networks). In addition to standard 10
Mbps operation, they also support full-duplex 20 Mbps operation.
The LXT901A/907A Transceiver interfaces a back-end controller to either an AUI drop cable or a
twisted-pair (TP) cable. The controller interface includes a transmit and receive clock and NRZ
data channels, as well as mode control logic and signaling. The AUI interface comprises three
circuits: Data Output (DO), Data Input (DI) and Collision (CI). The twisted-pair interface is
comprised of two circuits: Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to
the three basic interfaces, the LXT901A/907A Transceiver contains an internal crystal oscillator
and four LED drivers for visual status reporting.
Functions are defined from the back-end controller side of the interface. The Transmit function
refers to data transmitted by the back-end to the AUI cable (PLS-Only mode) or to the twisted-pair
network (Integrated PLS/MAU mode). The Receive function refers to data received by the back-
end from the AUI cable (PLS-Only) or from the twisted-pair network (Integrated PLS/MAU
mode). In the integrated PLS/MAU mode, the LXT901A/907A Transceiver performs all required
MAU functions defined by the IEEE 802.3 10BASE–T specification, such as collision detection,
link integrity testing, signal quality error messaging, jabber control, and loopback. In the PLS-only
mode, the LXT901A/907A Transceiver receives incoming signals from the AUI DI circuit, with ±
18 ns of jitter, and drives the AUI DO circuit.
2.1
Controller Compatibility Modes
The LXT901A/907A Transceiver are compatible with most industry standard controllers, including
devices produced by Motorola*, AMD*, Intel, Fujitsu*, National Semiconductor*, Seeq*, and
Texas Instruments*. Four different control signal timing and polarity schemes (Modes 1 through 4)
are required to achieve this compatibility. Mode select pins (MD0 and MD1) determine controller
compatibility modes as listed in Table 2. Refer to Test Specifications for a complete set of timing
diagrams for each mode.
Table 2. Controller Compatibility Modes
Setting
Controller Mode
MD1
MD0
Mode 1
For Motorola 68EN360, MPC860, Advanced
Micro Devices AM7990 or compatible
controllers
Low
Low
Low
Mode 2
High
For Intel 82596 or
compatible controllers
1
12
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Table 2. Controller Compatibility Modes
Setting
Controller Mode
MD1
MD0
Mode 3
High
High
Low
For Fujitsu MB86950, MB86960 or
compatible controllers (Seeq 8005)
2
Mode 4
For National Semiconductor 8390 or
compatible controllers
High
(TI TMS380C26)
1. Refer to Intel Application Note 51 when designing with Intel
Controllers.
2. SEEQ controllers require inverters on CLK1, LBK, RCLK and
COL.
2.2
Transmit Function
The LXT901A/907A Transceiver receives NRZ data from the controller at the TXD input, as
shown in
Figure 1, “Intel® LXT901A/907A Transceiver Block Diagram” on page 7, and passes it through a
Manchester encoder. The encoded data is then transferred to either the AUI cable (the DO circuit)
or the twisted-pair network (the TPO circuit). The advanced integrated pulse shaping and filtering
network produces the output signal on TPON and TPOP as shown in Figure 3. The TPO output is
pre-distorted and pre-filtered to meet the 10BASE-T jitter template. An internal continuous
resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse
shaping circuitry. Integrated filters simplify the design work required for FCC compliant EMI
performance. During idle periods, the LXT901A/907A Transceiver transmits link integrity test
pulses on the TPO circuit (if LI is enabled and integrated, PLS/ MAU mode is selected). External
resistors control the termination impedance for the LXT907A Transceiver. External resistors and
the STP pin control termination impedance on the LXT901A Transceiver.
Figure 3. TPO Output Waveform
2.2.1
Jabber Control Function
Figure 4 is a state diagram of the LXT901A/907A Transceiver jabber control function. The on-chip
watchdog timer prevents the DTE from locking into a continuous transmit mode. When a
transmission exceeds the time limit, the watchdog timer disables the transmit and loopback
functions, and activates the JAB pin. Once the LXT901A/907A Transceiver is in the jabber state,
the TXD circuit must remain idle for a period of 250 to 750 ms before it exits the jabber state.
Datasheet
13
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 4. Jabber Control Function
Power On
No Output
DO=Active
Nonjabber Output
Start_XMIT_MAX_Timer
DO=Idle
DO=Active ∗
XMIT_Max_Timer_Done
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Idle
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab_ Timer_Done
DO=Active ∗
Unjab_Timer_Not_Done
2.2.2
SQE Function
In the integrated PLS/MAU mode, the LXT901A/907A Transceiver supports the signal quality
error (SQE) function as shown in Figure 5 on page 15, although the SQE function can be disabled
on the LXT907A Transceiver. After every successful transmission on the 10BASE-T network,
when SQE is enabled, the LXT901A/907A Transceiver transmits the SQE signal for 10 bit times ±
5 bit times over the internal CI circuit, which is indicated on the COL pin of the device. When
using the AUI of the LXT901A/907A Transceiver, the SQE function is determined by the external
MAU attached.
2.2.2.1
SQE Disable Function (LXT907A Transceiver only)
SQE must be disabled for normal operation in hub and switch applications. The
LXT907A Transceiver is configured with an SQE Disable function. The SQE function is disabled
when DSQE is set High, and enabled when DSQE is Low.
14
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 5. SQE Function
Power On
Output Idle
DO=Active
Output Detected
DO=Idle
SQE Wait Test
Start_SQE_Test__Wait_Timer
SQE_Test__Wait_Timer_Done ∗
XMIT=Enable
XMIT=Disable
SQE Test
Start_SQE_Test_Timer
CI=SQE
SQE_Test_Timer_Done
2.3
Receive Function
The LXT901A/907A Transceiver receive function acquires timing and data from the twisted-pair
network (the TPI circuit) or from the AUI (the DI circuit). Valid received signals are passed
through the on-chip filters and Manchester decoder, then output as decoded NRZ data and receive
timing on the RXD and RCLK pins, respectively.
An internal RC filter and an intelligent squelch function discriminate noise from link test pulses
and valid data streams. The receive function is activated only by valid data streams above the
squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs
falls below 75 percent of the threshold level (unsquelched) for 8 bit times (typical), the
LXT901A/907A Transceiver receive function enters the idle state. If the polarity of the TPI circuit
is reversed, LXT901A/907A Transceiver detects the polarity reverse and reports it via the PLR
output. The LXT901A/907A Transceiver automatically corrects reversed polarity.
2.3.1
Polarity Reverse Function
The LXT901A/907A Transceiver polarity reverse function uses both link pulses and end-of-frame
data to determine the polarity of the received signal. A reversed polarity condition is detected when
eight opposite receive link pulses are detected without receipt of a link pulse of the expected
polarity. Reversed polarity is also detected if four frames are received with a reversed start-of-idle.
Whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to
zero. If the LXT901A/907A Transceiver enters the link fail state and no valid data or link pulses
Datasheet
15
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. If Link
Integrity Testing is disabled, polarity detection is based only on received data. Polarity correction is
always enabled.
2.3.2
Collision Detection Function
The collision detection function operates on the twisted- pair side of the interface. For standard
(half-duplex) 10BASE-T operation, a collision is defined as the simultaneous presence of valid
signals on both the TPI circuit and the TPO circuit. The LXT901A/907A Transceiver reports
collisions to the back-end via the COL pin. If the TPI circuit becomes active while there is activity
on the TPO circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal
loopback. Figure 6 on page 16 is a state diagram of the LXT901A/907A Transceiver collision
detection function. Refer to Test Specifications for collision detection and COL/CI output timing.
Note: For full-duplex operation on the TP or AUI port, the collision detection circuitry must be disabled
by setting FDE Low.
Figure 6. Collision Detection Function
A
Power On
DO=Active ∗
TPI=Idle ∗
XMIT=Enable
Idle
TPI=Active
Output
Input
DI=TPI
TPO=DO
DI=DO
DO=Active ∗
TPI=Active ∗
XMIT=Enable
DO=Active ∗
TPI=Active ∗
XMIT=Enable
Collision
TPO=DO
DI=TPI
CI=SQE
A
A
DO=Idle+
XMIT=Disable
TPI=Idle
DO=Active ∗
TPI=Idle
DO=Idle
16
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
2.4
Loopback Functions
2.4.1
Standard TP Loopback
The LXT901A/907A Transceiver provides the standard loopback function defined by the
10BASE-T specification for the twisted-pair port. The loopback function operates in conjunction
with the transmit function. Data transmitted by the back-end is internally looped back within the
LXT901A/907A Transceiver from the TXD pin through the Manchester encoder/decoder to the
RXD pin and returned to the back-end. This standard loopback function is disabled when a data
collision occurs, clearing the RXD circuit for the TPI data. Standard loopback is also disabled
during link fail and jabber states. The LXT901A/907A Transceiver also provides three additional
loopback functions.
2.4.2
2.4.3
2.4.4
Forced TP Loopback
“Forced” twisted-pair loopback is controlled by the LBK pin. When the twisted-pair port is
selected and LBK is High, twisted-pair loopback is “forced”, overriding collisions on the twisted-
pair circuit. When LBK is Low, normal loopback is in effect.
AUI Loopback
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data transmitted by the back-end is internally looped back from the TXD pin through the
Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs.
External Loopback
An external loopback mode, useful for system-level testing, is controlled by the LEDC/FDE pin.
When LEDC/FDE is tied Low, the LXT901A/907A Transceiver disables the collision detection
and internal loopback circuits, to allow external loopback. External loopback mode can be set on
either twisted-pair or AUI ports.
2.5
Link Integrity Test Function
Figure 7 on page 18 is a state diagram of the LXT901A/907A Transceiver Link Integrity test
function. The link integrity test is used to determine the status of the receive side twisted-pair
cable. Link integrity testing is enabled when the LI pin is tied High. When enabled, the receiver
recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial
data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state
and disables the transmit and normal loopback functions. The LXT901A/907A Transceiver ignores
any link integrity pulse with an interval less than 2 - 7 ms. The LXT901A/907A Transceiver
remains in the link fail state until it detects either a serial data packet or two or more link integrity
pulses.
Datasheet
17
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 7. Link Integrity Test Function
Power On
Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
TPI=Active+
(Link_Test_Rcvd=True
∗ Link_Test_Min_Timer_Done)
Link_Loss_Timer_Done
∗ TPI=Idle
∗ Link_Test_Rcvd=False
Link Test Fail Reset
Link Test Fail Wait
Link_Count=0
XMIT=Disable
RCVR=Disable
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
TPI=Active
Link_Test_Rcvd=False
∗ TPI=Idle
TPI=Active
Link_Test_Rcvd=Idle
∗ TPI=Idle
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max
Link_Test_Min_Timer_Done
∗ Link_Test_Rcvd=True
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
(TPI=Idle ∗ Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
∗ Link_Test_Rcvd=True)
TPI=Idle ∗
DO=Idle
18
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
2.6
Link Pulse Transmission
When not transmitting data, the LXT901A/907A Transceiver transmits IEEE 802.3-compliant
standard link pulses. Figure 8 shows the link integrity pulse timing.
Figure 8. Transmitted Link Integrity Pulse Timing
10-20 ms
10-20 ms
10-20 ms
10-20 ms
10-20 ms 10-20 ms
10-20 ms
10-20 ms
10-20 ms
3.0
Application Information
3.1
Twisted-Pair Impedance Matching
Resistors must be installed on each input and output pair to match impedance of the network media
being used. The LXT907A Transceiver is configured with 100Ω termination for Unshielded
Twisted-Pair (UTP). In this case, the positive and negative sides of both output pairs are shorted
together (TPOPA/TPOPB and TPONA/TPONB) and tied to the transformer through a 24.9Ω 1%
series resistor.
The LXT901A Transceiver is designed with an STP Select pin that allows the device to match both
100Ω and 150Ω media. A dual resistor combination can be configured to accommodate either line
termination as shown in Figure 16 on page 28. When 100Ω termination is selected, both A and B
pairs are driven in parallel. When 150Ω termination is selected, the B pair is tri-stated and only the
A pair is driven.
3.2
Crystal Information
Designers should test and validate crystals before committing to a specific component. Based on
limited evaluation, Table 3 lists some suitable crystals.
Table 3. Suitable Crystals
Manufacturer
Part Number
MP-1
MP-2
MTRON
3.3
Magnetics Information
The LXT901A/LXT907A Transceiver requires a 1:1 ratio for the receive transformer and a 1:√2
ratio for the transmit transformer on the twisted-pair interface. The AUI Interface requires a 1:1
ratio for the data-in, data-out, and collision-pair transformers. A cross-reference list of suitable
Datasheet
19
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
magnetics and part numbers is available in Application Note 73, Magnetic Manufacturers (248991-
001), which can be found on the Intel web site (developer.intel.com/design/network/). Designers
must test and validate all components for suitability in their applications.
3.4
Typical Applications
Figure 9 on page 21 through Figure 16 on page 28 show typical LXT901A/907A Transceiver
applications.
3.4.1
Auto Port Select with External Loopback Control
Figure 9 on page 21 is a typical LXT901A/907A Transceiver application. The diagram groups
similar pins together, but does not represent the actual LXT901A/907A Transceiver pinout. The
controller interface pins (transmit data, clock and enable; receive data and clock; and the collision
detect, carrier detect and loopback control pins) are shown at the top left of the diagram.
Programmable option pins are grouped at the center left of the diagram. The PAUI pin is tied Low
and all other option pins are tied High. This setup selects the following options:
• Automatic Port Selection
(PAUI Low and AUTOSEL High)
• Normal Receive Threshold (NTH High)
• Mode 4, compatible with National NS8390 controllers (MD0 High, MD1 High)
• SQE Disabled (DSQE High for LXT907A Transceiver only)
• UTP is selected (STP High for LXT901A Transceiver only)
• Link Testing Enabled (LI High)
Status outputs are grouped at the lower left of the diagram. Local status outputs drive LED
indicators.
Power and ground pins are shown at the bottom of the diagram. A single power supply is used for
both VCC1 and VCC2, with a decoupling capacitor installed between the power and ground
busses. An additional power and ground pin (VCCA and GNDA) is supported in designs using the
64-pin LQFP package. A single power supply is used for all three power and ground pins (VCC1,
VCC2, VCCA) and (GND1, GND2, GNDA). Install a decoupling capacitor between each power
and ground buss.
The twisted-pair and AUI interfaces are shown at the upper and lower right of the diagram,
respectively. Impedance matching resistors for 100Ω UTP are installed in each I/O pair and no
external filters are required.
20
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 9. LAN Adapter Board - Auto Port Select with External LPBK Control
20 pF
20 pF
0.1 μF
20 MHz
CLKI
TXD
2
CLKO
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
RJ45
6
1
1 : 1 16
TPIN
TPIP
TEN
TCLK
RCLK
RXD
CD
50 Ω
50 Ω
NS8390 BACK-END
CONTROLLER
INTERFACE
5
4
3
2
1
3
14
COL
LBK
LOOPBACK
ENABLE
TPONB
TPONA
24.9 Ω 1%
24.9 Ω 1%
1 : 2 11
6
8
PAUI
AUTOSEL
NTH
9
PROGRAMMING
OPTIONS
MD0
TPOPB
TPOPA
MD1
DSQE (907A)
STP (901A)
LI
1
78 Ω
1
16
JAB
PLR
9
CIN
LINE STATUS
2
3
4
5
6
7
8
10
11
12
13
14
15
330
330 330 330
2
4
15
13
CIP
LEDC/FDE
LEDR
LEDT/PDN
78 Ω
78 Ω
Green
Red Red Red
1 : 1
DON
LEDL
5
12
10
DOP
DIN
1 : 1
7
Fuse
8
9
TEST
DIP
12.4 kΩ
+3.3 V
VCC1
VCC2
RBIAS
1 %
+ 12 V
GND1 GND2
Chassis
Gnd
1
0.1 μF
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
1
2
Datasheet
21
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
3.4.2
Full-Duplex Support
Figure 10 shows the LXT907A Transceiver with a Texas Instruments 380C24 CommProcessor.
The 380C24 is compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C24,
or other full-duplex capable controller, the LXT907A Transceiver supports full-duplex Ethernet,
effectively doubling the available bandwidth of the network. In this application, the SQE function
is enabled (DSQE tied Low), and the AUI port is not used.
Figure 10. Full-Duplex Operation
20 pF
20 pF
CLKO
0.1 μF
TMS380C24
20 MHz
4
CLKI
TXD
2
RJ45
6
TXD
1
1 : 1 16
TPIN
TPIP
TXEN
TXC
TEN
TCLK
RCLK
RXD
CD
50 Ω
50 Ω
RXC
5
4
3
2
1
3
14
RXD
CSN
COLL
COL
LBK
LPBK
TPONB
TPONA
1N914
1
1 : 2
24.9 Ω 1%
24.9 Ω 1%
11
*TEST0
OUTSEL0
6
8
LEDC/FDE
10 KΩ
9
TPOPB
AUTOSEL
NTH
*Open Collector
Driver
TPOPA
MD0
MD1
4.7 KΩ
PROGRAMMING
OPTIONS
LI
DSQE
(907A)
CIN
CIP
Half/Full Duplex Selection controlled by TMS380C24 Pins
Test0 and OUTSEL0.
1
2
The TMS380C26 may be substituted for dual network
support of 10BASE-T and Token Ring.
JAB
PLR
LINE STATUS
DON
DOP
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
3
4
330 330
330
PAUI
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
LEDR
LEDT/PDN
LEDL
Red Red
Green
DIN
DIP
TEST
12.4 kΩ
+3.3 V
VCC1
VCC2
RBIAS
GND2
1 %
3
GND1
0.1 μF
22
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
3.4.3
Dual Network Support - 10Base-T and Token Ring
Figure 11 shows the LXT901A/907A Transceiver with a Texas Instruments 380C26
CommProcessor. The 380C26 is compatible with Mode 4 (MD0 and MD1 both High). When used
with the 380C26, both the LXT901A/907A Transceiver and a TMS38054 Token Ring transceiver
can be tied to a single RJ-45, allowing dual network support from a single connector. The
LXT901A/907A Transceiver AUI port is not used. The DSQE pin on the LXT907A Transceiver is
tied Low and the STP pin on the LXT901A Transceiver is tied High.
Figure 11. 380C26 Interface for Dual Network Support of 10BASE-T and Token Ring
From TI TMS38054 Token
Ring Transceiver
To TI TMS38054 Token Ring
Transceiver
20 pF
20 pF
CLKO
0.1 μF
3
20 MHz
CLKI
TXD
380C26
TXD
2
RJ45
1
1 : 1 16
TPIN
TPIP
6
TXE
TEN
TCLK
RCLK
RXD
CD
50 Ω
50 Ω
TXC
RXC
5
3
14
RXD
CRS
4
COL
COL
LBK
LBK
3
TPONB
TPONA
1 : 2
11
24.9 Ω 1%
24.9 Ω 1%
6
8
AUTOSEL
NTH
2
9
PROGRAMMING
OPTIONS
MD0
1
TPOPA
TPOPB
MD1
STP 901A only
DSQE 907A only
LI
JAB
PLR
CIN
CIP
LINE STATUS
330
330 330 330
TEST
PAUI
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
LEDC/FDE
LEDR
LEDT/PDN
LEDL
1
2
3
Green Red Red Red
DON
DOP
Additional magnetics and switching logic (not shown)
are required to implement the dual network solution.
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
DIN
DIP
12.4 kΩ
+3.3 V
VCC1
VCC2
RBIAS
GND2
1 %
1
GND1
0.1 μF
Datasheet
23
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
3.4.4
Manual Port Select with Link Test Function
With MD0 tied Low and MD1 tied High, the LXT901A/907A Transceiver logic and framing are
set to Mode 3 (compatible with Fujitsu MB86950 and MB86960, and Seeq 8005 controllers).
Figure 12 shows the setup for Fujitsu controllers. Figure 13 on page 25 shows the four inverters
required to interface with the Seeq 8005 controller. As seen in Figure 9 on page 21 both these
Mode 3 applications show the LI pin tied High, enabling Link Testing; and the STP
(LXT901A Transceiver only) and NTH pins are both tied High, selecting the standard receiver
threshold and 100Ω termination for unshielded TP cable. However, in these applications
AUTOSEL is tied Low, allowing external port selection through the PAUI pin.
Figure 12. LAN Adapter Board - Manual Port Select with Link Test Function
20 pF
20 pF
0.1 μF
20 MHz
2
CLKI
TXD
CLKO
RJ45
6
TXD
TEN
1
1 : 1 16
TPIN
TPIP
TEN
TCLK
RCLK
RXD
CD
TCKN
RCKN
RXD
50 Ω
50 Ω
MB86950 or MB86960
BACK-END/
CONTROLLER
INTERFACE
5
4
3
2
1
3
14
XCD
XCOL
LBC
COL
LBK
TPONB
TPONA
1 :
2
24.9 Ω 1%
24.9 Ω 1%
11
9
Port Selection
6
8
PAUI
AUTOSEL
NTH
MD0
TPOPA
TPOPB
MD1
DSQE (907A)
STP (901A)
LI
1
78 Ω
16
1
JAB
PLR
9
CIN
LINE STATUS
2
3
4
5
6
7
8
10
11
12
13
14
15
330
330
330
330
2
4
15
13
CIP
LEDC/FDE
LEDR
LEDT/PDN
LEDL
78 Ω
Green
Red
Red
Red
1 : 1
DON
5
12
10
DOP
DIN
78 Ω
1 : 1
7
Fuse
8
9
TEST
DIP
12.4 kΩ
+3.3 V
VCC1
VCC2
RBIAS
+ 12 V
1 %
1
Chassis
Gnd
GND1 GND2
0.1 μF
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
1
2
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
24
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 13. Manual Port Select with Seeq 8005 Controller
External
20 MHz
Source
Left Open
CLKO
0.1 μF
2
CLKI
LPBK
CSN
RxD
CLKI
LBK
RJ45
6
1
16
14
1 : 1
TPIN
TPIP
CD
50 Ω
50 Ω
RXD
RCLK
COL
8005
RxC
5
4
3
2
1
3
COLL
TxEN
TxC
TEN
TCLK
TXD
TxD
TPONB
TPONA
1 : 2
24.9 Ω 1%
24.9 Ω 1%
11
6
8
PAUI
AUTOSEL
NTH
Port Selection
9
MD0
MD1
TPOPA
TPOPB
DSQE (907A)
STP (901A)
LI
1
78 Ω
16
1
JAB
PLR
CIN
9
LINE STATUS
2
3
4
5
6
7
8
10
11
12
13
14
15
330
330
330
330
Red
2
4
15
13
CIP
LEDC/FDE
LEDR
LEDT/PDN
LEDL
78 Ω
1 : 1
Green
Red
Red
DON
5
12
10
TEST
DOP
DIN
78
1 : 1
7
Fuse
8
9
DIP
+3.3 V
12.4 kΩ
VCC1
VCC2
RBIAS
+ 12 V
1 %
Chassis
Gnd
GND1 GND2
1
0.1 μF
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
1
2
Datasheet
25
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
3.4.5
Three Media Application
Figure 14 shows the LXT907A Transceiver in Mode 2 (compatible with Intel 82596 controllers)
with additional media options for the AUI port. Two transformers are used to couple the AUI port
to either a D-connector or a BNC connector. A DP8392 coax transceiver with PM6044 power
supply are required to drive the thin coax network through the BNC.
Figure 14. Three Media Application
LXT907A
26
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
3.4.6
AUI Encoder/Decoder Only
In this application (Figure 15), the DTE is connected to a coaxial network through the AUI.
AUTOSEL is tied Low and PAUI is tied High to manually select the AUI port. The twisted-pair
port is not used. With MD1 and MD0 both Low, the logic and framing are set to Mode 1
(compatible with AMD AM7990 controllers). The LI pin is tied Low, disabling the link test
function. The DSQE pin is also Low, enabling the SQE function on the LXT907A Transceiver. The
LBK input controls loopback. A 20 MHz system clock is supplied at CLK1, with CLK0 left open.
Figure 15. AUI Encoder/Decoder Only Application
SYSTEM
CLOCK
Left Open
CLKO
20 MHz
CLKI
TX
TENA
TXD
TEN
TCLK
RCLK
RXD
CD
TCLK
RCLK
AM7990 BACK-END/
CONTROLLER
INTERFACE
RX
RENA
CLSN
LBK
COL
LBK
LOOPBACK
CONTROL
AUTOSEL
PAUI
1
2
3
4
5
6
7
8
78 Ω
1
16
9
CIN
NTH
PROGRAMMING
OPTIONS
MD0
10
11
12
13
14
15
MD1
2
4
15
13
CIP
DSQE (907A)
78 Ω
78 Ω
DON
LI
5
12
10
DOP
DIN
JAB
PLR
LINE STATUS
7
330
330 330 330
Fuse
8
9
LEDC/FDE
LEDR
DIP
GREEN
Red Red Red
LEDT/PDN
LEDL
+ 12 V
Chassis
Gnd
TEST
1
+3.3 V
12.4 kΩ
VCC1
VCC2
RBIAS
Bias resistor RBIAS should be
located close to the pin and
isolated from the other signals
1 %
1
GND1 GND2
Datasheet
27
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
3.4.7
150Ω Shielded Twisted-Pair Only (LXT901A Transceiver only)
Figure 16 shows the LXT901A Transceiver in a typical twisted-pair only application. The DTE is
connected to a 10BASE-T network through the twisted-pair RJ-45 connector. Note that the AUI
port is not used. With MD0 tied High and MD1 Low, the LXT901A Transceiver logic and framing
are set to Mode 2 (compatible with Intel 82596 controllers).
A 20 MHz system clock input at CLK1 is used in place of the crystal oscillator. (CLK0 is left
open). The L1 pin externally controls the link test function. The STP and NTH pins are both tied
Low, selecting the reduced receiver threshold and 150 Ω termination for shielded twisted-pair
cable. The switch at LEDT/PDN manually controls the power down mode.
Figure 16. 150 Ω Shielded Twisted-Pair Only Application (LXT901A Transceiver )
0.1 μF
20 MHz
SYSTEM
CLOCK
Left Open
CLK0
CLK1
TXD
2
CLK
RJ45
6
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
1
1 : 1 16
TPIN
TPIP
TEN
75 Ω
75 Ω
TCLK
RCLK
RXD
82596
5
4
3
2
1
BACK-END/
CONTROLLER
INTERFACE
3
14
RCLK
CD
COL
LBK
75 Ω 1%
TPONB
TPONA
1 :
2
11
9
6
8
AUTOSEL
PAUI
NTH
37.5 Ω 1%
37.5 Ω 1%
MD0
PROGRAMMING
OPTIONS
TPOPA
TPOPB
MD1
STP
75 Ω 1%
LI
Link Test Enable
JAB
PLR
LINE STATUS
10K
10K
TEST
LEDC/FDE
LEDR
LEDL
12.4 kΩ 1%
RBIAS
LEDT/PDN
VCC1
+3.3 V
1
GND1 GND2
VCC2
1
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
2
28
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
4.0
Test Specifications
Note: Table 4 through Table 13 and Figure 17 through Figure 42 represent the performance specifications
of the LXT901A/907A Transceiver. These specifications are guaranteed by test except where noted
“by design.” Minimum and maximum values listed in Table 6 through Table 13 apply over the
recommended operating conditions specified in Table 5.
For all Quality and Reliability issues (for example, parts packaging and thermal specifications),
please send your questions to Intel at the following e-mail address: qr.requests@intel.com.
Table 4. Absolute Maximum Values
Parameter
Symbol
Min
Max
Units
Supply voltage
VCC
-0.3
-65
6
V
Storage temperature
TSTG
+150
ºC
Caution: Exceeding these values may cause permanent damage. Functional operation under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
Table 5. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Recommended supply voltage1
VCC
3.13
3.3
3.47
V
Recommended operating temperature
(Commercial)
TOP
0
–
+70
ºC
1. Voltages with respect to ground unless otherwise specified. Power supply should be filtered to suppress
high frequency transients, consistent with good PCB design.
Table 6. I/O Electrical Characteristics
1
Parameter
Input Low voltage2
Sym
Min
Typ
Max
Units
Test Conditions
VIL
VIH
VOL
VOL
–
2.0
–
–
–
–
–
0.8
–
V
V
–
–
Input High voltage2
0.4
10
V
IOL = 1.6 mA
Output Low voltage
µ
A
–
%VCC
IOL < 10
Output Low voltage
(Open drain LED driver)
VOLL
–
–
0.7
%VCC
IOLL = 10 mA
µ
µ
VOH
VOH
–
2.4
90
–
–
–
7
–
–
V
%VCC
ns
IOH = 40
IOH < 10
A
Output High voltage
A
Output rise
time
CMOS
TTL
12
CLOAD = 20 pF
–
–
–
7
8
ns
TCLK & RCLK
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
Datasheet
29
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Table 6. I/O Electrical Characteristics (Continued)
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
CMOS
TTL
–
–
–
–
–
–
7
7
–
12
8
ns
ns
ns
CLOAD= 20 pF
Output fall time
TCLK & RCLK
–
–
CLKI rise time (externally driven)
10
CLKI duty cycle (externally
driven)
–
–
40/60
%
–
ICC
ICC
–
–
65
95
85
mA
mA
Idle Mode
120
Transmitting on TP
Normal Mode
Supply current
Transmitting on
AUI
ICC
ICC
–
–
95
120
2
mA
mA
Power Down
Mode
0.03
–
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
Table 7. AUI Electrical Characteristics
1
Parameter
Input Low current
Symbol
Min
Typ
Max
Units
Test Conditions
µ
µ
IIL
IIH
–
–
–
–
–
-700
500
A
–
–
–
Input High current
A
Differential output voltage
VOD
±550
±1200
mV
mV
5 MHz square wave
input
Differential squelch threshold
VDS
150
250
350
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 8. TP Electrical Characteristics
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Transmit output impedance
ZOUT
–
5
–
Ω
–
0 line length for
internal MAU
2
Transmit timing jitter addition
–
–
±3.3
±10
ns
After line model
specified by IEEE
802.3 for 10BASE-T
internal MAU
Transmit timing jitter added by the
MAU and PLS sections
–
–
±3.3
±5.5
ns
2, 3
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and
3.5 ns from the MAU.
30
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Table 8. TP Electrical Characteristics (Continued)
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Between TPIP/TPIN,
CIP/CIN & DIP/DIN
Receive input impedance
ZIN
–
20
–
kΩ
Normal
threshol
d; NTH =
1
5 MHz square wave
input
VDS
VDS
300
180
400
250
585
345
mV
mV
Differential squelch
Threshold
Reduced
threshol
d; NTH =
0
5 MHz square wave
input
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and
3.5 ns from the MAU.
Table 9. Switching Characteristics
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
Maximum transmit time
Unjab time
–
–
–
–
–
–
20
250
50
2
–
–
150
750
150
7
ms
ms
ms
ms
ms
ms
Jabber Timing
Time link loss receive
Link min receive
–
–
Link Integrity
Timing
Link max receive
Link transmit period
50
8
–
150
24
10
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 10. RCLK/Start-of-Frame Timing
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
AUI
tDATA
tDATA
tCD
–
–
900
1200
25
1100
1500
200
550
–
ns
ns
ns
ns
ns
ns
ns
ns
Decoder acquisition
time
TP
AUI
–
CD turn-on delay
TP
tCD
–
425
70
Mode 1
tRDS
tRDS
tRDH
tRDH
60
30
10
30
Receive data setup
from RCLK
Modes 2, 3 and 4
Mode 1
45
–
20
–
Receive data hold
from RCLK
Modes 2, 3 and 4
45
–
RCLK shut off delay from CD assert
(LXT907A Transceiver only; Mode 3)
tsws
–
±100
–
ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Datasheet
31
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Table 11. RCLK/End-of-Frame Timing
Parameter
RCLK after CD off
Type
Sym
Mode 1
Mode 2
Mode 3
Mode 4
Units
Min
Max
Max
Typ1
tRC
tRD
5
1
27
375
475
–
5
BT
ns
Rcv data throughput delay
400
500
5
375
475
50
375
475
–
2
CD turn off delay
tCDOFF
tIFG
ns
Receive block out after TEN off
BT
RCLK switching delay after CD
off (LXT907A Transceiver only;
Mode 3)
Typ1
tSWE
–
–
120(±80)
–
ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. CD turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last
bit.
Table 12. Transmit Timing
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
TEN setup from TCLK
tEHCH
tDSCH
tCHEL
tCHDU
tSTUD
tSTUD
tTPD
22
22
5
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
TXD setup from TCLK
TEN hold after TCLK
–
–
TXD hold after TCLK
5
–
–
Transmit start-up delay - AUI
Transmit start-up delay - TP
Transmit through-put delay - AUI
Transmit through-put delay - TP
–
220
430
–
450
450
300
350
–
–
tTPD
–
300
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 13. Collision, COL/CI Output and Loopback Timing
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
COL turn-on delay
tCOLD
tCOLOFF
tSQED
tSQEP
–
–
40
420
1.2
1000
25
500
500
1.6
1500
–
ns
ns
COL turn-off delay
µ
s
COL (SQE) Delay after TEN off
COL (SQE) Pulse Duration
LBK setup from TEN
LBK hold after TEN
0.65
500
10
ns
ns
ns
tKHEH
tKHEL
10
0
–
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
32
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
4.1
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)
Figures 17 - 22
Figure 17. Mode 1 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
Figure 18. Mode 1 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
tRC
RCLK
RXD
1
0
1
0
1
0
1
0
0
Datasheet
33
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 19. Mode 1 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 20. Mode 1 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 21. Mode 1 COL/CI Output Timing
TEN
tSQED
COL
tSQEP
Figure 22. Mode 1 Loopback Timing
LBK
tKHEH
tKHEL
TEN
34
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
4.2
Timing Diagrams for Mode 2 (MD1 = Low, MD0 = High)
Figures 23 - 28
Figure 23. Mode 2 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
or DIP/DIN
CD
tCD
RCLK
tRDS
tRDH
1
tDATA
RXD
1
0
1
0
0
1
0
1
1
1
0
1
Figure 24. Mode 2 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
CD
tCDOFF
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
Datasheet
35
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 25. Mode 2 Transmit Timing
TEN
tEHCH
TCLK
tCHEL
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 26. Mode 2 Collision Detect Timing
CI
tCOLD
tCOLOFF
COL
Figure 27. Mode 2 COL/CI Output Timing
tIFG
TEN
COL
tSQED
tSQEP
Figure 28. Mode 2 Loopback Timing
LBK
tKHEH
tKHEL
TEN
36
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
4.3
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Figures 29 - 36
Figure 29. Mode 3 RCLK/Start-of-Frame Timing (LXT901A Transceiver)
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
1
tRDH
1
tDATA
RXD
0
1
0
0
1
0
1
1
1
0
1
Figure 30. Mode 3 RCLK/End-of-Frame Timing (LXT901A Transceiver)
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
RCLK
27 bits
RXD
1
0
1
0
1
0
1
0
0
Datasheet
37
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 31. Mode 3 RCLK/Start-of-Frame Timing (LXT907A Transceiver)
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
tSWS
Recovered from Input Data Stream
RCLK
tRDS
1
Generated from TCLK
tDATA
tRDH
1
RXD
0
1
0
0
1
0
1
1
1
0
1
Figure 32. Mode 3 RCLK/End-of-Frame Timing (LXT907A Transceiver)
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
tSWE
RCLK
Recovered Clock
Generated from TCLK
RXD
1
0
1
0
1
0
1
0
0
38
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 33. Mode 3 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
TPO
tTPD
Figure 34. Mode 3 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 35. Mode 3 COL/CI Output Timing
TEN
tSQED
tSQEP
COL
Figure 36. Mode 3 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
39
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
4.4
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Figures 37 - 42
Figure 37. Mode 4 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
Figure 38. Mode 4 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
40
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 39. Mode 4 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
TXD
tDSCH
tCHDU
tTPD
tSTUD
TPO
Figure 40. Mode 4 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 41. Mode 4 COL/CI Output Timing
TEN
tSQED
COL
tSQEP
Figure 42. Mode 4 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
41
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
5.0
Mechanical Specifications
Figure 43. 44-Pin PLCC
44-Pin Plastic Leaded Chip Carrier
• Part Number LXT901APC and LXT907APC (Commercial Temperature Range)
C
L
Inches
Millimeters
C
B
Dim
Min
Max
Min
Max
A
A1
A2
B
0.165
0.090
0.062
0.050
0.026
0.685
0.650
0.013
0.180
0.120
0.083
–
4.191
2.286
1.575
1.270
0.660
17.399
16.510
0.330
4.572
3.048
2.108
–
C
0.032
0.695
0.656
0.021
0.813
17.653
16.662
0.533
D
D1
F
D1
D
D
A2
A
A1
F
42
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 44. 64-Pin LQFP
64-Pin Low-Profile Quad Flat Package
•Part Number LXT901ALC and LXT907ALC (Commercial Temperature Range)
D
Inches
Millimeters
D1
Dim
Min
Max
Min
Max
A
A1
A2
B
–
0.063
0.006
0.057
.011
–
1.60
0.15
1.45
0.27
0.002
0.053
0.007
0.05
1.35
0.17
E1
E
D
0.472 BSC
12.00 BSC
D1
E
0.394 BSC
0.472 BSC
0.394 BSC
0.020 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.50 BSC
E1
e
e
e
/
2
L
0.018
0.030
0.45
0.75
L1
θ3
θ
0.039 REF
1.00 REF
11o
0o
13o
7o
11o
0o
13o
7o
θ3
L1
A2
A
θ
A1
B
θ3
L
Datasheet
43
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
5.1
Top-Label Marking
Figure 45 shows a sample LQFP package for the LXT901A Transceiver.
Note:
In contrast to the Pb-Free (RoHS-compliant) LQFP package, the non-RoHS-compliant packages
do not have the “e3” symbol in the last line of the package label.
Figure 45. Sample LQFP Package – Intel® DJLXT901ALC Transceiver
Pin1
Part Number
FPO Number
LXT901ALC A4
XXXXXXXX
BSMC
Bottom Side Mark Code
B5392-01
Figure 46 shows a sample Pb-free RoHS-compliant LQFP package for the LXT901A Transceiver.
Figure 46. Sample Pb-Free (RoHS-Compliant) LQFP Package –
Intel® WJLXT901ALC Transceiver
Pin 1
Part Number
WJLXT901C A4
FPO Number
XXXXXXXX
Pb-Free Indication
BSMC
e3
Bottom Side Mark Code
B5374-01
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 47 shows a sample TQFP package for the LXT907A Transceiver.
In contrast to the Pb-Free (RoHS-compliant) TQFP package, the non-RoHS-compliant packages
do not have the “e3” symbol in the last line of the package label.
Figure 47. Sample TQFP Package – Intel® DJLXT907ALC Transceiver
Pin1
Part Number
LXT907ALC A4
FPO Number
XXXXXXXX
BSMC
Bottom Side Mark Code
B5419-01
Figure 50 shows a Pb-Free (RoHS-Compliant) TQFP package for the LXT907A Transceiver.
Figure 48. Sample Pb-Free (RoHS-Compliant) TQFP Package –
Intel® WJLXT907ALC Transceiver
Pin 1
Part Number
WJLXT907C A4
FPO Number
XXXXXXXX
Pb-Free Indication
BSMC
e3
Bottom Side Mark Code
B5394-01
Datasheet
45
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 49 shows a sample PLCC package for the LXT901A/907A Transceiver.
Note: In contrast to the Pb-Free (RoHS-compliant) PLCC package, the non-RoHS-compliant packages
do not have the “e3” symbol in the last line of the package label.
Figure 49. Sample PLCC Package – Intel® NLXT90xAPC Transceiver
Pin1
Part Number
LXT90xAPC A4
FPO Number
XXXXXXXX
BSMC
Bottom Side Mark Code
B5393-01
Figure 50 shows a Pb-Free (RoHS-Compliant) PLCC package for the
LXT901A/907A Transceiver.
Figure 50. Sample Pb-Free (RoHS-Compliant) PLCC Package –
Intel® EELXT90xAPC Transceiver
Pin 1
Part Number
EELXT90xC A4
FPO Number
XXXXXXXX
Pb-Free Indication
BSMC
e3
Bottom Side Mark Code
B5377-01
46
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
6.0
Ordering Information
Table 14 lists the LXT901A/907A Transceivers product ordering information. Figure 51 provides
the ordering information matrix.
Table 14. Product Information
Intel Number
Revision
Package Type
Pin Count
RoHS Compliant
DJLXT901ALC.A4
WJLXT901ALC.A4
DJLXT907ALC.A4
WJLXT907ALC.A4
NLXT901APC.E2
EELXT901APC.E2
NLXT907APC.E2
EELXT907APC.E2
A4
A4
A4
A4
E2
E2
E2
E2
LQFP
LQFP
TQFP
TQFP
PLCC
PLCC
PLCC
PLCC
64
64
32
32
44
44
44
44
No
Yes
No
Yes
No
Yes
No
Yes
Datasheet
47
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
Intel® LXT901A/907A Universal 3.3 V Ethernet Transceiver
Figure 51 shows an order matrix with sample information for the LXT901A/907A Transceivers.
Figure 51. Ordering Information Matrix – Sample
DJ
LXT
901A
L
C
A4
Product Revision
xn = 2 Alphanumeric characters
Temperature Range
A = Ambient (0 – 550 C)
C = Commercial (0 – 700 C)
E = Extended (-40 – 850 C)
Internal Package Designator
L = LQFP
P = PLCC
N = DIP
Q = PQFP
H = QFP
T = TQFP
B = BGA
C = CBGA
E = TBGA
K = HSBGA (BGA with heat slug
Product Code
xxxxx = 3-5 Digit alphanumeric
IXA Product Prefix
LXT = PHY layer device
IXE = Switching engine
IXF = Formatting device (MAC/Framer)
IXP = Network processor
Intel Package Designator
Package
Leaded
Pb-Free
WB
WJ
HQFP
LQFP
HB
DJ
FA
BJ
JA
TQFP
TQFP
FA
WD
QU
EG
WG
UB
PQFP
PQFP
PQFP
QFN
HD
KU
S
HG
LB
PD
PA
N
QFN
UC
EP
EE
RU
PC
EL
PR
PDIP
SSOP
PLCC
MMAP
MMAP
PBGA
PBGA
PBGA
PBGA
CBGA
FCBGA
TBGA
HZ
RC
FL
FW
GD
GW
HF
HL
TL
LU
EW
WF
JP
SC
B5326-02
48
Datasheet
Document Number: 249098
Revision Number: 003
Revision Date: 27-Nov-2005
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